2 * i386 virtual CPU header
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #define TARGET_LONG_BITS 32
27 #if defined(__i386__) && !defined(CONFIG_SOFTMMU)
56 /* segment descriptor fields */
57 #define DESC_G_MASK (1 << 23)
58 #define DESC_B_SHIFT 22
59 #define DESC_B_MASK (1 << DESC_B_SHIFT)
60 #define DESC_AVL_MASK (1 << 20)
61 #define DESC_P_MASK (1 << 15)
62 #define DESC_DPL_SHIFT 13
63 #define DESC_S_MASK (1 << 12)
64 #define DESC_TYPE_SHIFT 8
65 #define DESC_A_MASK (1 << 8)
67 #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */
68 #define DESC_C_MASK (1 << 10) /* code: conforming */
69 #define DESC_R_MASK (1 << 9) /* code: readable */
71 #define DESC_E_MASK (1 << 10) /* data: expansion direction */
72 #define DESC_W_MASK (1 << 9) /* data: writable */
74 #define DESC_TSS_BUSY_MASK (1 << 9)
88 #define TF_MASK 0x00000100
89 #define IF_MASK 0x00000200
90 #define DF_MASK 0x00000400
91 #define IOPL_MASK 0x00003000
92 #define NT_MASK 0x00004000
93 #define RF_MASK 0x00010000
94 #define VM_MASK 0x00020000
95 #define AC_MASK 0x00040000
96 #define VIF_MASK 0x00080000
97 #define VIP_MASK 0x00100000
98 #define ID_MASK 0x00200000
100 /* hidden flags - used internally by qemu to represent additionnal cpu
101 states. Only the CPL and INHIBIT_IRQ are not redundant. We avoid
102 using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring
105 #define HF_CPL_SHIFT 0
106 /* true if soft mmu is being used */
107 #define HF_SOFTMMU_SHIFT 2
108 /* true if hardware interrupts must be disabled for next instruction */
109 #define HF_INHIBIT_IRQ_SHIFT 3
110 /* 16 or 32 segments */
111 #define HF_CS32_SHIFT 4
112 #define HF_SS32_SHIFT 5
113 /* zero base for DS, ES and SS */
114 #define HF_ADDSEG_SHIFT 6
115 /* copy of CR0.PE (protected mode) */
116 #define HF_PE_SHIFT 7
117 #define HF_TF_SHIFT 8 /* must be same as eflags */
118 #define HF_IOPL_SHIFT 12 /* must be same as eflags */
119 #define HF_VM_SHIFT 17 /* must be same as eflags */
121 #define HF_CPL_MASK (3 << HF_CPL_SHIFT)
122 #define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT)
123 #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT)
124 #define HF_CS32_MASK (1 << HF_CS32_SHIFT)
125 #define HF_SS32_MASK (1 << HF_SS32_SHIFT)
126 #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT)
127 #define HF_PE_MASK (1 << HF_PE_SHIFT)
128 #define HF_TF_MASK (1 << HF_TF_SHIFT)
130 #define CR0_PE_MASK (1 << 0)
131 #define CR0_TS_MASK (1 << 3)
132 #define CR0_WP_MASK (1 << 16)
133 #define CR0_AM_MASK (1 << 18)
134 #define CR0_PG_MASK (1 << 31)
136 #define CR4_VME_MASK (1 << 0)
137 #define CR4_PVI_MASK (1 << 1)
138 #define CR4_TSD_MASK (1 << 2)
139 #define CR4_DE_MASK (1 << 3)
140 #define CR4_PSE_MASK (1 << 4)
141 #define CR4_PAE_MASK (1 << 5)
142 #define CR4_PGE_MASK (1 << 7)
144 #define PG_PRESENT_BIT 0
146 #define PG_USER_BIT 2
149 #define PG_ACCESSED_BIT 5
150 #define PG_DIRTY_BIT 6
152 #define PG_GLOBAL_BIT 8
154 #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT)
155 #define PG_RW_MASK (1 << PG_RW_BIT)
156 #define PG_USER_MASK (1 << PG_USER_BIT)
157 #define PG_PWT_MASK (1 << PG_PWT_BIT)
158 #define PG_PCD_MASK (1 << PG_PCD_BIT)
159 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
160 #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT)
161 #define PG_PSE_MASK (1 << PG_PSE_BIT)
162 #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT)
164 #define PG_ERROR_W_BIT 1
166 #define PG_ERROR_P_MASK 0x01
167 #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT)
168 #define PG_ERROR_U_MASK 0x04
169 #define PG_ERROR_RSVD_MASK 0x08
171 #define MSR_IA32_APICBASE 0x1b
172 #define MSR_IA32_APICBASE_BSP (1<<8)
173 #define MSR_IA32_APICBASE_ENABLE (1<<11)
174 #define MSR_IA32_APICBASE_BASE (0xfffff<<12)
176 #define MSR_IA32_SYSENTER_CS 0x174
177 #define MSR_IA32_SYSENTER_ESP 0x175
178 #define MSR_IA32_SYSENTER_EIP 0x176
180 #define EXCP00_DIVZ 0
181 #define EXCP01_SSTP 1
183 #define EXCP03_INT3 3
184 #define EXCP04_INTO 4
185 #define EXCP05_BOUND 5
186 #define EXCP06_ILLOP 6
187 #define EXCP07_PREX 7
188 #define EXCP08_DBLE 8
189 #define EXCP09_XERR 9
190 #define EXCP0A_TSS 10
191 #define EXCP0B_NOSEG 11
192 #define EXCP0C_STACK 12
193 #define EXCP0D_GPF 13
194 #define EXCP0E_PAGE 14
195 #define EXCP10_COPR 16
196 #define EXCP11_ALGN 17
197 #define EXCP12_MCHK 18
200 CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
201 CC_OP_EFLAGS, /* all cc are explicitely computed, CC_SRC = flags */
203 CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
207 CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
211 CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
215 CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
219 CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
223 CC_OP_LOGICB, /* modify all flags, CC_DST = res */
227 CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
231 CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */
235 CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
239 CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
247 #define USE_X86LDOUBLE
250 #ifdef USE_X86LDOUBLE
251 typedef long double CPU86_LDouble;
253 typedef double CPU86_LDouble;
256 typedef struct SegmentCache {
263 typedef struct CPUX86State {
264 /* standard registers */
267 uint32_t eflags; /* eflags register. During CPU emulation, CC
268 flags and DF are set to zero because they are
271 /* emulator internal eflags handling */
275 int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
276 uint32_t hflags; /* hidden flags, see HF_xxx constants */
279 unsigned int fpstt; /* top of stack index */
282 uint8_t fptags[8]; /* 0 = valid, 1 = empty */
283 CPU86_LDouble fpregs[8];
285 /* emulator internal variables */
295 SegmentCache segs[6]; /* selector values */
298 SegmentCache gdt; /* only base and limit are used */
299 SegmentCache idt; /* only base and limit are used */
301 /* sysenter registers */
302 uint32_t sysenter_cs;
303 uint32_t sysenter_esp;
304 uint32_t sysenter_eip;
306 /* temporary data for USE_CODE_COPY mode */
310 /* exception/interrupt handling */
314 int exception_is_int;
315 int exception_next_eip;
316 struct TranslationBlock *current_tb; /* currently executing TB */
317 uint32_t cr[5]; /* NOTE: cr1 is unused */
318 uint32_t dr[8]; /* debug registers */
319 int interrupt_request;
320 int user_mode_only; /* user mode only simulation */
322 /* soft mmu support */
324 /* 0 = kernel, 1 = user */
325 CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
326 CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
328 /* ice debug support */
329 uint32_t breakpoints[MAX_BREAKPOINTS];
331 int singlestep_enabled;
338 void cpu_x86_outb(CPUX86State *env, int addr, int val);
339 void cpu_x86_outw(CPUX86State *env, int addr, int val);
340 void cpu_x86_outl(CPUX86State *env, int addr, int val);
341 int cpu_x86_inb(CPUX86State *env, int addr);
342 int cpu_x86_inw(CPUX86State *env, int addr);
343 int cpu_x86_inl(CPUX86State *env, int addr);
346 CPUX86State *cpu_x86_init(void);
347 int cpu_x86_exec(CPUX86State *s);
348 void cpu_x86_close(CPUX86State *s);
349 int cpu_x86_get_pic_interrupt(CPUX86State *s);
351 /* this function must always be used to load data in the segment
352 cache: it synchronizes the hflags with the segment cache values */
353 static inline void cpu_x86_load_seg_cache(CPUX86State *env,
354 int seg_reg, unsigned int selector,
355 uint8_t *base, unsigned int limit,
359 unsigned int new_hflags;
361 sc = &env->segs[seg_reg];
362 sc->selector = selector;
367 /* update the hidden flags */
368 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
369 >> (DESC_B_SHIFT - HF_CS32_SHIFT);
370 new_hflags |= (env->segs[R_SS].flags & DESC_B_MASK)
371 >> (DESC_B_SHIFT - HF_SS32_SHIFT);
372 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
373 /* XXX: try to avoid this test. The problem comes from the
374 fact that is real mode or vm86 mode we only modify the
375 'base' and 'selector' fields of the segment cache to go
376 faster. A solution may be to force addseg to one in
378 new_hflags |= HF_ADDSEG_MASK;
380 new_hflags |= (((unsigned long)env->segs[R_DS].base |
381 (unsigned long)env->segs[R_ES].base |
382 (unsigned long)env->segs[R_SS].base) != 0) <<
385 env->hflags = (env->hflags &
386 ~(HF_CS32_MASK | HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
389 /* wrapper, just in case memory mappings must be changed */
390 static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)
393 s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl;
395 #error HF_CPL_MASK is hardcoded
399 /* the following helpers are only usable in user mode simulation as
400 they can trigger unexpected exceptions */
401 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
402 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32);
403 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32);
405 /* you can call this signal handler from your SIGBUS and SIGSEGV
406 signal handlers to inform the virtual CPU of exceptions. non zero
407 is returned if the signal was handled by the virtual CPU. */
409 int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
411 void cpu_x86_set_a20(CPUX86State *env, int a20_state);
413 /* will be suppressed */
414 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
417 #define X86_DUMP_FPU 0x0001 /* dump FPU state too */
418 #define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
419 void cpu_x86_dump_state(CPUX86State *env, FILE *f, int flags);
421 #define TARGET_PAGE_BITS 12
424 #endif /* CPU_I386_H */