2 * i386 execution defines
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include "dyngen-exec.h"
23 /* XXX: factorize this mess */
25 #define TARGET_LONG_BITS 64
27 #define TARGET_LONG_BITS 32
32 register struct CPUX86State *env asm(AREG0);
37 #define EAX (env->regs[R_EAX])
38 #define ECX (env->regs[R_ECX])
39 #define EDX (env->regs[R_EDX])
40 #define EBX (env->regs[R_EBX])
41 #define ESP (env->regs[R_ESP])
42 #define EBP (env->regs[R_EBP])
43 #define ESI (env->regs[R_ESI])
44 #define EDI (env->regs[R_EDI])
45 #define EIP (env->eip)
48 #define CC_SRC (env->cc_src)
49 #define CC_DST (env->cc_dst)
50 #define CC_OP (env->cc_op)
53 #define FT0 (env->ft0)
54 #define ST0 (env->fpregs[env->fpstt].d)
55 #define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d)
61 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
62 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
63 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
64 void cpu_x86_flush_tlb(CPUX86State *env, target_ulong addr);
65 int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
66 int is_write, int mmu_idx, int is_softmmu);
67 void tlb_fill(target_ulong addr, int is_write, int mmu_idx,
69 void __hidden cpu_lock(void);
70 void __hidden cpu_unlock(void);
71 void do_interrupt(int intno, int is_int, int error_code,
72 target_ulong next_eip, int is_hw);
73 void do_interrupt_user(int intno, int is_int, int error_code,
74 target_ulong next_eip);
75 void raise_interrupt(int intno, int is_int, int error_code,
77 void raise_exception_err(int exception_index, int error_code);
78 void raise_exception(int exception_index);
79 void do_smm_enter(void);
80 void __hidden cpu_loop_exit(void);
82 void OPPROTO op_movl_eflags_T0(void);
83 void OPPROTO op_movl_T0_eflags(void);
85 /* n must be a constant to be efficient */
86 static inline target_long lshift(target_long x, int n)
96 static inline void svm_check_intercept(uint32_t type)
98 helper_svm_check_intercept_param(type, 0);
101 #if !defined(CONFIG_USER_ONLY)
103 #include "softmmu_exec.h"
105 #endif /* !defined(CONFIG_USER_ONLY) */
107 #ifdef USE_X86LDOUBLE
108 /* use long double functions */
109 #define floatx_to_int32 floatx80_to_int32
110 #define floatx_to_int64 floatx80_to_int64
111 #define floatx_to_int32_round_to_zero floatx80_to_int32_round_to_zero
112 #define floatx_to_int64_round_to_zero floatx80_to_int64_round_to_zero
113 #define int32_to_floatx int32_to_floatx80
114 #define int64_to_floatx int64_to_floatx80
115 #define float32_to_floatx float32_to_floatx80
116 #define float64_to_floatx float64_to_floatx80
117 #define floatx_to_float32 floatx80_to_float32
118 #define floatx_to_float64 floatx80_to_float64
119 #define floatx_abs floatx80_abs
120 #define floatx_chs floatx80_chs
121 #define floatx_round_to_int floatx80_round_to_int
122 #define floatx_compare floatx80_compare
123 #define floatx_compare_quiet floatx80_compare_quiet
135 #define floatx_to_int32 float64_to_int32
136 #define floatx_to_int64 float64_to_int64
137 #define floatx_to_int32_round_to_zero float64_to_int32_round_to_zero
138 #define floatx_to_int64_round_to_zero float64_to_int64_round_to_zero
139 #define int32_to_floatx int32_to_float64
140 #define int64_to_floatx int64_to_float64
141 #define float32_to_floatx float32_to_float64
142 #define float64_to_floatx(x, e) (x)
143 #define floatx_to_float32 float64_to_float32
144 #define floatx_to_float64(x, e) (x)
145 #define floatx_abs float64_abs
146 #define floatx_chs float64_chs
147 #define floatx_round_to_int float64_round_to_int
148 #define floatx_compare float64_compare
149 #define floatx_compare_quiet float64_compare_quiet
152 extern CPU86_LDouble sin(CPU86_LDouble x);
153 extern CPU86_LDouble cos(CPU86_LDouble x);
154 extern CPU86_LDouble sqrt(CPU86_LDouble x);
155 extern CPU86_LDouble pow(CPU86_LDouble, CPU86_LDouble);
156 extern CPU86_LDouble log(CPU86_LDouble x);
157 extern CPU86_LDouble tan(CPU86_LDouble x);
158 extern CPU86_LDouble atan2(CPU86_LDouble, CPU86_LDouble);
159 extern CPU86_LDouble floor(CPU86_LDouble x);
160 extern CPU86_LDouble ceil(CPU86_LDouble x);
162 #define RC_MASK 0xc00
163 #define RC_NEAR 0x000
164 #define RC_DOWN 0x400
166 #define RC_CHOP 0xc00
168 #define MAXTAN 9223372036854775808.0
170 #ifdef USE_X86LDOUBLE
176 unsigned long long lower;
177 unsigned short upper;
181 /* the following deal with x86 long double-precision numbers */
182 #define MAXEXPD 0x7fff
183 #define EXPBIAS 16383
184 #define EXPD(fp) (fp.l.upper & 0x7fff)
185 #define SIGND(fp) ((fp.l.upper) & 0x8000)
186 #define MANTD(fp) (fp.l.lower)
187 #define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7fff)) | EXPBIAS
191 /* NOTE: arm is horrible as double 32 bit words are stored in big endian ! */
194 #if !defined(WORDS_BIGENDIAN) && !defined(__arm__)
210 /* the following deal with IEEE double-precision numbers */
211 #define MAXEXPD 0x7ff
213 #define EXPD(fp) (((fp.l.upper) >> 20) & 0x7FF)
214 #define SIGND(fp) ((fp.l.upper) & 0x80000000)
216 #define MANTD(fp) (fp.l.lower | ((uint64_t)(fp.l.upper & ((1 << 20) - 1)) << 32))
218 #define MANTD(fp) (fp.ll & ((1LL << 52) - 1))
220 #define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7ff << 20)) | (EXPBIAS << 20)
223 static inline void fpush(void)
225 env->fpstt = (env->fpstt - 1) & 7;
226 env->fptags[env->fpstt] = 0; /* validate stack entry */
229 static inline void fpop(void)
231 env->fptags[env->fpstt] = 1; /* invvalidate stack entry */
232 env->fpstt = (env->fpstt + 1) & 7;
235 #ifndef USE_X86LDOUBLE
236 static inline CPU86_LDouble helper_fldt(target_ulong ptr)
243 upper = lduw(ptr + 8);
244 /* XXX: handle overflow ? */
245 e = (upper & 0x7fff) - 16383 + EXPBIAS; /* exponent */
246 e |= (upper >> 4) & 0x800; /* sign */
247 ll = (ldq(ptr) >> 11) & ((1LL << 52) - 1);
249 temp.l.upper = (e << 20) | (ll >> 32);
252 temp.ll = ll | ((uint64_t)e << 52);
257 static inline void helper_fstt(CPU86_LDouble f, target_ulong ptr)
264 stq(ptr, (MANTD(temp) << 11) | (1LL << 63));
265 /* exponent + sign */
266 e = EXPD(temp) - EXPBIAS + 16383;
267 e |= SIGND(temp) >> 16;
272 /* we use memory access macros */
274 static inline CPU86_LDouble helper_fldt(target_ulong ptr)
278 temp.l.lower = ldq(ptr);
279 temp.l.upper = lduw(ptr + 8);
283 static inline void helper_fstt(CPU86_LDouble f, target_ulong ptr)
288 stq(ptr, temp.l.lower);
289 stw(ptr + 8, temp.l.upper);
292 #endif /* USE_X86LDOUBLE */
294 #define FPUS_IE (1 << 0)
295 #define FPUS_DE (1 << 1)
296 #define FPUS_ZE (1 << 2)
297 #define FPUS_OE (1 << 3)
298 #define FPUS_UE (1 << 4)
299 #define FPUS_PE (1 << 5)
300 #define FPUS_SF (1 << 6)
301 #define FPUS_SE (1 << 7)
302 #define FPUS_B (1 << 15)
306 extern const CPU86_LDouble f15rk[7];
308 void fpu_raise_exception(void);
309 void restore_native_fp_state(CPUState *env);
310 void save_native_fp_state(CPUState *env);
312 extern const uint8_t parity_table[256];
313 extern const uint8_t rclw_table[32];
314 extern const uint8_t rclb_table[32];
316 static inline uint32_t compute_eflags(void)
318 return env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
321 /* NOTE: CC_OP must be modified manually to CC_OP_EFLAGS */
322 static inline void load_eflags(int eflags, int update_mask)
324 CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
325 DF = 1 - (2 * ((eflags >> 10) & 1));
326 env->eflags = (env->eflags & ~update_mask) |
327 (eflags & update_mask) | 0x2;
330 static inline void env_to_regs(void)
333 EAX = env->regs[R_EAX];
336 ECX = env->regs[R_ECX];
339 EDX = env->regs[R_EDX];
342 EBX = env->regs[R_EBX];
345 ESP = env->regs[R_ESP];
348 EBP = env->regs[R_EBP];
351 ESI = env->regs[R_ESI];
354 EDI = env->regs[R_EDI];
358 static inline void regs_to_env(void)
361 env->regs[R_EAX] = EAX;
364 env->regs[R_ECX] = ECX;
367 env->regs[R_EDX] = EDX;
370 env->regs[R_EBX] = EBX;
373 env->regs[R_ESP] = ESP;
376 env->regs[R_EBP] = EBP;
379 env->regs[R_ESI] = ESI;
382 env->regs[R_EDI] = EDI;
386 static inline int cpu_halted(CPUState *env) {
387 /* handle exit of HALTED state */
390 /* disable halt condition */
391 if (((env->interrupt_request & CPU_INTERRUPT_HARD) &&
392 (env->eflags & IF_MASK)) ||
393 (env->interrupt_request & CPU_INTERRUPT_NMI)) {
400 /* load efer and update the corresponding hflags. XXX: do consistency
401 checks with cpuid bits ? */
402 static inline void cpu_load_efer(CPUState *env, uint64_t val)
405 env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK);
406 if (env->efer & MSR_EFER_LMA)
407 env->hflags |= HF_LMA_MASK;
408 if (env->efer & MSR_EFER_SVME)
409 env->hflags |= HF_SVME_MASK;