4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
34 #define PREFIX_REPZ 0x01
35 #define PREFIX_REPNZ 0x02
36 #define PREFIX_LOCK 0x04
37 #define PREFIX_DATA 0x08
38 #define PREFIX_ADR 0x10
41 #define X86_64_ONLY(x) x
42 #define X86_64_DEF(x...) x
43 #define CODE64(s) ((s)->code64)
44 #define REX_X(s) ((s)->rex_x)
45 #define REX_B(s) ((s)->rex_b)
46 /* XXX: gcc generates push/pop in some opcodes, so we cannot use them */
48 #define BUGGY_64(x) NULL
51 #define X86_64_ONLY(x) NULL
52 #define X86_64_DEF(x...)
58 //#define MACRO_TEST 1
60 /* global register indexes */
61 static TCGv cpu_env, cpu_T[2], cpu_A0, cpu_cc_op, cpu_cc_src, cpu_cc_dst;
63 /* local register indexes (only used inside old micro ops) */
64 static TCGv cpu_tmp0, cpu_tmp1_i64, cpu_tmp2_i32, cpu_tmp3_i32, cpu_tmp4, cpu_ptr0, cpu_ptr1;
65 static TCGv cpu_tmp5, cpu_tmp6;
68 static int x86_64_hregs;
71 typedef struct DisasContext {
72 /* current insn context */
73 int override; /* -1 if no override */
76 target_ulong pc; /* pc = eip + cs_base */
77 int is_jmp; /* 1 = means jump (stop translation), 2 means CPU
78 static state change (stop translation) */
79 /* current block context */
80 target_ulong cs_base; /* base of CS segment */
81 int pe; /* protected mode */
82 int code32; /* 32 bit code segment */
84 int lma; /* long mode active */
85 int code64; /* 64 bit code segment */
88 int ss32; /* 32 bit stack segment */
89 int cc_op; /* current CC operation */
90 int addseg; /* non zero if either DS/ES/SS have a non zero base */
91 int f_st; /* currently unused */
92 int vm86; /* vm86 mode */
95 int tf; /* TF cpu flag */
96 int singlestep_enabled; /* "hardware" single step enabled */
97 int jmp_opt; /* use direct block chaining for direct jumps */
98 int mem_index; /* select memory access functions */
99 uint64_t flags; /* all execution flags */
100 struct TranslationBlock *tb;
101 int popl_esp_hack; /* for correct popl with esp base handling */
102 int rip_offset; /* only used in x86_64, but left for simplicity */
104 int cpuid_ext_features;
105 int cpuid_ext2_features;
108 static void gen_eob(DisasContext *s);
109 static void gen_jmp(DisasContext *s, target_ulong eip);
110 static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num);
112 /* i386 arith/logic operations */
132 OP_SHL1, /* undocumented */
145 /* I386 int registers */
146 OR_EAX, /* MUST be even numbered */
155 OR_TMP0 = 16, /* temporary operand register */
157 OR_A0, /* temporary register used when doing address evaluation */
160 static inline void gen_op_movl_T0_0(void)
162 tcg_gen_movi_tl(cpu_T[0], 0);
165 static inline void gen_op_movl_T0_im(int32_t val)
167 tcg_gen_movi_tl(cpu_T[0], val);
170 static inline void gen_op_movl_T0_imu(uint32_t val)
172 tcg_gen_movi_tl(cpu_T[0], val);
175 static inline void gen_op_movl_T1_im(int32_t val)
177 tcg_gen_movi_tl(cpu_T[1], val);
180 static inline void gen_op_movl_T1_imu(uint32_t val)
182 tcg_gen_movi_tl(cpu_T[1], val);
185 static inline void gen_op_movl_A0_im(uint32_t val)
187 tcg_gen_movi_tl(cpu_A0, val);
191 static inline void gen_op_movq_A0_im(int64_t val)
193 tcg_gen_movi_tl(cpu_A0, val);
197 static inline void gen_movtl_T0_im(target_ulong val)
199 tcg_gen_movi_tl(cpu_T[0], val);
202 static inline void gen_movtl_T1_im(target_ulong val)
204 tcg_gen_movi_tl(cpu_T[1], val);
207 static inline void gen_op_andl_T0_ffff(void)
209 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
212 static inline void gen_op_andl_T0_im(uint32_t val)
214 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], val);
217 static inline void gen_op_movl_T0_T1(void)
219 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
222 static inline void gen_op_andl_A0_ffff(void)
224 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffff);
229 #define NB_OP_SIZES 4
231 #define DEF_REGS(prefix, suffix) \
232 prefix ## EAX ## suffix,\
233 prefix ## ECX ## suffix,\
234 prefix ## EDX ## suffix,\
235 prefix ## EBX ## suffix,\
236 prefix ## ESP ## suffix,\
237 prefix ## EBP ## suffix,\
238 prefix ## ESI ## suffix,\
239 prefix ## EDI ## suffix,\
240 prefix ## R8 ## suffix,\
241 prefix ## R9 ## suffix,\
242 prefix ## R10 ## suffix,\
243 prefix ## R11 ## suffix,\
244 prefix ## R12 ## suffix,\
245 prefix ## R13 ## suffix,\
246 prefix ## R14 ## suffix,\
247 prefix ## R15 ## suffix,
249 #else /* !TARGET_X86_64 */
251 #define NB_OP_SIZES 3
253 #define DEF_REGS(prefix, suffix) \
254 prefix ## EAX ## suffix,\
255 prefix ## ECX ## suffix,\
256 prefix ## EDX ## suffix,\
257 prefix ## EBX ## suffix,\
258 prefix ## ESP ## suffix,\
259 prefix ## EBP ## suffix,\
260 prefix ## ESI ## suffix,\
261 prefix ## EDI ## suffix,
263 #endif /* !TARGET_X86_64 */
265 #if defined(WORDS_BIGENDIAN)
266 #define REG_B_OFFSET (sizeof(target_ulong) - 1)
267 #define REG_H_OFFSET (sizeof(target_ulong) - 2)
268 #define REG_W_OFFSET (sizeof(target_ulong) - 2)
269 #define REG_L_OFFSET (sizeof(target_ulong) - 4)
270 #define REG_LH_OFFSET (sizeof(target_ulong) - 8)
272 #define REG_B_OFFSET 0
273 #define REG_H_OFFSET 1
274 #define REG_W_OFFSET 0
275 #define REG_L_OFFSET 0
276 #define REG_LH_OFFSET 4
279 static inline void gen_op_mov_reg_TN(int ot, int t_index, int reg)
283 if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) {
284 tcg_gen_st8_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg]) + REG_B_OFFSET);
286 tcg_gen_st8_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg - 4]) + REG_H_OFFSET);
290 tcg_gen_st16_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);
294 tcg_gen_st32_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
295 /* high part of register set to zero */
296 tcg_gen_movi_tl(cpu_tmp0, 0);
297 tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET);
301 tcg_gen_st_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg]));
306 tcg_gen_st32_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
312 static inline void gen_op_mov_reg_T0(int ot, int reg)
314 gen_op_mov_reg_TN(ot, 0, reg);
317 static inline void gen_op_mov_reg_T1(int ot, int reg)
319 gen_op_mov_reg_TN(ot, 1, reg);
322 static inline void gen_op_mov_reg_A0(int size, int reg)
326 tcg_gen_st16_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);
330 tcg_gen_st32_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
331 /* high part of register set to zero */
332 tcg_gen_movi_tl(cpu_tmp0, 0);
333 tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET);
337 tcg_gen_st_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]));
342 tcg_gen_st32_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
348 static inline void gen_op_mov_TN_reg(int ot, int t_index, int reg)
352 if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) {
355 tcg_gen_ld8u_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg - 4]) + REG_H_OFFSET);
360 tcg_gen_ld_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg]));
365 static inline void gen_op_movl_A0_reg(int reg)
367 tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
370 static inline void gen_op_addl_A0_im(int32_t val)
372 tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
374 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
379 static inline void gen_op_addq_A0_im(int64_t val)
381 tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
385 static void gen_add_A0_im(DisasContext *s, int val)
389 gen_op_addq_A0_im(val);
392 gen_op_addl_A0_im(val);
395 static inline void gen_op_addl_T0_T1(void)
397 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
400 static inline void gen_op_jmp_T0(void)
402 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, eip));
405 static inline void gen_op_addw_ESP_im(int32_t val)
407 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ESP]));
408 tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, val);
409 tcg_gen_st16_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ESP]) + REG_W_OFFSET);
412 static inline void gen_op_addl_ESP_im(int32_t val)
414 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ESP]));
415 tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, val);
417 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffff);
419 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ESP]));
423 static inline void gen_op_addq_ESP_im(int32_t val)
425 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ESP]));
426 tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, val);
427 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ESP]));
431 static inline void gen_op_set_cc_op(int32_t val)
433 tcg_gen_movi_i32(cpu_cc_op, val);
436 static inline void gen_op_addl_A0_reg_sN(int shift, int reg)
438 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
440 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
441 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
443 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
447 static inline void gen_op_movl_A0_seg(int reg)
449 tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base) + REG_L_OFFSET);
452 static inline void gen_op_addl_A0_seg(int reg)
454 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base));
455 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
457 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
462 static inline void gen_op_movq_A0_seg(int reg)
464 tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base));
467 static inline void gen_op_addq_A0_seg(int reg)
469 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base));
470 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
473 static inline void gen_op_movq_A0_reg(int reg)
475 tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]));
478 static inline void gen_op_addq_A0_reg_sN(int shift, int reg)
480 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
482 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
483 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
487 static GenOpFunc *gen_op_cmov_reg_T1_T0[NB_OP_SIZES - 1][CPU_NB_REGS] = {
489 DEF_REGS(gen_op_cmovw_, _T1_T0)
492 DEF_REGS(gen_op_cmovl_, _T1_T0)
496 DEF_REGS(gen_op_cmovq_, _T1_T0)
501 static inline void gen_op_lds_T0_A0(int idx)
503 int mem_index = (idx >> 2) - 1;
506 tcg_gen_qemu_ld8s(cpu_T[0], cpu_A0, mem_index);
509 tcg_gen_qemu_ld16s(cpu_T[0], cpu_A0, mem_index);
513 tcg_gen_qemu_ld32s(cpu_T[0], cpu_A0, mem_index);
518 /* sign does not matter, except for lidt/lgdt call (TODO: fix it) */
519 static inline void gen_op_ld_T0_A0(int idx)
521 int mem_index = (idx >> 2) - 1;
524 tcg_gen_qemu_ld8u(cpu_T[0], cpu_A0, mem_index);
527 tcg_gen_qemu_ld16u(cpu_T[0], cpu_A0, mem_index);
530 tcg_gen_qemu_ld32u(cpu_T[0], cpu_A0, mem_index);
534 tcg_gen_qemu_ld64(cpu_T[0], cpu_A0, mem_index);
539 static inline void gen_op_ldu_T0_A0(int idx)
541 gen_op_ld_T0_A0(idx);
544 static inline void gen_op_ld_T1_A0(int idx)
546 int mem_index = (idx >> 2) - 1;
549 tcg_gen_qemu_ld8u(cpu_T[1], cpu_A0, mem_index);
552 tcg_gen_qemu_ld16u(cpu_T[1], cpu_A0, mem_index);
555 tcg_gen_qemu_ld32u(cpu_T[1], cpu_A0, mem_index);
559 tcg_gen_qemu_ld64(cpu_T[1], cpu_A0, mem_index);
564 static inline void gen_op_st_T0_A0(int idx)
566 int mem_index = (idx >> 2) - 1;
569 tcg_gen_qemu_st8(cpu_T[0], cpu_A0, mem_index);
572 tcg_gen_qemu_st16(cpu_T[0], cpu_A0, mem_index);
575 tcg_gen_qemu_st32(cpu_T[0], cpu_A0, mem_index);
579 tcg_gen_qemu_st64(cpu_T[0], cpu_A0, mem_index);
584 static inline void gen_op_st_T1_A0(int idx)
586 int mem_index = (idx >> 2) - 1;
589 tcg_gen_qemu_st8(cpu_T[1], cpu_A0, mem_index);
592 tcg_gen_qemu_st16(cpu_T[1], cpu_A0, mem_index);
595 tcg_gen_qemu_st32(cpu_T[1], cpu_A0, mem_index);
599 tcg_gen_qemu_st64(cpu_T[1], cpu_A0, mem_index);
604 static inline void gen_jmp_im(target_ulong pc)
606 tcg_gen_movi_tl(cpu_tmp0, pc);
607 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, eip));
610 static inline void gen_string_movl_A0_ESI(DisasContext *s)
614 override = s->override;
618 gen_op_movq_A0_seg(override);
619 gen_op_addq_A0_reg_sN(0, R_ESI);
621 gen_op_movq_A0_reg(R_ESI);
627 if (s->addseg && override < 0)
630 gen_op_movl_A0_seg(override);
631 gen_op_addl_A0_reg_sN(0, R_ESI);
633 gen_op_movl_A0_reg(R_ESI);
636 /* 16 address, always override */
639 gen_op_movl_A0_reg(R_ESI);
640 gen_op_andl_A0_ffff();
641 gen_op_addl_A0_seg(override);
645 static inline void gen_string_movl_A0_EDI(DisasContext *s)
649 gen_op_movq_A0_reg(R_EDI);
654 gen_op_movl_A0_seg(R_ES);
655 gen_op_addl_A0_reg_sN(0, R_EDI);
657 gen_op_movl_A0_reg(R_EDI);
660 gen_op_movl_A0_reg(R_EDI);
661 gen_op_andl_A0_ffff();
662 gen_op_addl_A0_seg(R_ES);
666 static GenOpFunc *gen_op_movl_T0_Dshift[4] = {
667 gen_op_movl_T0_Dshiftb,
668 gen_op_movl_T0_Dshiftw,
669 gen_op_movl_T0_Dshiftl,
670 X86_64_ONLY(gen_op_movl_T0_Dshiftq),
673 static GenOpFunc1 *gen_op_jnz_ecx[3] = {
676 X86_64_ONLY(gen_op_jnz_ecxq),
679 static GenOpFunc1 *gen_op_jz_ecx[3] = {
682 X86_64_ONLY(gen_op_jz_ecxq),
685 static GenOpFunc *gen_op_dec_ECX[3] = {
688 X86_64_ONLY(gen_op_decq_ECX),
691 static GenOpFunc1 *gen_op_string_jnz_sub[2][4] = {
696 X86_64_ONLY(gen_op_jnz_subq),
702 X86_64_ONLY(gen_op_jz_subq),
706 static void *helper_in_func[3] = {
712 static void *helper_out_func[3] = {
718 static void *gen_check_io_func[3] = {
724 static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip,
728 target_ulong next_eip;
731 if (s->pe && (s->cpl > s->iopl || s->vm86)) {
732 if (s->cc_op != CC_OP_DYNAMIC)
733 gen_op_set_cc_op(s->cc_op);
736 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
737 tcg_gen_helper_0_1(gen_check_io_func[ot],
740 if(s->flags & (1ULL << INTERCEPT_IOIO_PROT)) {
742 if (s->cc_op != CC_OP_DYNAMIC)
743 gen_op_set_cc_op(s->cc_op);
747 svm_flags |= (1 << (4 + ot));
748 next_eip = s->pc - s->cs_base;
749 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
750 tcg_gen_helper_0_3(helper_svm_check_io,
752 tcg_const_i32(svm_flags),
753 tcg_const_i32(next_eip - cur_eip));
757 static inline void gen_movs(DisasContext *s, int ot)
759 gen_string_movl_A0_ESI(s);
760 gen_op_ld_T0_A0(ot + s->mem_index);
761 gen_string_movl_A0_EDI(s);
762 gen_op_st_T0_A0(ot + s->mem_index);
763 gen_op_movl_T0_Dshift[ot]();
766 gen_op_addq_ESI_T0();
767 gen_op_addq_EDI_T0();
771 gen_op_addl_ESI_T0();
772 gen_op_addl_EDI_T0();
774 gen_op_addw_ESI_T0();
775 gen_op_addw_EDI_T0();
779 static inline void gen_update_cc_op(DisasContext *s)
781 if (s->cc_op != CC_OP_DYNAMIC) {
782 gen_op_set_cc_op(s->cc_op);
783 s->cc_op = CC_OP_DYNAMIC;
787 static void gen_op_update1_cc(void)
789 tcg_gen_discard_tl(cpu_cc_src);
790 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
793 static void gen_op_update2_cc(void)
795 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
796 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
799 static inline void gen_op_cmpl_T0_T1_cc(void)
801 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
802 tcg_gen_sub_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);
805 static inline void gen_op_testl_T0_T1_cc(void)
807 tcg_gen_discard_tl(cpu_cc_src);
808 tcg_gen_and_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);
811 static void gen_op_update_neg_cc(void)
813 tcg_gen_neg_tl(cpu_cc_src, cpu_T[0]);
814 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
817 /* XXX: does not work with gdbstub "ice" single step - not a
819 static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip)
823 l1 = gen_new_label();
824 l2 = gen_new_label();
825 gen_op_jnz_ecx[s->aflag](l1);
827 gen_jmp_tb(s, next_eip, 1);
832 static inline void gen_stos(DisasContext *s, int ot)
834 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
835 gen_string_movl_A0_EDI(s);
836 gen_op_st_T0_A0(ot + s->mem_index);
837 gen_op_movl_T0_Dshift[ot]();
840 gen_op_addq_EDI_T0();
844 gen_op_addl_EDI_T0();
846 gen_op_addw_EDI_T0();
850 static inline void gen_lods(DisasContext *s, int ot)
852 gen_string_movl_A0_ESI(s);
853 gen_op_ld_T0_A0(ot + s->mem_index);
854 gen_op_mov_reg_T0(ot, R_EAX);
855 gen_op_movl_T0_Dshift[ot]();
858 gen_op_addq_ESI_T0();
862 gen_op_addl_ESI_T0();
864 gen_op_addw_ESI_T0();
868 static inline void gen_scas(DisasContext *s, int ot)
870 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
871 gen_string_movl_A0_EDI(s);
872 gen_op_ld_T1_A0(ot + s->mem_index);
873 gen_op_cmpl_T0_T1_cc();
874 gen_op_movl_T0_Dshift[ot]();
877 gen_op_addq_EDI_T0();
881 gen_op_addl_EDI_T0();
883 gen_op_addw_EDI_T0();
887 static inline void gen_cmps(DisasContext *s, int ot)
889 gen_string_movl_A0_ESI(s);
890 gen_op_ld_T0_A0(ot + s->mem_index);
891 gen_string_movl_A0_EDI(s);
892 gen_op_ld_T1_A0(ot + s->mem_index);
893 gen_op_cmpl_T0_T1_cc();
894 gen_op_movl_T0_Dshift[ot]();
897 gen_op_addq_ESI_T0();
898 gen_op_addq_EDI_T0();
902 gen_op_addl_ESI_T0();
903 gen_op_addl_EDI_T0();
905 gen_op_addw_ESI_T0();
906 gen_op_addw_EDI_T0();
910 static inline void gen_ins(DisasContext *s, int ot)
912 gen_string_movl_A0_EDI(s);
914 gen_op_st_T0_A0(ot + s->mem_index);
915 gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
916 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
917 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
918 tcg_gen_helper_1_1(helper_in_func[ot], cpu_T[0], cpu_tmp2_i32);
919 gen_op_st_T0_A0(ot + s->mem_index);
920 gen_op_movl_T0_Dshift[ot]();
923 gen_op_addq_EDI_T0();
927 gen_op_addl_EDI_T0();
929 gen_op_addw_EDI_T0();
933 static inline void gen_outs(DisasContext *s, int ot)
935 gen_string_movl_A0_ESI(s);
936 gen_op_ld_T0_A0(ot + s->mem_index);
938 gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
939 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
940 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
941 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[0]);
942 tcg_gen_helper_0_2(helper_out_func[ot], cpu_tmp2_i32, cpu_tmp3_i32);
944 gen_op_movl_T0_Dshift[ot]();
947 gen_op_addq_ESI_T0();
951 gen_op_addl_ESI_T0();
953 gen_op_addw_ESI_T0();
957 /* same method as Valgrind : we generate jumps to current or next
959 #define GEN_REPZ(op) \
960 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
961 target_ulong cur_eip, target_ulong next_eip) \
964 gen_update_cc_op(s); \
965 l2 = gen_jz_ecx_string(s, next_eip); \
967 gen_op_dec_ECX[s->aflag](); \
968 /* a loop would cause two single step exceptions if ECX = 1 \
969 before rep string_insn */ \
971 gen_op_jz_ecx[s->aflag](l2); \
972 gen_jmp(s, cur_eip); \
975 #define GEN_REPZ2(op) \
976 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
977 target_ulong cur_eip, \
978 target_ulong next_eip, \
982 gen_update_cc_op(s); \
983 l2 = gen_jz_ecx_string(s, next_eip); \
985 gen_op_dec_ECX[s->aflag](); \
986 gen_op_set_cc_op(CC_OP_SUBB + ot); \
987 gen_op_string_jnz_sub[nz][ot](l2);\
989 gen_op_jz_ecx[s->aflag](l2); \
990 gen_jmp(s, cur_eip); \
1012 static GenOpFunc1 *gen_jcc_sub[4][8] = {
1043 #ifdef TARGET_X86_64
1046 BUGGY_64(gen_op_jb_subq),
1048 BUGGY_64(gen_op_jbe_subq),
1051 BUGGY_64(gen_op_jl_subq),
1052 BUGGY_64(gen_op_jle_subq),
1056 static GenOpFunc1 *gen_op_loop[3][4] = {
1067 #ifdef TARGET_X86_64
1076 static GenOpFunc *gen_setcc_slow[8] = {
1087 static GenOpFunc *gen_setcc_sub[4][8] = {
1090 gen_op_setb_T0_subb,
1091 gen_op_setz_T0_subb,
1092 gen_op_setbe_T0_subb,
1093 gen_op_sets_T0_subb,
1095 gen_op_setl_T0_subb,
1096 gen_op_setle_T0_subb,
1100 gen_op_setb_T0_subw,
1101 gen_op_setz_T0_subw,
1102 gen_op_setbe_T0_subw,
1103 gen_op_sets_T0_subw,
1105 gen_op_setl_T0_subw,
1106 gen_op_setle_T0_subw,
1110 gen_op_setb_T0_subl,
1111 gen_op_setz_T0_subl,
1112 gen_op_setbe_T0_subl,
1113 gen_op_sets_T0_subl,
1115 gen_op_setl_T0_subl,
1116 gen_op_setle_T0_subl,
1118 #ifdef TARGET_X86_64
1121 gen_op_setb_T0_subq,
1122 gen_op_setz_T0_subq,
1123 gen_op_setbe_T0_subq,
1124 gen_op_sets_T0_subq,
1126 gen_op_setl_T0_subq,
1127 gen_op_setle_T0_subq,
1132 static void *helper_fp_arith_ST0_FT0[8] = {
1133 helper_fadd_ST0_FT0,
1134 helper_fmul_ST0_FT0,
1135 helper_fcom_ST0_FT0,
1136 helper_fcom_ST0_FT0,
1137 helper_fsub_ST0_FT0,
1138 helper_fsubr_ST0_FT0,
1139 helper_fdiv_ST0_FT0,
1140 helper_fdivr_ST0_FT0,
1143 /* NOTE the exception in "r" op ordering */
1144 static void *helper_fp_arith_STN_ST0[8] = {
1145 helper_fadd_STN_ST0,
1146 helper_fmul_STN_ST0,
1149 helper_fsubr_STN_ST0,
1150 helper_fsub_STN_ST0,
1151 helper_fdivr_STN_ST0,
1152 helper_fdiv_STN_ST0,
1155 /* compute eflags.C to reg */
1156 static void gen_compute_eflags_c(TCGv reg)
1158 #if TCG_TARGET_REG_BITS == 32
1159 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_cc_op, 3);
1160 tcg_gen_addi_i32(cpu_tmp2_i32, cpu_tmp2_i32,
1161 (long)cc_table + offsetof(CCTable, compute_c));
1162 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0);
1163 tcg_gen_call(&tcg_ctx, cpu_tmp2_i32, TCG_CALL_PURE,
1164 1, &cpu_tmp2_i32, 0, NULL);
1166 tcg_gen_extu_i32_tl(cpu_tmp1_i64, cpu_cc_op);
1167 tcg_gen_shli_i64(cpu_tmp1_i64, cpu_tmp1_i64, 4);
1168 tcg_gen_addi_i64(cpu_tmp1_i64, cpu_tmp1_i64,
1169 (long)cc_table + offsetof(CCTable, compute_c));
1170 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_tmp1_i64, 0);
1171 tcg_gen_call(&tcg_ctx, cpu_tmp1_i64, TCG_CALL_PURE,
1172 1, &cpu_tmp2_i32, 0, NULL);
1174 tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);
1177 /* compute all eflags to cc_src */
1178 static void gen_compute_eflags(TCGv reg)
1180 #if TCG_TARGET_REG_BITS == 32
1181 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_cc_op, 3);
1182 tcg_gen_addi_i32(cpu_tmp2_i32, cpu_tmp2_i32,
1183 (long)cc_table + offsetof(CCTable, compute_all));
1184 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0);
1185 tcg_gen_call(&tcg_ctx, cpu_tmp2_i32, TCG_CALL_PURE,
1186 1, &cpu_tmp2_i32, 0, NULL);
1188 tcg_gen_extu_i32_tl(cpu_tmp1_i64, cpu_cc_op);
1189 tcg_gen_shli_i64(cpu_tmp1_i64, cpu_tmp1_i64, 4);
1190 tcg_gen_addi_i64(cpu_tmp1_i64, cpu_tmp1_i64,
1191 (long)cc_table + offsetof(CCTable, compute_all));
1192 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_tmp1_i64, 0);
1193 tcg_gen_call(&tcg_ctx, cpu_tmp1_i64, TCG_CALL_PURE,
1194 1, &cpu_tmp2_i32, 0, NULL);
1196 tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);
1199 /* if d == OR_TMP0, it means memory operand (address in A0) */
1200 static void gen_op(DisasContext *s1, int op, int ot, int d)
1203 gen_op_mov_TN_reg(ot, 0, d);
1205 gen_op_ld_T0_A0(ot + s1->mem_index);
1209 if (s1->cc_op != CC_OP_DYNAMIC)
1210 gen_op_set_cc_op(s1->cc_op);
1211 gen_compute_eflags_c(cpu_tmp4);
1212 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1213 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
1215 gen_op_mov_reg_T0(ot, d);
1217 gen_op_st_T0_A0(ot + s1->mem_index);
1218 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
1219 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1220 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4);
1221 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2);
1222 tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_ADDB + ot);
1223 s1->cc_op = CC_OP_DYNAMIC;
1226 if (s1->cc_op != CC_OP_DYNAMIC)
1227 gen_op_set_cc_op(s1->cc_op);
1228 gen_compute_eflags_c(cpu_tmp4);
1229 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1230 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
1232 gen_op_mov_reg_T0(ot, d);
1234 gen_op_st_T0_A0(ot + s1->mem_index);
1235 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
1236 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1237 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4);
1238 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2);
1239 tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_SUBB + ot);
1240 s1->cc_op = CC_OP_DYNAMIC;
1243 gen_op_addl_T0_T1();
1245 gen_op_mov_reg_T0(ot, d);
1247 gen_op_st_T0_A0(ot + s1->mem_index);
1248 gen_op_update2_cc();
1249 s1->cc_op = CC_OP_ADDB + ot;
1252 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1254 gen_op_mov_reg_T0(ot, d);
1256 gen_op_st_T0_A0(ot + s1->mem_index);
1257 gen_op_update2_cc();
1258 s1->cc_op = CC_OP_SUBB + ot;
1262 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1264 gen_op_mov_reg_T0(ot, d);
1266 gen_op_st_T0_A0(ot + s1->mem_index);
1267 gen_op_update1_cc();
1268 s1->cc_op = CC_OP_LOGICB + ot;
1271 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1273 gen_op_mov_reg_T0(ot, d);
1275 gen_op_st_T0_A0(ot + s1->mem_index);
1276 gen_op_update1_cc();
1277 s1->cc_op = CC_OP_LOGICB + ot;
1280 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1282 gen_op_mov_reg_T0(ot, d);
1284 gen_op_st_T0_A0(ot + s1->mem_index);
1285 gen_op_update1_cc();
1286 s1->cc_op = CC_OP_LOGICB + ot;
1289 gen_op_cmpl_T0_T1_cc();
1290 s1->cc_op = CC_OP_SUBB + ot;
1295 /* if d == OR_TMP0, it means memory operand (address in A0) */
1296 static void gen_inc(DisasContext *s1, int ot, int d, int c)
1299 gen_op_mov_TN_reg(ot, 0, d);
1301 gen_op_ld_T0_A0(ot + s1->mem_index);
1302 if (s1->cc_op != CC_OP_DYNAMIC)
1303 gen_op_set_cc_op(s1->cc_op);
1305 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 1);
1306 s1->cc_op = CC_OP_INCB + ot;
1308 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], -1);
1309 s1->cc_op = CC_OP_DECB + ot;
1312 gen_op_mov_reg_T0(ot, d);
1314 gen_op_st_T0_A0(ot + s1->mem_index);
1315 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1316 gen_compute_eflags_c(cpu_cc_src);
1319 static void gen_extu(int ot, TCGv reg)
1323 tcg_gen_ext8u_tl(reg, reg);
1326 tcg_gen_ext16u_tl(reg, reg);
1329 tcg_gen_ext32u_tl(reg, reg);
1336 static void gen_exts(int ot, TCGv reg)
1340 tcg_gen_ext8s_tl(reg, reg);
1343 tcg_gen_ext16s_tl(reg, reg);
1346 tcg_gen_ext32s_tl(reg, reg);
1353 /* XXX: add faster immediate case */
1354 static void gen_shift_rm_T1(DisasContext *s, int ot, int op1,
1355 int is_right, int is_arith)
1367 gen_op_ld_T0_A0(ot + s->mem_index);
1369 gen_op_mov_TN_reg(ot, 0, op1);
1371 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], mask);
1373 tcg_gen_addi_tl(cpu_tmp5, cpu_T[1], -1);
1377 gen_exts(ot, cpu_T[0]);
1378 tcg_gen_sar_tl(cpu_T3, cpu_T[0], cpu_tmp5);
1379 tcg_gen_sar_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1381 gen_extu(ot, cpu_T[0]);
1382 tcg_gen_shr_tl(cpu_T3, cpu_T[0], cpu_tmp5);
1383 tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1386 tcg_gen_shl_tl(cpu_T3, cpu_T[0], cpu_tmp5);
1387 tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1392 gen_op_st_T0_A0(ot + s->mem_index);
1394 gen_op_mov_reg_T0(ot, op1);
1396 /* update eflags if non zero shift */
1397 if (s->cc_op != CC_OP_DYNAMIC)
1398 gen_op_set_cc_op(s->cc_op);
1400 shift_label = gen_new_label();
1401 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T[1], tcg_const_tl(0), shift_label);
1403 tcg_gen_mov_tl(cpu_cc_src, cpu_T3);
1404 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1406 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot);
1408 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot);
1410 gen_set_label(shift_label);
1411 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1414 static inline void tcg_gen_lshift(TCGv ret, TCGv arg1, target_long arg2)
1417 tcg_gen_shli_tl(ret, arg1, arg2);
1419 tcg_gen_shri_tl(ret, arg1, -arg2);
1422 /* XXX: add faster immediate case */
1423 static void gen_rot_rm_T1(DisasContext *s, int ot, int op1,
1427 int label1, label2, data_bits;
1436 gen_op_ld_T0_A0(ot + s->mem_index);
1438 gen_op_mov_TN_reg(ot, 0, op1);
1440 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], mask);
1442 /* Must test zero case to avoid using undefined behaviour in TCG
1444 label1 = gen_new_label();
1445 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T[1], tcg_const_tl(0), label1);
1448 tcg_gen_andi_tl(cpu_tmp0, cpu_T[1], (1 << (3 + ot)) - 1);
1450 tcg_gen_mov_tl(cpu_tmp0, cpu_T[1]);
1452 gen_extu(ot, cpu_T[0]);
1453 tcg_gen_mov_tl(cpu_T3, cpu_T[0]);
1455 data_bits = 8 << ot;
1456 /* XXX: rely on behaviour of shifts when operand 2 overflows (XXX:
1457 fix TCG definition) */
1459 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_tmp0);
1460 tcg_gen_sub_tl(cpu_tmp0, tcg_const_tl(data_bits), cpu_tmp0);
1461 tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
1463 tcg_gen_shl_tl(cpu_tmp4, cpu_T[0], cpu_tmp0);
1464 tcg_gen_sub_tl(cpu_tmp0, tcg_const_tl(data_bits), cpu_tmp0);
1465 tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
1467 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
1469 gen_set_label(label1);
1472 gen_op_st_T0_A0(ot + s->mem_index);
1474 gen_op_mov_reg_T0(ot, op1);
1477 if (s->cc_op != CC_OP_DYNAMIC)
1478 gen_op_set_cc_op(s->cc_op);
1480 label2 = gen_new_label();
1481 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T[1], tcg_const_tl(0), label2);
1483 gen_compute_eflags(cpu_cc_src);
1484 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C));
1485 tcg_gen_xor_tl(cpu_tmp0, cpu_T3, cpu_T[0]);
1486 tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1));
1487 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O);
1488 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
1490 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], data_bits - 1);
1492 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], CC_C);
1493 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_T[0]);
1495 tcg_gen_discard_tl(cpu_cc_dst);
1496 tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1498 gen_set_label(label2);
1499 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1502 static void *helper_rotc[8] = {
1506 X86_64_ONLY(helper_rclq),
1510 X86_64_ONLY(helper_rcrq),
1513 /* XXX: add faster immediate = 1 case */
1514 static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1,
1519 if (s->cc_op != CC_OP_DYNAMIC)
1520 gen_op_set_cc_op(s->cc_op);
1524 gen_op_ld_T0_A0(ot + s->mem_index);
1526 gen_op_mov_TN_reg(ot, 0, op1);
1528 tcg_gen_helper_1_2(helper_rotc[ot + (is_right * 4)],
1529 cpu_T[0], cpu_T[0], cpu_T[1]);
1532 gen_op_st_T0_A0(ot + s->mem_index);
1534 gen_op_mov_reg_T0(ot, op1);
1537 label1 = gen_new_label();
1538 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T3, tcg_const_tl(-1), label1);
1540 tcg_gen_mov_tl(cpu_cc_src, cpu_T3);
1541 tcg_gen_discard_tl(cpu_cc_dst);
1542 tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1544 gen_set_label(label1);
1545 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1548 /* XXX: add faster immediate case */
1549 static void gen_shiftd_rm_T1_T3(DisasContext *s, int ot, int op1,
1552 int label1, label2, data_bits;
1562 gen_op_ld_T0_A0(ot + s->mem_index);
1564 gen_op_mov_TN_reg(ot, 0, op1);
1566 tcg_gen_andi_tl(cpu_T3, cpu_T3, mask);
1567 /* Must test zero case to avoid using undefined behaviour in TCG
1569 label1 = gen_new_label();
1570 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T3, tcg_const_tl(0), label1);
1572 tcg_gen_addi_tl(cpu_tmp5, cpu_T3, -1);
1573 if (ot == OT_WORD) {
1574 /* Note: we implement the Intel behaviour for shift count > 16 */
1576 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
1577 tcg_gen_shli_tl(cpu_tmp0, cpu_T[1], 16);
1578 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
1579 tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
1581 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_tmp5);
1583 /* only needed if count > 16, but a test would complicate */
1584 tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(32), cpu_T3);
1585 tcg_gen_shl_tl(cpu_tmp0, cpu_T[0], cpu_tmp5);
1587 tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T3);
1589 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
1591 /* XXX: not optimal */
1592 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
1593 tcg_gen_shli_tl(cpu_T[1], cpu_T[1], 16);
1594 tcg_gen_or_tl(cpu_T[1], cpu_T[1], cpu_T[0]);
1595 tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]);
1597 tcg_gen_shl_tl(cpu_tmp4, cpu_T[0], cpu_tmp5);
1598 tcg_gen_sub_tl(cpu_tmp0, tcg_const_tl(32), cpu_tmp5);
1599 tcg_gen_shr_tl(cpu_tmp6, cpu_T[1], cpu_tmp0);
1600 tcg_gen_or_tl(cpu_tmp4, cpu_tmp4, cpu_tmp6);
1602 tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T3);
1603 tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(32), cpu_T3);
1604 tcg_gen_shr_tl(cpu_T[1], cpu_T[1], cpu_tmp5);
1605 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1608 data_bits = 8 << ot;
1611 tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
1613 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_tmp5);
1615 tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T3);
1616 tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(data_bits), cpu_T3);
1617 tcg_gen_shl_tl(cpu_T[1], cpu_T[1], cpu_tmp5);
1618 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1622 tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]);
1624 tcg_gen_shl_tl(cpu_tmp4, cpu_T[0], cpu_tmp5);
1626 tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T3);
1627 tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(data_bits), cpu_T3);
1628 tcg_gen_shr_tl(cpu_T[1], cpu_T[1], cpu_tmp5);
1629 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1632 tcg_gen_mov_tl(cpu_T[1], cpu_tmp4);
1634 gen_set_label(label1);
1637 gen_op_st_T0_A0(ot + s->mem_index);
1639 gen_op_mov_reg_T0(ot, op1);
1642 if (s->cc_op != CC_OP_DYNAMIC)
1643 gen_op_set_cc_op(s->cc_op);
1645 label2 = gen_new_label();
1646 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T3, tcg_const_tl(0), label2);
1648 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
1649 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1651 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot);
1653 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot);
1655 gen_set_label(label2);
1656 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1659 static void gen_shift(DisasContext *s1, int op, int ot, int d, int s)
1662 gen_op_mov_TN_reg(ot, 1, s);
1665 gen_rot_rm_T1(s1, ot, d, 0);
1668 gen_rot_rm_T1(s1, ot, d, 1);
1672 gen_shift_rm_T1(s1, ot, d, 0, 0);
1675 gen_shift_rm_T1(s1, ot, d, 1, 0);
1678 gen_shift_rm_T1(s1, ot, d, 1, 1);
1681 gen_rotc_rm_T1(s1, ot, d, 0);
1684 gen_rotc_rm_T1(s1, ot, d, 1);
1689 static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c)
1691 /* currently not optimized */
1692 gen_op_movl_T1_im(c);
1693 gen_shift(s1, op, ot, d, OR_TMP1);
1696 static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ptr)
1704 int mod, rm, code, override, must_add_seg;
1706 override = s->override;
1707 must_add_seg = s->addseg;
1710 mod = (modrm >> 6) & 3;
1722 code = ldub_code(s->pc++);
1723 scale = (code >> 6) & 3;
1724 index = ((code >> 3) & 7) | REX_X(s);
1731 if ((base & 7) == 5) {
1733 disp = (int32_t)ldl_code(s->pc);
1735 if (CODE64(s) && !havesib) {
1736 disp += s->pc + s->rip_offset;
1743 disp = (int8_t)ldub_code(s->pc++);
1747 disp = ldl_code(s->pc);
1753 /* for correct popl handling with esp */
1754 if (base == 4 && s->popl_esp_hack)
1755 disp += s->popl_esp_hack;
1756 #ifdef TARGET_X86_64
1757 if (s->aflag == 2) {
1758 gen_op_movq_A0_reg(base);
1760 gen_op_addq_A0_im(disp);
1765 gen_op_movl_A0_reg(base);
1767 gen_op_addl_A0_im(disp);
1770 #ifdef TARGET_X86_64
1771 if (s->aflag == 2) {
1772 gen_op_movq_A0_im(disp);
1776 gen_op_movl_A0_im(disp);
1779 /* XXX: index == 4 is always invalid */
1780 if (havesib && (index != 4 || scale != 0)) {
1781 #ifdef TARGET_X86_64
1782 if (s->aflag == 2) {
1783 gen_op_addq_A0_reg_sN(scale, index);
1787 gen_op_addl_A0_reg_sN(scale, index);
1792 if (base == R_EBP || base == R_ESP)
1797 #ifdef TARGET_X86_64
1798 if (s->aflag == 2) {
1799 gen_op_addq_A0_seg(override);
1803 gen_op_addl_A0_seg(override);
1810 disp = lduw_code(s->pc);
1812 gen_op_movl_A0_im(disp);
1813 rm = 0; /* avoid SS override */
1820 disp = (int8_t)ldub_code(s->pc++);
1824 disp = lduw_code(s->pc);
1830 gen_op_movl_A0_reg(R_EBX);
1831 gen_op_addl_A0_reg_sN(0, R_ESI);
1834 gen_op_movl_A0_reg(R_EBX);
1835 gen_op_addl_A0_reg_sN(0, R_EDI);
1838 gen_op_movl_A0_reg(R_EBP);
1839 gen_op_addl_A0_reg_sN(0, R_ESI);
1842 gen_op_movl_A0_reg(R_EBP);
1843 gen_op_addl_A0_reg_sN(0, R_EDI);
1846 gen_op_movl_A0_reg(R_ESI);
1849 gen_op_movl_A0_reg(R_EDI);
1852 gen_op_movl_A0_reg(R_EBP);
1856 gen_op_movl_A0_reg(R_EBX);
1860 gen_op_addl_A0_im(disp);
1861 gen_op_andl_A0_ffff();
1865 if (rm == 2 || rm == 3 || rm == 6)
1870 gen_op_addl_A0_seg(override);
1880 static void gen_nop_modrm(DisasContext *s, int modrm)
1882 int mod, rm, base, code;
1884 mod = (modrm >> 6) & 3;
1894 code = ldub_code(s->pc++);
1930 /* used for LEA and MOV AX, mem */
1931 static void gen_add_A0_ds_seg(DisasContext *s)
1933 int override, must_add_seg;
1934 must_add_seg = s->addseg;
1936 if (s->override >= 0) {
1937 override = s->override;
1943 #ifdef TARGET_X86_64
1945 gen_op_addq_A0_seg(override);
1949 gen_op_addl_A0_seg(override);
1954 /* generate modrm memory load or store of 'reg'. TMP0 is used if reg !=
1956 static void gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_store)
1958 int mod, rm, opreg, disp;
1960 mod = (modrm >> 6) & 3;
1961 rm = (modrm & 7) | REX_B(s);
1965 gen_op_mov_TN_reg(ot, 0, reg);
1966 gen_op_mov_reg_T0(ot, rm);
1968 gen_op_mov_TN_reg(ot, 0, rm);
1970 gen_op_mov_reg_T0(ot, reg);
1973 gen_lea_modrm(s, modrm, &opreg, &disp);
1976 gen_op_mov_TN_reg(ot, 0, reg);
1977 gen_op_st_T0_A0(ot + s->mem_index);
1979 gen_op_ld_T0_A0(ot + s->mem_index);
1981 gen_op_mov_reg_T0(ot, reg);
1986 static inline uint32_t insn_get(DisasContext *s, int ot)
1992 ret = ldub_code(s->pc);
1996 ret = lduw_code(s->pc);
2001 ret = ldl_code(s->pc);
2008 static inline int insn_const_size(unsigned int ot)
2016 static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong eip)
2018 TranslationBlock *tb;
2021 pc = s->cs_base + eip;
2023 /* NOTE: we handle the case where the TB spans two pages here */
2024 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) ||
2025 (pc & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK)) {
2026 /* jump to same page: we can use a direct jump */
2027 tcg_gen_goto_tb(tb_num);
2029 tcg_gen_exit_tb((long)tb + tb_num);
2031 /* jump to another page: currently not optimized */
2037 static inline void gen_jcc(DisasContext *s, int b,
2038 target_ulong val, target_ulong next_eip)
2040 TranslationBlock *tb;
2047 jcc_op = (b >> 1) & 7;
2051 /* we optimize the cmp/jcc case */
2056 func = gen_jcc_sub[s->cc_op - CC_OP_SUBB][jcc_op];
2059 /* some jumps are easy to compute */
2101 func = gen_jcc_sub[(s->cc_op - CC_OP_ADDB) % 4][jcc_op];
2104 func = gen_jcc_sub[(s->cc_op - CC_OP_ADDB) % 4][jcc_op];
2116 if (s->cc_op != CC_OP_DYNAMIC) {
2117 gen_op_set_cc_op(s->cc_op);
2118 s->cc_op = CC_OP_DYNAMIC;
2122 gen_setcc_slow[jcc_op]();
2123 func = gen_op_jnz_T0_label;
2133 l1 = gen_new_label();
2136 gen_goto_tb(s, 0, next_eip);
2139 gen_goto_tb(s, 1, val);
2144 if (s->cc_op != CC_OP_DYNAMIC) {
2145 gen_op_set_cc_op(s->cc_op);
2146 s->cc_op = CC_OP_DYNAMIC;
2148 gen_setcc_slow[jcc_op]();
2154 l1 = gen_new_label();
2155 l2 = gen_new_label();
2156 gen_op_jnz_T0_label(l1);
2157 gen_jmp_im(next_eip);
2158 gen_op_jmp_label(l2);
2166 static void gen_setcc(DisasContext *s, int b)
2172 jcc_op = (b >> 1) & 7;
2174 /* we optimize the cmp/jcc case */
2179 func = gen_setcc_sub[s->cc_op - CC_OP_SUBB][jcc_op];
2184 /* some jumps are easy to compute */
2211 func = gen_setcc_sub[(s->cc_op - CC_OP_ADDB) % 4][jcc_op];
2214 func = gen_setcc_sub[(s->cc_op - CC_OP_ADDB) % 4][jcc_op];
2222 if (s->cc_op != CC_OP_DYNAMIC)
2223 gen_op_set_cc_op(s->cc_op);
2224 func = gen_setcc_slow[jcc_op];
2233 /* move T0 to seg_reg and compute if the CPU state may change. Never
2234 call this function with seg_reg == R_CS */
2235 static void gen_movl_seg_T0(DisasContext *s, int seg_reg, target_ulong cur_eip)
2237 if (s->pe && !s->vm86) {
2238 /* XXX: optimize by finding processor state dynamically */
2239 if (s->cc_op != CC_OP_DYNAMIC)
2240 gen_op_set_cc_op(s->cc_op);
2241 gen_jmp_im(cur_eip);
2242 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
2243 tcg_gen_helper_0_2(helper_load_seg, tcg_const_i32(seg_reg), cpu_tmp2_i32);
2244 /* abort translation because the addseg value may change or
2245 because ss32 may change. For R_SS, translation must always
2246 stop as a special handling must be done to disable hardware
2247 interrupts for the next instruction */
2248 if (seg_reg == R_SS || (s->code32 && seg_reg < R_FS))
2251 gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[seg_reg]));
2252 if (seg_reg == R_SS)
2257 static inline int svm_is_rep(int prefixes)
2259 return ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) ? 8 : 0);
2263 gen_svm_check_intercept_param(DisasContext *s, target_ulong pc_start,
2264 uint32_t type, uint64_t param)
2266 if(!(s->flags & (INTERCEPT_SVM_MASK)))
2267 /* no SVM activated */
2270 /* CRx and DRx reads/writes */
2271 case SVM_EXIT_READ_CR0 ... SVM_EXIT_EXCP_BASE - 1:
2272 if (s->cc_op != CC_OP_DYNAMIC) {
2273 gen_op_set_cc_op(s->cc_op);
2275 gen_jmp_im(pc_start - s->cs_base);
2276 tcg_gen_helper_0_2(helper_svm_check_intercept_param,
2277 tcg_const_i32(type), tcg_const_i64(param));
2278 /* this is a special case as we do not know if the interception occurs
2279 so we assume there was none */
2282 if(s->flags & (1ULL << INTERCEPT_MSR_PROT)) {
2283 if (s->cc_op != CC_OP_DYNAMIC) {
2284 gen_op_set_cc_op(s->cc_op);
2286 gen_jmp_im(pc_start - s->cs_base);
2287 tcg_gen_helper_0_2(helper_svm_check_intercept_param,
2288 tcg_const_i32(type), tcg_const_i64(param));
2289 /* this is a special case as we do not know if the interception occurs
2290 so we assume there was none */
2295 if(s->flags & (1ULL << ((type - SVM_EXIT_INTR) + INTERCEPT_INTR))) {
2296 if (s->cc_op != CC_OP_DYNAMIC) {
2297 gen_op_set_cc_op(s->cc_op);
2299 gen_jmp_im(pc_start - s->cs_base);
2300 tcg_gen_helper_0_2(helper_vmexit,
2301 tcg_const_i32(type), tcg_const_i64(param));
2302 /* we can optimize this one so TBs don't get longer
2303 than up to vmexit */
2312 gen_svm_check_intercept(DisasContext *s, target_ulong pc_start, uint64_t type)
2314 return gen_svm_check_intercept_param(s, pc_start, type, 0);
2317 static inline void gen_stack_update(DisasContext *s, int addend)
2319 #ifdef TARGET_X86_64
2321 gen_op_addq_ESP_im(addend);
2325 gen_op_addl_ESP_im(addend);
2327 gen_op_addw_ESP_im(addend);
2331 /* generate a push. It depends on ss32, addseg and dflag */
2332 static void gen_push_T0(DisasContext *s)
2334 #ifdef TARGET_X86_64
2336 gen_op_movq_A0_reg(R_ESP);
2338 gen_op_addq_A0_im(-8);
2339 gen_op_st_T0_A0(OT_QUAD + s->mem_index);
2341 gen_op_addq_A0_im(-2);
2342 gen_op_st_T0_A0(OT_WORD + s->mem_index);
2344 gen_op_mov_reg_A0(2, R_ESP);
2348 gen_op_movl_A0_reg(R_ESP);
2350 gen_op_addl_A0_im(-2);
2352 gen_op_addl_A0_im(-4);
2355 gen_op_movl_T1_A0();
2356 gen_op_addl_A0_seg(R_SS);
2359 gen_op_andl_A0_ffff();
2360 gen_op_movl_T1_A0();
2361 gen_op_addl_A0_seg(R_SS);
2363 gen_op_st_T0_A0(s->dflag + 1 + s->mem_index);
2364 if (s->ss32 && !s->addseg)
2365 gen_op_mov_reg_A0(1, R_ESP);
2367 gen_op_mov_reg_T1(s->ss32 + 1, R_ESP);
2371 /* generate a push. It depends on ss32, addseg and dflag */
2372 /* slower version for T1, only used for call Ev */
2373 static void gen_push_T1(DisasContext *s)
2375 #ifdef TARGET_X86_64
2377 gen_op_movq_A0_reg(R_ESP);
2379 gen_op_addq_A0_im(-8);
2380 gen_op_st_T1_A0(OT_QUAD + s->mem_index);
2382 gen_op_addq_A0_im(-2);
2383 gen_op_st_T0_A0(OT_WORD + s->mem_index);
2385 gen_op_mov_reg_A0(2, R_ESP);
2389 gen_op_movl_A0_reg(R_ESP);
2391 gen_op_addl_A0_im(-2);
2393 gen_op_addl_A0_im(-4);
2396 gen_op_addl_A0_seg(R_SS);
2399 gen_op_andl_A0_ffff();
2400 gen_op_addl_A0_seg(R_SS);
2402 gen_op_st_T1_A0(s->dflag + 1 + s->mem_index);
2404 if (s->ss32 && !s->addseg)
2405 gen_op_mov_reg_A0(1, R_ESP);
2407 gen_stack_update(s, (-2) << s->dflag);
2411 /* two step pop is necessary for precise exceptions */
2412 static void gen_pop_T0(DisasContext *s)
2414 #ifdef TARGET_X86_64
2416 gen_op_movq_A0_reg(R_ESP);
2417 gen_op_ld_T0_A0((s->dflag ? OT_QUAD : OT_WORD) + s->mem_index);
2421 gen_op_movl_A0_reg(R_ESP);
2424 gen_op_addl_A0_seg(R_SS);
2426 gen_op_andl_A0_ffff();
2427 gen_op_addl_A0_seg(R_SS);
2429 gen_op_ld_T0_A0(s->dflag + 1 + s->mem_index);
2433 static void gen_pop_update(DisasContext *s)
2435 #ifdef TARGET_X86_64
2436 if (CODE64(s) && s->dflag) {
2437 gen_stack_update(s, 8);
2441 gen_stack_update(s, 2 << s->dflag);
2445 static void gen_stack_A0(DisasContext *s)
2447 gen_op_movl_A0_reg(R_ESP);
2449 gen_op_andl_A0_ffff();
2450 gen_op_movl_T1_A0();
2452 gen_op_addl_A0_seg(R_SS);
2455 /* NOTE: wrap around in 16 bit not fully handled */
2456 static void gen_pusha(DisasContext *s)
2459 gen_op_movl_A0_reg(R_ESP);
2460 gen_op_addl_A0_im(-16 << s->dflag);
2462 gen_op_andl_A0_ffff();
2463 gen_op_movl_T1_A0();
2465 gen_op_addl_A0_seg(R_SS);
2466 for(i = 0;i < 8; i++) {
2467 gen_op_mov_TN_reg(OT_LONG, 0, 7 - i);
2468 gen_op_st_T0_A0(OT_WORD + s->dflag + s->mem_index);
2469 gen_op_addl_A0_im(2 << s->dflag);
2471 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2474 /* NOTE: wrap around in 16 bit not fully handled */
2475 static void gen_popa(DisasContext *s)
2478 gen_op_movl_A0_reg(R_ESP);
2480 gen_op_andl_A0_ffff();
2481 gen_op_movl_T1_A0();
2482 gen_op_addl_T1_im(16 << s->dflag);
2484 gen_op_addl_A0_seg(R_SS);
2485 for(i = 0;i < 8; i++) {
2486 /* ESP is not reloaded */
2488 gen_op_ld_T0_A0(OT_WORD + s->dflag + s->mem_index);
2489 gen_op_mov_reg_T0(OT_WORD + s->dflag, 7 - i);
2491 gen_op_addl_A0_im(2 << s->dflag);
2493 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2496 static void gen_enter(DisasContext *s, int esp_addend, int level)
2501 #ifdef TARGET_X86_64
2503 ot = s->dflag ? OT_QUAD : OT_WORD;
2506 gen_op_movl_A0_reg(R_ESP);
2507 gen_op_addq_A0_im(-opsize);
2508 gen_op_movl_T1_A0();
2511 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
2512 gen_op_st_T0_A0(ot + s->mem_index);
2514 /* XXX: must save state */
2515 tcg_gen_helper_0_3(helper_enter64_level,
2516 tcg_const_i32(level),
2517 tcg_const_i32((ot == OT_QUAD)),
2520 gen_op_mov_reg_T1(ot, R_EBP);
2521 gen_op_addl_T1_im( -esp_addend + (-opsize * level) );
2522 gen_op_mov_reg_T1(OT_QUAD, R_ESP);
2526 ot = s->dflag + OT_WORD;
2527 opsize = 2 << s->dflag;
2529 gen_op_movl_A0_reg(R_ESP);
2530 gen_op_addl_A0_im(-opsize);
2532 gen_op_andl_A0_ffff();
2533 gen_op_movl_T1_A0();
2535 gen_op_addl_A0_seg(R_SS);
2537 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
2538 gen_op_st_T0_A0(ot + s->mem_index);
2540 /* XXX: must save state */
2541 tcg_gen_helper_0_3(helper_enter_level,
2542 tcg_const_i32(level),
2543 tcg_const_i32(s->dflag),
2546 gen_op_mov_reg_T1(ot, R_EBP);
2547 gen_op_addl_T1_im( -esp_addend + (-opsize * level) );
2548 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2552 static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip)
2554 if (s->cc_op != CC_OP_DYNAMIC)
2555 gen_op_set_cc_op(s->cc_op);
2556 gen_jmp_im(cur_eip);
2557 tcg_gen_helper_0_1(helper_raise_exception, tcg_const_i32(trapno));
2561 /* an interrupt is different from an exception because of the
2563 static void gen_interrupt(DisasContext *s, int intno,
2564 target_ulong cur_eip, target_ulong next_eip)
2566 if (s->cc_op != CC_OP_DYNAMIC)
2567 gen_op_set_cc_op(s->cc_op);
2568 gen_jmp_im(cur_eip);
2569 tcg_gen_helper_0_2(helper_raise_interrupt,
2570 tcg_const_i32(intno),
2571 tcg_const_i32(next_eip - cur_eip));
2575 static void gen_debug(DisasContext *s, target_ulong cur_eip)
2577 if (s->cc_op != CC_OP_DYNAMIC)
2578 gen_op_set_cc_op(s->cc_op);
2579 gen_jmp_im(cur_eip);
2580 tcg_gen_helper_0_0(helper_debug);
2584 /* generate a generic end of block. Trace exception is also generated
2586 static void gen_eob(DisasContext *s)
2588 if (s->cc_op != CC_OP_DYNAMIC)
2589 gen_op_set_cc_op(s->cc_op);
2590 if (s->tb->flags & HF_INHIBIT_IRQ_MASK) {
2591 tcg_gen_helper_0_0(helper_reset_inhibit_irq);
2593 if (s->singlestep_enabled) {
2594 tcg_gen_helper_0_0(helper_debug);
2596 tcg_gen_helper_0_0(helper_single_step);
2603 /* generate a jump to eip. No segment change must happen before as a
2604 direct call to the next block may occur */
2605 static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num)
2608 if (s->cc_op != CC_OP_DYNAMIC) {
2609 gen_op_set_cc_op(s->cc_op);
2610 s->cc_op = CC_OP_DYNAMIC;
2612 gen_goto_tb(s, tb_num, eip);
2620 static void gen_jmp(DisasContext *s, target_ulong eip)
2622 gen_jmp_tb(s, eip, 0);
2625 static inline void gen_ldq_env_A0(int idx, int offset)
2627 int mem_index = (idx >> 2) - 1;
2628 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
2629 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset);
2632 static inline void gen_stq_env_A0(int idx, int offset)
2634 int mem_index = (idx >> 2) - 1;
2635 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset);
2636 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
2639 static inline void gen_ldo_env_A0(int idx, int offset)
2641 int mem_index = (idx >> 2) - 1;
2642 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
2643 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
2644 tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
2645 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_tmp0, mem_index);
2646 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
2649 static inline void gen_sto_env_A0(int idx, int offset)
2651 int mem_index = (idx >> 2) - 1;
2652 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
2653 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
2654 tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
2655 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
2656 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_tmp0, mem_index);
2659 static inline void gen_op_movo(int d_offset, int s_offset)
2661 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
2662 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2663 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset + 8);
2664 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset + 8);
2667 static inline void gen_op_movq(int d_offset, int s_offset)
2669 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
2670 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2673 static inline void gen_op_movl(int d_offset, int s_offset)
2675 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, s_offset);
2676 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, d_offset);
2679 static inline void gen_op_movq_env_0(int d_offset)
2681 tcg_gen_movi_i64(cpu_tmp1_i64, 0);
2682 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2685 #define SSE_SPECIAL ((void *)1)
2686 #define SSE_DUMMY ((void *)2)
2688 #define MMX_OP2(x) { helper_ ## x ## _mmx, helper_ ## x ## _xmm }
2689 #define SSE_FOP(x) { helper_ ## x ## ps, helper_ ## x ## pd, \
2690 helper_ ## x ## ss, helper_ ## x ## sd, }
2692 static void *sse_op_table1[256][4] = {
2693 /* 3DNow! extensions */
2694 [0x0e] = { SSE_DUMMY }, /* femms */
2695 [0x0f] = { SSE_DUMMY }, /* pf... */
2696 /* pure SSE operations */
2697 [0x10] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
2698 [0x11] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
2699 [0x12] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd, movsldup, movddup */
2700 [0x13] = { SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd */
2701 [0x14] = { helper_punpckldq_xmm, helper_punpcklqdq_xmm },
2702 [0x15] = { helper_punpckhdq_xmm, helper_punpckhqdq_xmm },
2703 [0x16] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd, movshdup */
2704 [0x17] = { SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd */
2706 [0x28] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */
2707 [0x29] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */
2708 [0x2a] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */
2709 [0x2b] = { SSE_SPECIAL, SSE_SPECIAL }, /* movntps, movntpd */
2710 [0x2c] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */
2711 [0x2d] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */
2712 [0x2e] = { helper_ucomiss, helper_ucomisd },
2713 [0x2f] = { helper_comiss, helper_comisd },
2714 [0x50] = { SSE_SPECIAL, SSE_SPECIAL }, /* movmskps, movmskpd */
2715 [0x51] = SSE_FOP(sqrt),
2716 [0x52] = { helper_rsqrtps, NULL, helper_rsqrtss, NULL },
2717 [0x53] = { helper_rcpps, NULL, helper_rcpss, NULL },
2718 [0x54] = { helper_pand_xmm, helper_pand_xmm }, /* andps, andpd */
2719 [0x55] = { helper_pandn_xmm, helper_pandn_xmm }, /* andnps, andnpd */
2720 [0x56] = { helper_por_xmm, helper_por_xmm }, /* orps, orpd */
2721 [0x57] = { helper_pxor_xmm, helper_pxor_xmm }, /* xorps, xorpd */
2722 [0x58] = SSE_FOP(add),
2723 [0x59] = SSE_FOP(mul),
2724 [0x5a] = { helper_cvtps2pd, helper_cvtpd2ps,
2725 helper_cvtss2sd, helper_cvtsd2ss },
2726 [0x5b] = { helper_cvtdq2ps, helper_cvtps2dq, helper_cvttps2dq },
2727 [0x5c] = SSE_FOP(sub),
2728 [0x5d] = SSE_FOP(min),
2729 [0x5e] = SSE_FOP(div),
2730 [0x5f] = SSE_FOP(max),
2732 [0xc2] = SSE_FOP(cmpeq),
2733 [0xc6] = { helper_shufps, helper_shufpd },
2735 /* MMX ops and their SSE extensions */
2736 [0x60] = MMX_OP2(punpcklbw),
2737 [0x61] = MMX_OP2(punpcklwd),
2738 [0x62] = MMX_OP2(punpckldq),
2739 [0x63] = MMX_OP2(packsswb),
2740 [0x64] = MMX_OP2(pcmpgtb),
2741 [0x65] = MMX_OP2(pcmpgtw),
2742 [0x66] = MMX_OP2(pcmpgtl),
2743 [0x67] = MMX_OP2(packuswb),
2744 [0x68] = MMX_OP2(punpckhbw),
2745 [0x69] = MMX_OP2(punpckhwd),
2746 [0x6a] = MMX_OP2(punpckhdq),
2747 [0x6b] = MMX_OP2(packssdw),
2748 [0x6c] = { NULL, helper_punpcklqdq_xmm },
2749 [0x6d] = { NULL, helper_punpckhqdq_xmm },
2750 [0x6e] = { SSE_SPECIAL, SSE_SPECIAL }, /* movd mm, ea */
2751 [0x6f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, , movqdu */
2752 [0x70] = { helper_pshufw_mmx,
2755 helper_pshuflw_xmm },
2756 [0x71] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftw */
2757 [0x72] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftd */
2758 [0x73] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftq */
2759 [0x74] = MMX_OP2(pcmpeqb),
2760 [0x75] = MMX_OP2(pcmpeqw),
2761 [0x76] = MMX_OP2(pcmpeql),
2762 [0x77] = { SSE_DUMMY }, /* emms */
2763 [0x7c] = { NULL, helper_haddpd, NULL, helper_haddps },
2764 [0x7d] = { NULL, helper_hsubpd, NULL, helper_hsubps },
2765 [0x7e] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movd, movd, , movq */
2766 [0x7f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, movdqu */
2767 [0xc4] = { SSE_SPECIAL, SSE_SPECIAL }, /* pinsrw */
2768 [0xc5] = { SSE_SPECIAL, SSE_SPECIAL }, /* pextrw */
2769 [0xd0] = { NULL, helper_addsubpd, NULL, helper_addsubps },
2770 [0xd1] = MMX_OP2(psrlw),
2771 [0xd2] = MMX_OP2(psrld),
2772 [0xd3] = MMX_OP2(psrlq),
2773 [0xd4] = MMX_OP2(paddq),
2774 [0xd5] = MMX_OP2(pmullw),
2775 [0xd6] = { NULL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL },
2776 [0xd7] = { SSE_SPECIAL, SSE_SPECIAL }, /* pmovmskb */
2777 [0xd8] = MMX_OP2(psubusb),
2778 [0xd9] = MMX_OP2(psubusw),
2779 [0xda] = MMX_OP2(pminub),
2780 [0xdb] = MMX_OP2(pand),
2781 [0xdc] = MMX_OP2(paddusb),
2782 [0xdd] = MMX_OP2(paddusw),
2783 [0xde] = MMX_OP2(pmaxub),
2784 [0xdf] = MMX_OP2(pandn),
2785 [0xe0] = MMX_OP2(pavgb),
2786 [0xe1] = MMX_OP2(psraw),
2787 [0xe2] = MMX_OP2(psrad),
2788 [0xe3] = MMX_OP2(pavgw),
2789 [0xe4] = MMX_OP2(pmulhuw),
2790 [0xe5] = MMX_OP2(pmulhw),
2791 [0xe6] = { NULL, helper_cvttpd2dq, helper_cvtdq2pd, helper_cvtpd2dq },
2792 [0xe7] = { SSE_SPECIAL , SSE_SPECIAL }, /* movntq, movntq */
2793 [0xe8] = MMX_OP2(psubsb),
2794 [0xe9] = MMX_OP2(psubsw),
2795 [0xea] = MMX_OP2(pminsw),
2796 [0xeb] = MMX_OP2(por),
2797 [0xec] = MMX_OP2(paddsb),
2798 [0xed] = MMX_OP2(paddsw),
2799 [0xee] = MMX_OP2(pmaxsw),
2800 [0xef] = MMX_OP2(pxor),
2801 [0xf0] = { NULL, NULL, NULL, SSE_SPECIAL }, /* lddqu */
2802 [0xf1] = MMX_OP2(psllw),
2803 [0xf2] = MMX_OP2(pslld),
2804 [0xf3] = MMX_OP2(psllq),
2805 [0xf4] = MMX_OP2(pmuludq),
2806 [0xf5] = MMX_OP2(pmaddwd),
2807 [0xf6] = MMX_OP2(psadbw),
2808 [0xf7] = MMX_OP2(maskmov),
2809 [0xf8] = MMX_OP2(psubb),
2810 [0xf9] = MMX_OP2(psubw),
2811 [0xfa] = MMX_OP2(psubl),
2812 [0xfb] = MMX_OP2(psubq),
2813 [0xfc] = MMX_OP2(paddb),
2814 [0xfd] = MMX_OP2(paddw),
2815 [0xfe] = MMX_OP2(paddl),
2818 static void *sse_op_table2[3 * 8][2] = {
2819 [0 + 2] = MMX_OP2(psrlw),
2820 [0 + 4] = MMX_OP2(psraw),
2821 [0 + 6] = MMX_OP2(psllw),
2822 [8 + 2] = MMX_OP2(psrld),
2823 [8 + 4] = MMX_OP2(psrad),
2824 [8 + 6] = MMX_OP2(pslld),
2825 [16 + 2] = MMX_OP2(psrlq),
2826 [16 + 3] = { NULL, helper_psrldq_xmm },
2827 [16 + 6] = MMX_OP2(psllq),
2828 [16 + 7] = { NULL, helper_pslldq_xmm },
2831 static void *sse_op_table3[4 * 3] = {
2834 X86_64_ONLY(helper_cvtsq2ss),
2835 X86_64_ONLY(helper_cvtsq2sd),
2839 X86_64_ONLY(helper_cvttss2sq),
2840 X86_64_ONLY(helper_cvttsd2sq),
2844 X86_64_ONLY(helper_cvtss2sq),
2845 X86_64_ONLY(helper_cvtsd2sq),
2848 static void *sse_op_table4[8][4] = {
2859 static void *sse_op_table5[256] = {
2860 [0x0c] = helper_pi2fw,
2861 [0x0d] = helper_pi2fd,
2862 [0x1c] = helper_pf2iw,
2863 [0x1d] = helper_pf2id,
2864 [0x8a] = helper_pfnacc,
2865 [0x8e] = helper_pfpnacc,
2866 [0x90] = helper_pfcmpge,
2867 [0x94] = helper_pfmin,
2868 [0x96] = helper_pfrcp,
2869 [0x97] = helper_pfrsqrt,
2870 [0x9a] = helper_pfsub,
2871 [0x9e] = helper_pfadd,
2872 [0xa0] = helper_pfcmpgt,
2873 [0xa4] = helper_pfmax,
2874 [0xa6] = helper_movq, /* pfrcpit1; no need to actually increase precision */
2875 [0xa7] = helper_movq, /* pfrsqit1 */
2876 [0xaa] = helper_pfsubr,
2877 [0xae] = helper_pfacc,
2878 [0xb0] = helper_pfcmpeq,
2879 [0xb4] = helper_pfmul,
2880 [0xb6] = helper_movq, /* pfrcpit2 */
2881 [0xb7] = helper_pmulhrw_mmx,
2882 [0xbb] = helper_pswapd,
2883 [0xbf] = helper_pavgb_mmx /* pavgusb */
2886 static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
2888 int b1, op1_offset, op2_offset, is_xmm, val, ot;
2889 int modrm, mod, rm, reg, reg_addr, offset_addr;
2893 if (s->prefix & PREFIX_DATA)
2895 else if (s->prefix & PREFIX_REPZ)
2897 else if (s->prefix & PREFIX_REPNZ)
2901 sse_op2 = sse_op_table1[b][b1];
2904 if ((b <= 0x5f && b >= 0x10) || b == 0xc6 || b == 0xc2) {
2914 /* simple MMX/SSE operation */
2915 if (s->flags & HF_TS_MASK) {
2916 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
2919 if (s->flags & HF_EM_MASK) {
2921 gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
2924 if (is_xmm && !(s->flags & HF_OSFXSR_MASK))
2927 if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW))
2930 tcg_gen_helper_0_0(helper_emms);
2935 tcg_gen_helper_0_0(helper_emms);
2938 /* prepare MMX state (XXX: optimize by storing fptt and fptags in
2939 the static cpu state) */
2941 tcg_gen_helper_0_0(helper_enter_mmx);
2944 modrm = ldub_code(s->pc++);
2945 reg = ((modrm >> 3) & 7);
2948 mod = (modrm >> 6) & 3;
2949 if (sse_op2 == SSE_SPECIAL) {
2952 case 0x0e7: /* movntq */
2955 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
2956 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
2958 case 0x1e7: /* movntdq */
2959 case 0x02b: /* movntps */
2960 case 0x12b: /* movntps */
2961 case 0x3f0: /* lddqu */
2964 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
2965 gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
2967 case 0x6e: /* movd mm, ea */
2968 #ifdef TARGET_X86_64
2969 if (s->dflag == 2) {
2970 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0);
2971 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,fpregs[reg].mmx));
2975 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
2976 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
2977 offsetof(CPUX86State,fpregs[reg].mmx));
2978 tcg_gen_helper_0_2(helper_movl_mm_T0_mmx, cpu_ptr0, cpu_T[0]);
2981 case 0x16e: /* movd xmm, ea */
2982 #ifdef TARGET_X86_64
2983 if (s->dflag == 2) {
2984 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0);
2985 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
2986 offsetof(CPUX86State,xmm_regs[reg]));
2987 tcg_gen_helper_0_2(helper_movq_mm_T0_xmm, cpu_ptr0, cpu_T[0]);
2991 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
2992 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
2993 offsetof(CPUX86State,xmm_regs[reg]));
2994 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
2995 tcg_gen_helper_0_2(helper_movl_mm_T0_xmm, cpu_ptr0, cpu_tmp2_i32);
2998 case 0x6f: /* movq mm, ea */
3000 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3001 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
3004 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
3005 offsetof(CPUX86State,fpregs[rm].mmx));
3006 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
3007 offsetof(CPUX86State,fpregs[reg].mmx));
3010 case 0x010: /* movups */
3011 case 0x110: /* movupd */
3012 case 0x028: /* movaps */
3013 case 0x128: /* movapd */
3014 case 0x16f: /* movdqa xmm, ea */
3015 case 0x26f: /* movdqu xmm, ea */
3017 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3018 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3020 rm = (modrm & 7) | REX_B(s);
3021 gen_op_movo(offsetof(CPUX86State,xmm_regs[reg]),
3022 offsetof(CPUX86State,xmm_regs[rm]));
3025 case 0x210: /* movss xmm, ea */
3027 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3028 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3029 gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3031 gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
3032 gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3033 gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3035 rm = (modrm & 7) | REX_B(s);
3036 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3037 offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
3040 case 0x310: /* movsd xmm, ea */
3042 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3043 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3045 gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3046 gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3048 rm = (modrm & 7) | REX_B(s);
3049 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3050 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3053 case 0x012: /* movlps */
3054 case 0x112: /* movlpd */
3056 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3057 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3060 rm = (modrm & 7) | REX_B(s);
3061 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3062 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
3065 case 0x212: /* movsldup */
3067 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3068 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3070 rm = (modrm & 7) | REX_B(s);
3071 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3072 offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
3073 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
3074 offsetof(CPUX86State,xmm_regs[rm].XMM_L(2)));
3076 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
3077 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3078 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
3079 offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3081 case 0x312: /* movddup */
3083 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3084 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3086 rm = (modrm & 7) | REX_B(s);
3087 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3088 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3090 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
3091 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3093 case 0x016: /* movhps */
3094 case 0x116: /* movhpd */
3096 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3097 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3100 rm = (modrm & 7) | REX_B(s);
3101 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
3102 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3105 case 0x216: /* movshdup */
3107 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3108 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3110 rm = (modrm & 7) | REX_B(s);
3111 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
3112 offsetof(CPUX86State,xmm_regs[rm].XMM_L(1)));
3113 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
3114 offsetof(CPUX86State,xmm_regs[rm].XMM_L(3)));
3116 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3117 offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
3118 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
3119 offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3121 case 0x7e: /* movd ea, mm */
3122 #ifdef TARGET_X86_64
3123 if (s->dflag == 2) {
3124 tcg_gen_ld_i64(cpu_T[0], cpu_env,
3125 offsetof(CPUX86State,fpregs[reg].mmx));
3126 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
3130 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
3131 offsetof(CPUX86State,fpregs[reg].mmx.MMX_L(0)));
3132 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
3135 case 0x17e: /* movd ea, xmm */
3136 #ifdef TARGET_X86_64
3137 if (s->dflag == 2) {
3138 tcg_gen_ld_i64(cpu_T[0], cpu_env,
3139 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3140 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
3144 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
3145 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3146 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
3149 case 0x27e: /* movq xmm, ea */
3151 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3152 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3154 rm = (modrm & 7) | REX_B(s);
3155 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3156 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3158 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3160 case 0x7f: /* movq ea, mm */
3162 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3163 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
3166 gen_op_movq(offsetof(CPUX86State,fpregs[rm].mmx),
3167 offsetof(CPUX86State,fpregs[reg].mmx));
3170 case 0x011: /* movups */
3171 case 0x111: /* movupd */
3172 case 0x029: /* movaps */
3173 case 0x129: /* movapd */
3174 case 0x17f: /* movdqa ea, xmm */
3175 case 0x27f: /* movdqu ea, xmm */
3177 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3178 gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3180 rm = (modrm & 7) | REX_B(s);
3181 gen_op_movo(offsetof(CPUX86State,xmm_regs[rm]),
3182 offsetof(CPUX86State,xmm_regs[reg]));
3185 case 0x211: /* movss ea, xmm */
3187 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3188 gen_op_movl_T0_env(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3189 gen_op_st_T0_A0(OT_LONG + s->mem_index);
3191 rm = (modrm & 7) | REX_B(s);
3192 gen_op_movl(offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)),
3193 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3196 case 0x311: /* movsd ea, xmm */
3198 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3199 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3201 rm = (modrm & 7) | REX_B(s);
3202 gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
3203 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3206 case 0x013: /* movlps */
3207 case 0x113: /* movlpd */
3209 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3210 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3215 case 0x017: /* movhps */
3216 case 0x117: /* movhpd */
3218 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3219 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3224 case 0x71: /* shift mm, im */
3227 case 0x171: /* shift xmm, im */
3230 val = ldub_code(s->pc++);
3232 gen_op_movl_T0_im(val);
3233 gen_op_movl_env_T0(offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3235 gen_op_movl_env_T0(offsetof(CPUX86State,xmm_t0.XMM_L(1)));
3236 op1_offset = offsetof(CPUX86State,xmm_t0);
3238 gen_op_movl_T0_im(val);
3239 gen_op_movl_env_T0(offsetof(CPUX86State,mmx_t0.MMX_L(0)));
3241 gen_op_movl_env_T0(offsetof(CPUX86State,mmx_t0.MMX_L(1)));
3242 op1_offset = offsetof(CPUX86State,mmx_t0);
3244 sse_op2 = sse_op_table2[((b - 1) & 3) * 8 + (((modrm >> 3)) & 7)][b1];
3248 rm = (modrm & 7) | REX_B(s);
3249 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3252 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3254 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset);
3255 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op1_offset);
3256 tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_ptr1);
3258 case 0x050: /* movmskps */
3259 rm = (modrm & 7) | REX_B(s);
3260 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3261 offsetof(CPUX86State,xmm_regs[rm]));
3262 tcg_gen_helper_1_1(helper_movmskps, cpu_tmp2_i32, cpu_ptr0);
3263 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3264 gen_op_mov_reg_T0(OT_LONG, reg);
3266 case 0x150: /* movmskpd */
3267 rm = (modrm & 7) | REX_B(s);
3268 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3269 offsetof(CPUX86State,xmm_regs[rm]));
3270 tcg_gen_helper_1_1(helper_movmskpd, cpu_tmp2_i32, cpu_ptr0);
3271 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3272 gen_op_mov_reg_T0(OT_LONG, reg);
3274 case 0x02a: /* cvtpi2ps */
3275 case 0x12a: /* cvtpi2pd */
3276 tcg_gen_helper_0_0(helper_enter_mmx);
3278 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3279 op2_offset = offsetof(CPUX86State,mmx_t0);
3280 gen_ldq_env_A0(s->mem_index, op2_offset);
3283 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3285 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3286 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3287 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3290 tcg_gen_helper_0_2(helper_cvtpi2ps, cpu_ptr0, cpu_ptr1);
3294 tcg_gen_helper_0_2(helper_cvtpi2pd, cpu_ptr0, cpu_ptr1);
3298 case 0x22a: /* cvtsi2ss */
3299 case 0x32a: /* cvtsi2sd */
3300 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3301 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3302 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3303 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3304 sse_op2 = sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2)];
3305 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3306 tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_tmp2_i32);
3308 case 0x02c: /* cvttps2pi */
3309 case 0x12c: /* cvttpd2pi */
3310 case 0x02d: /* cvtps2pi */
3311 case 0x12d: /* cvtpd2pi */
3312 tcg_gen_helper_0_0(helper_enter_mmx);
3314 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3315 op2_offset = offsetof(CPUX86State,xmm_t0);
3316 gen_ldo_env_A0(s->mem_index, op2_offset);
3318 rm = (modrm & 7) | REX_B(s);
3319 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3321 op1_offset = offsetof(CPUX86State,fpregs[reg & 7].mmx);
3322 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3323 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3326 tcg_gen_helper_0_2(helper_cvttps2pi, cpu_ptr0, cpu_ptr1);
3329 tcg_gen_helper_0_2(helper_cvttpd2pi, cpu_ptr0, cpu_ptr1);
3332 tcg_gen_helper_0_2(helper_cvtps2pi, cpu_ptr0, cpu_ptr1);
3335 tcg_gen_helper_0_2(helper_cvtpd2pi, cpu_ptr0, cpu_ptr1);
3339 case 0x22c: /* cvttss2si */
3340 case 0x32c: /* cvttsd2si */
3341 case 0x22d: /* cvtss2si */
3342 case 0x32d: /* cvtsd2si */
3343 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3345 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3347 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_Q(0)));
3349 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3350 gen_op_movl_env_T0(offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3352 op2_offset = offsetof(CPUX86State,xmm_t0);
3354 rm = (modrm & 7) | REX_B(s);
3355 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3357 sse_op2 = sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2) + 4 +
3359 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset);
3360 if (ot == OT_LONG) {
3361 tcg_gen_helper_1_1(sse_op2, cpu_tmp2_i32, cpu_ptr0);
3362 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3364 tcg_gen_helper_1_1(sse_op2, cpu_T[0], cpu_ptr0);
3366 gen_op_mov_reg_T0(ot, reg);
3368 case 0xc4: /* pinsrw */
3371 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3372 val = ldub_code(s->pc++);
3375 tcg_gen_st16_tl(cpu_T[0], cpu_env,
3376 offsetof(CPUX86State,xmm_regs[reg].XMM_W(val)));
3379 tcg_gen_st16_tl(cpu_T[0], cpu_env,
3380 offsetof(CPUX86State,fpregs[reg].mmx.MMX_W(val)));
3383 case 0xc5: /* pextrw */
3387 val = ldub_code(s->pc++);
3390 rm = (modrm & 7) | REX_B(s);
3391 tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
3392 offsetof(CPUX86State,xmm_regs[rm].XMM_W(val)));
3396 tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
3397 offsetof(CPUX86State,fpregs[rm].mmx.MMX_W(val)));
3399 reg = ((modrm >> 3) & 7) | rex_r;
3400 gen_op_mov_reg_T0(OT_LONG, reg);
3402 case 0x1d6: /* movq ea, xmm */
3404 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3405 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3407 rm = (modrm & 7) | REX_B(s);
3408 gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
3409 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3410 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
3413 case 0x2d6: /* movq2dq */
3414 tcg_gen_helper_0_0(helper_enter_mmx);
3416 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3417 offsetof(CPUX86State,fpregs[rm].mmx));
3418 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3420 case 0x3d6: /* movdq2q */
3421 tcg_gen_helper_0_0(helper_enter_mmx);
3422 rm = (modrm & 7) | REX_B(s);
3423 gen_op_movq(offsetof(CPUX86State,fpregs[reg & 7].mmx),
3424 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3426 case 0xd7: /* pmovmskb */
3431 rm = (modrm & 7) | REX_B(s);
3432 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[rm]));
3433 tcg_gen_helper_1_1(helper_pmovmskb_xmm, cpu_tmp2_i32, cpu_ptr0);
3436 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,fpregs[rm].mmx));
3437 tcg_gen_helper_1_1(helper_pmovmskb_mmx, cpu_tmp2_i32, cpu_ptr0);
3439 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3440 reg = ((modrm >> 3) & 7) | rex_r;
3441 gen_op_mov_reg_T0(OT_LONG, reg);
3447 /* generic MMX or SSE operation */
3449 case 0x70: /* pshufx insn */
3450 case 0xc6: /* pshufx insn */
3451 case 0xc2: /* compare insns */
3458 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3460 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3461 op2_offset = offsetof(CPUX86State,xmm_t0);
3462 if (b1 >= 2 && ((b >= 0x50 && b <= 0x5f && b != 0x5b) ||
3464 /* specific case for SSE single instructions */
3467 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3468 gen_op_movl_env_T0(offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3471 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_D(0)));
3474 gen_ldo_env_A0(s->mem_index, op2_offset);
3477 rm = (modrm & 7) | REX_B(s);
3478 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3481 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
3483 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3484 op2_offset = offsetof(CPUX86State,mmx_t0);
3485 gen_ldq_env_A0(s->mem_index, op2_offset);
3488 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3492 case 0x0f: /* 3DNow! data insns */
3493 if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW))
3495 val = ldub_code(s->pc++);
3496 sse_op2 = sse_op_table5[val];
3499 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3500 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3501 tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_ptr1);
3503 case 0x70: /* pshufx insn */
3504 case 0xc6: /* pshufx insn */
3505 val = ldub_code(s->pc++);
3506 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3507 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3508 tcg_gen_helper_0_3(sse_op2, cpu_ptr0, cpu_ptr1, tcg_const_i32(val));
3512 val = ldub_code(s->pc++);
3515 sse_op2 = sse_op_table4[val][b1];
3516 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3517 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3518 tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_ptr1);
3521 /* maskmov : we must prepare A0 */
3524 #ifdef TARGET_X86_64
3525 if (s->aflag == 2) {
3526 gen_op_movq_A0_reg(R_EDI);
3530 gen_op_movl_A0_reg(R_EDI);
3532 gen_op_andl_A0_ffff();
3534 gen_add_A0_ds_seg(s);
3536 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3537 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3538 tcg_gen_helper_0_3(sse_op2, cpu_ptr0, cpu_ptr1, cpu_A0);
3541 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3542 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3543 tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_ptr1);
3546 if (b == 0x2e || b == 0x2f) {
3547 /* just to keep the EFLAGS optimization correct */
3549 s->cc_op = CC_OP_EFLAGS;
3554 /* convert one instruction. s->is_jmp is set if the translation must
3555 be stopped. Return the next pc value */
3556 static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
3558 int b, prefixes, aflag, dflag;
3560 int modrm, reg, rm, mod, reg_addr, op, opreg, offset_addr, val;
3561 target_ulong next_eip, tval;
3571 #ifdef TARGET_X86_64
3576 s->rip_offset = 0; /* for relative ip address */
3578 b = ldub_code(s->pc);
3580 /* check prefixes */
3581 #ifdef TARGET_X86_64
3585 prefixes |= PREFIX_REPZ;
3588 prefixes |= PREFIX_REPNZ;
3591 prefixes |= PREFIX_LOCK;
3612 prefixes |= PREFIX_DATA;
3615 prefixes |= PREFIX_ADR;
3619 rex_w = (b >> 3) & 1;
3620 rex_r = (b & 0x4) << 1;
3621 s->rex_x = (b & 0x2) << 2;
3622 REX_B(s) = (b & 0x1) << 3;
3623 x86_64_hregs = 1; /* select uniform byte register addressing */
3627 /* 0x66 is ignored if rex.w is set */
3630 if (prefixes & PREFIX_DATA)
3633 if (!(prefixes & PREFIX_ADR))
3640 prefixes |= PREFIX_REPZ;
3643 prefixes |= PREFIX_REPNZ;
3646 prefixes |= PREFIX_LOCK;
3667 prefixes |= PREFIX_DATA;
3670 prefixes |= PREFIX_ADR;
3673 if (prefixes & PREFIX_DATA)
3675 if (prefixes & PREFIX_ADR)
3679 s->prefix = prefixes;
3683 /* lock generation */
3684 if (prefixes & PREFIX_LOCK)
3685 tcg_gen_helper_0_0(helper_lock);
3687 /* now check op code */
3691 /**************************/
3692 /* extended op code */
3693 b = ldub_code(s->pc++) | 0x100;
3696 /**************************/
3714 ot = dflag + OT_WORD;
3717 case 0: /* OP Ev, Gv */
3718 modrm = ldub_code(s->pc++);
3719 reg = ((modrm >> 3) & 7) | rex_r;
3720 mod = (modrm >> 6) & 3;
3721 rm = (modrm & 7) | REX_B(s);
3723 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3725 } else if (op == OP_XORL && rm == reg) {
3727 /* xor reg, reg optimisation */
3729 s->cc_op = CC_OP_LOGICB + ot;
3730 gen_op_mov_reg_T0(ot, reg);
3731 gen_op_update1_cc();
3736 gen_op_mov_TN_reg(ot, 1, reg);
3737 gen_op(s, op, ot, opreg);
3739 case 1: /* OP Gv, Ev */
3740 modrm = ldub_code(s->pc++);
3741 mod = (modrm >> 6) & 3;
3742 reg = ((modrm >> 3) & 7) | rex_r;
3743 rm = (modrm & 7) | REX_B(s);
3745 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3746 gen_op_ld_T1_A0(ot + s->mem_index);
3747 } else if (op == OP_XORL && rm == reg) {
3750 gen_op_mov_TN_reg(ot, 1, rm);
3752 gen_op(s, op, ot, reg);
3754 case 2: /* OP A, Iv */
3755 val = insn_get(s, ot);
3756 gen_op_movl_T1_im(val);
3757 gen_op(s, op, ot, OR_EAX);
3763 case 0x80: /* GRP1 */
3773 ot = dflag + OT_WORD;
3775 modrm = ldub_code(s->pc++);
3776 mod = (modrm >> 6) & 3;
3777 rm = (modrm & 7) | REX_B(s);
3778 op = (modrm >> 3) & 7;
3784 s->rip_offset = insn_const_size(ot);
3785 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3796 val = insn_get(s, ot);
3799 val = (int8_t)insn_get(s, OT_BYTE);
3802 gen_op_movl_T1_im(val);
3803 gen_op(s, op, ot, opreg);
3807 /**************************/
3808 /* inc, dec, and other misc arith */
3809 case 0x40 ... 0x47: /* inc Gv */
3810 ot = dflag ? OT_LONG : OT_WORD;
3811 gen_inc(s, ot, OR_EAX + (b & 7), 1);
3813 case 0x48 ... 0x4f: /* dec Gv */
3814 ot = dflag ? OT_LONG : OT_WORD;
3815 gen_inc(s, ot, OR_EAX + (b & 7), -1);
3817 case 0xf6: /* GRP3 */
3822 ot = dflag + OT_WORD;
3824 modrm = ldub_code(s->pc++);
3825 mod = (modrm >> 6) & 3;
3826 rm = (modrm & 7) | REX_B(s);
3827 op = (modrm >> 3) & 7;
3830 s->rip_offset = insn_const_size(ot);
3831 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3832 gen_op_ld_T0_A0(ot + s->mem_index);
3834 gen_op_mov_TN_reg(ot, 0, rm);
3839 val = insn_get(s, ot);
3840 gen_op_movl_T1_im(val);
3841 gen_op_testl_T0_T1_cc();
3842 s->cc_op = CC_OP_LOGICB + ot;
3845 tcg_gen_not_tl(cpu_T[0], cpu_T[0]);
3847 gen_op_st_T0_A0(ot + s->mem_index);
3849 gen_op_mov_reg_T0(ot, rm);
3853 tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
3855 gen_op_st_T0_A0(ot + s->mem_index);
3857 gen_op_mov_reg_T0(ot, rm);
3859 gen_op_update_neg_cc();
3860 s->cc_op = CC_OP_SUBB + ot;
3865 gen_op_mulb_AL_T0();
3866 s->cc_op = CC_OP_MULB;
3869 gen_op_mulw_AX_T0();
3870 s->cc_op = CC_OP_MULW;
3874 gen_op_mull_EAX_T0();
3875 s->cc_op = CC_OP_MULL;
3877 #ifdef TARGET_X86_64
3879 gen_op_mulq_EAX_T0();
3880 s->cc_op = CC_OP_MULQ;
3888 gen_op_imulb_AL_T0();
3889 s->cc_op = CC_OP_MULB;
3892 gen_op_imulw_AX_T0();
3893 s->cc_op = CC_OP_MULW;
3897 gen_op_imull_EAX_T0();
3898 s->cc_op = CC_OP_MULL;
3900 #ifdef TARGET_X86_64
3902 gen_op_imulq_EAX_T0();
3903 s->cc_op = CC_OP_MULQ;
3911 gen_jmp_im(pc_start - s->cs_base);
3912 tcg_gen_helper_0_1(helper_divb_AL, cpu_T[0]);
3915 gen_jmp_im(pc_start - s->cs_base);
3916 tcg_gen_helper_0_1(helper_divw_AX, cpu_T[0]);
3920 gen_jmp_im(pc_start - s->cs_base);
3921 tcg_gen_helper_0_1(helper_divl_EAX, cpu_T[0]);
3923 #ifdef TARGET_X86_64
3925 gen_jmp_im(pc_start - s->cs_base);
3926 tcg_gen_helper_0_1(helper_divq_EAX, cpu_T[0]);
3934 gen_jmp_im(pc_start - s->cs_base);
3935 tcg_gen_helper_0_1(helper_idivb_AL, cpu_T[0]);
3938 gen_jmp_im(pc_start - s->cs_base);
3939 tcg_gen_helper_0_1(helper_idivw_AX, cpu_T[0]);
3943 gen_jmp_im(pc_start - s->cs_base);
3944 tcg_gen_helper_0_1(helper_idivl_EAX, cpu_T[0]);
3946 #ifdef TARGET_X86_64
3948 gen_jmp_im(pc_start - s->cs_base);
3949 tcg_gen_helper_0_1(helper_idivq_EAX, cpu_T[0]);
3959 case 0xfe: /* GRP4 */
3960 case 0xff: /* GRP5 */
3964 ot = dflag + OT_WORD;
3966 modrm = ldub_code(s->pc++);
3967 mod = (modrm >> 6) & 3;
3968 rm = (modrm & 7) | REX_B(s);
3969 op = (modrm >> 3) & 7;
3970 if (op >= 2 && b == 0xfe) {
3974 if (op == 2 || op == 4) {
3975 /* operand size for jumps is 64 bit */
3977 } else if (op == 3 || op == 5) {
3978 /* for call calls, the operand is 16 or 32 bit, even
3980 ot = dflag ? OT_LONG : OT_WORD;
3981 } else if (op == 6) {
3982 /* default push size is 64 bit */
3983 ot = dflag ? OT_QUAD : OT_WORD;
3987 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3988 if (op >= 2 && op != 3 && op != 5)
3989 gen_op_ld_T0_A0(ot + s->mem_index);
3991 gen_op_mov_TN_reg(ot, 0, rm);
3995 case 0: /* inc Ev */
4000 gen_inc(s, ot, opreg, 1);
4002 case 1: /* dec Ev */
4007 gen_inc(s, ot, opreg, -1);
4009 case 2: /* call Ev */
4010 /* XXX: optimize if memory (no 'and' is necessary) */
4012 gen_op_andl_T0_ffff();
4013 next_eip = s->pc - s->cs_base;
4014 gen_movtl_T1_im(next_eip);
4019 case 3: /* lcall Ev */
4020 gen_op_ld_T1_A0(ot + s->mem_index);
4021 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
4022 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
4024 if (s->pe && !s->vm86) {
4025 if (s->cc_op != CC_OP_DYNAMIC)
4026 gen_op_set_cc_op(s->cc_op);
4027 gen_jmp_im(pc_start - s->cs_base);
4028 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4029 tcg_gen_helper_0_4(helper_lcall_protected,
4030 cpu_tmp2_i32, cpu_T[1],
4031 tcg_const_i32(dflag),
4032 tcg_const_i32(s->pc - pc_start));
4034 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4035 tcg_gen_helper_0_4(helper_lcall_real,
4036 cpu_tmp2_i32, cpu_T[1],
4037 tcg_const_i32(dflag),
4038 tcg_const_i32(s->pc - s->cs_base));
4042 case 4: /* jmp Ev */
4044 gen_op_andl_T0_ffff();
4048 case 5: /* ljmp Ev */
4049 gen_op_ld_T1_A0(ot + s->mem_index);
4050 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
4051 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
4053 if (s->pe && !s->vm86) {
4054 if (s->cc_op != CC_OP_DYNAMIC)
4055 gen_op_set_cc_op(s->cc_op);
4056 gen_jmp_im(pc_start - s->cs_base);
4057 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4058 tcg_gen_helper_0_3(helper_ljmp_protected,
4061 tcg_const_i32(s->pc - pc_start));
4063 gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[R_CS]));
4064 gen_op_movl_T0_T1();
4069 case 6: /* push Ev */
4077 case 0x84: /* test Ev, Gv */
4082 ot = dflag + OT_WORD;
4084 modrm = ldub_code(s->pc++);
4085 mod = (modrm >> 6) & 3;
4086 rm = (modrm & 7) | REX_B(s);
4087 reg = ((modrm >> 3) & 7) | rex_r;
4089 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
4090 gen_op_mov_TN_reg(ot, 1, reg);
4091 gen_op_testl_T0_T1_cc();
4092 s->cc_op = CC_OP_LOGICB + ot;
4095 case 0xa8: /* test eAX, Iv */
4100 ot = dflag + OT_WORD;
4101 val = insn_get(s, ot);
4103 gen_op_mov_TN_reg(ot, 0, OR_EAX);
4104 gen_op_movl_T1_im(val);
4105 gen_op_testl_T0_T1_cc();
4106 s->cc_op = CC_OP_LOGICB + ot;
4109 case 0x98: /* CWDE/CBW */
4110 #ifdef TARGET_X86_64
4112 gen_op_movslq_RAX_EAX();
4116 gen_op_movswl_EAX_AX();
4118 gen_op_movsbw_AX_AL();
4120 case 0x99: /* CDQ/CWD */
4121 #ifdef TARGET_X86_64
4123 gen_op_movsqo_RDX_RAX();
4127 gen_op_movslq_EDX_EAX();
4129 gen_op_movswl_DX_AX();
4131 case 0x1af: /* imul Gv, Ev */
4132 case 0x69: /* imul Gv, Ev, I */
4134 ot = dflag + OT_WORD;
4135 modrm = ldub_code(s->pc++);
4136 reg = ((modrm >> 3) & 7) | rex_r;
4138 s->rip_offset = insn_const_size(ot);
4141 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
4143 val = insn_get(s, ot);
4144 gen_op_movl_T1_im(val);
4145 } else if (b == 0x6b) {
4146 val = (int8_t)insn_get(s, OT_BYTE);
4147 gen_op_movl_T1_im(val);
4149 gen_op_mov_TN_reg(ot, 1, reg);
4152 #ifdef TARGET_X86_64
4153 if (ot == OT_QUAD) {
4154 gen_op_imulq_T0_T1();
4157 if (ot == OT_LONG) {
4158 gen_op_imull_T0_T1();
4160 gen_op_imulw_T0_T1();
4162 gen_op_mov_reg_T0(ot, reg);
4163 s->cc_op = CC_OP_MULB + ot;
4166 case 0x1c1: /* xadd Ev, Gv */
4170 ot = dflag + OT_WORD;
4171 modrm = ldub_code(s->pc++);
4172 reg = ((modrm >> 3) & 7) | rex_r;
4173 mod = (modrm >> 6) & 3;
4175 rm = (modrm & 7) | REX_B(s);
4176 gen_op_mov_TN_reg(ot, 0, reg);
4177 gen_op_mov_TN_reg(ot, 1, rm);
4178 gen_op_addl_T0_T1();
4179 gen_op_mov_reg_T1(ot, reg);
4180 gen_op_mov_reg_T0(ot, rm);
4182 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4183 gen_op_mov_TN_reg(ot, 0, reg);
4184 gen_op_ld_T1_A0(ot + s->mem_index);
4185 gen_op_addl_T0_T1();
4186 gen_op_st_T0_A0(ot + s->mem_index);
4187 gen_op_mov_reg_T1(ot, reg);
4189 gen_op_update2_cc();
4190 s->cc_op = CC_OP_ADDB + ot;
4193 case 0x1b1: /* cmpxchg Ev, Gv */
4200 ot = dflag + OT_WORD;
4201 modrm = ldub_code(s->pc++);
4202 reg = ((modrm >> 3) & 7) | rex_r;
4203 mod = (modrm >> 6) & 3;
4204 gen_op_mov_TN_reg(ot, 1, reg);
4206 rm = (modrm & 7) | REX_B(s);
4207 gen_op_mov_TN_reg(ot, 0, rm);
4209 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4210 gen_op_ld_T0_A0(ot + s->mem_index);
4211 rm = 0; /* avoid warning */
4213 label1 = gen_new_label();
4214 tcg_gen_ld_tl(cpu_T3, cpu_env, offsetof(CPUState, regs[R_EAX]));
4215 tcg_gen_sub_tl(cpu_T3, cpu_T3, cpu_T[0]);
4216 gen_extu(ot, cpu_T3);
4217 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T3, tcg_const_tl(0), label1);
4218 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
4219 gen_op_mov_reg_T0(ot, R_EAX);
4220 gen_set_label(label1);
4222 gen_op_mov_reg_T1(ot, rm);
4224 gen_op_st_T1_A0(ot + s->mem_index);
4226 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4227 tcg_gen_mov_tl(cpu_cc_dst, cpu_T3);
4228 s->cc_op = CC_OP_SUBB + ot;
4231 case 0x1c7: /* cmpxchg8b */
4232 modrm = ldub_code(s->pc++);
4233 mod = (modrm >> 6) & 3;
4234 if ((mod == 3) || ((modrm & 0x38) != 0x8))
4236 gen_jmp_im(pc_start - s->cs_base);
4237 if (s->cc_op != CC_OP_DYNAMIC)
4238 gen_op_set_cc_op(s->cc_op);
4239 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4241 s->cc_op = CC_OP_EFLAGS;
4244 /**************************/
4246 case 0x50 ... 0x57: /* push */
4247 gen_op_mov_TN_reg(OT_LONG, 0, (b & 7) | REX_B(s));
4250 case 0x58 ... 0x5f: /* pop */
4252 ot = dflag ? OT_QUAD : OT_WORD;
4254 ot = dflag + OT_WORD;
4257 /* NOTE: order is important for pop %sp */
4259 gen_op_mov_reg_T0(ot, (b & 7) | REX_B(s));
4261 case 0x60: /* pusha */
4266 case 0x61: /* popa */
4271 case 0x68: /* push Iv */
4274 ot = dflag ? OT_QUAD : OT_WORD;
4276 ot = dflag + OT_WORD;
4279 val = insn_get(s, ot);
4281 val = (int8_t)insn_get(s, OT_BYTE);
4282 gen_op_movl_T0_im(val);
4285 case 0x8f: /* pop Ev */
4287 ot = dflag ? OT_QUAD : OT_WORD;
4289 ot = dflag + OT_WORD;
4291 modrm = ldub_code(s->pc++);
4292 mod = (modrm >> 6) & 3;
4295 /* NOTE: order is important for pop %sp */
4297 rm = (modrm & 7) | REX_B(s);
4298 gen_op_mov_reg_T0(ot, rm);
4300 /* NOTE: order is important too for MMU exceptions */
4301 s->popl_esp_hack = 1 << ot;
4302 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
4303 s->popl_esp_hack = 0;
4307 case 0xc8: /* enter */
4310 val = lduw_code(s->pc);
4312 level = ldub_code(s->pc++);
4313 gen_enter(s, val, level);
4316 case 0xc9: /* leave */
4317 /* XXX: exception not precise (ESP is updated before potential exception) */
4319 gen_op_mov_TN_reg(OT_QUAD, 0, R_EBP);
4320 gen_op_mov_reg_T0(OT_QUAD, R_ESP);
4321 } else if (s->ss32) {
4322 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
4323 gen_op_mov_reg_T0(OT_LONG, R_ESP);
4325 gen_op_mov_TN_reg(OT_WORD, 0, R_EBP);
4326 gen_op_mov_reg_T0(OT_WORD, R_ESP);
4330 ot = dflag ? OT_QUAD : OT_WORD;
4332 ot = dflag + OT_WORD;
4334 gen_op_mov_reg_T0(ot, R_EBP);
4337 case 0x06: /* push es */
4338 case 0x0e: /* push cs */
4339 case 0x16: /* push ss */
4340 case 0x1e: /* push ds */
4343 gen_op_movl_T0_seg(b >> 3);
4346 case 0x1a0: /* push fs */
4347 case 0x1a8: /* push gs */
4348 gen_op_movl_T0_seg((b >> 3) & 7);
4351 case 0x07: /* pop es */
4352 case 0x17: /* pop ss */
4353 case 0x1f: /* pop ds */
4358 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
4361 /* if reg == SS, inhibit interrupts/trace. */
4362 /* If several instructions disable interrupts, only the
4364 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
4365 tcg_gen_helper_0_0(helper_set_inhibit_irq);
4369 gen_jmp_im(s->pc - s->cs_base);
4373 case 0x1a1: /* pop fs */
4374 case 0x1a9: /* pop gs */
4376 gen_movl_seg_T0(s, (b >> 3) & 7, pc_start - s->cs_base);
4379 gen_jmp_im(s->pc - s->cs_base);
4384 /**************************/
4387 case 0x89: /* mov Gv, Ev */
4391 ot = dflag + OT_WORD;
4392 modrm = ldub_code(s->pc++);
4393 reg = ((modrm >> 3) & 7) | rex_r;
4395 /* generate a generic store */
4396 gen_ldst_modrm(s, modrm, ot, reg, 1);
4399 case 0xc7: /* mov Ev, Iv */
4403 ot = dflag + OT_WORD;
4404 modrm = ldub_code(s->pc++);
4405 mod = (modrm >> 6) & 3;
4407 s->rip_offset = insn_const_size(ot);
4408 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4410 val = insn_get(s, ot);
4411 gen_op_movl_T0_im(val);
4413 gen_op_st_T0_A0(ot + s->mem_index);
4415 gen_op_mov_reg_T0(ot, (modrm & 7) | REX_B(s));
4418 case 0x8b: /* mov Ev, Gv */
4422 ot = OT_WORD + dflag;
4423 modrm = ldub_code(s->pc++);
4424 reg = ((modrm >> 3) & 7) | rex_r;
4426 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
4427 gen_op_mov_reg_T0(ot, reg);
4429 case 0x8e: /* mov seg, Gv */
4430 modrm = ldub_code(s->pc++);
4431 reg = (modrm >> 3) & 7;
4432 if (reg >= 6 || reg == R_CS)
4434 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
4435 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
4437 /* if reg == SS, inhibit interrupts/trace */
4438 /* If several instructions disable interrupts, only the
4440 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
4441 tcg_gen_helper_0_0(helper_set_inhibit_irq);
4445 gen_jmp_im(s->pc - s->cs_base);
4449 case 0x8c: /* mov Gv, seg */
4450 modrm = ldub_code(s->pc++);
4451 reg = (modrm >> 3) & 7;
4452 mod = (modrm >> 6) & 3;
4455 gen_op_movl_T0_seg(reg);
4457 ot = OT_WORD + dflag;
4460 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
4463 case 0x1b6: /* movzbS Gv, Eb */
4464 case 0x1b7: /* movzwS Gv, Eb */
4465 case 0x1be: /* movsbS Gv, Eb */
4466 case 0x1bf: /* movswS Gv, Eb */
4469 /* d_ot is the size of destination */
4470 d_ot = dflag + OT_WORD;
4471 /* ot is the size of source */
4472 ot = (b & 1) + OT_BYTE;
4473 modrm = ldub_code(s->pc++);
4474 reg = ((modrm >> 3) & 7) | rex_r;
4475 mod = (modrm >> 6) & 3;
4476 rm = (modrm & 7) | REX_B(s);
4479 gen_op_mov_TN_reg(ot, 0, rm);
4480 switch(ot | (b & 8)) {
4482 gen_op_movzbl_T0_T0();
4485 gen_op_movsbl_T0_T0();
4488 gen_op_movzwl_T0_T0();
4492 gen_op_movswl_T0_T0();
4495 gen_op_mov_reg_T0(d_ot, reg);
4497 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4499 gen_op_lds_T0_A0(ot + s->mem_index);
4501 gen_op_ldu_T0_A0(ot + s->mem_index);
4503 gen_op_mov_reg_T0(d_ot, reg);
4508 case 0x8d: /* lea */
4509 ot = dflag + OT_WORD;
4510 modrm = ldub_code(s->pc++);
4511 mod = (modrm >> 6) & 3;
4514 reg = ((modrm >> 3) & 7) | rex_r;
4515 /* we must ensure that no segment is added */
4519 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4521 gen_op_mov_reg_A0(ot - OT_WORD, reg);
4524 case 0xa0: /* mov EAX, Ov */
4526 case 0xa2: /* mov Ov, EAX */
4529 target_ulong offset_addr;
4534 ot = dflag + OT_WORD;
4535 #ifdef TARGET_X86_64
4536 if (s->aflag == 2) {
4537 offset_addr = ldq_code(s->pc);
4539 gen_op_movq_A0_im(offset_addr);
4544 offset_addr = insn_get(s, OT_LONG);
4546 offset_addr = insn_get(s, OT_WORD);
4548 gen_op_movl_A0_im(offset_addr);
4550 gen_add_A0_ds_seg(s);
4552 gen_op_ld_T0_A0(ot + s->mem_index);
4553 gen_op_mov_reg_T0(ot, R_EAX);
4555 gen_op_mov_TN_reg(ot, 0, R_EAX);
4556 gen_op_st_T0_A0(ot + s->mem_index);
4560 case 0xd7: /* xlat */
4561 #ifdef TARGET_X86_64
4562 if (s->aflag == 2) {
4563 gen_op_movq_A0_reg(R_EBX);
4564 gen_op_addq_A0_AL();
4568 gen_op_movl_A0_reg(R_EBX);
4569 gen_op_addl_A0_AL();
4571 gen_op_andl_A0_ffff();
4573 gen_add_A0_ds_seg(s);
4574 gen_op_ldu_T0_A0(OT_BYTE + s->mem_index);
4575 gen_op_mov_reg_T0(OT_BYTE, R_EAX);
4577 case 0xb0 ... 0xb7: /* mov R, Ib */
4578 val = insn_get(s, OT_BYTE);
4579 gen_op_movl_T0_im(val);
4580 gen_op_mov_reg_T0(OT_BYTE, (b & 7) | REX_B(s));
4582 case 0xb8 ... 0xbf: /* mov R, Iv */
4583 #ifdef TARGET_X86_64
4587 tmp = ldq_code(s->pc);
4589 reg = (b & 7) | REX_B(s);
4590 gen_movtl_T0_im(tmp);
4591 gen_op_mov_reg_T0(OT_QUAD, reg);
4595 ot = dflag ? OT_LONG : OT_WORD;
4596 val = insn_get(s, ot);
4597 reg = (b & 7) | REX_B(s);
4598 gen_op_movl_T0_im(val);
4599 gen_op_mov_reg_T0(ot, reg);
4603 case 0x91 ... 0x97: /* xchg R, EAX */
4604 ot = dflag + OT_WORD;
4605 reg = (b & 7) | REX_B(s);
4609 case 0x87: /* xchg Ev, Gv */
4613 ot = dflag + OT_WORD;
4614 modrm = ldub_code(s->pc++);
4615 reg = ((modrm >> 3) & 7) | rex_r;
4616 mod = (modrm >> 6) & 3;
4618 rm = (modrm & 7) | REX_B(s);
4620 gen_op_mov_TN_reg(ot, 0, reg);
4621 gen_op_mov_TN_reg(ot, 1, rm);
4622 gen_op_mov_reg_T0(ot, rm);
4623 gen_op_mov_reg_T1(ot, reg);
4625 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4626 gen_op_mov_TN_reg(ot, 0, reg);
4627 /* for xchg, lock is implicit */
4628 if (!(prefixes & PREFIX_LOCK))
4629 tcg_gen_helper_0_0(helper_lock);
4630 gen_op_ld_T1_A0(ot + s->mem_index);
4631 gen_op_st_T0_A0(ot + s->mem_index);
4632 if (!(prefixes & PREFIX_LOCK))
4633 tcg_gen_helper_0_0(helper_unlock);
4634 gen_op_mov_reg_T1(ot, reg);
4637 case 0xc4: /* les Gv */
4642 case 0xc5: /* lds Gv */
4647 case 0x1b2: /* lss Gv */
4650 case 0x1b4: /* lfs Gv */
4653 case 0x1b5: /* lgs Gv */
4656 ot = dflag ? OT_LONG : OT_WORD;
4657 modrm = ldub_code(s->pc++);
4658 reg = ((modrm >> 3) & 7) | rex_r;
4659 mod = (modrm >> 6) & 3;
4662 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4663 gen_op_ld_T1_A0(ot + s->mem_index);
4664 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
4665 /* load the segment first to handle exceptions properly */
4666 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
4667 gen_movl_seg_T0(s, op, pc_start - s->cs_base);
4668 /* then put the data */
4669 gen_op_mov_reg_T1(ot, reg);
4671 gen_jmp_im(s->pc - s->cs_base);
4676 /************************/
4687 ot = dflag + OT_WORD;
4689 modrm = ldub_code(s->pc++);
4690 mod = (modrm >> 6) & 3;
4691 op = (modrm >> 3) & 7;
4697 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4700 opreg = (modrm & 7) | REX_B(s);
4705 gen_shift(s, op, ot, opreg, OR_ECX);
4708 shift = ldub_code(s->pc++);
4710 gen_shifti(s, op, ot, opreg, shift);
4725 case 0x1a4: /* shld imm */
4729 case 0x1a5: /* shld cl */
4733 case 0x1ac: /* shrd imm */
4737 case 0x1ad: /* shrd cl */
4741 ot = dflag + OT_WORD;
4742 modrm = ldub_code(s->pc++);
4743 mod = (modrm >> 6) & 3;
4744 rm = (modrm & 7) | REX_B(s);
4745 reg = ((modrm >> 3) & 7) | rex_r;
4747 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4752 gen_op_mov_TN_reg(ot, 1, reg);
4755 val = ldub_code(s->pc++);
4756 tcg_gen_movi_tl(cpu_T3, val);
4758 tcg_gen_ld_tl(cpu_T3, cpu_env, offsetof(CPUState, regs[R_ECX]));
4760 gen_shiftd_rm_T1_T3(s, ot, opreg, op);
4763 /************************/
4766 if (s->flags & (HF_EM_MASK | HF_TS_MASK)) {
4767 /* if CR0.EM or CR0.TS are set, generate an FPU exception */
4768 /* XXX: what to do if illegal op ? */
4769 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
4772 modrm = ldub_code(s->pc++);
4773 mod = (modrm >> 6) & 3;
4775 op = ((b & 7) << 3) | ((modrm >> 3) & 7);
4778 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4780 case 0x00 ... 0x07: /* fxxxs */
4781 case 0x10 ... 0x17: /* fixxxl */
4782 case 0x20 ... 0x27: /* fxxxl */
4783 case 0x30 ... 0x37: /* fixxx */
4790 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
4791 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4792 tcg_gen_helper_0_1(helper_flds_FT0, cpu_tmp2_i32);
4795 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
4796 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4797 tcg_gen_helper_0_1(helper_fildl_FT0, cpu_tmp2_i32);
4800 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
4801 (s->mem_index >> 2) - 1);
4802 tcg_gen_helper_0_1(helper_fldl_FT0, cpu_tmp1_i64);
4806 gen_op_lds_T0_A0(OT_WORD + s->mem_index);
4807 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4808 tcg_gen_helper_0_1(helper_fildl_FT0, cpu_tmp2_i32);
4812 tcg_gen_helper_0_0(helper_fp_arith_ST0_FT0[op1]);
4814 /* fcomp needs pop */
4815 tcg_gen_helper_0_0(helper_fpop);
4819 case 0x08: /* flds */
4820 case 0x0a: /* fsts */
4821 case 0x0b: /* fstps */
4822 case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */
4823 case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */
4824 case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */
4829 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
4830 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4831 tcg_gen_helper_0_1(helper_flds_ST0, cpu_tmp2_i32);
4834 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
4835 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4836 tcg_gen_helper_0_1(helper_fildl_ST0, cpu_tmp2_i32);
4839 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
4840 (s->mem_index >> 2) - 1);
4841 tcg_gen_helper_0_1(helper_fldl_ST0, cpu_tmp1_i64);
4845 gen_op_lds_T0_A0(OT_WORD + s->mem_index);
4846 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4847 tcg_gen_helper_0_1(helper_fildl_ST0, cpu_tmp2_i32);
4852 /* XXX: the corresponding CPUID bit must be tested ! */
4855 tcg_gen_helper_1_0(helper_fisttl_ST0, cpu_tmp2_i32);
4856 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
4857 gen_op_st_T0_A0(OT_LONG + s->mem_index);
4860 tcg_gen_helper_1_0(helper_fisttll_ST0, cpu_tmp1_i64);
4861 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
4862 (s->mem_index >> 2) - 1);
4866 tcg_gen_helper_1_0(helper_fistt_ST0, cpu_tmp2_i32);
4867 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
4868 gen_op_st_T0_A0(OT_WORD + s->mem_index);
4871 tcg_gen_helper_0_0(helper_fpop);
4876 tcg_gen_helper_1_0(helper_fsts_ST0, cpu_tmp2_i32);
4877 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
4878 gen_op_st_T0_A0(OT_LONG + s->mem_index);
4881 tcg_gen_helper_1_0(helper_fistl_ST0, cpu_tmp2_i32);
4882 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
4883 gen_op_st_T0_A0(OT_LONG + s->mem_index);
4886 tcg_gen_helper_1_0(helper_fstl_ST0, cpu_tmp1_i64);
4887 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
4888 (s->mem_index >> 2) - 1);
4892 tcg_gen_helper_1_0(helper_fist_ST0, cpu_tmp2_i32);
4893 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
4894 gen_op_st_T0_A0(OT_WORD + s->mem_index);
4898 tcg_gen_helper_0_0(helper_fpop);
4902 case 0x0c: /* fldenv mem */
4903 if (s->cc_op != CC_OP_DYNAMIC)
4904 gen_op_set_cc_op(s->cc_op);
4905 gen_jmp_im(pc_start - s->cs_base);
4906 tcg_gen_helper_0_2(helper_fldenv,
4907 cpu_A0, tcg_const_i32(s->dflag));
4909 case 0x0d: /* fldcw mem */
4910 gen_op_ld_T0_A0(OT_WORD + s->mem_index);
4911 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4912 tcg_gen_helper_0_1(helper_fldcw, cpu_tmp2_i32);
4914 case 0x0e: /* fnstenv mem */
4915 if (s->cc_op != CC_OP_DYNAMIC)
4916 gen_op_set_cc_op(s->cc_op);
4917 gen_jmp_im(pc_start - s->cs_base);
4918 tcg_gen_helper_0_2(helper_fstenv,
4919 cpu_A0, tcg_const_i32(s->dflag));
4921 case 0x0f: /* fnstcw mem */
4922 tcg_gen_helper_1_0(helper_fnstcw, cpu_tmp2_i32);
4923 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
4924 gen_op_st_T0_A0(OT_WORD + s->mem_index);
4926 case 0x1d: /* fldt mem */
4927 if (s->cc_op != CC_OP_DYNAMIC)
4928 gen_op_set_cc_op(s->cc_op);
4929 gen_jmp_im(pc_start - s->cs_base);
4930 tcg_gen_helper_0_1(helper_fldt_ST0, cpu_A0);
4932 case 0x1f: /* fstpt mem */
4933 if (s->cc_op != CC_OP_DYNAMIC)
4934 gen_op_set_cc_op(s->cc_op);
4935 gen_jmp_im(pc_start - s->cs_base);
4936 tcg_gen_helper_0_1(helper_fstt_ST0, cpu_A0);
4937 tcg_gen_helper_0_0(helper_fpop);
4939 case 0x2c: /* frstor mem */
4940 if (s->cc_op != CC_OP_DYNAMIC)
4941 gen_op_set_cc_op(s->cc_op);
4942 gen_jmp_im(pc_start - s->cs_base);
4943 tcg_gen_helper_0_2(helper_frstor,
4944 cpu_A0, tcg_const_i32(s->dflag));
4946 case 0x2e: /* fnsave mem */
4947 if (s->cc_op != CC_OP_DYNAMIC)
4948 gen_op_set_cc_op(s->cc_op);
4949 gen_jmp_im(pc_start - s->cs_base);
4950 tcg_gen_helper_0_2(helper_fsave,
4951 cpu_A0, tcg_const_i32(s->dflag));
4953 case 0x2f: /* fnstsw mem */
4954 tcg_gen_helper_1_0(helper_fnstsw, cpu_tmp2_i32);
4955 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
4956 gen_op_st_T0_A0(OT_WORD + s->mem_index);
4958 case 0x3c: /* fbld */
4959 if (s->cc_op != CC_OP_DYNAMIC)
4960 gen_op_set_cc_op(s->cc_op);
4961 gen_jmp_im(pc_start - s->cs_base);
4962 tcg_gen_helper_0_1(helper_fbld_ST0, cpu_A0);
4964 case 0x3e: /* fbstp */
4965 if (s->cc_op != CC_OP_DYNAMIC)
4966 gen_op_set_cc_op(s->cc_op);
4967 gen_jmp_im(pc_start - s->cs_base);
4968 tcg_gen_helper_0_1(helper_fbst_ST0, cpu_A0);
4969 tcg_gen_helper_0_0(helper_fpop);
4971 case 0x3d: /* fildll */
4972 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
4973 (s->mem_index >> 2) - 1);
4974 tcg_gen_helper_0_1(helper_fildll_ST0, cpu_tmp1_i64);
4976 case 0x3f: /* fistpll */
4977 tcg_gen_helper_1_0(helper_fistll_ST0, cpu_tmp1_i64);
4978 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
4979 (s->mem_index >> 2) - 1);
4980 tcg_gen_helper_0_0(helper_fpop);
4986 /* register float ops */
4990 case 0x08: /* fld sti */
4991 tcg_gen_helper_0_0(helper_fpush);
4992 tcg_gen_helper_0_1(helper_fmov_ST0_STN, tcg_const_i32((opreg + 1) & 7));
4994 case 0x09: /* fxchg sti */
4995 case 0x29: /* fxchg4 sti, undocumented op */
4996 case 0x39: /* fxchg7 sti, undocumented op */
4997 tcg_gen_helper_0_1(helper_fxchg_ST0_STN, tcg_const_i32(opreg));
4999 case 0x0a: /* grp d9/2 */
5002 /* check exceptions (FreeBSD FPU probe) */
5003 if (s->cc_op != CC_OP_DYNAMIC)
5004 gen_op_set_cc_op(s->cc_op);
5005 gen_jmp_im(pc_start - s->cs_base);
5006 tcg_gen_helper_0_0(helper_fwait);
5012 case 0x0c: /* grp d9/4 */
5015 tcg_gen_helper_0_0(helper_fchs_ST0);
5018 tcg_gen_helper_0_0(helper_fabs_ST0);
5021 tcg_gen_helper_0_0(helper_fldz_FT0);
5022 tcg_gen_helper_0_0(helper_fcom_ST0_FT0);
5025 tcg_gen_helper_0_0(helper_fxam_ST0);
5031 case 0x0d: /* grp d9/5 */
5035 tcg_gen_helper_0_0(helper_fpush);
5036 tcg_gen_helper_0_0(helper_fld1_ST0);
5039 tcg_gen_helper_0_0(helper_fpush);
5040 tcg_gen_helper_0_0(helper_fldl2t_ST0);
5043 tcg_gen_helper_0_0(helper_fpush);
5044 tcg_gen_helper_0_0(helper_fldl2e_ST0);
5047 tcg_gen_helper_0_0(helper_fpush);
5048 tcg_gen_helper_0_0(helper_fldpi_ST0);
5051 tcg_gen_helper_0_0(helper_fpush);
5052 tcg_gen_helper_0_0(helper_fldlg2_ST0);
5055 tcg_gen_helper_0_0(helper_fpush);
5056 tcg_gen_helper_0_0(helper_fldln2_ST0);
5059 tcg_gen_helper_0_0(helper_fpush);
5060 tcg_gen_helper_0_0(helper_fldz_ST0);
5067 case 0x0e: /* grp d9/6 */
5070 tcg_gen_helper_0_0(helper_f2xm1);
5073 tcg_gen_helper_0_0(helper_fyl2x);
5076 tcg_gen_helper_0_0(helper_fptan);
5078 case 3: /* fpatan */
5079 tcg_gen_helper_0_0(helper_fpatan);
5081 case 4: /* fxtract */
5082 tcg_gen_helper_0_0(helper_fxtract);
5084 case 5: /* fprem1 */
5085 tcg_gen_helper_0_0(helper_fprem1);
5087 case 6: /* fdecstp */
5088 tcg_gen_helper_0_0(helper_fdecstp);
5091 case 7: /* fincstp */
5092 tcg_gen_helper_0_0(helper_fincstp);
5096 case 0x0f: /* grp d9/7 */
5099 tcg_gen_helper_0_0(helper_fprem);
5101 case 1: /* fyl2xp1 */
5102 tcg_gen_helper_0_0(helper_fyl2xp1);
5105 tcg_gen_helper_0_0(helper_fsqrt);
5107 case 3: /* fsincos */
5108 tcg_gen_helper_0_0(helper_fsincos);
5110 case 5: /* fscale */
5111 tcg_gen_helper_0_0(helper_fscale);
5113 case 4: /* frndint */
5114 tcg_gen_helper_0_0(helper_frndint);
5117 tcg_gen_helper_0_0(helper_fsin);
5121 tcg_gen_helper_0_0(helper_fcos);
5125 case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
5126 case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
5127 case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
5133 tcg_gen_helper_0_1(helper_fp_arith_STN_ST0[op1], tcg_const_i32(opreg));
5135 tcg_gen_helper_0_0(helper_fpop);
5137 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5138 tcg_gen_helper_0_0(helper_fp_arith_ST0_FT0[op1]);
5142 case 0x02: /* fcom */
5143 case 0x22: /* fcom2, undocumented op */
5144 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5145 tcg_gen_helper_0_0(helper_fcom_ST0_FT0);
5147 case 0x03: /* fcomp */
5148 case 0x23: /* fcomp3, undocumented op */
5149 case 0x32: /* fcomp5, undocumented op */
5150 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5151 tcg_gen_helper_0_0(helper_fcom_ST0_FT0);
5152 tcg_gen_helper_0_0(helper_fpop);
5154 case 0x15: /* da/5 */
5156 case 1: /* fucompp */
5157 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(1));
5158 tcg_gen_helper_0_0(helper_fucom_ST0_FT0);
5159 tcg_gen_helper_0_0(helper_fpop);
5160 tcg_gen_helper_0_0(helper_fpop);
5168 case 0: /* feni (287 only, just do nop here) */
5170 case 1: /* fdisi (287 only, just do nop here) */
5173 tcg_gen_helper_0_0(helper_fclex);
5175 case 3: /* fninit */
5176 tcg_gen_helper_0_0(helper_fninit);
5178 case 4: /* fsetpm (287 only, just do nop here) */
5184 case 0x1d: /* fucomi */
5185 if (s->cc_op != CC_OP_DYNAMIC)
5186 gen_op_set_cc_op(s->cc_op);
5187 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5188 tcg_gen_helper_0_0(helper_fucomi_ST0_FT0);
5189 gen_op_fcomi_dummy();
5190 s->cc_op = CC_OP_EFLAGS;
5192 case 0x1e: /* fcomi */
5193 if (s->cc_op != CC_OP_DYNAMIC)
5194 gen_op_set_cc_op(s->cc_op);
5195 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5196 tcg_gen_helper_0_0(helper_fcomi_ST0_FT0);
5197 gen_op_fcomi_dummy();
5198 s->cc_op = CC_OP_EFLAGS;
5200 case 0x28: /* ffree sti */
5201 tcg_gen_helper_0_1(helper_ffree_STN, tcg_const_i32(opreg));
5203 case 0x2a: /* fst sti */
5204 tcg_gen_helper_0_1(helper_fmov_STN_ST0, tcg_const_i32(opreg));
5206 case 0x2b: /* fstp sti */
5207 case 0x0b: /* fstp1 sti, undocumented op */
5208 case 0x3a: /* fstp8 sti, undocumented op */
5209 case 0x3b: /* fstp9 sti, undocumented op */
5210 tcg_gen_helper_0_1(helper_fmov_STN_ST0, tcg_const_i32(opreg));
5211 tcg_gen_helper_0_0(helper_fpop);
5213 case 0x2c: /* fucom st(i) */
5214 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5215 tcg_gen_helper_0_0(helper_fucom_ST0_FT0);
5217 case 0x2d: /* fucomp st(i) */
5218 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5219 tcg_gen_helper_0_0(helper_fucom_ST0_FT0);
5220 tcg_gen_helper_0_0(helper_fpop);
5222 case 0x33: /* de/3 */
5224 case 1: /* fcompp */
5225 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(1));
5226 tcg_gen_helper_0_0(helper_fcom_ST0_FT0);
5227 tcg_gen_helper_0_0(helper_fpop);
5228 tcg_gen_helper_0_0(helper_fpop);
5234 case 0x38: /* ffreep sti, undocumented op */
5235 tcg_gen_helper_0_1(helper_ffree_STN, tcg_const_i32(opreg));
5236 tcg_gen_helper_0_0(helper_fpop);
5238 case 0x3c: /* df/4 */
5241 tcg_gen_helper_1_0(helper_fnstsw, cpu_tmp2_i32);
5242 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5243 gen_op_mov_reg_T0(OT_WORD, R_EAX);
5249 case 0x3d: /* fucomip */
5250 if (s->cc_op != CC_OP_DYNAMIC)
5251 gen_op_set_cc_op(s->cc_op);
5252 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5253 tcg_gen_helper_0_0(helper_fucomi_ST0_FT0);
5254 tcg_gen_helper_0_0(helper_fpop);
5255 gen_op_fcomi_dummy();
5256 s->cc_op = CC_OP_EFLAGS;
5258 case 0x3e: /* fcomip */
5259 if (s->cc_op != CC_OP_DYNAMIC)
5260 gen_op_set_cc_op(s->cc_op);
5261 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5262 tcg_gen_helper_0_0(helper_fcomi_ST0_FT0);
5263 tcg_gen_helper_0_0(helper_fpop);
5264 gen_op_fcomi_dummy();
5265 s->cc_op = CC_OP_EFLAGS;
5267 case 0x10 ... 0x13: /* fcmovxx */
5271 const static uint8_t fcmov_cc[8] = {
5277 op1 = fcmov_cc[op & 3] | ((op >> 3) & 1);
5279 l1 = gen_new_label();
5280 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T[0], tcg_const_tl(0), l1);
5281 tcg_gen_helper_0_1(helper_fmov_ST0_STN, tcg_const_i32(opreg));
5290 /************************/
5293 case 0xa4: /* movsS */
5298 ot = dflag + OT_WORD;
5300 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
5301 gen_repz_movs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
5307 case 0xaa: /* stosS */
5312 ot = dflag + OT_WORD;
5314 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
5315 gen_repz_stos(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
5320 case 0xac: /* lodsS */
5325 ot = dflag + OT_WORD;
5326 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
5327 gen_repz_lods(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
5332 case 0xae: /* scasS */
5337 ot = dflag + OT_WORD;
5338 if (prefixes & PREFIX_REPNZ) {
5339 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
5340 } else if (prefixes & PREFIX_REPZ) {
5341 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
5344 s->cc_op = CC_OP_SUBB + ot;
5348 case 0xa6: /* cmpsS */
5353 ot = dflag + OT_WORD;
5354 if (prefixes & PREFIX_REPNZ) {
5355 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
5356 } else if (prefixes & PREFIX_REPZ) {
5357 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
5360 s->cc_op = CC_OP_SUBB + ot;
5363 case 0x6c: /* insS */
5368 ot = dflag ? OT_LONG : OT_WORD;
5369 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
5370 gen_op_andl_T0_ffff();
5371 gen_check_io(s, ot, pc_start - s->cs_base,
5372 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes) | 4);
5373 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
5374 gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
5379 case 0x6e: /* outsS */
5384 ot = dflag ? OT_LONG : OT_WORD;
5385 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
5386 gen_op_andl_T0_ffff();
5387 gen_check_io(s, ot, pc_start - s->cs_base,
5388 svm_is_rep(prefixes) | 4);
5389 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
5390 gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
5396 /************************/
5404 ot = dflag ? OT_LONG : OT_WORD;
5405 val = ldub_code(s->pc++);
5406 gen_op_movl_T0_im(val);
5407 gen_check_io(s, ot, pc_start - s->cs_base,
5408 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
5409 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5410 tcg_gen_helper_1_1(helper_in_func[ot], cpu_T[1], cpu_tmp2_i32);
5411 gen_op_mov_reg_T1(ot, R_EAX);
5418 ot = dflag ? OT_LONG : OT_WORD;
5419 val = ldub_code(s->pc++);
5420 gen_op_movl_T0_im(val);
5421 gen_check_io(s, ot, pc_start - s->cs_base,
5422 svm_is_rep(prefixes));
5423 gen_op_mov_TN_reg(ot, 1, R_EAX);
5425 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5426 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
5427 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
5428 tcg_gen_helper_0_2(helper_out_func[ot], cpu_tmp2_i32, cpu_tmp3_i32);
5435 ot = dflag ? OT_LONG : OT_WORD;
5436 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
5437 gen_op_andl_T0_ffff();
5438 gen_check_io(s, ot, pc_start - s->cs_base,
5439 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
5440 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5441 tcg_gen_helper_1_1(helper_in_func[ot], cpu_T[1], cpu_tmp2_i32);
5442 gen_op_mov_reg_T1(ot, R_EAX);
5449 ot = dflag ? OT_LONG : OT_WORD;
5450 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
5451 gen_op_andl_T0_ffff();
5452 gen_check_io(s, ot, pc_start - s->cs_base,
5453 svm_is_rep(prefixes));
5454 gen_op_mov_TN_reg(ot, 1, R_EAX);
5456 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5457 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
5458 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
5459 tcg_gen_helper_0_2(helper_out_func[ot], cpu_tmp2_i32, cpu_tmp3_i32);
5462 /************************/
5464 case 0xc2: /* ret im */
5465 val = ldsw_code(s->pc);
5468 if (CODE64(s) && s->dflag)
5470 gen_stack_update(s, val + (2 << s->dflag));
5472 gen_op_andl_T0_ffff();
5476 case 0xc3: /* ret */
5480 gen_op_andl_T0_ffff();
5484 case 0xca: /* lret im */
5485 val = ldsw_code(s->pc);
5488 if (s->pe && !s->vm86) {
5489 if (s->cc_op != CC_OP_DYNAMIC)
5490 gen_op_set_cc_op(s->cc_op);
5491 gen_jmp_im(pc_start - s->cs_base);
5492 tcg_gen_helper_0_2(helper_lret_protected,
5493 tcg_const_i32(s->dflag),
5494 tcg_const_i32(val));
5498 gen_op_ld_T0_A0(1 + s->dflag + s->mem_index);
5500 gen_op_andl_T0_ffff();
5501 /* NOTE: keeping EIP updated is not a problem in case of
5505 gen_op_addl_A0_im(2 << s->dflag);
5506 gen_op_ld_T0_A0(1 + s->dflag + s->mem_index);
5507 gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[R_CS]));
5508 /* add stack offset */
5509 gen_stack_update(s, val + (4 << s->dflag));
5513 case 0xcb: /* lret */
5516 case 0xcf: /* iret */
5517 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_IRET))
5521 tcg_gen_helper_0_1(helper_iret_real, tcg_const_i32(s->dflag));
5522 s->cc_op = CC_OP_EFLAGS;
5523 } else if (s->vm86) {
5525 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5527 tcg_gen_helper_0_1(helper_iret_real, tcg_const_i32(s->dflag));
5528 s->cc_op = CC_OP_EFLAGS;
5531 if (s->cc_op != CC_OP_DYNAMIC)
5532 gen_op_set_cc_op(s->cc_op);
5533 gen_jmp_im(pc_start - s->cs_base);
5534 tcg_gen_helper_0_2(helper_iret_protected,
5535 tcg_const_i32(s->dflag),
5536 tcg_const_i32(s->pc - s->cs_base));
5537 s->cc_op = CC_OP_EFLAGS;
5541 case 0xe8: /* call im */
5544 tval = (int32_t)insn_get(s, OT_LONG);
5546 tval = (int16_t)insn_get(s, OT_WORD);
5547 next_eip = s->pc - s->cs_base;
5551 gen_movtl_T0_im(next_eip);
5556 case 0x9a: /* lcall im */
5558 unsigned int selector, offset;
5562 ot = dflag ? OT_LONG : OT_WORD;
5563 offset = insn_get(s, ot);
5564 selector = insn_get(s, OT_WORD);
5566 gen_op_movl_T0_im(selector);
5567 gen_op_movl_T1_imu(offset);
5570 case 0xe9: /* jmp im */
5572 tval = (int32_t)insn_get(s, OT_LONG);
5574 tval = (int16_t)insn_get(s, OT_WORD);
5575 tval += s->pc - s->cs_base;
5580 case 0xea: /* ljmp im */
5582 unsigned int selector, offset;
5586 ot = dflag ? OT_LONG : OT_WORD;
5587 offset = insn_get(s, ot);
5588 selector = insn_get(s, OT_WORD);
5590 gen_op_movl_T0_im(selector);
5591 gen_op_movl_T1_imu(offset);
5594 case 0xeb: /* jmp Jb */
5595 tval = (int8_t)insn_get(s, OT_BYTE);
5596 tval += s->pc - s->cs_base;
5601 case 0x70 ... 0x7f: /* jcc Jb */
5602 tval = (int8_t)insn_get(s, OT_BYTE);
5604 case 0x180 ... 0x18f: /* jcc Jv */
5606 tval = (int32_t)insn_get(s, OT_LONG);
5608 tval = (int16_t)insn_get(s, OT_WORD);
5611 next_eip = s->pc - s->cs_base;
5615 gen_jcc(s, b, tval, next_eip);
5618 case 0x190 ... 0x19f: /* setcc Gv */
5619 modrm = ldub_code(s->pc++);
5621 gen_ldst_modrm(s, modrm, OT_BYTE, OR_TMP0, 1);
5623 case 0x140 ... 0x14f: /* cmov Gv, Ev */
5624 ot = dflag + OT_WORD;
5625 modrm = ldub_code(s->pc++);
5626 reg = ((modrm >> 3) & 7) | rex_r;
5627 mod = (modrm >> 6) & 3;
5630 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
5631 gen_op_ld_T1_A0(ot + s->mem_index);
5633 rm = (modrm & 7) | REX_B(s);
5634 gen_op_mov_TN_reg(ot, 1, rm);
5636 gen_op_cmov_reg_T1_T0[ot - OT_WORD][reg]();
5639 /************************/
5641 case 0x9c: /* pushf */
5642 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_PUSHF))
5644 if (s->vm86 && s->iopl != 3) {
5645 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5647 if (s->cc_op != CC_OP_DYNAMIC)
5648 gen_op_set_cc_op(s->cc_op);
5649 gen_op_movl_T0_eflags();
5653 case 0x9d: /* popf */
5654 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_POPF))
5656 if (s->vm86 && s->iopl != 3) {
5657 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5662 gen_op_movl_eflags_T0_cpl0();
5664 gen_op_movw_eflags_T0_cpl0();
5667 if (s->cpl <= s->iopl) {
5669 gen_op_movl_eflags_T0_io();
5671 gen_op_movw_eflags_T0_io();
5675 gen_op_movl_eflags_T0();
5677 gen_op_movw_eflags_T0();
5682 s->cc_op = CC_OP_EFLAGS;
5683 /* abort translation because TF flag may change */
5684 gen_jmp_im(s->pc - s->cs_base);
5688 case 0x9e: /* sahf */
5691 gen_op_mov_TN_reg(OT_BYTE, 0, R_AH);
5692 if (s->cc_op != CC_OP_DYNAMIC)
5693 gen_op_set_cc_op(s->cc_op);
5694 gen_op_movb_eflags_T0();
5695 s->cc_op = CC_OP_EFLAGS;
5697 case 0x9f: /* lahf */
5700 if (s->cc_op != CC_OP_DYNAMIC)
5701 gen_op_set_cc_op(s->cc_op);
5702 gen_op_movl_T0_eflags();
5703 gen_op_mov_reg_T0(OT_BYTE, R_AH);
5705 case 0xf5: /* cmc */
5706 if (s->cc_op != CC_OP_DYNAMIC)
5707 gen_op_set_cc_op(s->cc_op);
5709 s->cc_op = CC_OP_EFLAGS;
5711 case 0xf8: /* clc */
5712 if (s->cc_op != CC_OP_DYNAMIC)
5713 gen_op_set_cc_op(s->cc_op);
5715 s->cc_op = CC_OP_EFLAGS;
5717 case 0xf9: /* stc */
5718 if (s->cc_op != CC_OP_DYNAMIC)
5719 gen_op_set_cc_op(s->cc_op);
5721 s->cc_op = CC_OP_EFLAGS;
5723 case 0xfc: /* cld */
5724 tcg_gen_movi_i32(cpu_tmp2_i32, 1);
5725 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUState, df));
5727 case 0xfd: /* std */
5728 tcg_gen_movi_i32(cpu_tmp2_i32, -1);
5729 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUState, df));
5732 /************************/
5733 /* bit operations */
5734 case 0x1ba: /* bt/bts/btr/btc Gv, im */
5735 ot = dflag + OT_WORD;
5736 modrm = ldub_code(s->pc++);
5737 op = (modrm >> 3) & 7;
5738 mod = (modrm >> 6) & 3;
5739 rm = (modrm & 7) | REX_B(s);
5742 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
5743 gen_op_ld_T0_A0(ot + s->mem_index);
5745 gen_op_mov_TN_reg(ot, 0, rm);
5748 val = ldub_code(s->pc++);
5749 gen_op_movl_T1_im(val);
5754 case 0x1a3: /* bt Gv, Ev */
5757 case 0x1ab: /* bts */
5760 case 0x1b3: /* btr */
5763 case 0x1bb: /* btc */
5766 ot = dflag + OT_WORD;
5767 modrm = ldub_code(s->pc++);
5768 reg = ((modrm >> 3) & 7) | rex_r;
5769 mod = (modrm >> 6) & 3;
5770 rm = (modrm & 7) | REX_B(s);
5771 gen_op_mov_TN_reg(OT_LONG, 1, reg);
5773 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
5774 /* specific case: we need to add a displacement */
5775 gen_exts(ot, cpu_T[1]);
5776 tcg_gen_sari_tl(cpu_tmp0, cpu_T[1], 3 + ot);
5777 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, ot);
5778 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
5779 gen_op_ld_T0_A0(ot + s->mem_index);
5781 gen_op_mov_TN_reg(ot, 0, rm);
5784 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], (1 << (3 + ot)) - 1);
5787 tcg_gen_shr_tl(cpu_cc_src, cpu_T[0], cpu_T[1]);
5788 tcg_gen_movi_tl(cpu_cc_dst, 0);
5791 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
5792 tcg_gen_movi_tl(cpu_tmp0, 1);
5793 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
5794 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
5797 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
5798 tcg_gen_movi_tl(cpu_tmp0, 1);
5799 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
5800 tcg_gen_not_tl(cpu_tmp0, cpu_tmp0);
5801 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
5805 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
5806 tcg_gen_movi_tl(cpu_tmp0, 1);
5807 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
5808 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
5811 s->cc_op = CC_OP_SARB + ot;
5814 gen_op_st_T0_A0(ot + s->mem_index);
5816 gen_op_mov_reg_T0(ot, rm);
5817 tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
5818 tcg_gen_movi_tl(cpu_cc_dst, 0);
5821 case 0x1bc: /* bsf */
5822 case 0x1bd: /* bsr */
5825 ot = dflag + OT_WORD;
5826 modrm = ldub_code(s->pc++);
5827 reg = ((modrm >> 3) & 7) | rex_r;
5828 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
5829 gen_extu(ot, cpu_T[0]);
5830 label1 = gen_new_label();
5831 tcg_gen_movi_tl(cpu_cc_dst, 0);
5832 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T[0], tcg_const_tl(0), label1);
5834 tcg_gen_helper_1_1(helper_bsr, cpu_T[0], cpu_T[0]);
5836 tcg_gen_helper_1_1(helper_bsf, cpu_T[0], cpu_T[0]);
5838 gen_op_mov_reg_T0(ot, reg);
5839 tcg_gen_movi_tl(cpu_cc_dst, 1);
5840 gen_set_label(label1);
5841 tcg_gen_discard_tl(cpu_cc_src);
5842 s->cc_op = CC_OP_LOGICB + ot;
5845 /************************/
5847 case 0x27: /* daa */
5850 if (s->cc_op != CC_OP_DYNAMIC)
5851 gen_op_set_cc_op(s->cc_op);
5853 s->cc_op = CC_OP_EFLAGS;
5855 case 0x2f: /* das */
5858 if (s->cc_op != CC_OP_DYNAMIC)
5859 gen_op_set_cc_op(s->cc_op);
5861 s->cc_op = CC_OP_EFLAGS;
5863 case 0x37: /* aaa */
5866 if (s->cc_op != CC_OP_DYNAMIC)
5867 gen_op_set_cc_op(s->cc_op);
5869 s->cc_op = CC_OP_EFLAGS;
5871 case 0x3f: /* aas */
5874 if (s->cc_op != CC_OP_DYNAMIC)
5875 gen_op_set_cc_op(s->cc_op);
5877 s->cc_op = CC_OP_EFLAGS;
5879 case 0xd4: /* aam */
5882 val = ldub_code(s->pc++);
5884 gen_exception(s, EXCP00_DIVZ, pc_start - s->cs_base);
5887 s->cc_op = CC_OP_LOGICB;
5890 case 0xd5: /* aad */
5893 val = ldub_code(s->pc++);
5895 s->cc_op = CC_OP_LOGICB;
5897 /************************/
5899 case 0x90: /* nop */
5900 /* XXX: xchg + rex handling */
5901 /* XXX: correct lock test for all insn */
5902 if (prefixes & PREFIX_LOCK)
5904 if (prefixes & PREFIX_REPZ) {
5905 gen_svm_check_intercept(s, pc_start, SVM_EXIT_PAUSE);
5908 case 0x9b: /* fwait */
5909 if ((s->flags & (HF_MP_MASK | HF_TS_MASK)) ==
5910 (HF_MP_MASK | HF_TS_MASK)) {
5911 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
5913 if (s->cc_op != CC_OP_DYNAMIC)
5914 gen_op_set_cc_op(s->cc_op);
5915 gen_jmp_im(pc_start - s->cs_base);
5916 tcg_gen_helper_0_0(helper_fwait);
5919 case 0xcc: /* int3 */
5920 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_SWINT))
5922 gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base);
5924 case 0xcd: /* int N */
5925 val = ldub_code(s->pc++);
5926 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_SWINT))
5928 if (s->vm86 && s->iopl != 3) {
5929 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5931 gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base);
5934 case 0xce: /* into */
5937 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_SWINT))
5939 if (s->cc_op != CC_OP_DYNAMIC)
5940 gen_op_set_cc_op(s->cc_op);
5941 gen_jmp_im(pc_start - s->cs_base);
5942 gen_op_into(s->pc - pc_start);
5944 case 0xf1: /* icebp (undocumented, exits to external debugger) */
5945 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_ICEBP))
5948 gen_debug(s, pc_start - s->cs_base);
5951 tb_flush(cpu_single_env);
5952 cpu_set_log(CPU_LOG_INT | CPU_LOG_TB_IN_ASM);
5955 case 0xfa: /* cli */
5957 if (s->cpl <= s->iopl) {
5958 tcg_gen_helper_0_0(helper_cli);
5960 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5964 tcg_gen_helper_0_0(helper_cli);
5966 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5970 case 0xfb: /* sti */
5972 if (s->cpl <= s->iopl) {
5974 tcg_gen_helper_0_0(helper_sti);
5975 /* interruptions are enabled only the first insn after sti */
5976 /* If several instructions disable interrupts, only the
5978 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
5979 tcg_gen_helper_0_0(helper_set_inhibit_irq);
5980 /* give a chance to handle pending irqs */
5981 gen_jmp_im(s->pc - s->cs_base);
5984 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5990 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5994 case 0x62: /* bound */
5997 ot = dflag ? OT_LONG : OT_WORD;
5998 modrm = ldub_code(s->pc++);
5999 reg = (modrm >> 3) & 7;
6000 mod = (modrm >> 6) & 3;
6003 gen_op_mov_TN_reg(ot, 0, reg);
6004 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6005 gen_jmp_im(pc_start - s->cs_base);
6006 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6008 tcg_gen_helper_0_2(helper_boundw, cpu_A0, cpu_tmp2_i32);
6010 tcg_gen_helper_0_2(helper_boundl, cpu_A0, cpu_tmp2_i32);
6012 case 0x1c8 ... 0x1cf: /* bswap reg */
6013 reg = (b & 7) | REX_B(s);
6014 #ifdef TARGET_X86_64
6016 gen_op_mov_TN_reg(OT_QUAD, 0, reg);
6017 tcg_gen_bswap_i64(cpu_T[0], cpu_T[0]);
6018 gen_op_mov_reg_T0(OT_QUAD, reg);
6022 gen_op_mov_TN_reg(OT_LONG, 0, reg);
6024 tmp0 = tcg_temp_new(TCG_TYPE_I32);
6025 tcg_gen_trunc_i64_i32(tmp0, cpu_T[0]);
6026 tcg_gen_bswap_i32(tmp0, tmp0);
6027 tcg_gen_extu_i32_i64(cpu_T[0], tmp0);
6028 gen_op_mov_reg_T0(OT_LONG, reg);
6032 gen_op_mov_TN_reg(OT_LONG, 0, reg);
6033 tcg_gen_bswap_i32(cpu_T[0], cpu_T[0]);
6034 gen_op_mov_reg_T0(OT_LONG, reg);
6038 case 0xd6: /* salc */
6041 if (s->cc_op != CC_OP_DYNAMIC)
6042 gen_op_set_cc_op(s->cc_op);
6045 case 0xe0: /* loopnz */
6046 case 0xe1: /* loopz */
6047 if (s->cc_op != CC_OP_DYNAMIC)
6048 gen_op_set_cc_op(s->cc_op);
6050 case 0xe2: /* loop */
6051 case 0xe3: /* jecxz */
6055 tval = (int8_t)insn_get(s, OT_BYTE);
6056 next_eip = s->pc - s->cs_base;
6061 l1 = gen_new_label();
6062 l2 = gen_new_label();
6065 gen_op_jz_ecx[s->aflag](l1);
6067 gen_op_dec_ECX[s->aflag]();
6070 gen_op_loop[s->aflag][b](l1);
6073 gen_jmp_im(next_eip);
6074 gen_op_jmp_label(l2);
6081 case 0x130: /* wrmsr */
6082 case 0x132: /* rdmsr */
6084 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6088 retval = gen_svm_check_intercept_param(s, pc_start, SVM_EXIT_MSR, 0);
6089 tcg_gen_helper_0_0(helper_rdmsr);
6091 retval = gen_svm_check_intercept_param(s, pc_start, SVM_EXIT_MSR, 1);
6092 tcg_gen_helper_0_0(helper_wrmsr);
6098 case 0x131: /* rdtsc */
6099 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_RDTSC))
6101 gen_jmp_im(pc_start - s->cs_base);
6102 tcg_gen_helper_0_0(helper_rdtsc);
6104 case 0x133: /* rdpmc */
6105 gen_jmp_im(pc_start - s->cs_base);
6106 tcg_gen_helper_0_0(helper_rdpmc);
6108 case 0x134: /* sysenter */
6112 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6114 if (s->cc_op != CC_OP_DYNAMIC) {
6115 gen_op_set_cc_op(s->cc_op);
6116 s->cc_op = CC_OP_DYNAMIC;
6118 gen_jmp_im(pc_start - s->cs_base);
6119 tcg_gen_helper_0_0(helper_sysenter);
6123 case 0x135: /* sysexit */
6127 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6129 if (s->cc_op != CC_OP_DYNAMIC) {
6130 gen_op_set_cc_op(s->cc_op);
6131 s->cc_op = CC_OP_DYNAMIC;
6133 gen_jmp_im(pc_start - s->cs_base);
6134 tcg_gen_helper_0_0(helper_sysexit);
6138 #ifdef TARGET_X86_64
6139 case 0x105: /* syscall */
6140 /* XXX: is it usable in real mode ? */
6141 if (s->cc_op != CC_OP_DYNAMIC) {
6142 gen_op_set_cc_op(s->cc_op);
6143 s->cc_op = CC_OP_DYNAMIC;
6145 gen_jmp_im(pc_start - s->cs_base);
6146 tcg_gen_helper_0_1(helper_syscall, tcg_const_i32(s->pc - pc_start));
6149 case 0x107: /* sysret */
6151 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6153 if (s->cc_op != CC_OP_DYNAMIC) {
6154 gen_op_set_cc_op(s->cc_op);
6155 s->cc_op = CC_OP_DYNAMIC;
6157 gen_jmp_im(pc_start - s->cs_base);
6158 tcg_gen_helper_0_1(helper_sysret, tcg_const_i32(s->dflag));
6159 /* condition codes are modified only in long mode */
6161 s->cc_op = CC_OP_EFLAGS;
6166 case 0x1a2: /* cpuid */
6167 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_CPUID))
6169 tcg_gen_helper_0_0(helper_cpuid);
6171 case 0xf4: /* hlt */
6173 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6175 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_HLT))
6177 if (s->cc_op != CC_OP_DYNAMIC)
6178 gen_op_set_cc_op(s->cc_op);
6179 gen_jmp_im(s->pc - s->cs_base);
6180 tcg_gen_helper_0_0(helper_hlt);
6185 modrm = ldub_code(s->pc++);
6186 mod = (modrm >> 6) & 3;
6187 op = (modrm >> 3) & 7;
6190 if (!s->pe || s->vm86)
6192 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ))
6194 gen_op_movl_T0_env(offsetof(CPUX86State,ldt.selector));
6198 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
6201 if (!s->pe || s->vm86)
6204 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6206 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE))
6208 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
6209 gen_jmp_im(pc_start - s->cs_base);
6210 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6211 tcg_gen_helper_0_1(helper_lldt, cpu_tmp2_i32);
6215 if (!s->pe || s->vm86)
6217 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ))
6219 gen_op_movl_T0_env(offsetof(CPUX86State,tr.selector));
6223 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
6226 if (!s->pe || s->vm86)
6229 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6231 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE))
6233 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
6234 gen_jmp_im(pc_start - s->cs_base);
6235 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6236 tcg_gen_helper_0_1(helper_ltr, cpu_tmp2_i32);
6241 if (!s->pe || s->vm86)
6243 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
6244 if (s->cc_op != CC_OP_DYNAMIC)
6245 gen_op_set_cc_op(s->cc_op);
6250 s->cc_op = CC_OP_EFLAGS;
6257 modrm = ldub_code(s->pc++);
6258 mod = (modrm >> 6) & 3;
6259 op = (modrm >> 3) & 7;
6265 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ))
6267 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6268 gen_op_movl_T0_env(offsetof(CPUX86State, gdt.limit));
6269 gen_op_st_T0_A0(OT_WORD + s->mem_index);
6270 gen_add_A0_im(s, 2);
6271 gen_op_movtl_T0_env(offsetof(CPUX86State, gdt.base));
6273 gen_op_andl_T0_im(0xffffff);
6274 gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
6279 case 0: /* monitor */
6280 if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) ||
6283 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_MONITOR))
6285 gen_jmp_im(pc_start - s->cs_base);
6286 #ifdef TARGET_X86_64
6287 if (s->aflag == 2) {
6288 gen_op_movq_A0_reg(R_EBX);
6289 gen_op_addq_A0_AL();
6293 gen_op_movl_A0_reg(R_EBX);
6294 gen_op_addl_A0_AL();
6296 gen_op_andl_A0_ffff();
6298 gen_add_A0_ds_seg(s);
6299 tcg_gen_helper_0_1(helper_monitor, cpu_A0);
6302 if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) ||
6305 if (s->cc_op != CC_OP_DYNAMIC) {
6306 gen_op_set_cc_op(s->cc_op);
6307 s->cc_op = CC_OP_DYNAMIC;
6309 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_MWAIT))
6311 gen_jmp_im(s->pc - s->cs_base);
6312 tcg_gen_helper_0_0(helper_mwait);
6319 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ))
6321 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6322 gen_op_movl_T0_env(offsetof(CPUX86State, idt.limit));
6323 gen_op_st_T0_A0(OT_WORD + s->mem_index);
6324 gen_add_A0_im(s, 2);
6325 gen_op_movtl_T0_env(offsetof(CPUX86State, idt.base));
6327 gen_op_andl_T0_im(0xffffff);
6328 gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
6336 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_VMRUN))
6338 if (s->cc_op != CC_OP_DYNAMIC)
6339 gen_op_set_cc_op(s->cc_op);
6340 gen_jmp_im(s->pc - s->cs_base);
6341 tcg_gen_helper_0_0(helper_vmrun);
6342 s->cc_op = CC_OP_EFLAGS;
6345 case 1: /* VMMCALL */
6346 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_VMMCALL))
6348 /* FIXME: cause #UD if hflags & SVM */
6349 tcg_gen_helper_0_0(helper_vmmcall);
6351 case 2: /* VMLOAD */
6352 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_VMLOAD))
6354 tcg_gen_helper_0_0(helper_vmload);
6356 case 3: /* VMSAVE */
6357 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_VMSAVE))
6359 tcg_gen_helper_0_0(helper_vmsave);
6362 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_STGI))
6364 tcg_gen_helper_0_0(helper_stgi);
6367 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_CLGI))
6369 tcg_gen_helper_0_0(helper_clgi);
6371 case 6: /* SKINIT */
6372 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_SKINIT))
6374 tcg_gen_helper_0_0(helper_skinit);
6376 case 7: /* INVLPGA */
6377 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_INVLPGA))
6379 tcg_gen_helper_0_0(helper_invlpga);
6384 } else if (s->cpl != 0) {
6385 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6387 if (gen_svm_check_intercept(s, pc_start,
6388 op==2 ? SVM_EXIT_GDTR_WRITE : SVM_EXIT_IDTR_WRITE))
6390 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6391 gen_op_ld_T1_A0(OT_WORD + s->mem_index);
6392 gen_add_A0_im(s, 2);
6393 gen_op_ld_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
6395 gen_op_andl_T0_im(0xffffff);
6397 gen_op_movtl_env_T0(offsetof(CPUX86State,gdt.base));
6398 gen_op_movl_env_T1(offsetof(CPUX86State,gdt.limit));
6400 gen_op_movtl_env_T0(offsetof(CPUX86State,idt.base));
6401 gen_op_movl_env_T1(offsetof(CPUX86State,idt.limit));
6406 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR0))
6408 gen_op_movl_T0_env(offsetof(CPUX86State,cr[0]));
6409 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 1);
6413 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6415 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0))
6417 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
6418 tcg_gen_helper_0_1(helper_lmsw, cpu_T[0]);
6419 gen_jmp_im(s->pc - s->cs_base);
6423 case 7: /* invlpg */
6425 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6428 #ifdef TARGET_X86_64
6429 if (CODE64(s) && rm == 0) {
6431 gen_op_movtl_T0_env(offsetof(CPUX86State,segs[R_GS].base));
6432 gen_op_movtl_T1_env(offsetof(CPUX86State,kernelgsbase));
6433 gen_op_movtl_env_T1(offsetof(CPUX86State,segs[R_GS].base));
6434 gen_op_movtl_env_T0(offsetof(CPUX86State,kernelgsbase));
6441 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_INVLPG))
6443 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6444 tcg_gen_helper_0_1(helper_invlpg, cpu_A0);
6445 gen_jmp_im(s->pc - s->cs_base);
6454 case 0x108: /* invd */
6455 case 0x109: /* wbinvd */
6457 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6459 if (gen_svm_check_intercept(s, pc_start, (b & 2) ? SVM_EXIT_INVD : SVM_EXIT_WBINVD))
6464 case 0x63: /* arpl or movslS (x86_64) */
6465 #ifdef TARGET_X86_64
6468 /* d_ot is the size of destination */
6469 d_ot = dflag + OT_WORD;
6471 modrm = ldub_code(s->pc++);
6472 reg = ((modrm >> 3) & 7) | rex_r;
6473 mod = (modrm >> 6) & 3;
6474 rm = (modrm & 7) | REX_B(s);
6477 gen_op_mov_TN_reg(OT_LONG, 0, rm);
6479 if (d_ot == OT_QUAD)
6480 gen_op_movslq_T0_T0();
6481 gen_op_mov_reg_T0(d_ot, reg);
6483 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6484 if (d_ot == OT_QUAD) {
6485 gen_op_lds_T0_A0(OT_LONG + s->mem_index);
6487 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
6489 gen_op_mov_reg_T0(d_ot, reg);
6494 if (!s->pe || s->vm86)
6496 ot = dflag ? OT_LONG : OT_WORD;
6497 modrm = ldub_code(s->pc++);
6498 reg = (modrm >> 3) & 7;
6499 mod = (modrm >> 6) & 3;
6502 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6503 gen_op_ld_T0_A0(ot + s->mem_index);
6505 gen_op_mov_TN_reg(ot, 0, rm);
6507 gen_op_mov_TN_reg(ot, 1, reg);
6508 if (s->cc_op != CC_OP_DYNAMIC)
6509 gen_op_set_cc_op(s->cc_op);
6511 s->cc_op = CC_OP_EFLAGS;
6513 gen_op_st_T0_A0(ot + s->mem_index);
6515 gen_op_mov_reg_T0(ot, rm);
6517 gen_op_arpl_update();
6520 case 0x102: /* lar */
6521 case 0x103: /* lsl */
6522 if (!s->pe || s->vm86)
6524 ot = dflag ? OT_LONG : OT_WORD;
6525 modrm = ldub_code(s->pc++);
6526 reg = ((modrm >> 3) & 7) | rex_r;
6527 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
6528 gen_op_mov_TN_reg(ot, 1, reg);
6529 if (s->cc_op != CC_OP_DYNAMIC)
6530 gen_op_set_cc_op(s->cc_op);
6535 s->cc_op = CC_OP_EFLAGS;
6536 gen_op_mov_reg_T1(ot, reg);
6539 modrm = ldub_code(s->pc++);
6540 mod = (modrm >> 6) & 3;
6541 op = (modrm >> 3) & 7;
6543 case 0: /* prefetchnta */
6544 case 1: /* prefetchnt0 */
6545 case 2: /* prefetchnt0 */
6546 case 3: /* prefetchnt0 */
6549 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6550 /* nothing more to do */
6552 default: /* nop (multi byte) */
6553 gen_nop_modrm(s, modrm);
6557 case 0x119 ... 0x11f: /* nop (multi byte) */
6558 modrm = ldub_code(s->pc++);
6559 gen_nop_modrm(s, modrm);
6561 case 0x120: /* mov reg, crN */
6562 case 0x122: /* mov crN, reg */
6564 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6566 modrm = ldub_code(s->pc++);
6567 if ((modrm & 0xc0) != 0xc0)
6569 rm = (modrm & 7) | REX_B(s);
6570 reg = ((modrm >> 3) & 7) | rex_r;
6582 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0 + reg);
6583 gen_op_mov_TN_reg(ot, 0, rm);
6584 tcg_gen_helper_0_2(helper_movl_crN_T0,
6585 tcg_const_i32(reg), cpu_T[0]);
6586 gen_jmp_im(s->pc - s->cs_base);
6589 gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR0 + reg);
6590 #if !defined(CONFIG_USER_ONLY)
6592 tcg_gen_helper_1_0(helper_movtl_T0_cr8, cpu_T[0]);
6595 gen_op_movtl_T0_env(offsetof(CPUX86State,cr[reg]));
6596 gen_op_mov_reg_T0(ot, rm);
6604 case 0x121: /* mov reg, drN */
6605 case 0x123: /* mov drN, reg */
6607 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6609 modrm = ldub_code(s->pc++);
6610 if ((modrm & 0xc0) != 0xc0)
6612 rm = (modrm & 7) | REX_B(s);
6613 reg = ((modrm >> 3) & 7) | rex_r;
6618 /* XXX: do it dynamically with CR4.DE bit */
6619 if (reg == 4 || reg == 5 || reg >= 8)
6622 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_DR0 + reg);
6623 gen_op_mov_TN_reg(ot, 0, rm);
6624 tcg_gen_helper_0_2(helper_movl_drN_T0,
6625 tcg_const_i32(reg), cpu_T[0]);
6626 gen_jmp_im(s->pc - s->cs_base);
6629 gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_DR0 + reg);
6630 gen_op_movtl_T0_env(offsetof(CPUX86State,dr[reg]));
6631 gen_op_mov_reg_T0(ot, rm);
6635 case 0x106: /* clts */
6637 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6639 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0);
6640 tcg_gen_helper_0_0(helper_clts);
6641 /* abort block because static cpu state changed */
6642 gen_jmp_im(s->pc - s->cs_base);
6646 /* MMX/3DNow!/SSE/SSE2/SSE3 support */
6647 case 0x1c3: /* MOVNTI reg, mem */
6648 if (!(s->cpuid_features & CPUID_SSE2))
6650 ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
6651 modrm = ldub_code(s->pc++);
6652 mod = (modrm >> 6) & 3;
6655 reg = ((modrm >> 3) & 7) | rex_r;
6656 /* generate a generic store */
6657 gen_ldst_modrm(s, modrm, ot, reg, 1);
6660 modrm = ldub_code(s->pc++);
6661 mod = (modrm >> 6) & 3;
6662 op = (modrm >> 3) & 7;
6664 case 0: /* fxsave */
6665 if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) ||
6666 (s->flags & HF_EM_MASK))
6668 if (s->flags & HF_TS_MASK) {
6669 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
6672 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6673 if (s->cc_op != CC_OP_DYNAMIC)
6674 gen_op_set_cc_op(s->cc_op);
6675 gen_jmp_im(pc_start - s->cs_base);
6676 tcg_gen_helper_0_2(helper_fxsave,
6677 cpu_A0, tcg_const_i32((s->dflag == 2)));
6679 case 1: /* fxrstor */
6680 if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) ||
6681 (s->flags & HF_EM_MASK))
6683 if (s->flags & HF_TS_MASK) {
6684 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
6687 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6688 if (s->cc_op != CC_OP_DYNAMIC)
6689 gen_op_set_cc_op(s->cc_op);
6690 gen_jmp_im(pc_start - s->cs_base);
6691 tcg_gen_helper_0_2(helper_fxrstor,
6692 cpu_A0, tcg_const_i32((s->dflag == 2)));
6694 case 2: /* ldmxcsr */
6695 case 3: /* stmxcsr */
6696 if (s->flags & HF_TS_MASK) {
6697 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
6700 if ((s->flags & HF_EM_MASK) || !(s->flags & HF_OSFXSR_MASK) ||
6703 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6705 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
6706 gen_op_movl_env_T0(offsetof(CPUX86State, mxcsr));
6708 gen_op_movl_T0_env(offsetof(CPUX86State, mxcsr));
6709 gen_op_st_T0_A0(OT_LONG + s->mem_index);
6712 case 5: /* lfence */
6713 case 6: /* mfence */
6714 if ((modrm & 0xc7) != 0xc0 || !(s->cpuid_features & CPUID_SSE))
6717 case 7: /* sfence / clflush */
6718 if ((modrm & 0xc7) == 0xc0) {
6720 /* XXX: also check for cpuid_ext2_features & CPUID_EXT2_EMMX */
6721 if (!(s->cpuid_features & CPUID_SSE))
6725 if (!(s->cpuid_features & CPUID_CLFLUSH))
6727 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6734 case 0x10d: /* 3DNow! prefetch(w) */
6735 modrm = ldub_code(s->pc++);
6736 mod = (modrm >> 6) & 3;
6739 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6740 /* ignore for now */
6742 case 0x1aa: /* rsm */
6743 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_RSM))
6745 if (!(s->flags & HF_SMM_MASK))
6747 if (s->cc_op != CC_OP_DYNAMIC) {
6748 gen_op_set_cc_op(s->cc_op);
6749 s->cc_op = CC_OP_DYNAMIC;
6751 gen_jmp_im(s->pc - s->cs_base);
6752 tcg_gen_helper_0_0(helper_rsm);
6755 case 0x10e ... 0x10f:
6756 /* 3DNow! instructions, ignore prefixes */
6757 s->prefix &= ~(PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA);
6758 case 0x110 ... 0x117:
6759 case 0x128 ... 0x12f:
6760 case 0x150 ... 0x177:
6761 case 0x17c ... 0x17f:
6763 case 0x1c4 ... 0x1c6:
6764 case 0x1d0 ... 0x1fe:
6765 gen_sse(s, b, pc_start, rex_r);
6770 /* lock generation */
6771 if (s->prefix & PREFIX_LOCK)
6772 tcg_gen_helper_0_0(helper_unlock);
6775 if (s->prefix & PREFIX_LOCK)
6776 tcg_gen_helper_0_0(helper_unlock);
6777 /* XXX: ensure that no lock was generated */
6778 gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
6782 static void tcg_macro_func(TCGContext *s, int macro_id, const int *dead_args)
6787 tcg_gen_helper_0_1(helper_divl_EAX_T0, cpu_T[0]);
6793 void optimize_flags_init(void)
6795 #if TCG_TARGET_REG_BITS == 32
6796 assert(sizeof(CCTable) == (1 << 3));
6798 assert(sizeof(CCTable) == (1 << 4));
6800 tcg_set_macro_func(&tcg_ctx, tcg_macro_func);
6802 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
6803 #if TARGET_LONG_BITS > HOST_LONG_BITS
6804 cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
6805 TCG_AREG0, offsetof(CPUState, t0), "T0");
6806 cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
6807 TCG_AREG0, offsetof(CPUState, t1), "T1");
6808 cpu_A0 = tcg_global_mem_new(TCG_TYPE_TL,
6809 TCG_AREG0, offsetof(CPUState, t2), "A0");
6811 cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
6812 cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
6813 cpu_A0 = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "A0");
6815 cpu_T3 = tcg_global_mem_new(TCG_TYPE_TL,
6816 TCG_AREG0, offsetof(CPUState, t3), "T3");
6817 #if defined(__i386__) && (TARGET_LONG_BITS <= HOST_LONG_BITS)
6818 /* XXX: must be suppressed once there are less fixed registers */
6819 cpu_tmp1_i64 = tcg_global_reg2_new_hack(TCG_TYPE_I64, TCG_AREG1, TCG_AREG2, "tmp1");
6821 cpu_cc_op = tcg_global_mem_new(TCG_TYPE_I32,
6822 TCG_AREG0, offsetof(CPUState, cc_op), "cc_op");
6823 cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL,
6824 TCG_AREG0, offsetof(CPUState, cc_src), "cc_src");
6825 cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL,
6826 TCG_AREG0, offsetof(CPUState, cc_dst), "cc_dst");
6829 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
6830 basic block 'tb'. If search_pc is TRUE, also generate PC
6831 information for each intermediate instruction. */
6832 static inline int gen_intermediate_code_internal(CPUState *env,
6833 TranslationBlock *tb,
6836 DisasContext dc1, *dc = &dc1;
6837 target_ulong pc_ptr;
6838 uint16_t *gen_opc_end;
6841 target_ulong pc_start;
6842 target_ulong cs_base;
6844 /* generate intermediate code */
6846 cs_base = tb->cs_base;
6848 cflags = tb->cflags;
6850 dc->pe = (flags >> HF_PE_SHIFT) & 1;
6851 dc->code32 = (flags >> HF_CS32_SHIFT) & 1;
6852 dc->ss32 = (flags >> HF_SS32_SHIFT) & 1;
6853 dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1;
6855 dc->vm86 = (flags >> VM_SHIFT) & 1;
6856 dc->cpl = (flags >> HF_CPL_SHIFT) & 3;
6857 dc->iopl = (flags >> IOPL_SHIFT) & 3;
6858 dc->tf = (flags >> TF_SHIFT) & 1;
6859 dc->singlestep_enabled = env->singlestep_enabled;
6860 dc->cc_op = CC_OP_DYNAMIC;
6861 dc->cs_base = cs_base;
6863 dc->popl_esp_hack = 0;
6864 /* select memory access functions */
6866 if (flags & HF_SOFTMMU_MASK) {
6868 dc->mem_index = 2 * 4;
6870 dc->mem_index = 1 * 4;
6872 dc->cpuid_features = env->cpuid_features;
6873 dc->cpuid_ext_features = env->cpuid_ext_features;
6874 dc->cpuid_ext2_features = env->cpuid_ext2_features;
6875 #ifdef TARGET_X86_64
6876 dc->lma = (flags >> HF_LMA_SHIFT) & 1;
6877 dc->code64 = (flags >> HF_CS64_SHIFT) & 1;
6880 dc->jmp_opt = !(dc->tf || env->singlestep_enabled ||
6881 (flags & HF_INHIBIT_IRQ_MASK)
6882 #ifndef CONFIG_SOFTMMU
6883 || (flags & HF_SOFTMMU_MASK)
6887 /* check addseg logic */
6888 if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32))
6889 printf("ERROR addseg\n");
6892 cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL);
6893 #if !(defined(__i386__) && (TARGET_LONG_BITS <= HOST_LONG_BITS))
6894 cpu_tmp1_i64 = tcg_temp_new(TCG_TYPE_I64);
6896 cpu_tmp2_i32 = tcg_temp_new(TCG_TYPE_I32);
6897 cpu_tmp3_i32 = tcg_temp_new(TCG_TYPE_I32);
6898 cpu_tmp4 = tcg_temp_new(TCG_TYPE_TL);
6899 cpu_tmp5 = tcg_temp_new(TCG_TYPE_TL);
6900 cpu_tmp6 = tcg_temp_new(TCG_TYPE_TL);
6901 cpu_ptr0 = tcg_temp_new(TCG_TYPE_PTR);
6902 cpu_ptr1 = tcg_temp_new(TCG_TYPE_PTR);
6904 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
6906 dc->is_jmp = DISAS_NEXT;
6911 if (env->nb_breakpoints > 0) {
6912 for(j = 0; j < env->nb_breakpoints; j++) {
6913 if (env->breakpoints[j] == pc_ptr) {
6914 gen_debug(dc, pc_ptr - dc->cs_base);
6920 j = gen_opc_ptr - gen_opc_buf;
6924 gen_opc_instr_start[lj++] = 0;
6926 gen_opc_pc[lj] = pc_ptr;
6927 gen_opc_cc_op[lj] = dc->cc_op;
6928 gen_opc_instr_start[lj] = 1;
6930 pc_ptr = disas_insn(dc, pc_ptr);
6931 /* stop translation if indicated */
6934 /* if single step mode, we generate only one instruction and
6935 generate an exception */
6936 /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
6937 the flag and abort the translation to give the irqs a
6938 change to be happen */
6939 if (dc->tf || dc->singlestep_enabled ||
6940 (flags & HF_INHIBIT_IRQ_MASK) ||
6941 (cflags & CF_SINGLE_INSN)) {
6942 gen_jmp_im(pc_ptr - dc->cs_base);
6946 /* if too long translation, stop generation too */
6947 if (gen_opc_ptr >= gen_opc_end ||
6948 (pc_ptr - pc_start) >= (TARGET_PAGE_SIZE - 32)) {
6949 gen_jmp_im(pc_ptr - dc->cs_base);
6954 *gen_opc_ptr = INDEX_op_end;
6955 /* we don't forget to fill the last values */
6957 j = gen_opc_ptr - gen_opc_buf;
6960 gen_opc_instr_start[lj++] = 0;
6964 if (loglevel & CPU_LOG_TB_CPU) {
6965 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
6967 if (loglevel & CPU_LOG_TB_IN_ASM) {
6969 fprintf(logfile, "----------------\n");
6970 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
6971 #ifdef TARGET_X86_64
6976 disas_flags = !dc->code32;
6977 target_disas(logfile, pc_start, pc_ptr - pc_start, disas_flags);
6978 fprintf(logfile, "\n");
6979 if (loglevel & CPU_LOG_TB_OP_OPT) {
6980 fprintf(logfile, "OP before opt:\n");
6981 tcg_dump_ops(&tcg_ctx, logfile);
6982 fprintf(logfile, "\n");
6988 tb->size = pc_ptr - pc_start;
6992 int gen_intermediate_code(CPUState *env, TranslationBlock *tb)
6994 return gen_intermediate_code_internal(env, tb, 0);
6997 int gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
6999 return gen_intermediate_code_internal(env, tb, 1);
7002 void gen_pc_load(CPUState *env, TranslationBlock *tb,
7003 unsigned long searched_pc, int pc_pos, void *puc)
7007 if (loglevel & CPU_LOG_TB_OP) {
7009 fprintf(logfile, "RESTORE:\n");
7010 for(i = 0;i <= pc_pos; i++) {
7011 if (gen_opc_instr_start[i]) {
7012 fprintf(logfile, "0x%04x: " TARGET_FMT_lx "\n", i, gen_opc_pc[i]);
7015 fprintf(logfile, "spc=0x%08lx pc_pos=0x%x eip=" TARGET_FMT_lx " cs_base=%x\n",
7016 searched_pc, pc_pos, gen_opc_pc[pc_pos] - tb->cs_base,
7017 (uint32_t)tb->cs_base);
7020 env->eip = gen_opc_pc[pc_pos] - tb->cs_base;
7021 cc_op = gen_opc_cc_op[pc_pos];
7022 if (cc_op != CC_OP_DYNAMIC)