4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
32 /* XXX: move that elsewhere */
33 static uint16_t *gen_opc_ptr;
34 static uint32_t *gen_opparam_ptr;
36 #define PREFIX_REPZ 0x01
37 #define PREFIX_REPNZ 0x02
38 #define PREFIX_LOCK 0x04
39 #define PREFIX_DATA 0x08
40 #define PREFIX_ADR 0x10
43 #define X86_64_ONLY(x) x
44 #define X86_64_DEF(x...) x
45 #define CODE64(s) ((s)->code64)
46 #define REX_X(s) ((s)->rex_x)
47 #define REX_B(s) ((s)->rex_b)
48 /* XXX: gcc generates push/pop in some opcodes, so we cannot use them */
50 #define BUGGY_64(x) NULL
53 #define X86_64_ONLY(x) NULL
54 #define X86_64_DEF(x...)
61 static int x86_64_hregs;
64 #ifdef USE_DIRECT_JUMP
67 #define TBPARAM(x) (long)(x)
70 typedef struct DisasContext {
71 /* current insn context */
72 int override; /* -1 if no override */
75 target_ulong pc; /* pc = eip + cs_base */
76 int is_jmp; /* 1 = means jump (stop translation), 2 means CPU
77 static state change (stop translation) */
78 /* current block context */
79 target_ulong cs_base; /* base of CS segment */
80 int pe; /* protected mode */
81 int code32; /* 32 bit code segment */
83 int lma; /* long mode active */
84 int code64; /* 64 bit code segment */
87 int ss32; /* 32 bit stack segment */
88 int cc_op; /* current CC operation */
89 int addseg; /* non zero if either DS/ES/SS have a non zero base */
90 int f_st; /* currently unused */
91 int vm86; /* vm86 mode */
94 int tf; /* TF cpu flag */
95 int singlestep_enabled; /* "hardware" single step enabled */
96 int jmp_opt; /* use direct block chaining for direct jumps */
97 int mem_index; /* select memory access functions */
98 int flags; /* all execution flags */
99 struct TranslationBlock *tb;
100 int popl_esp_hack; /* for correct popl with esp base handling */
101 int rip_offset; /* only used in x86_64, but left for simplicity */
105 static void gen_eob(DisasContext *s);
106 static void gen_jmp(DisasContext *s, target_ulong eip);
107 static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num);
109 /* i386 arith/logic operations */
129 OP_SHL1, /* undocumented */
134 #define DEF(s, n, copy_size) INDEX_op_ ## s,
151 /* I386 int registers */
152 OR_EAX, /* MUST be even numbered */
161 OR_TMP0 = 16, /* temporary operand register */
163 OR_A0, /* temporary register used when doing address evaluation */
168 #define NB_OP_SIZES 4
170 #define DEF_REGS(prefix, suffix) \
171 prefix ## EAX ## suffix,\
172 prefix ## ECX ## suffix,\
173 prefix ## EDX ## suffix,\
174 prefix ## EBX ## suffix,\
175 prefix ## ESP ## suffix,\
176 prefix ## EBP ## suffix,\
177 prefix ## ESI ## suffix,\
178 prefix ## EDI ## suffix,\
179 prefix ## R8 ## suffix,\
180 prefix ## R9 ## suffix,\
181 prefix ## R10 ## suffix,\
182 prefix ## R11 ## suffix,\
183 prefix ## R12 ## suffix,\
184 prefix ## R13 ## suffix,\
185 prefix ## R14 ## suffix,\
186 prefix ## R15 ## suffix,
188 #define DEF_BREGS(prefixb, prefixh, suffix) \
190 static void prefixb ## ESP ## suffix ## _wrapper(void) \
193 prefixb ## ESP ## suffix (); \
195 prefixh ## EAX ## suffix (); \
198 static void prefixb ## EBP ## suffix ## _wrapper(void) \
201 prefixb ## EBP ## suffix (); \
203 prefixh ## ECX ## suffix (); \
206 static void prefixb ## ESI ## suffix ## _wrapper(void) \
209 prefixb ## ESI ## suffix (); \
211 prefixh ## EDX ## suffix (); \
214 static void prefixb ## EDI ## suffix ## _wrapper(void) \
217 prefixb ## EDI ## suffix (); \
219 prefixh ## EBX ## suffix (); \
222 DEF_BREGS(gen_op_movb_, gen_op_movh_, _T0)
223 DEF_BREGS(gen_op_movb_, gen_op_movh_, _T1)
224 DEF_BREGS(gen_op_movl_T0_, gen_op_movh_T0_, )
225 DEF_BREGS(gen_op_movl_T1_, gen_op_movh_T1_, )
227 #else /* !TARGET_X86_64 */
229 #define NB_OP_SIZES 3
231 #define DEF_REGS(prefix, suffix) \
232 prefix ## EAX ## suffix,\
233 prefix ## ECX ## suffix,\
234 prefix ## EDX ## suffix,\
235 prefix ## EBX ## suffix,\
236 prefix ## ESP ## suffix,\
237 prefix ## EBP ## suffix,\
238 prefix ## ESI ## suffix,\
239 prefix ## EDI ## suffix,
241 #endif /* !TARGET_X86_64 */
243 static GenOpFunc *gen_op_mov_reg_T0[NB_OP_SIZES][CPU_NB_REGS] = {
250 gen_op_movb_ESP_T0_wrapper,
251 gen_op_movb_EBP_T0_wrapper,
252 gen_op_movb_ESI_T0_wrapper,
253 gen_op_movb_EDI_T0_wrapper,
270 DEF_REGS(gen_op_movw_, _T0)
273 DEF_REGS(gen_op_movl_, _T0)
277 DEF_REGS(gen_op_movq_, _T0)
282 static GenOpFunc *gen_op_mov_reg_T1[NB_OP_SIZES][CPU_NB_REGS] = {
289 gen_op_movb_ESP_T1_wrapper,
290 gen_op_movb_EBP_T1_wrapper,
291 gen_op_movb_ESI_T1_wrapper,
292 gen_op_movb_EDI_T1_wrapper,
309 DEF_REGS(gen_op_movw_, _T1)
312 DEF_REGS(gen_op_movl_, _T1)
316 DEF_REGS(gen_op_movq_, _T1)
321 static GenOpFunc *gen_op_mov_reg_A0[NB_OP_SIZES - 1][CPU_NB_REGS] = {
323 DEF_REGS(gen_op_movw_, _A0)
326 DEF_REGS(gen_op_movl_, _A0)
330 DEF_REGS(gen_op_movq_, _A0)
335 static GenOpFunc *gen_op_mov_TN_reg[NB_OP_SIZES][2][CPU_NB_REGS] =
344 gen_op_movl_T0_ESP_wrapper,
345 gen_op_movl_T0_EBP_wrapper,
346 gen_op_movl_T0_ESI_wrapper,
347 gen_op_movl_T0_EDI_wrapper,
369 gen_op_movl_T1_ESP_wrapper,
370 gen_op_movl_T1_EBP_wrapper,
371 gen_op_movl_T1_ESI_wrapper,
372 gen_op_movl_T1_EDI_wrapper,
391 DEF_REGS(gen_op_movl_T0_, )
394 DEF_REGS(gen_op_movl_T1_, )
399 DEF_REGS(gen_op_movl_T0_, )
402 DEF_REGS(gen_op_movl_T1_, )
408 DEF_REGS(gen_op_movl_T0_, )
411 DEF_REGS(gen_op_movl_T1_, )
417 static GenOpFunc *gen_op_movl_A0_reg[CPU_NB_REGS] = {
418 DEF_REGS(gen_op_movl_A0_, )
421 static GenOpFunc *gen_op_addl_A0_reg_sN[4][CPU_NB_REGS] = {
423 DEF_REGS(gen_op_addl_A0_, )
426 DEF_REGS(gen_op_addl_A0_, _s1)
429 DEF_REGS(gen_op_addl_A0_, _s2)
432 DEF_REGS(gen_op_addl_A0_, _s3)
437 static GenOpFunc *gen_op_movq_A0_reg[CPU_NB_REGS] = {
438 DEF_REGS(gen_op_movq_A0_, )
441 static GenOpFunc *gen_op_addq_A0_reg_sN[4][CPU_NB_REGS] = {
443 DEF_REGS(gen_op_addq_A0_, )
446 DEF_REGS(gen_op_addq_A0_, _s1)
449 DEF_REGS(gen_op_addq_A0_, _s2)
452 DEF_REGS(gen_op_addq_A0_, _s3)
457 static GenOpFunc *gen_op_cmov_reg_T1_T0[NB_OP_SIZES - 1][CPU_NB_REGS] = {
459 DEF_REGS(gen_op_cmovw_, _T1_T0)
462 DEF_REGS(gen_op_cmovl_, _T1_T0)
466 DEF_REGS(gen_op_cmovq_, _T1_T0)
471 static GenOpFunc *gen_op_arith_T0_T1_cc[8] = {
482 #define DEF_ARITHC(SUFFIX)\
484 gen_op_adcb ## SUFFIX ## _T0_T1_cc,\
485 gen_op_sbbb ## SUFFIX ## _T0_T1_cc,\
488 gen_op_adcw ## SUFFIX ## _T0_T1_cc,\
489 gen_op_sbbw ## SUFFIX ## _T0_T1_cc,\
492 gen_op_adcl ## SUFFIX ## _T0_T1_cc,\
493 gen_op_sbbl ## SUFFIX ## _T0_T1_cc,\
496 X86_64_ONLY(gen_op_adcq ## SUFFIX ## _T0_T1_cc),\
497 X86_64_ONLY(gen_op_sbbq ## SUFFIX ## _T0_T1_cc),\
500 static GenOpFunc *gen_op_arithc_T0_T1_cc[4][2] = {
504 static GenOpFunc *gen_op_arithc_mem_T0_T1_cc[3 * 4][2] = {
506 #ifndef CONFIG_USER_ONLY
512 static const int cc_op_arithb[8] = {
523 #define DEF_CMPXCHG(SUFFIX)\
524 gen_op_cmpxchgb ## SUFFIX ## _T0_T1_EAX_cc,\
525 gen_op_cmpxchgw ## SUFFIX ## _T0_T1_EAX_cc,\
526 gen_op_cmpxchgl ## SUFFIX ## _T0_T1_EAX_cc,\
527 X86_64_ONLY(gen_op_cmpxchgq ## SUFFIX ## _T0_T1_EAX_cc),
529 static GenOpFunc *gen_op_cmpxchg_T0_T1_EAX_cc[4] = {
533 static GenOpFunc *gen_op_cmpxchg_mem_T0_T1_EAX_cc[3 * 4] = {
535 #ifndef CONFIG_USER_ONLY
541 #define DEF_SHIFT(SUFFIX)\
543 gen_op_rolb ## SUFFIX ## _T0_T1_cc,\
544 gen_op_rorb ## SUFFIX ## _T0_T1_cc,\
545 gen_op_rclb ## SUFFIX ## _T0_T1_cc,\
546 gen_op_rcrb ## SUFFIX ## _T0_T1_cc,\
547 gen_op_shlb ## SUFFIX ## _T0_T1_cc,\
548 gen_op_shrb ## SUFFIX ## _T0_T1_cc,\
549 gen_op_shlb ## SUFFIX ## _T0_T1_cc,\
550 gen_op_sarb ## SUFFIX ## _T0_T1_cc,\
553 gen_op_rolw ## SUFFIX ## _T0_T1_cc,\
554 gen_op_rorw ## SUFFIX ## _T0_T1_cc,\
555 gen_op_rclw ## SUFFIX ## _T0_T1_cc,\
556 gen_op_rcrw ## SUFFIX ## _T0_T1_cc,\
557 gen_op_shlw ## SUFFIX ## _T0_T1_cc,\
558 gen_op_shrw ## SUFFIX ## _T0_T1_cc,\
559 gen_op_shlw ## SUFFIX ## _T0_T1_cc,\
560 gen_op_sarw ## SUFFIX ## _T0_T1_cc,\
563 gen_op_roll ## SUFFIX ## _T0_T1_cc,\
564 gen_op_rorl ## SUFFIX ## _T0_T1_cc,\
565 gen_op_rcll ## SUFFIX ## _T0_T1_cc,\
566 gen_op_rcrl ## SUFFIX ## _T0_T1_cc,\
567 gen_op_shll ## SUFFIX ## _T0_T1_cc,\
568 gen_op_shrl ## SUFFIX ## _T0_T1_cc,\
569 gen_op_shll ## SUFFIX ## _T0_T1_cc,\
570 gen_op_sarl ## SUFFIX ## _T0_T1_cc,\
573 X86_64_ONLY(gen_op_rolq ## SUFFIX ## _T0_T1_cc),\
574 X86_64_ONLY(gen_op_rorq ## SUFFIX ## _T0_T1_cc),\
575 X86_64_ONLY(gen_op_rclq ## SUFFIX ## _T0_T1_cc),\
576 X86_64_ONLY(gen_op_rcrq ## SUFFIX ## _T0_T1_cc),\
577 X86_64_ONLY(gen_op_shlq ## SUFFIX ## _T0_T1_cc),\
578 X86_64_ONLY(gen_op_shrq ## SUFFIX ## _T0_T1_cc),\
579 X86_64_ONLY(gen_op_shlq ## SUFFIX ## _T0_T1_cc),\
580 X86_64_ONLY(gen_op_sarq ## SUFFIX ## _T0_T1_cc),\
583 static GenOpFunc *gen_op_shift_T0_T1_cc[4][8] = {
587 static GenOpFunc *gen_op_shift_mem_T0_T1_cc[3 * 4][8] = {
589 #ifndef CONFIG_USER_ONLY
595 #define DEF_SHIFTD(SUFFIX, op)\
601 gen_op_shldw ## SUFFIX ## _T0_T1_ ## op ## _cc,\
602 gen_op_shrdw ## SUFFIX ## _T0_T1_ ## op ## _cc,\
605 gen_op_shldl ## SUFFIX ## _T0_T1_ ## op ## _cc,\
606 gen_op_shrdl ## SUFFIX ## _T0_T1_ ## op ## _cc,\
609 X86_64_DEF(gen_op_shldq ## SUFFIX ## _T0_T1_ ## op ## _cc,\
610 gen_op_shrdq ## SUFFIX ## _T0_T1_ ## op ## _cc,)\
613 static GenOpFunc1 *gen_op_shiftd_T0_T1_im_cc[4][2] = {
617 static GenOpFunc *gen_op_shiftd_T0_T1_ECX_cc[4][2] = {
621 static GenOpFunc1 *gen_op_shiftd_mem_T0_T1_im_cc[3 * 4][2] = {
623 #ifndef CONFIG_USER_ONLY
624 DEF_SHIFTD(_kernel, im)
625 DEF_SHIFTD(_user, im)
629 static GenOpFunc *gen_op_shiftd_mem_T0_T1_ECX_cc[3 * 4][2] = {
630 DEF_SHIFTD(_raw, ECX)
631 #ifndef CONFIG_USER_ONLY
632 DEF_SHIFTD(_kernel, ECX)
633 DEF_SHIFTD(_user, ECX)
637 static GenOpFunc *gen_op_btx_T0_T1_cc[3][4] = {
640 gen_op_btsw_T0_T1_cc,
641 gen_op_btrw_T0_T1_cc,
642 gen_op_btcw_T0_T1_cc,
646 gen_op_btsl_T0_T1_cc,
647 gen_op_btrl_T0_T1_cc,
648 gen_op_btcl_T0_T1_cc,
653 gen_op_btsq_T0_T1_cc,
654 gen_op_btrq_T0_T1_cc,
655 gen_op_btcq_T0_T1_cc,
660 static GenOpFunc *gen_op_add_bit_A0_T1[3] = {
661 gen_op_add_bitw_A0_T1,
662 gen_op_add_bitl_A0_T1,
663 X86_64_ONLY(gen_op_add_bitq_A0_T1),
666 static GenOpFunc *gen_op_bsx_T0_cc[3][2] = {
683 static GenOpFunc *gen_op_lds_T0_A0[3 * 4] = {
684 gen_op_ldsb_raw_T0_A0,
685 gen_op_ldsw_raw_T0_A0,
686 X86_64_ONLY(gen_op_ldsl_raw_T0_A0),
688 #ifndef CONFIG_USER_ONLY
689 gen_op_ldsb_kernel_T0_A0,
690 gen_op_ldsw_kernel_T0_A0,
691 X86_64_ONLY(gen_op_ldsl_kernel_T0_A0),
694 gen_op_ldsb_user_T0_A0,
695 gen_op_ldsw_user_T0_A0,
696 X86_64_ONLY(gen_op_ldsl_user_T0_A0),
701 static GenOpFunc *gen_op_ldu_T0_A0[3 * 4] = {
702 gen_op_ldub_raw_T0_A0,
703 gen_op_lduw_raw_T0_A0,
707 #ifndef CONFIG_USER_ONLY
708 gen_op_ldub_kernel_T0_A0,
709 gen_op_lduw_kernel_T0_A0,
713 gen_op_ldub_user_T0_A0,
714 gen_op_lduw_user_T0_A0,
720 /* sign does not matter, except for lidt/lgdt call (TODO: fix it) */
721 static GenOpFunc *gen_op_ld_T0_A0[3 * 4] = {
722 gen_op_ldub_raw_T0_A0,
723 gen_op_lduw_raw_T0_A0,
724 gen_op_ldl_raw_T0_A0,
725 X86_64_ONLY(gen_op_ldq_raw_T0_A0),
727 #ifndef CONFIG_USER_ONLY
728 gen_op_ldub_kernel_T0_A0,
729 gen_op_lduw_kernel_T0_A0,
730 gen_op_ldl_kernel_T0_A0,
731 X86_64_ONLY(gen_op_ldq_kernel_T0_A0),
733 gen_op_ldub_user_T0_A0,
734 gen_op_lduw_user_T0_A0,
735 gen_op_ldl_user_T0_A0,
736 X86_64_ONLY(gen_op_ldq_user_T0_A0),
740 static GenOpFunc *gen_op_ld_T1_A0[3 * 4] = {
741 gen_op_ldub_raw_T1_A0,
742 gen_op_lduw_raw_T1_A0,
743 gen_op_ldl_raw_T1_A0,
744 X86_64_ONLY(gen_op_ldq_raw_T1_A0),
746 #ifndef CONFIG_USER_ONLY
747 gen_op_ldub_kernel_T1_A0,
748 gen_op_lduw_kernel_T1_A0,
749 gen_op_ldl_kernel_T1_A0,
750 X86_64_ONLY(gen_op_ldq_kernel_T1_A0),
752 gen_op_ldub_user_T1_A0,
753 gen_op_lduw_user_T1_A0,
754 gen_op_ldl_user_T1_A0,
755 X86_64_ONLY(gen_op_ldq_user_T1_A0),
759 static GenOpFunc *gen_op_st_T0_A0[3 * 4] = {
760 gen_op_stb_raw_T0_A0,
761 gen_op_stw_raw_T0_A0,
762 gen_op_stl_raw_T0_A0,
763 X86_64_ONLY(gen_op_stq_raw_T0_A0),
765 #ifndef CONFIG_USER_ONLY
766 gen_op_stb_kernel_T0_A0,
767 gen_op_stw_kernel_T0_A0,
768 gen_op_stl_kernel_T0_A0,
769 X86_64_ONLY(gen_op_stq_kernel_T0_A0),
771 gen_op_stb_user_T0_A0,
772 gen_op_stw_user_T0_A0,
773 gen_op_stl_user_T0_A0,
774 X86_64_ONLY(gen_op_stq_user_T0_A0),
778 static GenOpFunc *gen_op_st_T1_A0[3 * 4] = {
780 gen_op_stw_raw_T1_A0,
781 gen_op_stl_raw_T1_A0,
782 X86_64_ONLY(gen_op_stq_raw_T1_A0),
784 #ifndef CONFIG_USER_ONLY
786 gen_op_stw_kernel_T1_A0,
787 gen_op_stl_kernel_T1_A0,
788 X86_64_ONLY(gen_op_stq_kernel_T1_A0),
791 gen_op_stw_user_T1_A0,
792 gen_op_stl_user_T1_A0,
793 X86_64_ONLY(gen_op_stq_user_T1_A0),
797 static inline void gen_jmp_im(target_ulong pc)
800 if (pc == (uint32_t)pc) {
801 gen_op_movl_eip_im(pc);
802 } else if (pc == (int32_t)pc) {
803 gen_op_movq_eip_im(pc);
805 gen_op_movq_eip_im64(pc >> 32, pc);
808 gen_op_movl_eip_im(pc);
812 static inline void gen_string_movl_A0_ESI(DisasContext *s)
816 override = s->override;
820 gen_op_movq_A0_seg(offsetof(CPUX86State,segs[override].base));
821 gen_op_addq_A0_reg_sN[0][R_ESI]();
823 gen_op_movq_A0_reg[R_ESI]();
829 if (s->addseg && override < 0)
832 gen_op_movl_A0_seg(offsetof(CPUX86State,segs[override].base));
833 gen_op_addl_A0_reg_sN[0][R_ESI]();
835 gen_op_movl_A0_reg[R_ESI]();
838 /* 16 address, always override */
841 gen_op_movl_A0_reg[R_ESI]();
842 gen_op_andl_A0_ffff();
843 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
847 static inline void gen_string_movl_A0_EDI(DisasContext *s)
851 gen_op_movq_A0_reg[R_EDI]();
856 gen_op_movl_A0_seg(offsetof(CPUX86State,segs[R_ES].base));
857 gen_op_addl_A0_reg_sN[0][R_EDI]();
859 gen_op_movl_A0_reg[R_EDI]();
862 gen_op_movl_A0_reg[R_EDI]();
863 gen_op_andl_A0_ffff();
864 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_ES].base));
868 static GenOpFunc *gen_op_movl_T0_Dshift[4] = {
869 gen_op_movl_T0_Dshiftb,
870 gen_op_movl_T0_Dshiftw,
871 gen_op_movl_T0_Dshiftl,
872 X86_64_ONLY(gen_op_movl_T0_Dshiftq),
875 static GenOpFunc1 *gen_op_jnz_ecx[3] = {
878 X86_64_ONLY(gen_op_jnz_ecxq),
881 static GenOpFunc1 *gen_op_jz_ecx[3] = {
884 X86_64_ONLY(gen_op_jz_ecxq),
887 static GenOpFunc *gen_op_dec_ECX[3] = {
890 X86_64_ONLY(gen_op_decq_ECX),
893 static GenOpFunc1 *gen_op_string_jnz_sub[2][4] = {
898 X86_64_ONLY(gen_op_jnz_subq),
904 X86_64_ONLY(gen_op_jz_subq),
908 static GenOpFunc *gen_op_in_DX_T0[3] = {
914 static GenOpFunc *gen_op_out_DX_T0[3] = {
920 static GenOpFunc *gen_op_in[3] = {
926 static GenOpFunc *gen_op_out[3] = {
932 static GenOpFunc *gen_check_io_T0[3] = {
938 static GenOpFunc *gen_check_io_DX[3] = {
944 static void gen_check_io(DisasContext *s, int ot, int use_dx, target_ulong cur_eip)
946 if (s->pe && (s->cpl > s->iopl || s->vm86)) {
947 if (s->cc_op != CC_OP_DYNAMIC)
948 gen_op_set_cc_op(s->cc_op);
951 gen_check_io_DX[ot]();
953 gen_check_io_T0[ot]();
957 static inline void gen_movs(DisasContext *s, int ot)
959 gen_string_movl_A0_ESI(s);
960 gen_op_ld_T0_A0[ot + s->mem_index]();
961 gen_string_movl_A0_EDI(s);
962 gen_op_st_T0_A0[ot + s->mem_index]();
963 gen_op_movl_T0_Dshift[ot]();
966 gen_op_addq_ESI_T0();
967 gen_op_addq_EDI_T0();
971 gen_op_addl_ESI_T0();
972 gen_op_addl_EDI_T0();
974 gen_op_addw_ESI_T0();
975 gen_op_addw_EDI_T0();
979 static inline void gen_update_cc_op(DisasContext *s)
981 if (s->cc_op != CC_OP_DYNAMIC) {
982 gen_op_set_cc_op(s->cc_op);
983 s->cc_op = CC_OP_DYNAMIC;
987 /* XXX: does not work with gdbstub "ice" single step - not a
989 static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip)
993 l1 = gen_new_label();
994 l2 = gen_new_label();
995 gen_op_jnz_ecx[s->aflag](l1);
997 gen_jmp_tb(s, next_eip, 1);
1002 static inline void gen_stos(DisasContext *s, int ot)
1004 gen_op_mov_TN_reg[OT_LONG][0][R_EAX]();
1005 gen_string_movl_A0_EDI(s);
1006 gen_op_st_T0_A0[ot + s->mem_index]();
1007 gen_op_movl_T0_Dshift[ot]();
1008 #ifdef TARGET_X86_64
1009 if (s->aflag == 2) {
1010 gen_op_addq_EDI_T0();
1014 gen_op_addl_EDI_T0();
1016 gen_op_addw_EDI_T0();
1020 static inline void gen_lods(DisasContext *s, int ot)
1022 gen_string_movl_A0_ESI(s);
1023 gen_op_ld_T0_A0[ot + s->mem_index]();
1024 gen_op_mov_reg_T0[ot][R_EAX]();
1025 gen_op_movl_T0_Dshift[ot]();
1026 #ifdef TARGET_X86_64
1027 if (s->aflag == 2) {
1028 gen_op_addq_ESI_T0();
1032 gen_op_addl_ESI_T0();
1034 gen_op_addw_ESI_T0();
1038 static inline void gen_scas(DisasContext *s, int ot)
1040 gen_op_mov_TN_reg[OT_LONG][0][R_EAX]();
1041 gen_string_movl_A0_EDI(s);
1042 gen_op_ld_T1_A0[ot + s->mem_index]();
1043 gen_op_cmpl_T0_T1_cc();
1044 gen_op_movl_T0_Dshift[ot]();
1045 #ifdef TARGET_X86_64
1046 if (s->aflag == 2) {
1047 gen_op_addq_EDI_T0();
1051 gen_op_addl_EDI_T0();
1053 gen_op_addw_EDI_T0();
1057 static inline void gen_cmps(DisasContext *s, int ot)
1059 gen_string_movl_A0_ESI(s);
1060 gen_op_ld_T0_A0[ot + s->mem_index]();
1061 gen_string_movl_A0_EDI(s);
1062 gen_op_ld_T1_A0[ot + s->mem_index]();
1063 gen_op_cmpl_T0_T1_cc();
1064 gen_op_movl_T0_Dshift[ot]();
1065 #ifdef TARGET_X86_64
1066 if (s->aflag == 2) {
1067 gen_op_addq_ESI_T0();
1068 gen_op_addq_EDI_T0();
1072 gen_op_addl_ESI_T0();
1073 gen_op_addl_EDI_T0();
1075 gen_op_addw_ESI_T0();
1076 gen_op_addw_EDI_T0();
1080 static inline void gen_ins(DisasContext *s, int ot)
1082 gen_string_movl_A0_EDI(s);
1084 gen_op_st_T0_A0[ot + s->mem_index]();
1085 gen_op_in_DX_T0[ot]();
1086 gen_op_st_T0_A0[ot + s->mem_index]();
1087 gen_op_movl_T0_Dshift[ot]();
1088 #ifdef TARGET_X86_64
1089 if (s->aflag == 2) {
1090 gen_op_addq_EDI_T0();
1094 gen_op_addl_EDI_T0();
1096 gen_op_addw_EDI_T0();
1100 static inline void gen_outs(DisasContext *s, int ot)
1102 gen_string_movl_A0_ESI(s);
1103 gen_op_ld_T0_A0[ot + s->mem_index]();
1104 gen_op_out_DX_T0[ot]();
1105 gen_op_movl_T0_Dshift[ot]();
1106 #ifdef TARGET_X86_64
1107 if (s->aflag == 2) {
1108 gen_op_addq_ESI_T0();
1112 gen_op_addl_ESI_T0();
1114 gen_op_addw_ESI_T0();
1118 /* same method as Valgrind : we generate jumps to current or next
1120 #define GEN_REPZ(op) \
1121 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1122 target_ulong cur_eip, target_ulong next_eip) \
1125 gen_update_cc_op(s); \
1126 l2 = gen_jz_ecx_string(s, next_eip); \
1127 gen_ ## op(s, ot); \
1128 gen_op_dec_ECX[s->aflag](); \
1129 /* a loop would cause two single step exceptions if ECX = 1 \
1130 before rep string_insn */ \
1132 gen_op_jz_ecx[s->aflag](l2); \
1133 gen_jmp(s, cur_eip); \
1136 #define GEN_REPZ2(op) \
1137 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1138 target_ulong cur_eip, \
1139 target_ulong next_eip, \
1143 gen_update_cc_op(s); \
1144 l2 = gen_jz_ecx_string(s, next_eip); \
1145 gen_ ## op(s, ot); \
1146 gen_op_dec_ECX[s->aflag](); \
1147 gen_op_set_cc_op(CC_OP_SUBB + ot); \
1148 gen_op_string_jnz_sub[nz][ot](l2);\
1150 gen_op_jz_ecx[s->aflag](l2); \
1151 gen_jmp(s, cur_eip); \
1173 static GenOpFunc1 *gen_jcc_sub[4][8] = {
1204 #ifdef TARGET_X86_64
1207 BUGGY_64(gen_op_jb_subq),
1209 BUGGY_64(gen_op_jbe_subq),
1212 BUGGY_64(gen_op_jl_subq),
1213 BUGGY_64(gen_op_jle_subq),
1217 static GenOpFunc1 *gen_op_loop[3][4] = {
1228 #ifdef TARGET_X86_64
1237 static GenOpFunc *gen_setcc_slow[8] = {
1248 static GenOpFunc *gen_setcc_sub[4][8] = {
1251 gen_op_setb_T0_subb,
1252 gen_op_setz_T0_subb,
1253 gen_op_setbe_T0_subb,
1254 gen_op_sets_T0_subb,
1256 gen_op_setl_T0_subb,
1257 gen_op_setle_T0_subb,
1261 gen_op_setb_T0_subw,
1262 gen_op_setz_T0_subw,
1263 gen_op_setbe_T0_subw,
1264 gen_op_sets_T0_subw,
1266 gen_op_setl_T0_subw,
1267 gen_op_setle_T0_subw,
1271 gen_op_setb_T0_subl,
1272 gen_op_setz_T0_subl,
1273 gen_op_setbe_T0_subl,
1274 gen_op_sets_T0_subl,
1276 gen_op_setl_T0_subl,
1277 gen_op_setle_T0_subl,
1279 #ifdef TARGET_X86_64
1282 gen_op_setb_T0_subq,
1283 gen_op_setz_T0_subq,
1284 gen_op_setbe_T0_subq,
1285 gen_op_sets_T0_subq,
1287 gen_op_setl_T0_subq,
1288 gen_op_setle_T0_subq,
1293 static GenOpFunc *gen_op_fp_arith_ST0_FT0[8] = {
1294 gen_op_fadd_ST0_FT0,
1295 gen_op_fmul_ST0_FT0,
1296 gen_op_fcom_ST0_FT0,
1297 gen_op_fcom_ST0_FT0,
1298 gen_op_fsub_ST0_FT0,
1299 gen_op_fsubr_ST0_FT0,
1300 gen_op_fdiv_ST0_FT0,
1301 gen_op_fdivr_ST0_FT0,
1304 /* NOTE the exception in "r" op ordering */
1305 static GenOpFunc1 *gen_op_fp_arith_STN_ST0[8] = {
1306 gen_op_fadd_STN_ST0,
1307 gen_op_fmul_STN_ST0,
1310 gen_op_fsubr_STN_ST0,
1311 gen_op_fsub_STN_ST0,
1312 gen_op_fdivr_STN_ST0,
1313 gen_op_fdiv_STN_ST0,
1316 /* if d == OR_TMP0, it means memory operand (address in A0) */
1317 static void gen_op(DisasContext *s1, int op, int ot, int d)
1319 GenOpFunc *gen_update_cc;
1322 gen_op_mov_TN_reg[ot][0][d]();
1324 gen_op_ld_T0_A0[ot + s1->mem_index]();
1329 if (s1->cc_op != CC_OP_DYNAMIC)
1330 gen_op_set_cc_op(s1->cc_op);
1332 gen_op_arithc_T0_T1_cc[ot][op - OP_ADCL]();
1333 gen_op_mov_reg_T0[ot][d]();
1335 gen_op_arithc_mem_T0_T1_cc[ot + s1->mem_index][op - OP_ADCL]();
1337 s1->cc_op = CC_OP_DYNAMIC;
1340 gen_op_addl_T0_T1();
1341 s1->cc_op = CC_OP_ADDB + ot;
1342 gen_update_cc = gen_op_update2_cc;
1345 gen_op_subl_T0_T1();
1346 s1->cc_op = CC_OP_SUBB + ot;
1347 gen_update_cc = gen_op_update2_cc;
1353 gen_op_arith_T0_T1_cc[op]();
1354 s1->cc_op = CC_OP_LOGICB + ot;
1355 gen_update_cc = gen_op_update1_cc;
1358 gen_op_cmpl_T0_T1_cc();
1359 s1->cc_op = CC_OP_SUBB + ot;
1360 gen_update_cc = NULL;
1363 if (op != OP_CMPL) {
1365 gen_op_mov_reg_T0[ot][d]();
1367 gen_op_st_T0_A0[ot + s1->mem_index]();
1369 /* the flags update must happen after the memory write (precise
1370 exception support) */
1376 /* if d == OR_TMP0, it means memory operand (address in A0) */
1377 static void gen_inc(DisasContext *s1, int ot, int d, int c)
1380 gen_op_mov_TN_reg[ot][0][d]();
1382 gen_op_ld_T0_A0[ot + s1->mem_index]();
1383 if (s1->cc_op != CC_OP_DYNAMIC)
1384 gen_op_set_cc_op(s1->cc_op);
1387 s1->cc_op = CC_OP_INCB + ot;
1390 s1->cc_op = CC_OP_DECB + ot;
1393 gen_op_mov_reg_T0[ot][d]();
1395 gen_op_st_T0_A0[ot + s1->mem_index]();
1396 gen_op_update_inc_cc();
1399 static void gen_shift(DisasContext *s1, int op, int ot, int d, int s)
1402 gen_op_mov_TN_reg[ot][0][d]();
1404 gen_op_ld_T0_A0[ot + s1->mem_index]();
1406 gen_op_mov_TN_reg[ot][1][s]();
1407 /* for zero counts, flags are not updated, so must do it dynamically */
1408 if (s1->cc_op != CC_OP_DYNAMIC)
1409 gen_op_set_cc_op(s1->cc_op);
1412 gen_op_shift_T0_T1_cc[ot][op]();
1414 gen_op_shift_mem_T0_T1_cc[ot + s1->mem_index][op]();
1416 gen_op_mov_reg_T0[ot][d]();
1417 s1->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1420 static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c)
1422 /* currently not optimized */
1423 gen_op_movl_T1_im(c);
1424 gen_shift(s1, op, ot, d, OR_TMP1);
1427 static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ptr)
1435 int mod, rm, code, override, must_add_seg;
1437 override = s->override;
1438 must_add_seg = s->addseg;
1441 mod = (modrm >> 6) & 3;
1453 code = ldub_code(s->pc++);
1454 scale = (code >> 6) & 3;
1455 index = ((code >> 3) & 7) | REX_X(s);
1462 if ((base & 7) == 5) {
1464 disp = (int32_t)ldl_code(s->pc);
1466 if (CODE64(s) && !havesib) {
1467 disp += s->pc + s->rip_offset;
1474 disp = (int8_t)ldub_code(s->pc++);
1478 disp = ldl_code(s->pc);
1484 /* for correct popl handling with esp */
1485 if (base == 4 && s->popl_esp_hack)
1486 disp += s->popl_esp_hack;
1487 #ifdef TARGET_X86_64
1488 if (s->aflag == 2) {
1489 gen_op_movq_A0_reg[base]();
1491 if ((int32_t)disp == disp)
1492 gen_op_addq_A0_im(disp);
1494 gen_op_addq_A0_im64(disp >> 32, disp);
1499 gen_op_movl_A0_reg[base]();
1501 gen_op_addl_A0_im(disp);
1504 #ifdef TARGET_X86_64
1505 if (s->aflag == 2) {
1506 if ((int32_t)disp == disp)
1507 gen_op_movq_A0_im(disp);
1509 gen_op_movq_A0_im64(disp >> 32, disp);
1513 gen_op_movl_A0_im(disp);
1516 /* XXX: index == 4 is always invalid */
1517 if (havesib && (index != 4 || scale != 0)) {
1518 #ifdef TARGET_X86_64
1519 if (s->aflag == 2) {
1520 gen_op_addq_A0_reg_sN[scale][index]();
1524 gen_op_addl_A0_reg_sN[scale][index]();
1529 if (base == R_EBP || base == R_ESP)
1534 #ifdef TARGET_X86_64
1535 if (s->aflag == 2) {
1536 gen_op_addq_A0_seg(offsetof(CPUX86State,segs[override].base));
1540 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
1547 disp = lduw_code(s->pc);
1549 gen_op_movl_A0_im(disp);
1550 rm = 0; /* avoid SS override */
1557 disp = (int8_t)ldub_code(s->pc++);
1561 disp = lduw_code(s->pc);
1567 gen_op_movl_A0_reg[R_EBX]();
1568 gen_op_addl_A0_reg_sN[0][R_ESI]();
1571 gen_op_movl_A0_reg[R_EBX]();
1572 gen_op_addl_A0_reg_sN[0][R_EDI]();
1575 gen_op_movl_A0_reg[R_EBP]();
1576 gen_op_addl_A0_reg_sN[0][R_ESI]();
1579 gen_op_movl_A0_reg[R_EBP]();
1580 gen_op_addl_A0_reg_sN[0][R_EDI]();
1583 gen_op_movl_A0_reg[R_ESI]();
1586 gen_op_movl_A0_reg[R_EDI]();
1589 gen_op_movl_A0_reg[R_EBP]();
1593 gen_op_movl_A0_reg[R_EBX]();
1597 gen_op_addl_A0_im(disp);
1598 gen_op_andl_A0_ffff();
1602 if (rm == 2 || rm == 3 || rm == 6)
1607 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
1617 /* used for LEA and MOV AX, mem */
1618 static void gen_add_A0_ds_seg(DisasContext *s)
1620 int override, must_add_seg;
1621 must_add_seg = s->addseg;
1623 if (s->override >= 0) {
1624 override = s->override;
1630 #ifdef TARGET_X86_64
1632 gen_op_addq_A0_seg(offsetof(CPUX86State,segs[override].base));
1636 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
1641 /* generate modrm memory load or store of 'reg'. TMP0 is used if reg !=
1643 static void gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_store)
1645 int mod, rm, opreg, disp;
1647 mod = (modrm >> 6) & 3;
1648 rm = (modrm & 7) | REX_B(s);
1652 gen_op_mov_TN_reg[ot][0][reg]();
1653 gen_op_mov_reg_T0[ot][rm]();
1655 gen_op_mov_TN_reg[ot][0][rm]();
1657 gen_op_mov_reg_T0[ot][reg]();
1660 gen_lea_modrm(s, modrm, &opreg, &disp);
1663 gen_op_mov_TN_reg[ot][0][reg]();
1664 gen_op_st_T0_A0[ot + s->mem_index]();
1666 gen_op_ld_T0_A0[ot + s->mem_index]();
1668 gen_op_mov_reg_T0[ot][reg]();
1673 static inline uint32_t insn_get(DisasContext *s, int ot)
1679 ret = ldub_code(s->pc);
1683 ret = lduw_code(s->pc);
1688 ret = ldl_code(s->pc);
1695 static inline int insn_const_size(unsigned int ot)
1703 static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong eip)
1705 TranslationBlock *tb;
1708 pc = s->cs_base + eip;
1710 /* NOTE: we handle the case where the TB spans two pages here */
1711 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) ||
1712 (pc & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK)) {
1713 /* jump to same page: we can use a direct jump */
1715 gen_op_goto_tb0(TBPARAM(tb));
1717 gen_op_goto_tb1(TBPARAM(tb));
1719 gen_op_movl_T0_im((long)tb + tb_num);
1722 /* jump to another page: currently not optimized */
1728 static inline void gen_jcc(DisasContext *s, int b,
1729 target_ulong val, target_ulong next_eip)
1731 TranslationBlock *tb;
1738 jcc_op = (b >> 1) & 7;
1742 /* we optimize the cmp/jcc case */
1747 func = gen_jcc_sub[s->cc_op - CC_OP_SUBB][jcc_op];
1750 /* some jumps are easy to compute */
1792 func = gen_jcc_sub[(s->cc_op - CC_OP_ADDB) % 4][jcc_op];
1795 func = gen_jcc_sub[(s->cc_op - CC_OP_ADDB) % 4][jcc_op];
1807 if (s->cc_op != CC_OP_DYNAMIC) {
1808 gen_op_set_cc_op(s->cc_op);
1809 s->cc_op = CC_OP_DYNAMIC;
1813 gen_setcc_slow[jcc_op]();
1814 func = gen_op_jnz_T0_label;
1824 l1 = gen_new_label();
1827 gen_goto_tb(s, 0, next_eip);
1830 gen_goto_tb(s, 1, val);
1835 if (s->cc_op != CC_OP_DYNAMIC) {
1836 gen_op_set_cc_op(s->cc_op);
1837 s->cc_op = CC_OP_DYNAMIC;
1839 gen_setcc_slow[jcc_op]();
1845 l1 = gen_new_label();
1846 l2 = gen_new_label();
1847 gen_op_jnz_T0_label(l1);
1848 gen_jmp_im(next_eip);
1849 gen_op_jmp_label(l2);
1857 static void gen_setcc(DisasContext *s, int b)
1863 jcc_op = (b >> 1) & 7;
1865 /* we optimize the cmp/jcc case */
1870 func = gen_setcc_sub[s->cc_op - CC_OP_SUBB][jcc_op];
1875 /* some jumps are easy to compute */
1902 func = gen_setcc_sub[(s->cc_op - CC_OP_ADDB) % 4][jcc_op];
1905 func = gen_setcc_sub[(s->cc_op - CC_OP_ADDB) % 4][jcc_op];
1913 if (s->cc_op != CC_OP_DYNAMIC)
1914 gen_op_set_cc_op(s->cc_op);
1915 func = gen_setcc_slow[jcc_op];
1924 /* move T0 to seg_reg and compute if the CPU state may change. Never
1925 call this function with seg_reg == R_CS */
1926 static void gen_movl_seg_T0(DisasContext *s, int seg_reg, target_ulong cur_eip)
1928 if (s->pe && !s->vm86) {
1929 /* XXX: optimize by finding processor state dynamically */
1930 if (s->cc_op != CC_OP_DYNAMIC)
1931 gen_op_set_cc_op(s->cc_op);
1932 gen_jmp_im(cur_eip);
1933 gen_op_movl_seg_T0(seg_reg);
1934 /* abort translation because the addseg value may change or
1935 because ss32 may change. For R_SS, translation must always
1936 stop as a special handling must be done to disable hardware
1937 interrupts for the next instruction */
1938 if (seg_reg == R_SS || (s->code32 && seg_reg < R_FS))
1941 gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[seg_reg]));
1942 if (seg_reg == R_SS)
1947 static inline void gen_stack_update(DisasContext *s, int addend)
1949 #ifdef TARGET_X86_64
1952 gen_op_addq_ESP_8();
1954 gen_op_addq_ESP_im(addend);
1959 gen_op_addl_ESP_2();
1960 else if (addend == 4)
1961 gen_op_addl_ESP_4();
1963 gen_op_addl_ESP_im(addend);
1966 gen_op_addw_ESP_2();
1967 else if (addend == 4)
1968 gen_op_addw_ESP_4();
1970 gen_op_addw_ESP_im(addend);
1974 /* generate a push. It depends on ss32, addseg and dflag */
1975 static void gen_push_T0(DisasContext *s)
1977 #ifdef TARGET_X86_64
1979 gen_op_movq_A0_reg[R_ESP]();
1982 gen_op_st_T0_A0[OT_QUAD + s->mem_index]();
1985 gen_op_st_T0_A0[OT_WORD + s->mem_index]();
1987 gen_op_movq_ESP_A0();
1991 gen_op_movl_A0_reg[R_ESP]();
1998 gen_op_movl_T1_A0();
1999 gen_op_addl_A0_SS();
2002 gen_op_andl_A0_ffff();
2003 gen_op_movl_T1_A0();
2004 gen_op_addl_A0_SS();
2006 gen_op_st_T0_A0[s->dflag + 1 + s->mem_index]();
2007 if (s->ss32 && !s->addseg)
2008 gen_op_movl_ESP_A0();
2010 gen_op_mov_reg_T1[s->ss32 + 1][R_ESP]();
2014 /* generate a push. It depends on ss32, addseg and dflag */
2015 /* slower version for T1, only used for call Ev */
2016 static void gen_push_T1(DisasContext *s)
2018 #ifdef TARGET_X86_64
2020 gen_op_movq_A0_reg[R_ESP]();
2023 gen_op_st_T1_A0[OT_QUAD + s->mem_index]();
2026 gen_op_st_T0_A0[OT_WORD + s->mem_index]();
2028 gen_op_movq_ESP_A0();
2032 gen_op_movl_A0_reg[R_ESP]();
2039 gen_op_addl_A0_SS();
2042 gen_op_andl_A0_ffff();
2043 gen_op_addl_A0_SS();
2045 gen_op_st_T1_A0[s->dflag + 1 + s->mem_index]();
2047 if (s->ss32 && !s->addseg)
2048 gen_op_movl_ESP_A0();
2050 gen_stack_update(s, (-2) << s->dflag);
2054 /* two step pop is necessary for precise exceptions */
2055 static void gen_pop_T0(DisasContext *s)
2057 #ifdef TARGET_X86_64
2059 gen_op_movq_A0_reg[R_ESP]();
2060 gen_op_ld_T0_A0[(s->dflag ? OT_QUAD : OT_WORD) + s->mem_index]();
2064 gen_op_movl_A0_reg[R_ESP]();
2067 gen_op_addl_A0_SS();
2069 gen_op_andl_A0_ffff();
2070 gen_op_addl_A0_SS();
2072 gen_op_ld_T0_A0[s->dflag + 1 + s->mem_index]();
2076 static void gen_pop_update(DisasContext *s)
2078 #ifdef TARGET_X86_64
2079 if (CODE64(s) && s->dflag) {
2080 gen_stack_update(s, 8);
2084 gen_stack_update(s, 2 << s->dflag);
2088 static void gen_stack_A0(DisasContext *s)
2090 gen_op_movl_A0_ESP();
2092 gen_op_andl_A0_ffff();
2093 gen_op_movl_T1_A0();
2095 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
2098 /* NOTE: wrap around in 16 bit not fully handled */
2099 static void gen_pusha(DisasContext *s)
2102 gen_op_movl_A0_ESP();
2103 gen_op_addl_A0_im(-16 << s->dflag);
2105 gen_op_andl_A0_ffff();
2106 gen_op_movl_T1_A0();
2108 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
2109 for(i = 0;i < 8; i++) {
2110 gen_op_mov_TN_reg[OT_LONG][0][7 - i]();
2111 gen_op_st_T0_A0[OT_WORD + s->dflag + s->mem_index]();
2112 gen_op_addl_A0_im(2 << s->dflag);
2114 gen_op_mov_reg_T1[OT_WORD + s->ss32][R_ESP]();
2117 /* NOTE: wrap around in 16 bit not fully handled */
2118 static void gen_popa(DisasContext *s)
2121 gen_op_movl_A0_ESP();
2123 gen_op_andl_A0_ffff();
2124 gen_op_movl_T1_A0();
2125 gen_op_addl_T1_im(16 << s->dflag);
2127 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
2128 for(i = 0;i < 8; i++) {
2129 /* ESP is not reloaded */
2131 gen_op_ld_T0_A0[OT_WORD + s->dflag + s->mem_index]();
2132 gen_op_mov_reg_T0[OT_WORD + s->dflag][7 - i]();
2134 gen_op_addl_A0_im(2 << s->dflag);
2136 gen_op_mov_reg_T1[OT_WORD + s->ss32][R_ESP]();
2139 static void gen_enter(DisasContext *s, int esp_addend, int level)
2144 #ifdef TARGET_X86_64
2146 ot = s->dflag ? OT_QUAD : OT_WORD;
2149 gen_op_movl_A0_ESP();
2150 gen_op_addq_A0_im(-opsize);
2151 gen_op_movl_T1_A0();
2154 gen_op_mov_TN_reg[OT_LONG][0][R_EBP]();
2155 gen_op_st_T0_A0[ot + s->mem_index]();
2157 gen_op_enter64_level(level, (ot == OT_QUAD));
2159 gen_op_mov_reg_T1[ot][R_EBP]();
2160 gen_op_addl_T1_im( -esp_addend + (-opsize * level) );
2161 gen_op_mov_reg_T1[OT_QUAD][R_ESP]();
2165 ot = s->dflag + OT_WORD;
2166 opsize = 2 << s->dflag;
2168 gen_op_movl_A0_ESP();
2169 gen_op_addl_A0_im(-opsize);
2171 gen_op_andl_A0_ffff();
2172 gen_op_movl_T1_A0();
2174 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
2176 gen_op_mov_TN_reg[OT_LONG][0][R_EBP]();
2177 gen_op_st_T0_A0[ot + s->mem_index]();
2179 gen_op_enter_level(level, s->dflag);
2181 gen_op_mov_reg_T1[ot][R_EBP]();
2182 gen_op_addl_T1_im( -esp_addend + (-opsize * level) );
2183 gen_op_mov_reg_T1[OT_WORD + s->ss32][R_ESP]();
2187 static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip)
2189 if (s->cc_op != CC_OP_DYNAMIC)
2190 gen_op_set_cc_op(s->cc_op);
2191 gen_jmp_im(cur_eip);
2192 gen_op_raise_exception(trapno);
2196 /* an interrupt is different from an exception because of the
2197 priviledge checks */
2198 static void gen_interrupt(DisasContext *s, int intno,
2199 target_ulong cur_eip, target_ulong next_eip)
2201 if (s->cc_op != CC_OP_DYNAMIC)
2202 gen_op_set_cc_op(s->cc_op);
2203 gen_jmp_im(cur_eip);
2204 gen_op_raise_interrupt(intno, (int)(next_eip - cur_eip));
2208 static void gen_debug(DisasContext *s, target_ulong cur_eip)
2210 if (s->cc_op != CC_OP_DYNAMIC)
2211 gen_op_set_cc_op(s->cc_op);
2212 gen_jmp_im(cur_eip);
2217 /* generate a generic end of block. Trace exception is also generated
2219 static void gen_eob(DisasContext *s)
2221 if (s->cc_op != CC_OP_DYNAMIC)
2222 gen_op_set_cc_op(s->cc_op);
2223 if (s->tb->flags & HF_INHIBIT_IRQ_MASK) {
2224 gen_op_reset_inhibit_irq();
2226 if (s->singlestep_enabled) {
2229 gen_op_raise_exception(EXCP01_SSTP);
2237 /* generate a jump to eip. No segment change must happen before as a
2238 direct call to the next block may occur */
2239 static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num)
2242 if (s->cc_op != CC_OP_DYNAMIC) {
2243 gen_op_set_cc_op(s->cc_op);
2244 s->cc_op = CC_OP_DYNAMIC;
2246 gen_goto_tb(s, tb_num, eip);
2254 static void gen_jmp(DisasContext *s, target_ulong eip)
2256 gen_jmp_tb(s, eip, 0);
2259 static void gen_movtl_T0_im(target_ulong val)
2261 #ifdef TARGET_X86_64
2262 if ((int32_t)val == val) {
2263 gen_op_movl_T0_im(val);
2265 gen_op_movq_T0_im64(val >> 32, val);
2268 gen_op_movl_T0_im(val);
2272 static void gen_movtl_T1_im(target_ulong val)
2274 #ifdef TARGET_X86_64
2275 if ((int32_t)val == val) {
2276 gen_op_movl_T1_im(val);
2278 gen_op_movq_T1_im64(val >> 32, val);
2281 gen_op_movl_T1_im(val);
2285 static void gen_add_A0_im(DisasContext *s, int val)
2287 #ifdef TARGET_X86_64
2289 gen_op_addq_A0_im(val);
2292 gen_op_addl_A0_im(val);
2295 static GenOpFunc1 *gen_ldq_env_A0[3] = {
2296 gen_op_ldq_raw_env_A0,
2297 #ifndef CONFIG_USER_ONLY
2298 gen_op_ldq_kernel_env_A0,
2299 gen_op_ldq_user_env_A0,
2303 static GenOpFunc1 *gen_stq_env_A0[3] = {
2304 gen_op_stq_raw_env_A0,
2305 #ifndef CONFIG_USER_ONLY
2306 gen_op_stq_kernel_env_A0,
2307 gen_op_stq_user_env_A0,
2311 static GenOpFunc1 *gen_ldo_env_A0[3] = {
2312 gen_op_ldo_raw_env_A0,
2313 #ifndef CONFIG_USER_ONLY
2314 gen_op_ldo_kernel_env_A0,
2315 gen_op_ldo_user_env_A0,
2319 static GenOpFunc1 *gen_sto_env_A0[3] = {
2320 gen_op_sto_raw_env_A0,
2321 #ifndef CONFIG_USER_ONLY
2322 gen_op_sto_kernel_env_A0,
2323 gen_op_sto_user_env_A0,
2327 #define SSE_SPECIAL ((GenOpFunc2 *)1)
2329 #define MMX_OP2(x) { gen_op_ ## x ## _mmx, gen_op_ ## x ## _xmm }
2330 #define SSE_FOP(x) { gen_op_ ## x ## ps, gen_op_ ## x ## pd, \
2331 gen_op_ ## x ## ss, gen_op_ ## x ## sd, }
2333 static GenOpFunc2 *sse_op_table1[256][4] = {
2334 /* pure SSE operations */
2335 [0x10] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
2336 [0x11] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
2337 [0x12] = { SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd */
2338 [0x13] = { SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd */
2339 [0x14] = { gen_op_punpckldq_xmm, gen_op_punpcklqdq_xmm },
2340 [0x15] = { gen_op_punpckhdq_xmm, gen_op_punpckhqdq_xmm },
2341 [0x16] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd, movshdup */
2342 [0x17] = { SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd */
2344 [0x28] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */
2345 [0x29] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */
2346 [0x2a] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */
2347 [0x2b] = { SSE_SPECIAL, SSE_SPECIAL }, /* movntps, movntpd */
2348 [0x2c] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */
2349 [0x2d] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */
2350 [0x2e] = { gen_op_ucomiss, gen_op_ucomisd },
2351 [0x2f] = { gen_op_comiss, gen_op_comisd },
2352 [0x50] = { SSE_SPECIAL, SSE_SPECIAL }, /* movmskps, movmskpd */
2353 [0x51] = SSE_FOP(sqrt),
2354 [0x52] = { gen_op_rsqrtps, NULL, gen_op_rsqrtss, NULL },
2355 [0x53] = { gen_op_rcpps, NULL, gen_op_rcpss, NULL },
2356 [0x54] = { gen_op_pand_xmm, gen_op_pand_xmm }, /* andps, andpd */
2357 [0x55] = { gen_op_pandn_xmm, gen_op_pandn_xmm }, /* andnps, andnpd */
2358 [0x56] = { gen_op_por_xmm, gen_op_por_xmm }, /* orps, orpd */
2359 [0x57] = { gen_op_pxor_xmm, gen_op_pxor_xmm }, /* xorps, xorpd */
2360 [0x58] = SSE_FOP(add),
2361 [0x59] = SSE_FOP(mul),
2362 [0x5a] = { gen_op_cvtps2pd, gen_op_cvtpd2ps,
2363 gen_op_cvtss2sd, gen_op_cvtsd2ss },
2364 [0x5b] = { gen_op_cvtdq2ps, gen_op_cvtps2dq, gen_op_cvttps2dq },
2365 [0x5c] = SSE_FOP(sub),
2366 [0x5d] = SSE_FOP(min),
2367 [0x5e] = SSE_FOP(div),
2368 [0x5f] = SSE_FOP(max),
2370 [0xc2] = SSE_FOP(cmpeq),
2371 [0xc6] = { (GenOpFunc2 *)gen_op_shufps, (GenOpFunc2 *)gen_op_shufpd },
2373 /* MMX ops and their SSE extensions */
2374 [0x60] = MMX_OP2(punpcklbw),
2375 [0x61] = MMX_OP2(punpcklwd),
2376 [0x62] = MMX_OP2(punpckldq),
2377 [0x63] = MMX_OP2(packsswb),
2378 [0x64] = MMX_OP2(pcmpgtb),
2379 [0x65] = MMX_OP2(pcmpgtw),
2380 [0x66] = MMX_OP2(pcmpgtl),
2381 [0x67] = MMX_OP2(packuswb),
2382 [0x68] = MMX_OP2(punpckhbw),
2383 [0x69] = MMX_OP2(punpckhwd),
2384 [0x6a] = MMX_OP2(punpckhdq),
2385 [0x6b] = MMX_OP2(packssdw),
2386 [0x6c] = { NULL, gen_op_punpcklqdq_xmm },
2387 [0x6d] = { NULL, gen_op_punpckhqdq_xmm },
2388 [0x6e] = { SSE_SPECIAL, SSE_SPECIAL }, /* movd mm, ea */
2389 [0x6f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, , movqdu */
2390 [0x70] = { (GenOpFunc2 *)gen_op_pshufw_mmx,
2391 (GenOpFunc2 *)gen_op_pshufd_xmm,
2392 (GenOpFunc2 *)gen_op_pshufhw_xmm,
2393 (GenOpFunc2 *)gen_op_pshuflw_xmm },
2394 [0x71] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftw */
2395 [0x72] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftd */
2396 [0x73] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftq */
2397 [0x74] = MMX_OP2(pcmpeqb),
2398 [0x75] = MMX_OP2(pcmpeqw),
2399 [0x76] = MMX_OP2(pcmpeql),
2400 [0x77] = { SSE_SPECIAL }, /* emms */
2401 [0x7c] = { NULL, gen_op_haddpd, NULL, gen_op_haddps },
2402 [0x7d] = { NULL, gen_op_hsubpd, NULL, gen_op_hsubps },
2403 [0x7e] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movd, movd, , movq */
2404 [0x7f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, movdqu */
2405 [0xc4] = { SSE_SPECIAL, SSE_SPECIAL }, /* pinsrw */
2406 [0xc5] = { SSE_SPECIAL, SSE_SPECIAL }, /* pextrw */
2407 [0xd0] = { NULL, gen_op_addsubpd, NULL, gen_op_addsubps },
2408 [0xd1] = MMX_OP2(psrlw),
2409 [0xd2] = MMX_OP2(psrld),
2410 [0xd3] = MMX_OP2(psrlq),
2411 [0xd4] = MMX_OP2(paddq),
2412 [0xd5] = MMX_OP2(pmullw),
2413 [0xd6] = { NULL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL },
2414 [0xd7] = { SSE_SPECIAL, SSE_SPECIAL }, /* pmovmskb */
2415 [0xd8] = MMX_OP2(psubusb),
2416 [0xd9] = MMX_OP2(psubusw),
2417 [0xda] = MMX_OP2(pminub),
2418 [0xdb] = MMX_OP2(pand),
2419 [0xdc] = MMX_OP2(paddusb),
2420 [0xdd] = MMX_OP2(paddusw),
2421 [0xde] = MMX_OP2(pmaxub),
2422 [0xdf] = MMX_OP2(pandn),
2423 [0xe0] = MMX_OP2(pavgb),
2424 [0xe1] = MMX_OP2(psraw),
2425 [0xe2] = MMX_OP2(psrad),
2426 [0xe3] = MMX_OP2(pavgw),
2427 [0xe4] = MMX_OP2(pmulhuw),
2428 [0xe5] = MMX_OP2(pmulhw),
2429 [0xe6] = { NULL, gen_op_cvttpd2dq, gen_op_cvtdq2pd, gen_op_cvtpd2dq },
2430 [0xe7] = { SSE_SPECIAL , SSE_SPECIAL }, /* movntq, movntq */
2431 [0xe8] = MMX_OP2(psubsb),
2432 [0xe9] = MMX_OP2(psubsw),
2433 [0xea] = MMX_OP2(pminsw),
2434 [0xeb] = MMX_OP2(por),
2435 [0xec] = MMX_OP2(paddsb),
2436 [0xed] = MMX_OP2(paddsw),
2437 [0xee] = MMX_OP2(pmaxsw),
2438 [0xef] = MMX_OP2(pxor),
2439 [0xf0] = { NULL, NULL, NULL, SSE_SPECIAL }, /* lddqu (PNI) */
2440 [0xf1] = MMX_OP2(psllw),
2441 [0xf2] = MMX_OP2(pslld),
2442 [0xf3] = MMX_OP2(psllq),
2443 [0xf4] = MMX_OP2(pmuludq),
2444 [0xf5] = MMX_OP2(pmaddwd),
2445 [0xf6] = MMX_OP2(psadbw),
2446 [0xf7] = MMX_OP2(maskmov),
2447 [0xf8] = MMX_OP2(psubb),
2448 [0xf9] = MMX_OP2(psubw),
2449 [0xfa] = MMX_OP2(psubl),
2450 [0xfb] = MMX_OP2(psubq),
2451 [0xfc] = MMX_OP2(paddb),
2452 [0xfd] = MMX_OP2(paddw),
2453 [0xfe] = MMX_OP2(paddl),
2456 static GenOpFunc2 *sse_op_table2[3 * 8][2] = {
2457 [0 + 2] = MMX_OP2(psrlw),
2458 [0 + 4] = MMX_OP2(psraw),
2459 [0 + 6] = MMX_OP2(psllw),
2460 [8 + 2] = MMX_OP2(psrld),
2461 [8 + 4] = MMX_OP2(psrad),
2462 [8 + 6] = MMX_OP2(pslld),
2463 [16 + 2] = MMX_OP2(psrlq),
2464 [16 + 3] = { NULL, gen_op_psrldq_xmm },
2465 [16 + 6] = MMX_OP2(psllq),
2466 [16 + 7] = { NULL, gen_op_pslldq_xmm },
2469 static GenOpFunc1 *sse_op_table3[4 * 3] = {
2472 X86_64_ONLY(gen_op_cvtsq2ss),
2473 X86_64_ONLY(gen_op_cvtsq2sd),
2477 X86_64_ONLY(gen_op_cvttss2sq),
2478 X86_64_ONLY(gen_op_cvttsd2sq),
2482 X86_64_ONLY(gen_op_cvtss2sq),
2483 X86_64_ONLY(gen_op_cvtsd2sq),
2486 static GenOpFunc2 *sse_op_table4[8][4] = {
2497 static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
2499 int b1, op1_offset, op2_offset, is_xmm, val, ot;
2500 int modrm, mod, rm, reg, reg_addr, offset_addr;
2501 GenOpFunc2 *sse_op2;
2502 GenOpFunc3 *sse_op3;
2505 if (s->prefix & PREFIX_DATA)
2507 else if (s->prefix & PREFIX_REPZ)
2509 else if (s->prefix & PREFIX_REPNZ)
2513 sse_op2 = sse_op_table1[b][b1];
2516 if (b <= 0x5f || b == 0xc6 || b == 0xc2) {
2526 /* simple MMX/SSE operation */
2527 if (s->flags & HF_TS_MASK) {
2528 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
2531 if (s->flags & HF_EM_MASK) {
2533 gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
2536 if (is_xmm && !(s->flags & HF_OSFXSR_MASK))
2543 /* prepare MMX state (XXX: optimize by storing fptt and fptags in
2544 the static cpu state) */
2549 modrm = ldub_code(s->pc++);
2550 reg = ((modrm >> 3) & 7);
2553 mod = (modrm >> 6) & 3;
2554 if (sse_op2 == SSE_SPECIAL) {
2557 case 0x0e7: /* movntq */
2560 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
2561 gen_stq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,fpregs[reg].mmx));
2563 case 0x1e7: /* movntdq */
2564 case 0x02b: /* movntps */
2565 case 0x12b: /* movntps */
2566 case 0x2f0: /* lddqu */
2569 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
2570 gen_sto_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg]));
2572 case 0x6e: /* movd mm, ea */
2573 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
2574 gen_op_movl_mm_T0_mmx(offsetof(CPUX86State,fpregs[reg].mmx));
2576 case 0x16e: /* movd xmm, ea */
2577 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
2578 gen_op_movl_mm_T0_xmm(offsetof(CPUX86State,xmm_regs[reg]));
2580 case 0x6f: /* movq mm, ea */
2582 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
2583 gen_ldq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,fpregs[reg].mmx));
2586 gen_op_movq(offsetof(CPUX86State,fpregs[reg].mmx),
2587 offsetof(CPUX86State,fpregs[rm].mmx));
2590 case 0x010: /* movups */
2591 case 0x110: /* movupd */
2592 case 0x028: /* movaps */
2593 case 0x128: /* movapd */
2594 case 0x16f: /* movdqa xmm, ea */
2595 case 0x26f: /* movdqu xmm, ea */
2597 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
2598 gen_ldo_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg]));
2600 rm = (modrm & 7) | REX_B(s);
2601 gen_op_movo(offsetof(CPUX86State,xmm_regs[reg]),
2602 offsetof(CPUX86State,xmm_regs[rm]));
2605 case 0x210: /* movss xmm, ea */
2607 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
2608 gen_op_ld_T0_A0[OT_LONG + s->mem_index]();
2609 gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
2611 gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
2612 gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
2613 gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
2615 rm = (modrm & 7) | REX_B(s);
2616 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
2617 offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
2620 case 0x310: /* movsd xmm, ea */
2622 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
2623 gen_ldq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
2625 gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
2626 gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
2628 rm = (modrm & 7) | REX_B(s);
2629 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
2630 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
2633 case 0x012: /* movlps */
2634 case 0x112: /* movlpd */
2636 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
2637 gen_ldq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
2640 rm = (modrm & 7) | REX_B(s);
2641 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
2642 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
2645 case 0x016: /* movhps */
2646 case 0x116: /* movhpd */
2648 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
2649 gen_ldq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
2652 rm = (modrm & 7) | REX_B(s);
2653 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
2654 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
2657 case 0x216: /* movshdup */
2659 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
2660 gen_ldo_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg]));
2662 rm = (modrm & 7) | REX_B(s);
2663 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
2664 offsetof(CPUX86State,xmm_regs[rm].XMM_L(1)));
2665 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
2666 offsetof(CPUX86State,xmm_regs[rm].XMM_L(3)));
2668 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
2669 offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
2670 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
2671 offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
2673 case 0x7e: /* movd ea, mm */
2674 gen_op_movl_T0_mm_mmx(offsetof(CPUX86State,fpregs[reg].mmx));
2675 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
2677 case 0x17e: /* movd ea, xmm */
2678 gen_op_movl_T0_mm_xmm(offsetof(CPUX86State,xmm_regs[reg]));
2679 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
2681 case 0x27e: /* movq xmm, ea */
2683 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
2684 gen_ldq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
2686 rm = (modrm & 7) | REX_B(s);
2687 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
2688 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
2690 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
2692 case 0x7f: /* movq ea, mm */
2694 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
2695 gen_stq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,fpregs[reg].mmx));
2698 gen_op_movq(offsetof(CPUX86State,fpregs[rm].mmx),
2699 offsetof(CPUX86State,fpregs[reg].mmx));
2702 case 0x011: /* movups */
2703 case 0x111: /* movupd */
2704 case 0x029: /* movaps */
2705 case 0x129: /* movapd */
2706 case 0x17f: /* movdqa ea, xmm */
2707 case 0x27f: /* movdqu ea, xmm */
2709 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
2710 gen_sto_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg]));
2712 rm = (modrm & 7) | REX_B(s);
2713 gen_op_movo(offsetof(CPUX86State,xmm_regs[rm]),
2714 offsetof(CPUX86State,xmm_regs[reg]));
2717 case 0x211: /* movss ea, xmm */
2719 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
2720 gen_op_movl_T0_env(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
2721 gen_op_st_T0_A0[OT_LONG + s->mem_index]();
2723 rm = (modrm & 7) | REX_B(s);
2724 gen_op_movl(offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)),
2725 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
2728 case 0x311: /* movsd ea, xmm */
2730 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
2731 gen_stq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
2733 rm = (modrm & 7) | REX_B(s);
2734 gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
2735 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
2738 case 0x013: /* movlps */
2739 case 0x113: /* movlpd */
2741 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
2742 gen_stq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
2747 case 0x017: /* movhps */
2748 case 0x117: /* movhpd */
2750 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
2751 gen_stq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
2756 case 0x71: /* shift mm, im */
2759 case 0x171: /* shift xmm, im */
2762 val = ldub_code(s->pc++);
2764 gen_op_movl_T0_im(val);
2765 gen_op_movl_env_T0(offsetof(CPUX86State,xmm_t0.XMM_L(0)));
2767 gen_op_movl_env_T0(offsetof(CPUX86State,xmm_t0.XMM_L(1)));
2768 op1_offset = offsetof(CPUX86State,xmm_t0);
2770 gen_op_movl_T0_im(val);
2771 gen_op_movl_env_T0(offsetof(CPUX86State,mmx_t0.MMX_L(0)));
2773 gen_op_movl_env_T0(offsetof(CPUX86State,mmx_t0.MMX_L(1)));
2774 op1_offset = offsetof(CPUX86State,mmx_t0);
2776 sse_op2 = sse_op_table2[((b - 1) & 3) * 8 + (((modrm >> 3)) & 7)][b1];
2780 rm = (modrm & 7) | REX_B(s);
2781 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
2784 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
2786 sse_op2(op2_offset, op1_offset);
2788 case 0x050: /* movmskps */
2789 rm = (modrm & 7) | REX_B(s);
2790 gen_op_movmskps(offsetof(CPUX86State,xmm_regs[rm]));
2791 gen_op_mov_reg_T0[OT_LONG][reg]();
2793 case 0x150: /* movmskpd */
2794 rm = (modrm & 7) | REX_B(s);
2795 gen_op_movmskpd(offsetof(CPUX86State,xmm_regs[rm]));
2796 gen_op_mov_reg_T0[OT_LONG][reg]();
2798 case 0x02a: /* cvtpi2ps */
2799 case 0x12a: /* cvtpi2pd */
2802 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
2803 op2_offset = offsetof(CPUX86State,mmx_t0);
2804 gen_ldq_env_A0[s->mem_index >> 2](op2_offset);
2807 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
2809 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
2812 gen_op_cvtpi2ps(op1_offset, op2_offset);
2816 gen_op_cvtpi2pd(op1_offset, op2_offset);
2820 case 0x22a: /* cvtsi2ss */
2821 case 0x32a: /* cvtsi2sd */
2822 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
2823 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
2824 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
2825 sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2)](op1_offset);
2827 case 0x02c: /* cvttps2pi */
2828 case 0x12c: /* cvttpd2pi */
2829 case 0x02d: /* cvtps2pi */
2830 case 0x12d: /* cvtpd2pi */
2833 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
2834 op2_offset = offsetof(CPUX86State,xmm_t0);
2835 gen_ldo_env_A0[s->mem_index >> 2](op2_offset);
2837 rm = (modrm & 7) | REX_B(s);
2838 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
2840 op1_offset = offsetof(CPUX86State,fpregs[reg & 7].mmx);
2843 gen_op_cvttps2pi(op1_offset, op2_offset);
2846 gen_op_cvttpd2pi(op1_offset, op2_offset);
2849 gen_op_cvtps2pi(op1_offset, op2_offset);
2852 gen_op_cvtpd2pi(op1_offset, op2_offset);
2856 case 0x22c: /* cvttss2si */
2857 case 0x32c: /* cvttsd2si */
2858 case 0x22d: /* cvtss2si */
2859 case 0x32d: /* cvtsd2si */
2860 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
2862 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
2864 gen_ldq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_t0.XMM_Q(0)));
2866 gen_op_ld_T0_A0[OT_LONG + s->mem_index]();
2867 gen_op_movl_env_T0(offsetof(CPUX86State,xmm_t0.XMM_L(0)));
2869 op2_offset = offsetof(CPUX86State,xmm_t0);
2871 rm = (modrm & 7) | REX_B(s);
2872 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
2874 sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2) + 4 +
2875 (b & 1) * 4](op2_offset);
2876 gen_op_mov_reg_T0[ot][reg]();
2878 case 0xc4: /* pinsrw */
2880 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
2881 val = ldub_code(s->pc++);
2884 gen_op_pinsrw_xmm(offsetof(CPUX86State,xmm_regs[reg]), val);
2887 gen_op_pinsrw_mmx(offsetof(CPUX86State,fpregs[reg].mmx), val);
2890 case 0xc5: /* pextrw */
2894 val = ldub_code(s->pc++);
2897 rm = (modrm & 7) | REX_B(s);
2898 gen_op_pextrw_xmm(offsetof(CPUX86State,xmm_regs[rm]), val);
2902 gen_op_pextrw_mmx(offsetof(CPUX86State,fpregs[rm].mmx), val);
2904 reg = ((modrm >> 3) & 7) | rex_r;
2905 gen_op_mov_reg_T0[OT_LONG][reg]();
2907 case 0x1d6: /* movq ea, xmm */
2909 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
2910 gen_stq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
2912 rm = (modrm & 7) | REX_B(s);
2913 gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
2914 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
2915 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
2918 case 0x2d6: /* movq2dq */
2920 rm = (modrm & 7) | REX_B(s);
2921 gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
2922 offsetof(CPUX86State,fpregs[reg & 7].mmx));
2923 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
2925 case 0x3d6: /* movdq2q */
2928 gen_op_movq(offsetof(CPUX86State,fpregs[rm].mmx),
2929 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
2931 case 0xd7: /* pmovmskb */
2936 rm = (modrm & 7) | REX_B(s);
2937 gen_op_pmovmskb_xmm(offsetof(CPUX86State,xmm_regs[rm]));
2940 gen_op_pmovmskb_mmx(offsetof(CPUX86State,fpregs[rm].mmx));
2942 reg = ((modrm >> 3) & 7) | rex_r;
2943 gen_op_mov_reg_T0[OT_LONG][reg]();
2949 /* generic MMX or SSE operation */
2951 /* maskmov : we must prepare A0 */
2954 #ifdef TARGET_X86_64
2955 if (s->aflag == 2) {
2956 gen_op_movq_A0_reg[R_EDI]();
2960 gen_op_movl_A0_reg[R_EDI]();
2962 gen_op_andl_A0_ffff();
2964 gen_add_A0_ds_seg(s);
2967 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
2969 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
2970 op2_offset = offsetof(CPUX86State,xmm_t0);
2971 if (b1 >= 2 && ((b >= 0x50 && b <= 0x5f) ||
2973 /* specific case for SSE single instructions */
2976 gen_op_ld_T0_A0[OT_LONG + s->mem_index]();
2977 gen_op_movl_env_T0(offsetof(CPUX86State,xmm_t0.XMM_L(0)));
2980 gen_ldq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_t0.XMM_D(0)));
2983 gen_ldo_env_A0[s->mem_index >> 2](op2_offset);
2986 rm = (modrm & 7) | REX_B(s);
2987 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
2990 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
2992 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
2993 op2_offset = offsetof(CPUX86State,mmx_t0);
2994 gen_ldq_env_A0[s->mem_index >> 2](op2_offset);
2997 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3001 case 0x70: /* pshufx insn */
3002 case 0xc6: /* pshufx insn */
3003 val = ldub_code(s->pc++);
3004 sse_op3 = (GenOpFunc3 *)sse_op2;
3005 sse_op3(op1_offset, op2_offset, val);
3009 val = ldub_code(s->pc++);
3012 sse_op2 = sse_op_table4[val][b1];
3013 sse_op2(op1_offset, op2_offset);
3016 sse_op2(op1_offset, op2_offset);
3019 if (b == 0x2e || b == 0x2f) {
3020 s->cc_op = CC_OP_EFLAGS;
3026 /* convert one instruction. s->is_jmp is set if the translation must
3027 be stopped. Return the next pc value */
3028 static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
3030 int b, prefixes, aflag, dflag;
3032 int modrm, reg, rm, mod, reg_addr, op, opreg, offset_addr, val;
3033 target_ulong next_eip, tval;
3043 #ifdef TARGET_X86_64
3048 s->rip_offset = 0; /* for relative ip address */
3050 b = ldub_code(s->pc);
3052 /* check prefixes */
3053 #ifdef TARGET_X86_64
3057 prefixes |= PREFIX_REPZ;
3060 prefixes |= PREFIX_REPNZ;
3063 prefixes |= PREFIX_LOCK;
3084 prefixes |= PREFIX_DATA;
3087 prefixes |= PREFIX_ADR;
3091 rex_w = (b >> 3) & 1;
3092 rex_r = (b & 0x4) << 1;
3093 s->rex_x = (b & 0x2) << 2;
3094 REX_B(s) = (b & 0x1) << 3;
3095 x86_64_hregs = 1; /* select uniform byte register addressing */
3099 /* 0x66 is ignored if rex.w is set */
3102 if (prefixes & PREFIX_DATA)
3105 if (!(prefixes & PREFIX_ADR))
3112 prefixes |= PREFIX_REPZ;
3115 prefixes |= PREFIX_REPNZ;
3118 prefixes |= PREFIX_LOCK;
3139 prefixes |= PREFIX_DATA;
3142 prefixes |= PREFIX_ADR;
3145 if (prefixes & PREFIX_DATA)
3147 if (prefixes & PREFIX_ADR)
3151 s->prefix = prefixes;
3155 /* lock generation */
3156 if (prefixes & PREFIX_LOCK)
3159 /* now check op code */
3163 /**************************/
3164 /* extended op code */
3165 b = ldub_code(s->pc++) | 0x100;
3168 /**************************/
3186 ot = dflag + OT_WORD;
3189 case 0: /* OP Ev, Gv */
3190 modrm = ldub_code(s->pc++);
3191 reg = ((modrm >> 3) & 7) | rex_r;
3192 mod = (modrm >> 6) & 3;
3193 rm = (modrm & 7) | REX_B(s);
3195 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3197 } else if (op == OP_XORL && rm == reg) {
3199 /* xor reg, reg optimisation */
3201 s->cc_op = CC_OP_LOGICB + ot;
3202 gen_op_mov_reg_T0[ot][reg]();
3203 gen_op_update1_cc();
3208 gen_op_mov_TN_reg[ot][1][reg]();
3209 gen_op(s, op, ot, opreg);
3211 case 1: /* OP Gv, Ev */
3212 modrm = ldub_code(s->pc++);
3213 mod = (modrm >> 6) & 3;
3214 reg = ((modrm >> 3) & 7) | rex_r;
3215 rm = (modrm & 7) | REX_B(s);
3217 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3218 gen_op_ld_T1_A0[ot + s->mem_index]();
3219 } else if (op == OP_XORL && rm == reg) {
3222 gen_op_mov_TN_reg[ot][1][rm]();
3224 gen_op(s, op, ot, reg);
3226 case 2: /* OP A, Iv */
3227 val = insn_get(s, ot);
3228 gen_op_movl_T1_im(val);
3229 gen_op(s, op, ot, OR_EAX);
3235 case 0x80: /* GRP1 */
3245 ot = dflag + OT_WORD;
3247 modrm = ldub_code(s->pc++);
3248 mod = (modrm >> 6) & 3;
3249 rm = (modrm & 7) | REX_B(s);
3250 op = (modrm >> 3) & 7;
3256 s->rip_offset = insn_const_size(ot);
3257 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3268 val = insn_get(s, ot);
3271 val = (int8_t)insn_get(s, OT_BYTE);
3274 gen_op_movl_T1_im(val);
3275 gen_op(s, op, ot, opreg);
3279 /**************************/
3280 /* inc, dec, and other misc arith */
3281 case 0x40 ... 0x47: /* inc Gv */
3282 ot = dflag ? OT_LONG : OT_WORD;
3283 gen_inc(s, ot, OR_EAX + (b & 7), 1);
3285 case 0x48 ... 0x4f: /* dec Gv */
3286 ot = dflag ? OT_LONG : OT_WORD;
3287 gen_inc(s, ot, OR_EAX + (b & 7), -1);
3289 case 0xf6: /* GRP3 */
3294 ot = dflag + OT_WORD;
3296 modrm = ldub_code(s->pc++);
3297 mod = (modrm >> 6) & 3;
3298 rm = (modrm & 7) | REX_B(s);
3299 op = (modrm >> 3) & 7;
3302 s->rip_offset = insn_const_size(ot);
3303 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3304 gen_op_ld_T0_A0[ot + s->mem_index]();
3306 gen_op_mov_TN_reg[ot][0][rm]();
3311 val = insn_get(s, ot);
3312 gen_op_movl_T1_im(val);
3313 gen_op_testl_T0_T1_cc();
3314 s->cc_op = CC_OP_LOGICB + ot;
3319 gen_op_st_T0_A0[ot + s->mem_index]();
3321 gen_op_mov_reg_T0[ot][rm]();
3327 gen_op_st_T0_A0[ot + s->mem_index]();
3329 gen_op_mov_reg_T0[ot][rm]();
3331 gen_op_update_neg_cc();
3332 s->cc_op = CC_OP_SUBB + ot;
3337 gen_op_mulb_AL_T0();
3338 s->cc_op = CC_OP_MULB;
3341 gen_op_mulw_AX_T0();
3342 s->cc_op = CC_OP_MULW;
3346 gen_op_mull_EAX_T0();
3347 s->cc_op = CC_OP_MULL;
3349 #ifdef TARGET_X86_64
3351 gen_op_mulq_EAX_T0();
3352 s->cc_op = CC_OP_MULQ;
3360 gen_op_imulb_AL_T0();
3361 s->cc_op = CC_OP_MULB;
3364 gen_op_imulw_AX_T0();
3365 s->cc_op = CC_OP_MULW;
3369 gen_op_imull_EAX_T0();
3370 s->cc_op = CC_OP_MULL;
3372 #ifdef TARGET_X86_64
3374 gen_op_imulq_EAX_T0();
3375 s->cc_op = CC_OP_MULQ;
3383 gen_jmp_im(pc_start - s->cs_base);
3384 gen_op_divb_AL_T0();
3387 gen_jmp_im(pc_start - s->cs_base);
3388 gen_op_divw_AX_T0();
3392 gen_jmp_im(pc_start - s->cs_base);
3393 gen_op_divl_EAX_T0();
3395 #ifdef TARGET_X86_64
3397 gen_jmp_im(pc_start - s->cs_base);
3398 gen_op_divq_EAX_T0();
3406 gen_jmp_im(pc_start - s->cs_base);
3407 gen_op_idivb_AL_T0();
3410 gen_jmp_im(pc_start - s->cs_base);
3411 gen_op_idivw_AX_T0();
3415 gen_jmp_im(pc_start - s->cs_base);
3416 gen_op_idivl_EAX_T0();
3418 #ifdef TARGET_X86_64
3420 gen_jmp_im(pc_start - s->cs_base);
3421 gen_op_idivq_EAX_T0();
3431 case 0xfe: /* GRP4 */
3432 case 0xff: /* GRP5 */
3436 ot = dflag + OT_WORD;
3438 modrm = ldub_code(s->pc++);
3439 mod = (modrm >> 6) & 3;
3440 rm = (modrm & 7) | REX_B(s);
3441 op = (modrm >> 3) & 7;
3442 if (op >= 2 && b == 0xfe) {
3446 if (op == 2 || op == 4) {
3447 /* operand size for jumps is 64 bit */
3449 } else if (op == 3 || op == 5) {
3450 /* for call calls, the operand is 16 or 32 bit, even
3452 ot = dflag ? OT_LONG : OT_WORD;
3453 } else if (op == 6) {
3454 /* default push size is 64 bit */
3455 ot = dflag ? OT_QUAD : OT_WORD;
3459 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3460 if (op >= 2 && op != 3 && op != 5)
3461 gen_op_ld_T0_A0[ot + s->mem_index]();
3463 gen_op_mov_TN_reg[ot][0][rm]();
3467 case 0: /* inc Ev */
3472 gen_inc(s, ot, opreg, 1);
3474 case 1: /* dec Ev */
3479 gen_inc(s, ot, opreg, -1);
3481 case 2: /* call Ev */
3482 /* XXX: optimize if memory (no 'and' is necessary) */
3484 gen_op_andl_T0_ffff();
3485 next_eip = s->pc - s->cs_base;
3486 gen_movtl_T1_im(next_eip);
3491 case 3: /* lcall Ev */
3492 gen_op_ld_T1_A0[ot + s->mem_index]();
3493 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
3494 gen_op_ldu_T0_A0[OT_WORD + s->mem_index]();
3496 if (s->pe && !s->vm86) {
3497 if (s->cc_op != CC_OP_DYNAMIC)
3498 gen_op_set_cc_op(s->cc_op);
3499 gen_jmp_im(pc_start - s->cs_base);
3500 gen_op_lcall_protected_T0_T1(dflag, s->pc - pc_start);
3502 gen_op_lcall_real_T0_T1(dflag, s->pc - s->cs_base);
3506 case 4: /* jmp Ev */
3508 gen_op_andl_T0_ffff();
3512 case 5: /* ljmp Ev */
3513 gen_op_ld_T1_A0[ot + s->mem_index]();
3514 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
3515 gen_op_ldu_T0_A0[OT_WORD + s->mem_index]();
3517 if (s->pe && !s->vm86) {
3518 if (s->cc_op != CC_OP_DYNAMIC)
3519 gen_op_set_cc_op(s->cc_op);
3520 gen_jmp_im(pc_start - s->cs_base);
3521 gen_op_ljmp_protected_T0_T1(s->pc - pc_start);
3523 gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[R_CS]));
3524 gen_op_movl_T0_T1();
3529 case 6: /* push Ev */
3537 case 0x84: /* test Ev, Gv */
3542 ot = dflag + OT_WORD;
3544 modrm = ldub_code(s->pc++);
3545 mod = (modrm >> 6) & 3;
3546 rm = (modrm & 7) | REX_B(s);
3547 reg = ((modrm >> 3) & 7) | rex_r;
3549 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3550 gen_op_mov_TN_reg[ot][1][reg]();
3551 gen_op_testl_T0_T1_cc();
3552 s->cc_op = CC_OP_LOGICB + ot;
3555 case 0xa8: /* test eAX, Iv */
3560 ot = dflag + OT_WORD;
3561 val = insn_get(s, ot);
3563 gen_op_mov_TN_reg[ot][0][OR_EAX]();
3564 gen_op_movl_T1_im(val);
3565 gen_op_testl_T0_T1_cc();
3566 s->cc_op = CC_OP_LOGICB + ot;
3569 case 0x98: /* CWDE/CBW */
3570 #ifdef TARGET_X86_64
3572 gen_op_movslq_RAX_EAX();
3576 gen_op_movswl_EAX_AX();
3578 gen_op_movsbw_AX_AL();
3580 case 0x99: /* CDQ/CWD */
3581 #ifdef TARGET_X86_64
3583 gen_op_movsqo_RDX_RAX();
3587 gen_op_movslq_EDX_EAX();
3589 gen_op_movswl_DX_AX();
3591 case 0x1af: /* imul Gv, Ev */
3592 case 0x69: /* imul Gv, Ev, I */
3594 ot = dflag + OT_WORD;
3595 modrm = ldub_code(s->pc++);
3596 reg = ((modrm >> 3) & 7) | rex_r;
3598 s->rip_offset = insn_const_size(ot);
3601 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3603 val = insn_get(s, ot);
3604 gen_op_movl_T1_im(val);
3605 } else if (b == 0x6b) {
3606 val = (int8_t)insn_get(s, OT_BYTE);
3607 gen_op_movl_T1_im(val);
3609 gen_op_mov_TN_reg[ot][1][reg]();
3612 #ifdef TARGET_X86_64
3613 if (ot == OT_QUAD) {
3614 gen_op_imulq_T0_T1();
3617 if (ot == OT_LONG) {
3618 gen_op_imull_T0_T1();
3620 gen_op_imulw_T0_T1();
3622 gen_op_mov_reg_T0[ot][reg]();
3623 s->cc_op = CC_OP_MULB + ot;
3626 case 0x1c1: /* xadd Ev, Gv */
3630 ot = dflag + OT_WORD;
3631 modrm = ldub_code(s->pc++);
3632 reg = ((modrm >> 3) & 7) | rex_r;
3633 mod = (modrm >> 6) & 3;
3635 rm = (modrm & 7) | REX_B(s);
3636 gen_op_mov_TN_reg[ot][0][reg]();
3637 gen_op_mov_TN_reg[ot][1][rm]();
3638 gen_op_addl_T0_T1();
3639 gen_op_mov_reg_T1[ot][reg]();
3640 gen_op_mov_reg_T0[ot][rm]();
3642 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3643 gen_op_mov_TN_reg[ot][0][reg]();
3644 gen_op_ld_T1_A0[ot + s->mem_index]();
3645 gen_op_addl_T0_T1();
3646 gen_op_st_T0_A0[ot + s->mem_index]();
3647 gen_op_mov_reg_T1[ot][reg]();
3649 gen_op_update2_cc();
3650 s->cc_op = CC_OP_ADDB + ot;
3653 case 0x1b1: /* cmpxchg Ev, Gv */
3657 ot = dflag + OT_WORD;
3658 modrm = ldub_code(s->pc++);
3659 reg = ((modrm >> 3) & 7) | rex_r;
3660 mod = (modrm >> 6) & 3;
3661 gen_op_mov_TN_reg[ot][1][reg]();
3663 rm = (modrm & 7) | REX_B(s);
3664 gen_op_mov_TN_reg[ot][0][rm]();
3665 gen_op_cmpxchg_T0_T1_EAX_cc[ot]();
3666 gen_op_mov_reg_T0[ot][rm]();
3668 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3669 gen_op_ld_T0_A0[ot + s->mem_index]();
3670 gen_op_cmpxchg_mem_T0_T1_EAX_cc[ot + s->mem_index]();
3672 s->cc_op = CC_OP_SUBB + ot;
3674 case 0x1c7: /* cmpxchg8b */
3675 modrm = ldub_code(s->pc++);
3676 mod = (modrm >> 6) & 3;
3679 if (s->cc_op != CC_OP_DYNAMIC)
3680 gen_op_set_cc_op(s->cc_op);
3681 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3683 s->cc_op = CC_OP_EFLAGS;
3686 /**************************/
3688 case 0x50 ... 0x57: /* push */
3689 gen_op_mov_TN_reg[OT_LONG][0][(b & 7) | REX_B(s)]();
3692 case 0x58 ... 0x5f: /* pop */
3694 ot = dflag ? OT_QUAD : OT_WORD;
3696 ot = dflag + OT_WORD;
3699 /* NOTE: order is important for pop %sp */
3701 gen_op_mov_reg_T0[ot][(b & 7) | REX_B(s)]();
3703 case 0x60: /* pusha */
3708 case 0x61: /* popa */
3713 case 0x68: /* push Iv */
3716 ot = dflag ? OT_QUAD : OT_WORD;
3718 ot = dflag + OT_WORD;
3721 val = insn_get(s, ot);
3723 val = (int8_t)insn_get(s, OT_BYTE);
3724 gen_op_movl_T0_im(val);
3727 case 0x8f: /* pop Ev */
3729 ot = dflag ? OT_QUAD : OT_WORD;
3731 ot = dflag + OT_WORD;
3733 modrm = ldub_code(s->pc++);
3734 mod = (modrm >> 6) & 3;
3737 /* NOTE: order is important for pop %sp */
3739 rm = (modrm & 7) | REX_B(s);
3740 gen_op_mov_reg_T0[ot][rm]();
3742 /* NOTE: order is important too for MMU exceptions */
3743 s->popl_esp_hack = 1 << ot;
3744 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
3745 s->popl_esp_hack = 0;
3749 case 0xc8: /* enter */
3752 val = lduw_code(s->pc);
3754 level = ldub_code(s->pc++);
3755 gen_enter(s, val, level);
3758 case 0xc9: /* leave */
3759 /* XXX: exception not precise (ESP is updated before potential exception) */
3761 gen_op_mov_TN_reg[OT_QUAD][0][R_EBP]();
3762 gen_op_mov_reg_T0[OT_QUAD][R_ESP]();
3763 } else if (s->ss32) {
3764 gen_op_mov_TN_reg[OT_LONG][0][R_EBP]();
3765 gen_op_mov_reg_T0[OT_LONG][R_ESP]();
3767 gen_op_mov_TN_reg[OT_WORD][0][R_EBP]();
3768 gen_op_mov_reg_T0[OT_WORD][R_ESP]();
3772 ot = dflag ? OT_QUAD : OT_WORD;
3774 ot = dflag + OT_WORD;
3776 gen_op_mov_reg_T0[ot][R_EBP]();
3779 case 0x06: /* push es */
3780 case 0x0e: /* push cs */
3781 case 0x16: /* push ss */
3782 case 0x1e: /* push ds */
3785 gen_op_movl_T0_seg(b >> 3);
3788 case 0x1a0: /* push fs */
3789 case 0x1a8: /* push gs */
3790 gen_op_movl_T0_seg((b >> 3) & 7);
3793 case 0x07: /* pop es */
3794 case 0x17: /* pop ss */
3795 case 0x1f: /* pop ds */
3800 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
3803 /* if reg == SS, inhibit interrupts/trace. */
3804 /* If several instructions disable interrupts, only the
3806 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
3807 gen_op_set_inhibit_irq();
3811 gen_jmp_im(s->pc - s->cs_base);
3815 case 0x1a1: /* pop fs */
3816 case 0x1a9: /* pop gs */
3818 gen_movl_seg_T0(s, (b >> 3) & 7, pc_start - s->cs_base);
3821 gen_jmp_im(s->pc - s->cs_base);
3826 /**************************/
3829 case 0x89: /* mov Gv, Ev */
3833 ot = dflag + OT_WORD;
3834 modrm = ldub_code(s->pc++);
3835 reg = ((modrm >> 3) & 7) | rex_r;
3837 /* generate a generic store */
3838 gen_ldst_modrm(s, modrm, ot, reg, 1);
3841 case 0xc7: /* mov Ev, Iv */
3845 ot = dflag + OT_WORD;
3846 modrm = ldub_code(s->pc++);
3847 mod = (modrm >> 6) & 3;
3849 s->rip_offset = insn_const_size(ot);
3850 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3852 val = insn_get(s, ot);
3853 gen_op_movl_T0_im(val);
3855 gen_op_st_T0_A0[ot + s->mem_index]();
3857 gen_op_mov_reg_T0[ot][(modrm & 7) | REX_B(s)]();
3860 case 0x8b: /* mov Ev, Gv */
3864 ot = OT_WORD + dflag;
3865 modrm = ldub_code(s->pc++);
3866 reg = ((modrm >> 3) & 7) | rex_r;
3868 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3869 gen_op_mov_reg_T0[ot][reg]();
3871 case 0x8e: /* mov seg, Gv */
3872 modrm = ldub_code(s->pc++);
3873 reg = (modrm >> 3) & 7;
3874 if (reg >= 6 || reg == R_CS)
3876 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3877 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
3879 /* if reg == SS, inhibit interrupts/trace */
3880 /* If several instructions disable interrupts, only the
3882 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
3883 gen_op_set_inhibit_irq();
3887 gen_jmp_im(s->pc - s->cs_base);
3891 case 0x8c: /* mov Gv, seg */
3892 modrm = ldub_code(s->pc++);
3893 reg = (modrm >> 3) & 7;
3894 mod = (modrm >> 6) & 3;
3897 gen_op_movl_T0_seg(reg);
3899 ot = OT_WORD + dflag;
3902 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
3905 case 0x1b6: /* movzbS Gv, Eb */
3906 case 0x1b7: /* movzwS Gv, Eb */
3907 case 0x1be: /* movsbS Gv, Eb */
3908 case 0x1bf: /* movswS Gv, Eb */
3911 /* d_ot is the size of destination */
3912 d_ot = dflag + OT_WORD;
3913 /* ot is the size of source */
3914 ot = (b & 1) + OT_BYTE;
3915 modrm = ldub_code(s->pc++);
3916 reg = ((modrm >> 3) & 7) | rex_r;
3917 mod = (modrm >> 6) & 3;
3918 rm = (modrm & 7) | REX_B(s);
3921 gen_op_mov_TN_reg[ot][0][rm]();
3922 switch(ot | (b & 8)) {
3924 gen_op_movzbl_T0_T0();
3927 gen_op_movsbl_T0_T0();
3930 gen_op_movzwl_T0_T0();
3934 gen_op_movswl_T0_T0();
3937 gen_op_mov_reg_T0[d_ot][reg]();
3939 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3941 gen_op_lds_T0_A0[ot + s->mem_index]();
3943 gen_op_ldu_T0_A0[ot + s->mem_index]();
3945 gen_op_mov_reg_T0[d_ot][reg]();
3950 case 0x8d: /* lea */
3951 ot = dflag + OT_WORD;
3952 modrm = ldub_code(s->pc++);
3953 mod = (modrm >> 6) & 3;
3956 reg = ((modrm >> 3) & 7) | rex_r;
3957 /* we must ensure that no segment is added */
3961 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3963 gen_op_mov_reg_A0[ot - OT_WORD][reg]();
3966 case 0xa0: /* mov EAX, Ov */
3968 case 0xa2: /* mov Ov, EAX */
3971 target_ulong offset_addr;
3976 ot = dflag + OT_WORD;
3977 #ifdef TARGET_X86_64
3978 if (s->aflag == 2) {
3979 offset_addr = ldq_code(s->pc);
3981 if (offset_addr == (int32_t)offset_addr)
3982 gen_op_movq_A0_im(offset_addr);
3984 gen_op_movq_A0_im64(offset_addr >> 32, offset_addr);
3989 offset_addr = insn_get(s, OT_LONG);
3991 offset_addr = insn_get(s, OT_WORD);
3993 gen_op_movl_A0_im(offset_addr);
3995 gen_add_A0_ds_seg(s);
3997 gen_op_ld_T0_A0[ot + s->mem_index]();
3998 gen_op_mov_reg_T0[ot][R_EAX]();
4000 gen_op_mov_TN_reg[ot][0][R_EAX]();
4001 gen_op_st_T0_A0[ot + s->mem_index]();
4005 case 0xd7: /* xlat */
4006 #ifdef TARGET_X86_64
4007 if (s->aflag == 2) {
4008 gen_op_movq_A0_reg[R_EBX]();
4009 gen_op_addq_A0_AL();
4013 gen_op_movl_A0_reg[R_EBX]();
4014 gen_op_addl_A0_AL();
4016 gen_op_andl_A0_ffff();
4018 gen_add_A0_ds_seg(s);
4019 gen_op_ldu_T0_A0[OT_BYTE + s->mem_index]();
4020 gen_op_mov_reg_T0[OT_BYTE][R_EAX]();
4022 case 0xb0 ... 0xb7: /* mov R, Ib */
4023 val = insn_get(s, OT_BYTE);
4024 gen_op_movl_T0_im(val);
4025 gen_op_mov_reg_T0[OT_BYTE][(b & 7) | REX_B(s)]();
4027 case 0xb8 ... 0xbf: /* mov R, Iv */
4028 #ifdef TARGET_X86_64
4032 tmp = ldq_code(s->pc);
4034 reg = (b & 7) | REX_B(s);
4035 gen_movtl_T0_im(tmp);
4036 gen_op_mov_reg_T0[OT_QUAD][reg]();
4040 ot = dflag ? OT_LONG : OT_WORD;
4041 val = insn_get(s, ot);
4042 reg = (b & 7) | REX_B(s);
4043 gen_op_movl_T0_im(val);
4044 gen_op_mov_reg_T0[ot][reg]();
4048 case 0x91 ... 0x97: /* xchg R, EAX */
4049 ot = dflag + OT_WORD;
4050 reg = (b & 7) | REX_B(s);
4054 case 0x87: /* xchg Ev, Gv */
4058 ot = dflag + OT_WORD;
4059 modrm = ldub_code(s->pc++);
4060 reg = ((modrm >> 3) & 7) | rex_r;
4061 mod = (modrm >> 6) & 3;
4063 rm = (modrm & 7) | REX_B(s);
4065 gen_op_mov_TN_reg[ot][0][reg]();
4066 gen_op_mov_TN_reg[ot][1][rm]();
4067 gen_op_mov_reg_T0[ot][rm]();
4068 gen_op_mov_reg_T1[ot][reg]();
4070 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4071 gen_op_mov_TN_reg[ot][0][reg]();
4072 /* for xchg, lock is implicit */
4073 if (!(prefixes & PREFIX_LOCK))
4075 gen_op_ld_T1_A0[ot + s->mem_index]();
4076 gen_op_st_T0_A0[ot + s->mem_index]();
4077 if (!(prefixes & PREFIX_LOCK))
4079 gen_op_mov_reg_T1[ot][reg]();
4082 case 0xc4: /* les Gv */
4087 case 0xc5: /* lds Gv */
4092 case 0x1b2: /* lss Gv */
4095 case 0x1b4: /* lfs Gv */
4098 case 0x1b5: /* lgs Gv */
4101 ot = dflag ? OT_LONG : OT_WORD;
4102 modrm = ldub_code(s->pc++);
4103 reg = ((modrm >> 3) & 7) | rex_r;
4104 mod = (modrm >> 6) & 3;
4107 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4108 gen_op_ld_T1_A0[ot + s->mem_index]();
4109 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
4110 /* load the segment first to handle exceptions properly */
4111 gen_op_ldu_T0_A0[OT_WORD + s->mem_index]();
4112 gen_movl_seg_T0(s, op, pc_start - s->cs_base);
4113 /* then put the data */
4114 gen_op_mov_reg_T1[ot][reg]();
4116 gen_jmp_im(s->pc - s->cs_base);
4121 /************************/
4132 ot = dflag + OT_WORD;
4134 modrm = ldub_code(s->pc++);
4135 mod = (modrm >> 6) & 3;
4136 op = (modrm >> 3) & 7;
4142 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4145 opreg = (modrm & 7) | REX_B(s);
4150 gen_shift(s, op, ot, opreg, OR_ECX);
4153 shift = ldub_code(s->pc++);
4155 gen_shifti(s, op, ot, opreg, shift);
4170 case 0x1a4: /* shld imm */
4174 case 0x1a5: /* shld cl */
4178 case 0x1ac: /* shrd imm */
4182 case 0x1ad: /* shrd cl */
4186 ot = dflag + OT_WORD;
4187 modrm = ldub_code(s->pc++);
4188 mod = (modrm >> 6) & 3;
4189 rm = (modrm & 7) | REX_B(s);
4190 reg = ((modrm >> 3) & 7) | rex_r;
4193 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4194 gen_op_ld_T0_A0[ot + s->mem_index]();
4196 gen_op_mov_TN_reg[ot][0][rm]();
4198 gen_op_mov_TN_reg[ot][1][reg]();
4201 val = ldub_code(s->pc++);
4208 gen_op_shiftd_T0_T1_im_cc[ot][op](val);
4210 gen_op_shiftd_mem_T0_T1_im_cc[ot + s->mem_index][op](val);
4211 if (op == 0 && ot != OT_WORD)
4212 s->cc_op = CC_OP_SHLB + ot;
4214 s->cc_op = CC_OP_SARB + ot;
4217 if (s->cc_op != CC_OP_DYNAMIC)
4218 gen_op_set_cc_op(s->cc_op);
4220 gen_op_shiftd_T0_T1_ECX_cc[ot][op]();
4222 gen_op_shiftd_mem_T0_T1_ECX_cc[ot + s->mem_index][op]();
4223 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
4226 gen_op_mov_reg_T0[ot][rm]();
4230 /************************/
4233 if (s->flags & (HF_EM_MASK | HF_TS_MASK)) {
4234 /* if CR0.EM or CR0.TS are set, generate an FPU exception */
4235 /* XXX: what to do if illegal op ? */
4236 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
4239 modrm = ldub_code(s->pc++);
4240 mod = (modrm >> 6) & 3;
4242 op = ((b & 7) << 3) | ((modrm >> 3) & 7);
4245 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4247 case 0x00 ... 0x07: /* fxxxs */
4248 case 0x10 ... 0x17: /* fixxxl */
4249 case 0x20 ... 0x27: /* fxxxl */
4250 case 0x30 ... 0x37: /* fixxx */
4257 gen_op_flds_FT0_A0();
4260 gen_op_fildl_FT0_A0();
4263 gen_op_fldl_FT0_A0();
4267 gen_op_fild_FT0_A0();
4271 gen_op_fp_arith_ST0_FT0[op1]();
4273 /* fcomp needs pop */
4278 case 0x08: /* flds */
4279 case 0x0a: /* fsts */
4280 case 0x0b: /* fstps */
4281 case 0x18: /* fildl */
4282 case 0x1a: /* fistl */
4283 case 0x1b: /* fistpl */
4284 case 0x28: /* fldl */
4285 case 0x2a: /* fstl */
4286 case 0x2b: /* fstpl */
4287 case 0x38: /* filds */
4288 case 0x3a: /* fists */
4289 case 0x3b: /* fistps */
4295 gen_op_flds_ST0_A0();
4298 gen_op_fildl_ST0_A0();
4301 gen_op_fldl_ST0_A0();
4305 gen_op_fild_ST0_A0();
4312 gen_op_fsts_ST0_A0();
4315 gen_op_fistl_ST0_A0();
4318 gen_op_fstl_ST0_A0();
4322 gen_op_fist_ST0_A0();
4330 case 0x0c: /* fldenv mem */
4331 gen_op_fldenv_A0(s->dflag);
4333 case 0x0d: /* fldcw mem */
4336 case 0x0e: /* fnstenv mem */
4337 gen_op_fnstenv_A0(s->dflag);
4339 case 0x0f: /* fnstcw mem */
4342 case 0x1d: /* fldt mem */
4343 gen_op_fldt_ST0_A0();
4345 case 0x1f: /* fstpt mem */
4346 gen_op_fstt_ST0_A0();
4349 case 0x2c: /* frstor mem */
4350 gen_op_frstor_A0(s->dflag);
4352 case 0x2e: /* fnsave mem */
4353 gen_op_fnsave_A0(s->dflag);
4355 case 0x2f: /* fnstsw mem */
4358 case 0x3c: /* fbld */
4359 gen_op_fbld_ST0_A0();
4361 case 0x3e: /* fbstp */
4362 gen_op_fbst_ST0_A0();
4365 case 0x3d: /* fildll */
4366 gen_op_fildll_ST0_A0();
4368 case 0x3f: /* fistpll */
4369 gen_op_fistll_ST0_A0();
4376 /* register float ops */
4380 case 0x08: /* fld sti */
4382 gen_op_fmov_ST0_STN((opreg + 1) & 7);
4384 case 0x09: /* fxchg sti */
4385 case 0x29: /* fxchg4 sti, undocumented op */
4386 case 0x39: /* fxchg7 sti, undocumented op */
4387 gen_op_fxchg_ST0_STN(opreg);
4389 case 0x0a: /* grp d9/2 */
4392 /* check exceptions (FreeBSD FPU probe) */
4393 if (s->cc_op != CC_OP_DYNAMIC)
4394 gen_op_set_cc_op(s->cc_op);
4395 gen_jmp_im(pc_start - s->cs_base);
4402 case 0x0c: /* grp d9/4 */
4412 gen_op_fcom_ST0_FT0();
4421 case 0x0d: /* grp d9/5 */
4430 gen_op_fldl2t_ST0();
4434 gen_op_fldl2e_ST0();
4442 gen_op_fldlg2_ST0();
4446 gen_op_fldln2_ST0();
4457 case 0x0e: /* grp d9/6 */
4468 case 3: /* fpatan */
4471 case 4: /* fxtract */
4474 case 5: /* fprem1 */
4477 case 6: /* fdecstp */
4481 case 7: /* fincstp */
4486 case 0x0f: /* grp d9/7 */
4491 case 1: /* fyl2xp1 */
4497 case 3: /* fsincos */
4500 case 5: /* fscale */
4503 case 4: /* frndint */
4515 case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
4516 case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
4517 case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
4523 gen_op_fp_arith_STN_ST0[op1](opreg);
4527 gen_op_fmov_FT0_STN(opreg);
4528 gen_op_fp_arith_ST0_FT0[op1]();
4532 case 0x02: /* fcom */
4533 case 0x22: /* fcom2, undocumented op */
4534 gen_op_fmov_FT0_STN(opreg);
4535 gen_op_fcom_ST0_FT0();
4537 case 0x03: /* fcomp */
4538 case 0x23: /* fcomp3, undocumented op */
4539 case 0x32: /* fcomp5, undocumented op */
4540 gen_op_fmov_FT0_STN(opreg);
4541 gen_op_fcom_ST0_FT0();
4544 case 0x15: /* da/5 */
4546 case 1: /* fucompp */
4547 gen_op_fmov_FT0_STN(1);
4548 gen_op_fucom_ST0_FT0();
4558 case 0: /* feni (287 only, just do nop here) */
4560 case 1: /* fdisi (287 only, just do nop here) */
4565 case 3: /* fninit */
4568 case 4: /* fsetpm (287 only, just do nop here) */
4574 case 0x1d: /* fucomi */
4575 if (s->cc_op != CC_OP_DYNAMIC)
4576 gen_op_set_cc_op(s->cc_op);
4577 gen_op_fmov_FT0_STN(opreg);
4578 gen_op_fucomi_ST0_FT0();
4579 s->cc_op = CC_OP_EFLAGS;
4581 case 0x1e: /* fcomi */
4582 if (s->cc_op != CC_OP_DYNAMIC)
4583 gen_op_set_cc_op(s->cc_op);
4584 gen_op_fmov_FT0_STN(opreg);
4585 gen_op_fcomi_ST0_FT0();
4586 s->cc_op = CC_OP_EFLAGS;
4588 case 0x28: /* ffree sti */
4589 gen_op_ffree_STN(opreg);
4591 case 0x2a: /* fst sti */
4592 gen_op_fmov_STN_ST0(opreg);
4594 case 0x2b: /* fstp sti */
4595 case 0x0b: /* fstp1 sti, undocumented op */
4596 case 0x3a: /* fstp8 sti, undocumented op */
4597 case 0x3b: /* fstp9 sti, undocumented op */
4598 gen_op_fmov_STN_ST0(opreg);
4601 case 0x2c: /* fucom st(i) */
4602 gen_op_fmov_FT0_STN(opreg);
4603 gen_op_fucom_ST0_FT0();
4605 case 0x2d: /* fucomp st(i) */
4606 gen_op_fmov_FT0_STN(opreg);
4607 gen_op_fucom_ST0_FT0();
4610 case 0x33: /* de/3 */
4612 case 1: /* fcompp */
4613 gen_op_fmov_FT0_STN(1);
4614 gen_op_fcom_ST0_FT0();
4622 case 0x38: /* ffreep sti, undocumented op */
4623 gen_op_ffree_STN(opreg);
4626 case 0x3c: /* df/4 */
4629 gen_op_fnstsw_EAX();
4635 case 0x3d: /* fucomip */
4636 if (s->cc_op != CC_OP_DYNAMIC)
4637 gen_op_set_cc_op(s->cc_op);
4638 gen_op_fmov_FT0_STN(opreg);
4639 gen_op_fucomi_ST0_FT0();
4641 s->cc_op = CC_OP_EFLAGS;
4643 case 0x3e: /* fcomip */
4644 if (s->cc_op != CC_OP_DYNAMIC)
4645 gen_op_set_cc_op(s->cc_op);
4646 gen_op_fmov_FT0_STN(opreg);
4647 gen_op_fcomi_ST0_FT0();
4649 s->cc_op = CC_OP_EFLAGS;
4651 case 0x10 ... 0x13: /* fcmovxx */
4655 const static uint8_t fcmov_cc[8] = {
4661 op1 = fcmov_cc[op & 3] | ((op >> 3) & 1);
4663 gen_op_fcmov_ST0_STN_T0(opreg);
4670 #ifdef USE_CODE_COPY
4671 s->tb->cflags |= CF_TB_FP_USED;
4674 /************************/
4677 case 0xa4: /* movsS */
4682 ot = dflag + OT_WORD;
4684 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
4685 gen_repz_movs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
4691 case 0xaa: /* stosS */
4696 ot = dflag + OT_WORD;
4698 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
4699 gen_repz_stos(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
4704 case 0xac: /* lodsS */
4709 ot = dflag + OT_WORD;
4710 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
4711 gen_repz_lods(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
4716 case 0xae: /* scasS */
4721 ot = dflag + OT_WORD;
4722 if (prefixes & PREFIX_REPNZ) {
4723 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
4724 } else if (prefixes & PREFIX_REPZ) {
4725 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
4728 s->cc_op = CC_OP_SUBB + ot;
4732 case 0xa6: /* cmpsS */
4737 ot = dflag + OT_WORD;
4738 if (prefixes & PREFIX_REPNZ) {
4739 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
4740 } else if (prefixes & PREFIX_REPZ) {
4741 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
4744 s->cc_op = CC_OP_SUBB + ot;
4747 case 0x6c: /* insS */
4752 ot = dflag ? OT_LONG : OT_WORD;
4753 gen_check_io(s, ot, 1, pc_start - s->cs_base);
4754 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
4755 gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
4760 case 0x6e: /* outsS */
4765 ot = dflag ? OT_LONG : OT_WORD;
4766 gen_check_io(s, ot, 1, pc_start - s->cs_base);
4767 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
4768 gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
4774 /************************/
4781 ot = dflag ? OT_LONG : OT_WORD;
4782 val = ldub_code(s->pc++);
4783 gen_op_movl_T0_im(val);
4784 gen_check_io(s, ot, 0, pc_start - s->cs_base);
4786 gen_op_mov_reg_T1[ot][R_EAX]();
4793 ot = dflag ? OT_LONG : OT_WORD;
4794 val = ldub_code(s->pc++);
4795 gen_op_movl_T0_im(val);
4796 gen_check_io(s, ot, 0, pc_start - s->cs_base);
4797 gen_op_mov_TN_reg[ot][1][R_EAX]();
4805 ot = dflag ? OT_LONG : OT_WORD;
4806 gen_op_mov_TN_reg[OT_WORD][0][R_EDX]();
4807 gen_op_andl_T0_ffff();
4808 gen_check_io(s, ot, 0, pc_start - s->cs_base);
4810 gen_op_mov_reg_T1[ot][R_EAX]();
4817 ot = dflag ? OT_LONG : OT_WORD;
4818 gen_op_mov_TN_reg[OT_WORD][0][R_EDX]();
4819 gen_op_andl_T0_ffff();
4820 gen_check_io(s, ot, 0, pc_start - s->cs_base);
4821 gen_op_mov_TN_reg[ot][1][R_EAX]();
4825 /************************/
4827 case 0xc2: /* ret im */
4828 val = ldsw_code(s->pc);
4831 if (CODE64(s) && s->dflag)
4833 gen_stack_update(s, val + (2 << s->dflag));
4835 gen_op_andl_T0_ffff();
4839 case 0xc3: /* ret */
4843 gen_op_andl_T0_ffff();
4847 case 0xca: /* lret im */
4848 val = ldsw_code(s->pc);
4851 if (s->pe && !s->vm86) {
4852 if (s->cc_op != CC_OP_DYNAMIC)
4853 gen_op_set_cc_op(s->cc_op);
4854 gen_jmp_im(pc_start - s->cs_base);
4855 gen_op_lret_protected(s->dflag, val);
4859 gen_op_ld_T0_A0[1 + s->dflag + s->mem_index]();
4861 gen_op_andl_T0_ffff();
4862 /* NOTE: keeping EIP updated is not a problem in case of
4866 gen_op_addl_A0_im(2 << s->dflag);
4867 gen_op_ld_T0_A0[1 + s->dflag + s->mem_index]();
4868 gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[R_CS]));
4869 /* add stack offset */
4870 gen_stack_update(s, val + (4 << s->dflag));
4874 case 0xcb: /* lret */
4877 case 0xcf: /* iret */
4880 gen_op_iret_real(s->dflag);
4881 s->cc_op = CC_OP_EFLAGS;
4882 } else if (s->vm86) {
4884 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
4886 gen_op_iret_real(s->dflag);
4887 s->cc_op = CC_OP_EFLAGS;
4890 if (s->cc_op != CC_OP_DYNAMIC)
4891 gen_op_set_cc_op(s->cc_op);
4892 gen_jmp_im(pc_start - s->cs_base);
4893 gen_op_iret_protected(s->dflag, s->pc - s->cs_base);
4894 s->cc_op = CC_OP_EFLAGS;
4898 case 0xe8: /* call im */
4901 tval = (int32_t)insn_get(s, OT_LONG);
4903 tval = (int16_t)insn_get(s, OT_WORD);
4904 next_eip = s->pc - s->cs_base;
4908 gen_movtl_T0_im(next_eip);
4913 case 0x9a: /* lcall im */
4915 unsigned int selector, offset;
4919 ot = dflag ? OT_LONG : OT_WORD;
4920 offset = insn_get(s, ot);
4921 selector = insn_get(s, OT_WORD);
4923 gen_op_movl_T0_im(selector);
4924 gen_op_movl_T1_imu(offset);
4927 case 0xe9: /* jmp im */
4929 tval = (int32_t)insn_get(s, OT_LONG);
4931 tval = (int16_t)insn_get(s, OT_WORD);
4932 tval += s->pc - s->cs_base;
4937 case 0xea: /* ljmp im */
4939 unsigned int selector, offset;
4943 ot = dflag ? OT_LONG : OT_WORD;
4944 offset = insn_get(s, ot);
4945 selector = insn_get(s, OT_WORD);
4947 gen_op_movl_T0_im(selector);
4948 gen_op_movl_T1_imu(offset);
4951 case 0xeb: /* jmp Jb */
4952 tval = (int8_t)insn_get(s, OT_BYTE);
4953 tval += s->pc - s->cs_base;
4958 case 0x70 ... 0x7f: /* jcc Jb */
4959 tval = (int8_t)insn_get(s, OT_BYTE);
4961 case 0x180 ... 0x18f: /* jcc Jv */
4963 tval = (int32_t)insn_get(s, OT_LONG);
4965 tval = (int16_t)insn_get(s, OT_WORD);
4968 next_eip = s->pc - s->cs_base;
4972 gen_jcc(s, b, tval, next_eip);
4975 case 0x190 ... 0x19f: /* setcc Gv */
4976 modrm = ldub_code(s->pc++);
4978 gen_ldst_modrm(s, modrm, OT_BYTE, OR_TMP0, 1);
4980 case 0x140 ... 0x14f: /* cmov Gv, Ev */
4981 ot = dflag + OT_WORD;
4982 modrm = ldub_code(s->pc++);
4983 reg = ((modrm >> 3) & 7) | rex_r;
4984 mod = (modrm >> 6) & 3;
4987 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4988 gen_op_ld_T1_A0[ot + s->mem_index]();
4990 rm = (modrm & 7) | REX_B(s);
4991 gen_op_mov_TN_reg[ot][1][rm]();
4993 gen_op_cmov_reg_T1_T0[ot - OT_WORD][reg]();
4996 /************************/
4998 case 0x9c: /* pushf */
4999 if (s->vm86 && s->iopl != 3) {
5000 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5002 if (s->cc_op != CC_OP_DYNAMIC)
5003 gen_op_set_cc_op(s->cc_op);
5004 gen_op_movl_T0_eflags();
5008 case 0x9d: /* popf */
5009 if (s->vm86 && s->iopl != 3) {
5010 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5015 gen_op_movl_eflags_T0_cpl0();
5017 gen_op_movw_eflags_T0_cpl0();
5020 if (s->cpl <= s->iopl) {
5022 gen_op_movl_eflags_T0_io();
5024 gen_op_movw_eflags_T0_io();
5028 gen_op_movl_eflags_T0();
5030 gen_op_movw_eflags_T0();
5035 s->cc_op = CC_OP_EFLAGS;
5036 /* abort translation because TF flag may change */
5037 gen_jmp_im(s->pc - s->cs_base);
5041 case 0x9e: /* sahf */
5044 gen_op_mov_TN_reg[OT_BYTE][0][R_AH]();
5045 if (s->cc_op != CC_OP_DYNAMIC)
5046 gen_op_set_cc_op(s->cc_op);
5047 gen_op_movb_eflags_T0();
5048 s->cc_op = CC_OP_EFLAGS;
5050 case 0x9f: /* lahf */
5053 if (s->cc_op != CC_OP_DYNAMIC)
5054 gen_op_set_cc_op(s->cc_op);
5055 gen_op_movl_T0_eflags();
5056 gen_op_mov_reg_T0[OT_BYTE][R_AH]();
5058 case 0xf5: /* cmc */
5059 if (s->cc_op != CC_OP_DYNAMIC)
5060 gen_op_set_cc_op(s->cc_op);
5062 s->cc_op = CC_OP_EFLAGS;
5064 case 0xf8: /* clc */
5065 if (s->cc_op != CC_OP_DYNAMIC)
5066 gen_op_set_cc_op(s->cc_op);
5068 s->cc_op = CC_OP_EFLAGS;
5070 case 0xf9: /* stc */
5071 if (s->cc_op != CC_OP_DYNAMIC)
5072 gen_op_set_cc_op(s->cc_op);
5074 s->cc_op = CC_OP_EFLAGS;
5076 case 0xfc: /* cld */
5079 case 0xfd: /* std */
5083 /************************/
5084 /* bit operations */
5085 case 0x1ba: /* bt/bts/btr/btc Gv, im */
5086 ot = dflag + OT_WORD;
5087 modrm = ldub_code(s->pc++);
5088 op = ((modrm >> 3) & 7) | rex_r;
5089 mod = (modrm >> 6) & 3;
5090 rm = (modrm & 7) | REX_B(s);
5093 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
5094 gen_op_ld_T0_A0[ot + s->mem_index]();
5096 gen_op_mov_TN_reg[ot][0][rm]();
5099 val = ldub_code(s->pc++);
5100 gen_op_movl_T1_im(val);
5104 gen_op_btx_T0_T1_cc[ot - OT_WORD][op]();
5105 s->cc_op = CC_OP_SARB + ot;
5108 gen_op_st_T0_A0[ot + s->mem_index]();
5110 gen_op_mov_reg_T0[ot][rm]();
5111 gen_op_update_bt_cc();
5114 case 0x1a3: /* bt Gv, Ev */
5117 case 0x1ab: /* bts */
5120 case 0x1b3: /* btr */
5123 case 0x1bb: /* btc */
5126 ot = dflag + OT_WORD;
5127 modrm = ldub_code(s->pc++);
5128 reg = ((modrm >> 3) & 7) | rex_r;
5129 mod = (modrm >> 6) & 3;
5130 rm = (modrm & 7) | REX_B(s);
5131 gen_op_mov_TN_reg[OT_LONG][1][reg]();
5133 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
5134 /* specific case: we need to add a displacement */
5135 gen_op_add_bit_A0_T1[ot - OT_WORD]();
5136 gen_op_ld_T0_A0[ot + s->mem_index]();
5138 gen_op_mov_TN_reg[ot][0][rm]();
5140 gen_op_btx_T0_T1_cc[ot - OT_WORD][op]();
5141 s->cc_op = CC_OP_SARB + ot;
5144 gen_op_st_T0_A0[ot + s->mem_index]();
5146 gen_op_mov_reg_T0[ot][rm]();
5147 gen_op_update_bt_cc();
5150 case 0x1bc: /* bsf */
5151 case 0x1bd: /* bsr */
5152 ot = dflag + OT_WORD;
5153 modrm = ldub_code(s->pc++);
5154 reg = ((modrm >> 3) & 7) | rex_r;
5155 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
5156 /* NOTE: in order to handle the 0 case, we must load the
5157 result. It could be optimized with a generated jump */
5158 gen_op_mov_TN_reg[ot][1][reg]();
5159 gen_op_bsx_T0_cc[ot - OT_WORD][b & 1]();
5160 gen_op_mov_reg_T1[ot][reg]();
5161 s->cc_op = CC_OP_LOGICB + ot;
5163 /************************/
5165 case 0x27: /* daa */
5168 if (s->cc_op != CC_OP_DYNAMIC)
5169 gen_op_set_cc_op(s->cc_op);
5171 s->cc_op = CC_OP_EFLAGS;
5173 case 0x2f: /* das */
5176 if (s->cc_op != CC_OP_DYNAMIC)
5177 gen_op_set_cc_op(s->cc_op);
5179 s->cc_op = CC_OP_EFLAGS;
5181 case 0x37: /* aaa */
5184 if (s->cc_op != CC_OP_DYNAMIC)
5185 gen_op_set_cc_op(s->cc_op);
5187 s->cc_op = CC_OP_EFLAGS;
5189 case 0x3f: /* aas */
5192 if (s->cc_op != CC_OP_DYNAMIC)
5193 gen_op_set_cc_op(s->cc_op);
5195 s->cc_op = CC_OP_EFLAGS;
5197 case 0xd4: /* aam */
5200 val = ldub_code(s->pc++);
5202 s->cc_op = CC_OP_LOGICB;
5204 case 0xd5: /* aad */
5207 val = ldub_code(s->pc++);
5209 s->cc_op = CC_OP_LOGICB;
5211 /************************/
5213 case 0x90: /* nop */
5214 /* XXX: xchg + rex handling */
5215 /* XXX: correct lock test for all insn */
5216 if (prefixes & PREFIX_LOCK)
5219 case 0x9b: /* fwait */
5220 if ((s->flags & (HF_MP_MASK | HF_TS_MASK)) ==
5221 (HF_MP_MASK | HF_TS_MASK)) {
5222 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
5224 if (s->cc_op != CC_OP_DYNAMIC)
5225 gen_op_set_cc_op(s->cc_op);
5226 gen_jmp_im(pc_start - s->cs_base);
5230 case 0xcc: /* int3 */
5231 gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base);
5233 case 0xcd: /* int N */
5234 val = ldub_code(s->pc++);
5235 if (s->vm86 && s->iopl != 3) {
5236 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5238 gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base);
5241 case 0xce: /* into */
5244 if (s->cc_op != CC_OP_DYNAMIC)
5245 gen_op_set_cc_op(s->cc_op);
5246 gen_jmp_im(pc_start - s->cs_base);
5247 gen_op_into(s->pc - pc_start);
5249 case 0xf1: /* icebp (undocumented, exits to external debugger) */
5251 gen_debug(s, pc_start - s->cs_base);
5254 tb_flush(cpu_single_env);
5255 cpu_set_log(CPU_LOG_INT | CPU_LOG_TB_IN_ASM);
5258 case 0xfa: /* cli */
5260 if (s->cpl <= s->iopl) {
5263 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5269 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5273 case 0xfb: /* sti */
5275 if (s->cpl <= s->iopl) {
5278 /* interruptions are enabled only the first insn after sti */
5279 /* If several instructions disable interrupts, only the
5281 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
5282 gen_op_set_inhibit_irq();
5283 /* give a chance to handle pending irqs */
5284 gen_jmp_im(s->pc - s->cs_base);
5287 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5293 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5297 case 0x62: /* bound */
5300 ot = dflag ? OT_LONG : OT_WORD;
5301 modrm = ldub_code(s->pc++);
5302 reg = (modrm >> 3) & 7;
5303 mod = (modrm >> 6) & 3;
5306 gen_op_mov_TN_reg[ot][0][reg]();
5307 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
5308 gen_jmp_im(pc_start - s->cs_base);
5314 case 0x1c8 ... 0x1cf: /* bswap reg */
5315 reg = (b & 7) | REX_B(s);
5316 #ifdef TARGET_X86_64
5318 gen_op_mov_TN_reg[OT_QUAD][0][reg]();
5320 gen_op_mov_reg_T0[OT_QUAD][reg]();
5324 gen_op_mov_TN_reg[OT_LONG][0][reg]();
5326 gen_op_mov_reg_T0[OT_LONG][reg]();
5329 case 0xd6: /* salc */
5332 if (s->cc_op != CC_OP_DYNAMIC)
5333 gen_op_set_cc_op(s->cc_op);
5336 case 0xe0: /* loopnz */
5337 case 0xe1: /* loopz */
5338 if (s->cc_op != CC_OP_DYNAMIC)
5339 gen_op_set_cc_op(s->cc_op);
5341 case 0xe2: /* loop */
5342 case 0xe3: /* jecxz */
5346 tval = (int8_t)insn_get(s, OT_BYTE);
5347 next_eip = s->pc - s->cs_base;
5352 l1 = gen_new_label();
5353 l2 = gen_new_label();
5356 gen_op_jz_ecx[s->aflag](l1);
5358 gen_op_dec_ECX[s->aflag]();
5361 gen_op_loop[s->aflag][b](l1);
5364 gen_jmp_im(next_eip);
5365 gen_op_jmp_label(l2);
5372 case 0x130: /* wrmsr */
5373 case 0x132: /* rdmsr */
5375 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5383 case 0x131: /* rdtsc */
5384 gen_jmp_im(pc_start - s->cs_base);
5387 case 0x134: /* sysenter */
5391 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5393 if (s->cc_op != CC_OP_DYNAMIC) {
5394 gen_op_set_cc_op(s->cc_op);
5395 s->cc_op = CC_OP_DYNAMIC;
5397 gen_jmp_im(pc_start - s->cs_base);
5402 case 0x135: /* sysexit */
5406 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5408 if (s->cc_op != CC_OP_DYNAMIC) {
5409 gen_op_set_cc_op(s->cc_op);
5410 s->cc_op = CC_OP_DYNAMIC;
5412 gen_jmp_im(pc_start - s->cs_base);
5417 #ifdef TARGET_X86_64
5418 case 0x105: /* syscall */
5419 /* XXX: is it usable in real mode ? */
5420 if (s->cc_op != CC_OP_DYNAMIC) {
5421 gen_op_set_cc_op(s->cc_op);
5422 s->cc_op = CC_OP_DYNAMIC;
5424 gen_jmp_im(pc_start - s->cs_base);
5425 gen_op_syscall(s->pc - pc_start);
5428 case 0x107: /* sysret */
5430 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5432 if (s->cc_op != CC_OP_DYNAMIC) {
5433 gen_op_set_cc_op(s->cc_op);
5434 s->cc_op = CC_OP_DYNAMIC;
5436 gen_jmp_im(pc_start - s->cs_base);
5437 gen_op_sysret(s->dflag);
5438 /* condition codes are modified only in long mode */
5440 s->cc_op = CC_OP_EFLAGS;
5445 case 0x1a2: /* cpuid */
5448 case 0xf4: /* hlt */
5450 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5452 if (s->cc_op != CC_OP_DYNAMIC)
5453 gen_op_set_cc_op(s->cc_op);
5454 gen_jmp_im(s->pc - s->cs_base);
5460 modrm = ldub_code(s->pc++);
5461 mod = (modrm >> 6) & 3;
5462 op = (modrm >> 3) & 7;
5465 if (!s->pe || s->vm86)
5467 gen_op_movl_T0_env(offsetof(CPUX86State,ldt.selector));
5471 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
5474 if (!s->pe || s->vm86)
5477 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5479 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
5480 gen_jmp_im(pc_start - s->cs_base);
5485 if (!s->pe || s->vm86)
5487 gen_op_movl_T0_env(offsetof(CPUX86State,tr.selector));
5491 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
5494 if (!s->pe || s->vm86)
5497 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5499 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
5500 gen_jmp_im(pc_start - s->cs_base);
5506 if (!s->pe || s->vm86)
5508 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
5509 if (s->cc_op != CC_OP_DYNAMIC)
5510 gen_op_set_cc_op(s->cc_op);
5515 s->cc_op = CC_OP_EFLAGS;
5522 modrm = ldub_code(s->pc++);
5523 mod = (modrm >> 6) & 3;
5524 op = (modrm >> 3) & 7;
5530 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
5532 gen_op_movl_T0_env(offsetof(CPUX86State,gdt.limit));
5534 gen_op_movl_T0_env(offsetof(CPUX86State,idt.limit));
5535 gen_op_st_T0_A0[OT_WORD + s->mem_index]();
5536 gen_add_A0_im(s, 2);
5538 gen_op_movtl_T0_env(offsetof(CPUX86State,gdt.base));
5540 gen_op_movtl_T0_env(offsetof(CPUX86State,idt.base));
5542 gen_op_andl_T0_im(0xffffff);
5543 gen_op_st_T0_A0[CODE64(s) + OT_LONG + s->mem_index]();
5550 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5552 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
5553 gen_op_ld_T1_A0[OT_WORD + s->mem_index]();
5554 gen_add_A0_im(s, 2);
5555 gen_op_ld_T0_A0[CODE64(s) + OT_LONG + s->mem_index]();
5557 gen_op_andl_T0_im(0xffffff);
5559 gen_op_movtl_env_T0(offsetof(CPUX86State,gdt.base));
5560 gen_op_movl_env_T1(offsetof(CPUX86State,gdt.limit));
5562 gen_op_movtl_env_T0(offsetof(CPUX86State,idt.base));
5563 gen_op_movl_env_T1(offsetof(CPUX86State,idt.limit));
5568 gen_op_movl_T0_env(offsetof(CPUX86State,cr[0]));
5569 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 1);
5573 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5575 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
5577 gen_jmp_im(s->pc - s->cs_base);
5581 case 7: /* invlpg */
5583 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5586 #ifdef TARGET_X86_64
5587 if (CODE64(s) && (modrm & 7) == 0) {
5589 gen_op_movtl_T0_env(offsetof(CPUX86State,segs[R_GS].base));
5590 gen_op_movtl_T1_env(offsetof(CPUX86State,kernelgsbase));
5591 gen_op_movtl_env_T1(offsetof(CPUX86State,segs[R_GS].base));
5592 gen_op_movtl_env_T0(offsetof(CPUX86State,kernelgsbase));
5599 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
5601 gen_jmp_im(s->pc - s->cs_base);
5610 case 0x108: /* invd */
5611 case 0x109: /* wbinvd */
5613 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5618 case 0x63: /* arpl or movslS (x86_64) */
5619 #ifdef TARGET_X86_64
5622 /* d_ot is the size of destination */
5623 d_ot = dflag + OT_WORD;
5625 modrm = ldub_code(s->pc++);
5626 reg = ((modrm >> 3) & 7) | rex_r;
5627 mod = (modrm >> 6) & 3;
5628 rm = (modrm & 7) | REX_B(s);
5631 gen_op_mov_TN_reg[OT_LONG][0][rm]();
5633 if (d_ot == OT_QUAD)
5634 gen_op_movslq_T0_T0();
5635 gen_op_mov_reg_T0[d_ot][reg]();
5637 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
5638 if (d_ot == OT_QUAD) {
5639 gen_op_lds_T0_A0[OT_LONG + s->mem_index]();
5641 gen_op_ld_T0_A0[OT_LONG + s->mem_index]();
5643 gen_op_mov_reg_T0[d_ot][reg]();
5648 if (!s->pe || s->vm86)
5650 ot = dflag ? OT_LONG : OT_WORD;
5651 modrm = ldub_code(s->pc++);
5652 reg = (modrm >> 3) & 7;
5653 mod = (modrm >> 6) & 3;
5656 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
5657 gen_op_ld_T0_A0[ot + s->mem_index]();
5659 gen_op_mov_TN_reg[ot][0][rm]();
5661 if (s->cc_op != CC_OP_DYNAMIC)
5662 gen_op_set_cc_op(s->cc_op);
5664 s->cc_op = CC_OP_EFLAGS;
5666 gen_op_st_T0_A0[ot + s->mem_index]();
5668 gen_op_mov_reg_T0[ot][rm]();
5670 gen_op_arpl_update();
5673 case 0x102: /* lar */
5674 case 0x103: /* lsl */
5675 if (!s->pe || s->vm86)
5677 ot = dflag ? OT_LONG : OT_WORD;
5678 modrm = ldub_code(s->pc++);
5679 reg = ((modrm >> 3) & 7) | rex_r;
5680 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
5681 gen_op_mov_TN_reg[ot][1][reg]();
5682 if (s->cc_op != CC_OP_DYNAMIC)
5683 gen_op_set_cc_op(s->cc_op);
5688 s->cc_op = CC_OP_EFLAGS;
5689 gen_op_mov_reg_T1[ot][reg]();
5692 modrm = ldub_code(s->pc++);
5693 mod = (modrm >> 6) & 3;
5694 op = (modrm >> 3) & 7;
5696 case 0: /* prefetchnta */
5697 case 1: /* prefetchnt0 */
5698 case 2: /* prefetchnt0 */
5699 case 3: /* prefetchnt0 */
5702 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
5703 /* nothing more to do */
5709 case 0x120: /* mov reg, crN */
5710 case 0x122: /* mov crN, reg */
5712 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5714 modrm = ldub_code(s->pc++);
5715 if ((modrm & 0xc0) != 0xc0)
5717 rm = (modrm & 7) | REX_B(s);
5718 reg = ((modrm >> 3) & 7) | rex_r;
5730 gen_op_mov_TN_reg[ot][0][rm]();
5731 gen_op_movl_crN_T0(reg);
5732 gen_jmp_im(s->pc - s->cs_base);
5735 #if !defined(CONFIG_USER_ONLY)
5737 gen_op_movtl_T0_cr8();
5740 gen_op_movtl_T0_env(offsetof(CPUX86State,cr[reg]));
5741 gen_op_mov_reg_T0[ot][rm]();
5749 case 0x121: /* mov reg, drN */
5750 case 0x123: /* mov drN, reg */
5752 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5754 modrm = ldub_code(s->pc++);
5755 if ((modrm & 0xc0) != 0xc0)
5757 rm = (modrm & 7) | REX_B(s);
5758 reg = ((modrm >> 3) & 7) | rex_r;
5763 /* XXX: do it dynamically with CR4.DE bit */
5764 if (reg == 4 || reg == 5 || reg >= 8)
5767 gen_op_mov_TN_reg[ot][0][rm]();
5768 gen_op_movl_drN_T0(reg);
5769 gen_jmp_im(s->pc - s->cs_base);
5772 gen_op_movtl_T0_env(offsetof(CPUX86State,dr[reg]));
5773 gen_op_mov_reg_T0[ot][rm]();
5777 case 0x106: /* clts */
5779 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5782 /* abort block because static cpu state changed */
5783 gen_jmp_im(s->pc - s->cs_base);
5787 /* MMX/SSE/SSE2/PNI support */
5788 case 0x1c3: /* MOVNTI reg, mem */
5789 if (!(s->cpuid_features & CPUID_SSE2))
5791 ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
5792 modrm = ldub_code(s->pc++);
5793 mod = (modrm >> 6) & 3;
5796 reg = ((modrm >> 3) & 7) | rex_r;
5797 /* generate a generic store */
5798 gen_ldst_modrm(s, modrm, ot, reg, 1);
5801 modrm = ldub_code(s->pc++);
5802 mod = (modrm >> 6) & 3;
5803 op = (modrm >> 3) & 7;
5805 case 0: /* fxsave */
5806 if (mod == 3 || !(s->cpuid_features & CPUID_FXSR))
5808 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
5809 gen_op_fxsave_A0((s->dflag == 2));
5811 case 1: /* fxrstor */
5812 if (mod == 3 || !(s->cpuid_features & CPUID_FXSR))
5814 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
5815 gen_op_fxrstor_A0((s->dflag == 2));
5817 case 2: /* ldmxcsr */
5818 case 3: /* stmxcsr */
5819 if (s->flags & HF_TS_MASK) {
5820 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
5823 if ((s->flags & HF_EM_MASK) || !(s->flags & HF_OSFXSR_MASK) ||
5826 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
5828 gen_op_ld_T0_A0[OT_LONG + s->mem_index]();
5829 gen_op_movl_env_T0(offsetof(CPUX86State, mxcsr));
5831 gen_op_movl_T0_env(offsetof(CPUX86State, mxcsr));
5832 gen_op_st_T0_A0[OT_LONG + s->mem_index]();
5835 case 5: /* lfence */
5836 case 6: /* mfence */
5837 if ((modrm & 0xc7) != 0xc0 || !(s->cpuid_features & CPUID_SSE))
5840 case 7: /* sfence / clflush */
5841 if ((modrm & 0xc7) == 0xc0) {
5843 if (!(s->cpuid_features & CPUID_SSE))
5847 if (!(s->cpuid_features & CPUID_CLFLUSH))
5849 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
5856 case 0x10d: /* prefetch */
5857 modrm = ldub_code(s->pc++);
5858 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
5859 /* ignore for now */
5861 case 0x110 ... 0x117:
5862 case 0x128 ... 0x12f:
5863 case 0x150 ... 0x177:
5864 case 0x17c ... 0x17f:
5866 case 0x1c4 ... 0x1c6:
5867 case 0x1d0 ... 0x1fe:
5868 gen_sse(s, b, pc_start, rex_r);
5873 /* lock generation */
5874 if (s->prefix & PREFIX_LOCK)
5878 if (s->prefix & PREFIX_LOCK)
5880 /* XXX: ensure that no lock was generated */
5881 gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
5885 #define CC_OSZAPC (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C)
5886 #define CC_OSZAP (CC_O | CC_S | CC_Z | CC_A | CC_P)
5888 /* flags read by an operation */
5889 static uint16_t opc_read_flags[NB_OPS] = {
5890 [INDEX_op_aas] = CC_A,
5891 [INDEX_op_aaa] = CC_A,
5892 [INDEX_op_das] = CC_A | CC_C,
5893 [INDEX_op_daa] = CC_A | CC_C,
5895 /* subtle: due to the incl/decl implementation, C is used */
5896 [INDEX_op_update_inc_cc] = CC_C,
5898 [INDEX_op_into] = CC_O,
5900 [INDEX_op_jb_subb] = CC_C,
5901 [INDEX_op_jb_subw] = CC_C,
5902 [INDEX_op_jb_subl] = CC_C,
5904 [INDEX_op_jz_subb] = CC_Z,
5905 [INDEX_op_jz_subw] = CC_Z,
5906 [INDEX_op_jz_subl] = CC_Z,
5908 [INDEX_op_jbe_subb] = CC_Z | CC_C,
5909 [INDEX_op_jbe_subw] = CC_Z | CC_C,
5910 [INDEX_op_jbe_subl] = CC_Z | CC_C,
5912 [INDEX_op_js_subb] = CC_S,
5913 [INDEX_op_js_subw] = CC_S,
5914 [INDEX_op_js_subl] = CC_S,
5916 [INDEX_op_jl_subb] = CC_O | CC_S,
5917 [INDEX_op_jl_subw] = CC_O | CC_S,
5918 [INDEX_op_jl_subl] = CC_O | CC_S,
5920 [INDEX_op_jle_subb] = CC_O | CC_S | CC_Z,
5921 [INDEX_op_jle_subw] = CC_O | CC_S | CC_Z,
5922 [INDEX_op_jle_subl] = CC_O | CC_S | CC_Z,
5924 [INDEX_op_loopnzw] = CC_Z,
5925 [INDEX_op_loopnzl] = CC_Z,
5926 [INDEX_op_loopzw] = CC_Z,
5927 [INDEX_op_loopzl] = CC_Z,
5929 [INDEX_op_seto_T0_cc] = CC_O,
5930 [INDEX_op_setb_T0_cc] = CC_C,
5931 [INDEX_op_setz_T0_cc] = CC_Z,
5932 [INDEX_op_setbe_T0_cc] = CC_Z | CC_C,
5933 [INDEX_op_sets_T0_cc] = CC_S,
5934 [INDEX_op_setp_T0_cc] = CC_P,
5935 [INDEX_op_setl_T0_cc] = CC_O | CC_S,
5936 [INDEX_op_setle_T0_cc] = CC_O | CC_S | CC_Z,
5938 [INDEX_op_setb_T0_subb] = CC_C,
5939 [INDEX_op_setb_T0_subw] = CC_C,
5940 [INDEX_op_setb_T0_subl] = CC_C,
5942 [INDEX_op_setz_T0_subb] = CC_Z,
5943 [INDEX_op_setz_T0_subw] = CC_Z,
5944 [INDEX_op_setz_T0_subl] = CC_Z,
5946 [INDEX_op_setbe_T0_subb] = CC_Z | CC_C,
5947 [INDEX_op_setbe_T0_subw] = CC_Z | CC_C,
5948 [INDEX_op_setbe_T0_subl] = CC_Z | CC_C,
5950 [INDEX_op_sets_T0_subb] = CC_S,
5951 [INDEX_op_sets_T0_subw] = CC_S,
5952 [INDEX_op_sets_T0_subl] = CC_S,
5954 [INDEX_op_setl_T0_subb] = CC_O | CC_S,
5955 [INDEX_op_setl_T0_subw] = CC_O | CC_S,
5956 [INDEX_op_setl_T0_subl] = CC_O | CC_S,
5958 [INDEX_op_setle_T0_subb] = CC_O | CC_S | CC_Z,
5959 [INDEX_op_setle_T0_subw] = CC_O | CC_S | CC_Z,
5960 [INDEX_op_setle_T0_subl] = CC_O | CC_S | CC_Z,
5962 [INDEX_op_movl_T0_eflags] = CC_OSZAPC,
5963 [INDEX_op_cmc] = CC_C,
5964 [INDEX_op_salc] = CC_C,
5966 /* needed for correct flag optimisation before string ops */
5967 [INDEX_op_jnz_ecxw] = CC_OSZAPC,
5968 [INDEX_op_jnz_ecxl] = CC_OSZAPC,
5969 [INDEX_op_jz_ecxw] = CC_OSZAPC,
5970 [INDEX_op_jz_ecxl] = CC_OSZAPC,
5972 #ifdef TARGET_X86_64
5973 [INDEX_op_jb_subq] = CC_C,
5974 [INDEX_op_jz_subq] = CC_Z,
5975 [INDEX_op_jbe_subq] = CC_Z | CC_C,
5976 [INDEX_op_js_subq] = CC_S,
5977 [INDEX_op_jl_subq] = CC_O | CC_S,
5978 [INDEX_op_jle_subq] = CC_O | CC_S | CC_Z,
5980 [INDEX_op_loopnzq] = CC_Z,
5981 [INDEX_op_loopzq] = CC_Z,
5983 [INDEX_op_setb_T0_subq] = CC_C,
5984 [INDEX_op_setz_T0_subq] = CC_Z,
5985 [INDEX_op_setbe_T0_subq] = CC_Z | CC_C,
5986 [INDEX_op_sets_T0_subq] = CC_S,
5987 [INDEX_op_setl_T0_subq] = CC_O | CC_S,
5988 [INDEX_op_setle_T0_subq] = CC_O | CC_S | CC_Z,
5990 [INDEX_op_jnz_ecxq] = CC_OSZAPC,
5991 [INDEX_op_jz_ecxq] = CC_OSZAPC,
5994 #define DEF_READF(SUFFIX)\
5995 [INDEX_op_adcb ## SUFFIX ## _T0_T1_cc] = CC_C,\
5996 [INDEX_op_adcw ## SUFFIX ## _T0_T1_cc] = CC_C,\
5997 [INDEX_op_adcl ## SUFFIX ## _T0_T1_cc] = CC_C,\
5998 X86_64_DEF([INDEX_op_adcq ## SUFFIX ## _T0_T1_cc] = CC_C,)\
5999 [INDEX_op_sbbb ## SUFFIX ## _T0_T1_cc] = CC_C,\
6000 [INDEX_op_sbbw ## SUFFIX ## _T0_T1_cc] = CC_C,\
6001 [INDEX_op_sbbl ## SUFFIX ## _T0_T1_cc] = CC_C,\
6002 X86_64_DEF([INDEX_op_sbbq ## SUFFIX ## _T0_T1_cc] = CC_C,)\
6004 [INDEX_op_rclb ## SUFFIX ## _T0_T1_cc] = CC_C,\
6005 [INDEX_op_rclw ## SUFFIX ## _T0_T1_cc] = CC_C,\
6006 [INDEX_op_rcll ## SUFFIX ## _T0_T1_cc] = CC_C,\
6007 X86_64_DEF([INDEX_op_rclq ## SUFFIX ## _T0_T1_cc] = CC_C,)\
6008 [INDEX_op_rcrb ## SUFFIX ## _T0_T1_cc] = CC_C,\
6009 [INDEX_op_rcrw ## SUFFIX ## _T0_T1_cc] = CC_C,\
6010 [INDEX_op_rcrl ## SUFFIX ## _T0_T1_cc] = CC_C,\
6011 X86_64_DEF([INDEX_op_rcrq ## SUFFIX ## _T0_T1_cc] = CC_C,)
6015 #ifndef CONFIG_USER_ONLY
6021 /* flags written by an operation */
6022 static uint16_t opc_write_flags[NB_OPS] = {
6023 [INDEX_op_update2_cc] = CC_OSZAPC,
6024 [INDEX_op_update1_cc] = CC_OSZAPC,
6025 [INDEX_op_cmpl_T0_T1_cc] = CC_OSZAPC,
6026 [INDEX_op_update_neg_cc] = CC_OSZAPC,
6027 /* subtle: due to the incl/decl implementation, C is used */
6028 [INDEX_op_update_inc_cc] = CC_OSZAPC,
6029 [INDEX_op_testl_T0_T1_cc] = CC_OSZAPC,
6031 [INDEX_op_mulb_AL_T0] = CC_OSZAPC,
6032 [INDEX_op_mulw_AX_T0] = CC_OSZAPC,
6033 [INDEX_op_mull_EAX_T0] = CC_OSZAPC,
6034 X86_64_DEF([INDEX_op_mulq_EAX_T0] = CC_OSZAPC,)
6035 [INDEX_op_imulb_AL_T0] = CC_OSZAPC,
6036 [INDEX_op_imulw_AX_T0] = CC_OSZAPC,
6037 [INDEX_op_imull_EAX_T0] = CC_OSZAPC,
6038 X86_64_DEF([INDEX_op_imulq_EAX_T0] = CC_OSZAPC,)
6039 [INDEX_op_imulw_T0_T1] = CC_OSZAPC,
6040 [INDEX_op_imull_T0_T1] = CC_OSZAPC,
6041 X86_64_DEF([INDEX_op_imulq_T0_T1] = CC_OSZAPC,)
6044 [INDEX_op_ucomiss] = CC_OSZAPC,
6045 [INDEX_op_ucomisd] = CC_OSZAPC,
6046 [INDEX_op_comiss] = CC_OSZAPC,
6047 [INDEX_op_comisd] = CC_OSZAPC,
6050 [INDEX_op_aam] = CC_OSZAPC,
6051 [INDEX_op_aad] = CC_OSZAPC,
6052 [INDEX_op_aas] = CC_OSZAPC,
6053 [INDEX_op_aaa] = CC_OSZAPC,
6054 [INDEX_op_das] = CC_OSZAPC,
6055 [INDEX_op_daa] = CC_OSZAPC,
6057 [INDEX_op_movb_eflags_T0] = CC_S | CC_Z | CC_A | CC_P | CC_C,
6058 [INDEX_op_movw_eflags_T0] = CC_OSZAPC,
6059 [INDEX_op_movl_eflags_T0] = CC_OSZAPC,
6060 [INDEX_op_movw_eflags_T0_io] = CC_OSZAPC,
6061 [INDEX_op_movl_eflags_T0_io] = CC_OSZAPC,
6062 [INDEX_op_movw_eflags_T0_cpl0] = CC_OSZAPC,
6063 [INDEX_op_movl_eflags_T0_cpl0] = CC_OSZAPC,
6064 [INDEX_op_clc] = CC_C,
6065 [INDEX_op_stc] = CC_C,
6066 [INDEX_op_cmc] = CC_C,
6068 [INDEX_op_btw_T0_T1_cc] = CC_OSZAPC,
6069 [INDEX_op_btl_T0_T1_cc] = CC_OSZAPC,
6070 X86_64_DEF([INDEX_op_btq_T0_T1_cc] = CC_OSZAPC,)
6071 [INDEX_op_btsw_T0_T1_cc] = CC_OSZAPC,
6072 [INDEX_op_btsl_T0_T1_cc] = CC_OSZAPC,
6073 X86_64_DEF([INDEX_op_btsq_T0_T1_cc] = CC_OSZAPC,)
6074 [INDEX_op_btrw_T0_T1_cc] = CC_OSZAPC,
6075 [INDEX_op_btrl_T0_T1_cc] = CC_OSZAPC,
6076 X86_64_DEF([INDEX_op_btrq_T0_T1_cc] = CC_OSZAPC,)
6077 [INDEX_op_btcw_T0_T1_cc] = CC_OSZAPC,
6078 [INDEX_op_btcl_T0_T1_cc] = CC_OSZAPC,
6079 X86_64_DEF([INDEX_op_btcq_T0_T1_cc] = CC_OSZAPC,)
6081 [INDEX_op_bsfw_T0_cc] = CC_OSZAPC,
6082 [INDEX_op_bsfl_T0_cc] = CC_OSZAPC,
6083 X86_64_DEF([INDEX_op_bsfq_T0_cc] = CC_OSZAPC,)
6084 [INDEX_op_bsrw_T0_cc] = CC_OSZAPC,
6085 [INDEX_op_bsrl_T0_cc] = CC_OSZAPC,
6086 X86_64_DEF([INDEX_op_bsrq_T0_cc] = CC_OSZAPC,)
6088 [INDEX_op_cmpxchgb_T0_T1_EAX_cc] = CC_OSZAPC,
6089 [INDEX_op_cmpxchgw_T0_T1_EAX_cc] = CC_OSZAPC,
6090 [INDEX_op_cmpxchgl_T0_T1_EAX_cc] = CC_OSZAPC,
6091 X86_64_DEF([INDEX_op_cmpxchgq_T0_T1_EAX_cc] = CC_OSZAPC,)
6093 [INDEX_op_cmpxchg8b] = CC_Z,
6094 [INDEX_op_lar] = CC_Z,
6095 [INDEX_op_lsl] = CC_Z,
6096 [INDEX_op_verr] = CC_Z,
6097 [INDEX_op_verw] = CC_Z,
6098 [INDEX_op_fcomi_ST0_FT0] = CC_Z | CC_P | CC_C,
6099 [INDEX_op_fucomi_ST0_FT0] = CC_Z | CC_P | CC_C,
6101 #define DEF_WRITEF(SUFFIX)\
6102 [INDEX_op_adcb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6103 [INDEX_op_adcw ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6104 [INDEX_op_adcl ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6105 X86_64_DEF([INDEX_op_adcq ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,)\
6106 [INDEX_op_sbbb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6107 [INDEX_op_sbbw ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6108 [INDEX_op_sbbl ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6109 X86_64_DEF([INDEX_op_sbbq ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,)\
6111 [INDEX_op_rolb ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
6112 [INDEX_op_rolw ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
6113 [INDEX_op_roll ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
6114 X86_64_DEF([INDEX_op_rolq ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,)\
6115 [INDEX_op_rorb ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
6116 [INDEX_op_rorw ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
6117 [INDEX_op_rorl ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
6118 X86_64_DEF([INDEX_op_rorq ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,)\
6120 [INDEX_op_rclb ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
6121 [INDEX_op_rclw ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
6122 [INDEX_op_rcll ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
6123 X86_64_DEF([INDEX_op_rclq ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,)\
6124 [INDEX_op_rcrb ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
6125 [INDEX_op_rcrw ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
6126 [INDEX_op_rcrl ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
6127 X86_64_DEF([INDEX_op_rcrq ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,)\
6129 [INDEX_op_shlb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6130 [INDEX_op_shlw ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6131 [INDEX_op_shll ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6132 X86_64_DEF([INDEX_op_shlq ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,)\
6134 [INDEX_op_shrb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6135 [INDEX_op_shrw ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6136 [INDEX_op_shrl ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6137 X86_64_DEF([INDEX_op_shrq ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,)\
6139 [INDEX_op_sarb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6140 [INDEX_op_sarw ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6141 [INDEX_op_sarl ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6142 X86_64_DEF([INDEX_op_sarq ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,)\
6144 [INDEX_op_shldw ## SUFFIX ## _T0_T1_ECX_cc] = CC_OSZAPC,\
6145 [INDEX_op_shldl ## SUFFIX ## _T0_T1_ECX_cc] = CC_OSZAPC,\
6146 X86_64_DEF([INDEX_op_shldq ## SUFFIX ## _T0_T1_ECX_cc] = CC_OSZAPC,)\
6147 [INDEX_op_shldw ## SUFFIX ## _T0_T1_im_cc] = CC_OSZAPC,\
6148 [INDEX_op_shldl ## SUFFIX ## _T0_T1_im_cc] = CC_OSZAPC,\
6149 X86_64_DEF([INDEX_op_shldq ## SUFFIX ## _T0_T1_im_cc] = CC_OSZAPC,)\
6151 [INDEX_op_shrdw ## SUFFIX ## _T0_T1_ECX_cc] = CC_OSZAPC,\
6152 [INDEX_op_shrdl ## SUFFIX ## _T0_T1_ECX_cc] = CC_OSZAPC,\
6153 X86_64_DEF([INDEX_op_shrdq ## SUFFIX ## _T0_T1_ECX_cc] = CC_OSZAPC,)\
6154 [INDEX_op_shrdw ## SUFFIX ## _T0_T1_im_cc] = CC_OSZAPC,\
6155 [INDEX_op_shrdl ## SUFFIX ## _T0_T1_im_cc] = CC_OSZAPC,\
6156 X86_64_DEF([INDEX_op_shrdq ## SUFFIX ## _T0_T1_im_cc] = CC_OSZAPC,)\
6158 [INDEX_op_cmpxchgb ## SUFFIX ## _T0_T1_EAX_cc] = CC_OSZAPC,\
6159 [INDEX_op_cmpxchgw ## SUFFIX ## _T0_T1_EAX_cc] = CC_OSZAPC,\
6160 [INDEX_op_cmpxchgl ## SUFFIX ## _T0_T1_EAX_cc] = CC_OSZAPC,\
6161 X86_64_DEF([INDEX_op_cmpxchgq ## SUFFIX ## _T0_T1_EAX_cc] = CC_OSZAPC,)
6166 #ifndef CONFIG_USER_ONLY
6172 /* simpler form of an operation if no flags need to be generated */
6173 static uint16_t opc_simpler[NB_OPS] = {
6174 [INDEX_op_update2_cc] = INDEX_op_nop,
6175 [INDEX_op_update1_cc] = INDEX_op_nop,
6176 [INDEX_op_update_neg_cc] = INDEX_op_nop,
6178 /* broken: CC_OP logic must be rewritten */
6179 [INDEX_op_update_inc_cc] = INDEX_op_nop,
6182 [INDEX_op_shlb_T0_T1_cc] = INDEX_op_shlb_T0_T1,
6183 [INDEX_op_shlw_T0_T1_cc] = INDEX_op_shlw_T0_T1,
6184 [INDEX_op_shll_T0_T1_cc] = INDEX_op_shll_T0_T1,
6185 X86_64_DEF([INDEX_op_shlq_T0_T1_cc] = INDEX_op_shlq_T0_T1,)
6187 [INDEX_op_shrb_T0_T1_cc] = INDEX_op_shrb_T0_T1,
6188 [INDEX_op_shrw_T0_T1_cc] = INDEX_op_shrw_T0_T1,
6189 [INDEX_op_shrl_T0_T1_cc] = INDEX_op_shrl_T0_T1,
6190 X86_64_DEF([INDEX_op_shrq_T0_T1_cc] = INDEX_op_shrq_T0_T1,)
6192 [INDEX_op_sarb_T0_T1_cc] = INDEX_op_sarb_T0_T1,
6193 [INDEX_op_sarw_T0_T1_cc] = INDEX_op_sarw_T0_T1,
6194 [INDEX_op_sarl_T0_T1_cc] = INDEX_op_sarl_T0_T1,
6195 X86_64_DEF([INDEX_op_sarq_T0_T1_cc] = INDEX_op_sarq_T0_T1,)
6197 #define DEF_SIMPLER(SUFFIX)\
6198 [INDEX_op_rolb ## SUFFIX ## _T0_T1_cc] = INDEX_op_rolb ## SUFFIX ## _T0_T1,\
6199 [INDEX_op_rolw ## SUFFIX ## _T0_T1_cc] = INDEX_op_rolw ## SUFFIX ## _T0_T1,\
6200 [INDEX_op_roll ## SUFFIX ## _T0_T1_cc] = INDEX_op_roll ## SUFFIX ## _T0_T1,\
6201 X86_64_DEF([INDEX_op_rolq ## SUFFIX ## _T0_T1_cc] = INDEX_op_rolq ## SUFFIX ## _T0_T1,)\
6203 [INDEX_op_rorb ## SUFFIX ## _T0_T1_cc] = INDEX_op_rorb ## SUFFIX ## _T0_T1,\
6204 [INDEX_op_rorw ## SUFFIX ## _T0_T1_cc] = INDEX_op_rorw ## SUFFIX ## _T0_T1,\
6205 [INDEX_op_rorl ## SUFFIX ## _T0_T1_cc] = INDEX_op_rorl ## SUFFIX ## _T0_T1,\
6206 X86_64_DEF([INDEX_op_rorq ## SUFFIX ## _T0_T1_cc] = INDEX_op_rorq ## SUFFIX ## _T0_T1,)
6210 #ifndef CONFIG_USER_ONLY
6211 DEF_SIMPLER(_kernel)
6216 void optimize_flags_init(void)
6219 /* put default values in arrays */
6220 for(i = 0; i < NB_OPS; i++) {
6221 if (opc_simpler[i] == 0)
6226 /* CPU flags computation optimization: we move backward thru the
6227 generated code to see which flags are needed. The operation is
6228 modified if suitable */
6229 static void optimize_flags(uint16_t *opc_buf, int opc_buf_len)
6232 int live_flags, write_flags, op;
6234 opc_ptr = opc_buf + opc_buf_len;
6235 /* live_flags contains the flags needed by the next instructions
6236 in the code. At the end of the bloc, we consider that all the
6238 live_flags = CC_OSZAPC;
6239 while (opc_ptr > opc_buf) {
6241 /* if none of the flags written by the instruction is used,
6242 then we can try to find a simpler instruction */
6243 write_flags = opc_write_flags[op];
6244 if ((live_flags & write_flags) == 0) {
6245 *opc_ptr = opc_simpler[op];
6247 /* compute the live flags before the instruction */
6248 live_flags &= ~write_flags;
6249 live_flags |= opc_read_flags[op];
6253 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
6254 basic block 'tb'. If search_pc is TRUE, also generate PC
6255 information for each intermediate instruction. */
6256 static inline int gen_intermediate_code_internal(CPUState *env,
6257 TranslationBlock *tb,
6260 DisasContext dc1, *dc = &dc1;
6261 target_ulong pc_ptr;
6262 uint16_t *gen_opc_end;
6263 int flags, j, lj, cflags;
6264 target_ulong pc_start;
6265 target_ulong cs_base;
6267 /* generate intermediate code */
6269 cs_base = tb->cs_base;
6271 cflags = tb->cflags;
6273 dc->pe = (flags >> HF_PE_SHIFT) & 1;
6274 dc->code32 = (flags >> HF_CS32_SHIFT) & 1;
6275 dc->ss32 = (flags >> HF_SS32_SHIFT) & 1;
6276 dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1;
6278 dc->vm86 = (flags >> VM_SHIFT) & 1;
6279 dc->cpl = (flags >> HF_CPL_SHIFT) & 3;
6280 dc->iopl = (flags >> IOPL_SHIFT) & 3;
6281 dc->tf = (flags >> TF_SHIFT) & 1;
6282 dc->singlestep_enabled = env->singlestep_enabled;
6283 dc->cc_op = CC_OP_DYNAMIC;
6284 dc->cs_base = cs_base;
6286 dc->popl_esp_hack = 0;
6287 /* select memory access functions */
6289 if (flags & HF_SOFTMMU_MASK) {
6291 dc->mem_index = 2 * 4;
6293 dc->mem_index = 1 * 4;
6295 dc->cpuid_features = env->cpuid_features;
6296 #ifdef TARGET_X86_64
6297 dc->lma = (flags >> HF_LMA_SHIFT) & 1;
6298 dc->code64 = (flags >> HF_CS64_SHIFT) & 1;
6301 dc->jmp_opt = !(dc->tf || env->singlestep_enabled ||
6302 (flags & HF_INHIBIT_IRQ_MASK)
6303 #ifndef CONFIG_SOFTMMU
6304 || (flags & HF_SOFTMMU_MASK)
6308 /* check addseg logic */
6309 if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32))
6310 printf("ERROR addseg\n");
6313 gen_opc_ptr = gen_opc_buf;
6314 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
6315 gen_opparam_ptr = gen_opparam_buf;
6318 dc->is_jmp = DISAS_NEXT;
6323 if (env->nb_breakpoints > 0) {
6324 for(j = 0; j < env->nb_breakpoints; j++) {
6325 if (env->breakpoints[j] == pc_ptr) {
6326 gen_debug(dc, pc_ptr - dc->cs_base);
6332 j = gen_opc_ptr - gen_opc_buf;
6336 gen_opc_instr_start[lj++] = 0;
6338 gen_opc_pc[lj] = pc_ptr;
6339 gen_opc_cc_op[lj] = dc->cc_op;
6340 gen_opc_instr_start[lj] = 1;
6342 pc_ptr = disas_insn(dc, pc_ptr);
6343 /* stop translation if indicated */
6346 /* if single step mode, we generate only one instruction and
6347 generate an exception */
6348 /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
6349 the flag and abort the translation to give the irqs a
6350 change to be happen */
6351 if (dc->tf || dc->singlestep_enabled ||
6352 (flags & HF_INHIBIT_IRQ_MASK) ||
6353 (cflags & CF_SINGLE_INSN)) {
6354 gen_jmp_im(pc_ptr - dc->cs_base);
6358 /* if too long translation, stop generation too */
6359 if (gen_opc_ptr >= gen_opc_end ||
6360 (pc_ptr - pc_start) >= (TARGET_PAGE_SIZE - 32)) {
6361 gen_jmp_im(pc_ptr - dc->cs_base);
6366 *gen_opc_ptr = INDEX_op_end;
6367 /* we don't forget to fill the last values */
6369 j = gen_opc_ptr - gen_opc_buf;
6372 gen_opc_instr_start[lj++] = 0;
6376 if (loglevel & CPU_LOG_TB_CPU) {
6377 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
6379 if (loglevel & CPU_LOG_TB_IN_ASM) {
6381 fprintf(logfile, "----------------\n");
6382 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
6383 #ifdef TARGET_X86_64
6388 disas_flags = !dc->code32;
6389 target_disas(logfile, pc_start, pc_ptr - pc_start, disas_flags);
6390 fprintf(logfile, "\n");
6391 if (loglevel & CPU_LOG_TB_OP) {
6392 fprintf(logfile, "OP:\n");
6393 dump_ops(gen_opc_buf, gen_opparam_buf);
6394 fprintf(logfile, "\n");
6399 /* optimize flag computations */
6400 optimize_flags(gen_opc_buf, gen_opc_ptr - gen_opc_buf);
6403 if (loglevel & CPU_LOG_TB_OP_OPT) {
6404 fprintf(logfile, "AFTER FLAGS OPT:\n");
6405 dump_ops(gen_opc_buf, gen_opparam_buf);
6406 fprintf(logfile, "\n");
6410 tb->size = pc_ptr - pc_start;
6414 int gen_intermediate_code(CPUState *env, TranslationBlock *tb)
6416 return gen_intermediate_code_internal(env, tb, 0);
6419 int gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
6421 return gen_intermediate_code_internal(env, tb, 1);