1 Unsolved issues/bugs in the mips/mipsel backend
2 -----------------------------------------------
6 - no 64bit wide registers for FPU
7 - 64bit mul/div handling broken
8 - DM[FT]C not implemented
10 - TLB fails cornercase at address wrap around
11 - [ls][dw][lr] report broken (aligned) BadVAddr
12 - Missing per-CPU instruction decoding, currently all implemented
13 instructions are regarded as valid
14 - pcnet32 does not work for little endian emulation on big endian host
15 (probably not mips specific, but observable for mips-malta)
17 - We fake firmware support instead of doing the real thing