1 Unsolved issues/bugs in the mips/mipsel backend
2 -----------------------------------------------
6 - [ls][dw][lr] report broken (aligned) BadVAddr
7 - Missing per-CPU instruction decoding, currently all implemented
8 instructions are regarded as valid
9 - pcnet32 does not work for little endian emulation on big endian host
10 (probably not mips specific, but observable for mips-malta)
11 - CP1 enable/disable is checked at translation time, not at execution
12 time, so it will have delayed effect.
16 - No 64bit TLB support
17 - no 64bit wide registers for FPU
18 - 64bit mul/div handling broken
20 "Generic" 4Kc system emulation
21 ------------------------------
22 - Doesn't correspond to any real hardware.
24 MALTA system emulation
25 ----------------------
26 - We fake firmware support instead of doing the real thing
27 - Real firmware falls over when trying to init RAM, presumably due
28 to lacking I2C emulation.