1 #if !defined (__MIPS_CPU_H__)
4 #define TARGET_HAS_ICE 1
11 // uint_fast8_t and uint_fast16_t not in <sys/int_types.h>
12 // XXX: move that elsewhere
13 #if defined(HOST_SOLARIS) && SOLARISREV < 10
14 typedef unsigned char uint_fast8_t;
15 typedef unsigned int uint_fast16_t;
18 typedef union fpr_t fpr_t;
20 float64 fd; /* ieee double precision */
21 float32 fs[2];/* ieee single precision */
22 uint64_t d; /* binary single fixed-point */
23 uint32_t w[2]; /* binary single fixed-point */
25 /* define FP_ENDIAN_IDX to access the same location
26 * in the fpr_t union regardless of the host endianess
28 #if defined(WORDS_BIGENDIAN)
29 # define FP_ENDIAN_IDX 1
31 # define FP_ENDIAN_IDX 0
34 #if defined(MIPS_USES_R4K_TLB)
35 typedef struct tlb_t tlb_t;
52 typedef struct CPUMIPSState CPUMIPSState;
54 /* General integer registers */
56 /* Special registers */
60 #if defined(MIPS_USES_FPU)
61 /* Floating point registers */
63 #define FPR(cpu, n) ((fpr_t*)&(cpu)->fpr[(n) / 2])
64 #define FPR_FD(cpu, n) (FPR(cpu, n)->fd)
65 #define FPR_FS(cpu, n) (FPR(cpu, n)->fs[((n) & 1) ^ FP_ENDIAN_IDX])
66 #define FPR_D(cpu, n) (FPR(cpu, n)->d)
67 #define FPR_W(cpu, n) (FPR(cpu, n)->w[((n) & 1) ^ FP_ENDIAN_IDX])
69 #ifndef USE_HOST_FLOAT_REGS
74 float_status fp_status;
75 /* fpu implementation/revision register */
79 #define SET_FP_COND(reg) do { (reg) |= (1<<23); } while(0)
80 #define CLEAR_FP_COND(reg) do { (reg) &= ~(1<<23); } while(0)
81 #define IS_FP_COND_SET(reg) (((reg) & (1<<23)) != 0)
82 #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f)
83 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
84 #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f)
85 #define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v) << 12); } while(0)
86 #define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v) << 7); } while(0)
87 #define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v) << 2); } while(0)
89 #define FP_UNDERFLOW 2
93 #define FP_UNIMPLEMENTED 32
96 #if defined(MIPS_USES_R4K_TLB)
97 tlb_t tlb[MIPS_TLB_MAX];
102 uint64_t CP0_EntryLo0;
103 uint64_t CP0_EntryLo1;
104 uint64_t CP0_Context;
105 uint32_t CP0_PageMask;
106 uint32_t CP0_PageGrain;
109 uint32_t CP0_BadVAddr;
111 uint64_t CP0_EntryHi;
112 uint32_t CP0_Compare;
151 uint32_t CP0_Config0;
164 uint32_t CP0_Config1;
180 uint32_t CP0_Config2;
190 uint32_t CP0_Config3;
192 #define CP0C3_DSPP 10
201 uint32_t CP0_WatchLo;
202 uint32_t CP0_WatchHi;
203 uint32_t CP0_XContext;
204 uint32_t CP0_Framemask;
208 #define CP0DB_LSNM 28
209 #define CP0DB_Doze 27
210 #define CP0DB_Halt 26
212 #define CP0DB_IBEP 24
213 #define CP0DB_DBEP 21
214 #define CP0DB_IEXI 20
225 uint32_t CP0_Performance0;
230 uint32_t CP0_ErrorEPC;
233 int interrupt_request;
237 int user_mode_only; /* user mode only simulation */
238 uint32_t hflags; /* CPU State */
239 /* TMASK defines different execution modes */
240 #define MIPS_HFLAG_TMASK 0x007F
241 #define MIPS_HFLAG_MODE 0x001F /* execution modes */
242 #define MIPS_HFLAG_UM 0x0001 /* user mode */
243 #define MIPS_HFLAG_ERL 0x0002 /* Error mode */
244 #define MIPS_HFLAG_EXL 0x0004 /* Exception mode */
245 #define MIPS_HFLAG_DM 0x0008 /* Debug mode */
246 #define MIPS_HFLAG_SM 0x0010 /* Supervisor mode */
247 #define MIPS_HFLAG_RE 0x0040 /* Reversed endianness */
248 /* If translation is interrupted between the branch instruction and
249 * the delay slot, record what type of branch it is so that we can
250 * resume translation properly. It might be possible to reduce
251 * this from three bits to two. */
252 #define MIPS_HFLAG_BMASK 0x0380
253 #define MIPS_HFLAG_B 0x0080 /* Unconditional branch */
254 #define MIPS_HFLAG_BC 0x0100 /* Conditional branch */
255 #define MIPS_HFLAG_BL 0x0180 /* Likely branch */
256 #define MIPS_HFLAG_BR 0x0200 /* branch to register (can't link TB) */
257 target_ulong btarget; /* Jump / branch target */
258 int bcond; /* Branch condition (if needed) */
260 int halted; /* TRUE if the CPU is in suspend state */
262 int SYNCI_Step; /* Address step size for SYNCI */
263 int CCRes; /* Cycle count resolution/divisor */
268 const char *kernel_filename;
269 const char *kernel_cmdline;
270 const char *initrd_filename;
272 struct QEMUTimer *timer; /* Internal timer */
277 /* Memory access type :
278 * may be needed for precise access rights control and precise exceptions.
281 /* 1 bit to define user level / supervisor access */
284 /* 1 bit to indicate direction */
286 /* Type of instruction that generated the access */
287 ACCESS_CODE = 0x10, /* Code fetch access */
288 ACCESS_INT = 0x20, /* Integer load/store access */
289 ACCESS_FLOAT = 0x30, /* floating point load/store access */
325 EXCP_MTCP0 = 0x104, /* mtmsr instruction: */
326 /* may change privilege level */
327 EXCP_BRANCH = 0x108, /* branch instruction */
328 EXCP_ERET = 0x10C, /* return from interrupt */
329 EXCP_SYSCALL_USER = 0x110, /* System call in user mode only */
333 int cpu_mips_exec(CPUMIPSState *s);
334 CPUMIPSState *cpu_mips_init(void);
335 uint32_t cpu_mips_get_clock (void);
337 #endif /* !defined (__MIPS_CPU_H__) */