1 #if !defined (__MIPS_CPU_H__)
4 #define TARGET_HAS_ICE 1
11 typedef union fpr_t fpr_t;
18 #if defined(MIPS_USES_R4K_TLB)
19 typedef struct tlb_t tlb_t;
33 typedef struct CPUMIPSState CPUMIPSState;
35 /* General integer registers */
37 /* Special registers */
41 #if defined(MIPS_USES_FPU)
42 /* Floating point registers */
44 /* Floating point special purpose registers */
51 #if defined(MIPS_USES_R4K_TLB)
56 uint32_t CP0_EntryLo0;
57 uint32_t CP0_EntryLo1;
59 uint32_t CP0_PageMask;
61 uint32_t CP0_BadVAddr;
111 uint32_t CP0_WatchLo;
112 uint32_t CP0_WatchHi;
116 #define CP0DB_LSNM 28
117 #define CP0DB_Doze 27
118 #define CP0DB_Halt 26
120 #define CP0DB_IBEP 24
121 #define CP0DB_DBEP 21
122 #define CP0DB_IEXI 20
135 uint32_t CP0_ErrorEPC;
138 #if defined (USE_HOST_FLOAT_REGS) && defined(MIPS_USES_FPU)
139 double ft0, ft1, ft2;
141 struct QEMUTimer *timer; /* Internal timer */
142 int interrupt_request;
146 int user_mode_only; /* user mode only simulation */
147 uint32_t hflags; /* CPU State */
148 /* TMASK defines different execution modes */
149 #define MIPS_HFLAGS_TMASK 0x00FF
150 #define MIPS_HFLAG_MODE 0x001F /* execution modes */
151 #define MIPS_HFLAG_UM 0x0001 /* user mode */
152 #define MIPS_HFLAG_ERL 0x0002 /* Error mode */
153 #define MIPS_HFLAG_EXL 0x0004 /* Exception mode */
154 #define MIPS_HFLAG_DM 0x0008 /* Debug mode */
155 #define MIPS_HFLAG_SM 0x0010 /* Supervisor mode */
156 #define MIPS_HFLAG_RE 0x0040 /* Reversed endianness */
157 /* If translation is interrupted between the branch instruction and
158 * the delay slot, record what type of branch it is so that we can
159 * resume translation properly. It might be possible to reduce
160 * this from three bits to two. */
161 #define MIPS_HFLAG_BMASK 0x0380
162 #define MIPS_HFLAG_B 0x0080 /* Unconditional branch */
163 #define MIPS_HFLAG_BC 0x0100 /* Conditional branch */
164 #define MIPS_HFLAG_BL 0x0180 /* Likely branch */
165 #define MIPS_HFLAG_BR 0x0200 /* branch to register (can't link TB) */
166 target_ulong btarget; /* Jump / branch target */
167 int bcond; /* Branch condition (if needed) */
169 int halted; /* TRUE if the CPU is in suspend state */
176 /* Memory access type :
177 * may be needed for precise access rights control and precise exceptions.
180 /* 1 bit to define user level / supervisor access */
183 /* 1 bit to indicate direction */
185 /* Type of instruction that generated the access */
186 ACCESS_CODE = 0x10, /* Code fetch access */
187 ACCESS_INT = 0x20, /* Integer load/store access */
188 ACCESS_FLOAT = 0x30, /* floating point load/store access */
224 EXCP_MTCP0 = 0x104, /* mtmsr instruction: */
225 /* may change privilege level */
226 EXCP_BRANCH = 0x108, /* branch instruction */
227 EXCP_ERET = 0x10C, /* return from interrupt */
228 EXCP_SYSCALL_USER = 0x110, /* System call in user mode only */
232 int cpu_mips_exec(CPUMIPSState *s);
233 CPUMIPSState *cpu_mips_init(void);
234 uint32_t cpu_mips_get_clock (void);
236 #endif /* !defined (__MIPS_CPU_H__) */