1 #if !defined (__MIPS_CPU_H__)
4 #define TARGET_HAS_ICE 1
6 #define ELF_MACHINE EM_MIPS
11 #include "softfloat.h"
13 // uint_fast8_t and uint_fast16_t not in <sys/int_types.h>
14 // XXX: move that elsewhere
15 #if defined(HOST_SOLARIS) && HOST_SOLARIS < 10
16 typedef unsigned char uint_fast8_t;
17 typedef unsigned int uint_fast16_t;
22 typedef struct r4k_tlb_t r4k_tlb_t;
37 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
38 struct CPUMIPSTLBContext {
41 int (*map_address) (struct CPUMIPSState *env, target_ulong *physical, int *prot, target_ulong address, int rw, int access_type);
42 void (*do_tlbwi) (void);
43 void (*do_tlbwr) (void);
44 void (*do_tlbp) (void);
45 void (*do_tlbr) (void);
48 r4k_tlb_t tlb[MIPS_TLB_MAX];
53 typedef union fpr_t fpr_t;
55 float64 fd; /* ieee double precision */
56 float32 fs[2];/* ieee single precision */
57 uint64_t d; /* binary double fixed-point */
58 uint32_t w[2]; /* binary single fixed-point */
60 /* define FP_ENDIAN_IDX to access the same location
61 * in the fpr_t union regardless of the host endianess
63 #if defined(WORDS_BIGENDIAN)
64 # define FP_ENDIAN_IDX 1
66 # define FP_ENDIAN_IDX 0
69 typedef struct CPUMIPSFPUContext CPUMIPSFPUContext;
70 struct CPUMIPSFPUContext {
71 /* Floating point registers */
73 float_status fp_status;
74 /* fpu implementation/revision register (fir) */
87 #define SET_FP_COND(num,env) do { ((env)->fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
88 #define CLEAR_FP_COND(num,env) do { ((env)->fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
89 #define GET_FP_COND(env) ((((env)->fcr31 >> 24) & 0xfe) | (((env)->fcr31 >> 23) & 0x1))
90 #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f)
91 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
92 #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f)
93 #define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
94 #define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v & 0x1f) << 7); } while(0)
95 #define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v & 0x1f) << 2); } while(0)
96 #define UPDATE_FP_FLAGS(reg,v) do { (reg) |= ((v & 0x1f) << 2); } while(0)
98 #define FP_UNDERFLOW 2
101 #define FP_INVALID 16
102 #define FP_UNIMPLEMENTED 32
105 #define NB_MMU_MODES 3
107 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
108 struct CPUMIPSMVPContext {
109 int32_t CP0_MVPControl;
110 #define CP0MVPCo_CPA 3
111 #define CP0MVPCo_STLB 2
112 #define CP0MVPCo_VPC 1
113 #define CP0MVPCo_EVP 0
114 int32_t CP0_MVPConf0;
115 #define CP0MVPC0_M 31
116 #define CP0MVPC0_TLBS 29
117 #define CP0MVPC0_GS 28
118 #define CP0MVPC0_PCP 27
119 #define CP0MVPC0_PTLBE 16
120 #define CP0MVPC0_TCA 15
121 #define CP0MVPC0_PVPE 10
122 #define CP0MVPC0_PTC 0
123 int32_t CP0_MVPConf1;
124 #define CP0MVPC1_CIM 31
125 #define CP0MVPC1_CIF 30
126 #define CP0MVPC1_PCX 20
127 #define CP0MVPC1_PCP2 10
128 #define CP0MVPC1_PCP1 0
131 typedef struct mips_def_t mips_def_t;
133 #define MIPS_SHADOW_SET_MAX 16
134 #define MIPS_TC_MAX 5
135 #define MIPS_DSP_ACC 4
137 typedef struct CPUMIPSState CPUMIPSState;
138 struct CPUMIPSState {
139 /* General integer registers */
140 target_ulong gpr[MIPS_SHADOW_SET_MAX][32];
141 /* Special registers */
142 target_ulong PC[MIPS_TC_MAX];
143 #if TARGET_LONG_BITS > HOST_LONG_BITS
147 /* temporary hack for FP globals */
148 #ifndef USE_HOST_FLOAT_REGS
153 target_ulong HI[MIPS_TC_MAX][MIPS_DSP_ACC];
154 target_ulong LO[MIPS_TC_MAX][MIPS_DSP_ACC];
155 target_ulong ACX[MIPS_TC_MAX][MIPS_DSP_ACC];
156 target_ulong DSPControl[MIPS_TC_MAX];
158 CPUMIPSMVPContext *mvp;
159 CPUMIPSTLBContext *tlb;
160 CPUMIPSFPUContext *fpu;
162 target_ulong *current_tc_gprs;
163 target_ulong *current_tc_hi;
166 target_ulong SEGMask;
171 /* CP0_MVP* are per MVP registers. */
173 int32_t CP0_VPEControl;
174 #define CP0VPECo_YSI 21
175 #define CP0VPECo_GSI 20
176 #define CP0VPECo_EXCPT 16
177 #define CP0VPECo_TE 15
178 #define CP0VPECo_TargTC 0
179 int32_t CP0_VPEConf0;
180 #define CP0VPEC0_M 31
181 #define CP0VPEC0_XTC 21
182 #define CP0VPEC0_TCS 19
183 #define CP0VPEC0_SCS 18
184 #define CP0VPEC0_DSC 17
185 #define CP0VPEC0_ICS 16
186 #define CP0VPEC0_MVP 1
187 #define CP0VPEC0_VPA 0
188 int32_t CP0_VPEConf1;
189 #define CP0VPEC1_NCX 20
190 #define CP0VPEC1_NCP2 10
191 #define CP0VPEC1_NCP1 0
192 target_ulong CP0_YQMask;
193 target_ulong CP0_VPESchedule;
194 target_ulong CP0_VPEScheFBack;
196 #define CP0VPEOpt_IWX7 15
197 #define CP0VPEOpt_IWX6 14
198 #define CP0VPEOpt_IWX5 13
199 #define CP0VPEOpt_IWX4 12
200 #define CP0VPEOpt_IWX3 11
201 #define CP0VPEOpt_IWX2 10
202 #define CP0VPEOpt_IWX1 9
203 #define CP0VPEOpt_IWX0 8
204 #define CP0VPEOpt_DWX7 7
205 #define CP0VPEOpt_DWX6 6
206 #define CP0VPEOpt_DWX5 5
207 #define CP0VPEOpt_DWX4 4
208 #define CP0VPEOpt_DWX3 3
209 #define CP0VPEOpt_DWX2 2
210 #define CP0VPEOpt_DWX1 1
211 #define CP0VPEOpt_DWX0 0
212 target_ulong CP0_EntryLo0;
213 int32_t CP0_TCStatus[MIPS_TC_MAX];
214 #define CP0TCSt_TCU3 31
215 #define CP0TCSt_TCU2 30
216 #define CP0TCSt_TCU1 29
217 #define CP0TCSt_TCU0 28
218 #define CP0TCSt_TMX 27
219 #define CP0TCSt_RNST 23
220 #define CP0TCSt_TDS 21
221 #define CP0TCSt_DT 20
222 #define CP0TCSt_DA 15
224 #define CP0TCSt_TKSU 11
225 #define CP0TCSt_IXMT 10
226 #define CP0TCSt_TASID 0
227 int32_t CP0_TCBind[MIPS_TC_MAX];
228 #define CP0TCBd_CurTC 21
229 #define CP0TCBd_TBE 17
230 #define CP0TCBd_CurVPE 0
231 target_ulong CP0_TCHalt[MIPS_TC_MAX];
232 target_ulong CP0_TCContext[MIPS_TC_MAX];
233 target_ulong CP0_TCSchedule[MIPS_TC_MAX];
234 target_ulong CP0_TCScheFBack[MIPS_TC_MAX];
235 target_ulong CP0_EntryLo1;
236 target_ulong CP0_Context;
237 int32_t CP0_PageMask;
238 int32_t CP0_PageGrain;
240 int32_t CP0_SRSConf0_rw_bitmask;
241 int32_t CP0_SRSConf0;
242 #define CP0SRSC0_M 31
243 #define CP0SRSC0_SRS3 20
244 #define CP0SRSC0_SRS2 10
245 #define CP0SRSC0_SRS1 0
246 int32_t CP0_SRSConf1_rw_bitmask;
247 int32_t CP0_SRSConf1;
248 #define CP0SRSC1_M 31
249 #define CP0SRSC1_SRS6 20
250 #define CP0SRSC1_SRS5 10
251 #define CP0SRSC1_SRS4 0
252 int32_t CP0_SRSConf2_rw_bitmask;
253 int32_t CP0_SRSConf2;
254 #define CP0SRSC2_M 31
255 #define CP0SRSC2_SRS9 20
256 #define CP0SRSC2_SRS8 10
257 #define CP0SRSC2_SRS7 0
258 int32_t CP0_SRSConf3_rw_bitmask;
259 int32_t CP0_SRSConf3;
260 #define CP0SRSC3_M 31
261 #define CP0SRSC3_SRS12 20
262 #define CP0SRSC3_SRS11 10
263 #define CP0SRSC3_SRS10 0
264 int32_t CP0_SRSConf4_rw_bitmask;
265 int32_t CP0_SRSConf4;
266 #define CP0SRSC4_SRS15 20
267 #define CP0SRSC4_SRS14 10
268 #define CP0SRSC4_SRS13 0
270 target_ulong CP0_BadVAddr;
272 target_ulong CP0_EntryHi;
297 #define CP0IntCtl_IPTI 29
298 #define CP0IntCtl_IPPC1 26
299 #define CP0IntCtl_VS 5
301 #define CP0SRSCtl_HSS 26
302 #define CP0SRSCtl_EICSS 18
303 #define CP0SRSCtl_ESS 12
304 #define CP0SRSCtl_PSS 6
305 #define CP0SRSCtl_CSS 0
307 #define CP0SRSMap_SSV7 28
308 #define CP0SRSMap_SSV6 24
309 #define CP0SRSMap_SSV5 20
310 #define CP0SRSMap_SSV4 16
311 #define CP0SRSMap_SSV3 12
312 #define CP0SRSMap_SSV2 8
313 #define CP0SRSMap_SSV1 4
314 #define CP0SRSMap_SSV0 0
324 #define CP0Ca_IP_mask 0x0000FF00
326 target_ulong CP0_EPC;
370 #define CP0C3_DSPP 10
380 /* XXX: Maybe make LLAddr per-TC? */
381 target_ulong CP0_LLAddr;
382 target_ulong CP0_WatchLo[8];
383 int32_t CP0_WatchHi[8];
384 target_ulong CP0_XContext;
385 int32_t CP0_Framemask;
389 #define CP0DB_LSNM 28
390 #define CP0DB_Doze 27
391 #define CP0DB_Halt 26
393 #define CP0DB_IBEP 24
394 #define CP0DB_DBEP 21
395 #define CP0DB_IEXI 20
405 int32_t CP0_Debug_tcstatus[MIPS_TC_MAX];
406 target_ulong CP0_DEPC;
407 int32_t CP0_Performance0;
412 target_ulong CP0_ErrorEPC;
415 int interrupt_request;
417 int user_mode_only; /* user mode only simulation */
418 uint32_t hflags; /* CPU State */
419 /* TMASK defines different execution modes */
420 #define MIPS_HFLAG_TMASK 0x01FF
421 #define MIPS_HFLAG_MODE 0x0007 /* execution modes */
422 /* The KSU flags must be the lowest bits in hflags. The flag order
423 must be the same as defined for CP0 Status. This allows to use
424 the bits as the value of mmu_idx. */
425 #define MIPS_HFLAG_KSU 0x0003 /* kernel/supervisor/user mode mask */
426 #define MIPS_HFLAG_UM 0x0002 /* user mode flag */
427 #define MIPS_HFLAG_SM 0x0001 /* supervisor mode flag */
428 #define MIPS_HFLAG_KM 0x0000 /* kernel mode flag */
429 #define MIPS_HFLAG_DM 0x0004 /* Debug mode */
430 #define MIPS_HFLAG_64 0x0008 /* 64-bit instructions enabled */
431 #define MIPS_HFLAG_CP0 0x0010 /* CP0 enabled */
432 #define MIPS_HFLAG_FPU 0x0020 /* FPU enabled */
433 #define MIPS_HFLAG_F64 0x0040 /* 64-bit FPU enabled */
434 /* True if the MIPS IV COP1X instructions can be used. This also
435 controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
437 #define MIPS_HFLAG_COP1X 0x0080 /* COP1X instructions enabled */
438 #define MIPS_HFLAG_RE 0x0100 /* Reversed endianness */
439 /* If translation is interrupted between the branch instruction and
440 * the delay slot, record what type of branch it is so that we can
441 * resume translation properly. It might be possible to reduce
442 * this from three bits to two. */
443 #define MIPS_HFLAG_BMASK 0x0e00
444 #define MIPS_HFLAG_B 0x0200 /* Unconditional branch */
445 #define MIPS_HFLAG_BC 0x0400 /* Conditional branch */
446 #define MIPS_HFLAG_BL 0x0600 /* Likely branch */
447 #define MIPS_HFLAG_BR 0x0800 /* branch to register (can't link TB) */
448 target_ulong btarget; /* Jump / branch target */
449 int bcond; /* Branch condition (if needed) */
451 int SYNCI_Step; /* Address step size for SYNCI */
452 int CCRes; /* Cycle count resolution/divisor */
453 uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
454 uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
455 int insn_flags; /* Supported instruction set */
457 #ifdef CONFIG_USER_ONLY
458 target_ulong tls_value;
463 const mips_def_t *cpu_model;
464 #ifndef CONFIG_USER_ONLY
468 struct QEMUTimer *timer; /* Internal timer */
471 int no_mmu_map_address (CPUMIPSState *env, target_ulong *physical, int *prot,
472 target_ulong address, int rw, int access_type);
473 int fixed_mmu_map_address (CPUMIPSState *env, target_ulong *physical, int *prot,
474 target_ulong address, int rw, int access_type);
475 int r4k_map_address (CPUMIPSState *env, target_ulong *physical, int *prot,
476 target_ulong address, int rw, int access_type);
477 void r4k_do_tlbwi (void);
478 void r4k_do_tlbwr (void);
479 void r4k_do_tlbp (void);
480 void r4k_do_tlbr (void);
481 void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
483 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
486 #define CPUState CPUMIPSState
487 #define cpu_init cpu_mips_init
488 #define cpu_exec cpu_mips_exec
489 #define cpu_gen_code cpu_mips_gen_code
490 #define cpu_signal_handler cpu_mips_signal_handler
491 #define cpu_list mips_cpu_list
493 /* MMU modes definitions. We carefully match the indices with our
495 #define MMU_MODE0_SUFFIX _kernel
496 #define MMU_MODE1_SUFFIX _super
497 #define MMU_MODE2_SUFFIX _user
498 #define MMU_USER_IDX 2
499 static inline int cpu_mmu_index (CPUState *env)
501 return env->hflags & MIPS_HFLAG_KSU;
504 #if defined(CONFIG_USER_ONLY)
505 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
508 env->gpr[env->current_tc][29] = newsp;
509 env->gpr[env->current_tc][7] = 0;
510 env->gpr[env->current_tc][2] = 0;
516 /* Memory access type :
517 * may be needed for precise access rights control and precise exceptions.
520 /* 1 bit to define user level / supervisor access */
523 /* 1 bit to indicate direction */
525 /* Type of instruction that generated the access */
526 ACCESS_CODE = 0x10, /* Code fetch access */
527 ACCESS_INT = 0x20, /* Integer load/store access */
528 ACCESS_FLOAT = 0x30, /* floating point load/store access */
542 EXCP_EXT_INTERRUPT, /* 8 */
558 EXCP_DWATCH, /* 24 */
568 EXCP_LAST = EXCP_CACHE,
571 int cpu_mips_exec(CPUMIPSState *s);
572 CPUMIPSState *cpu_mips_init(const char *cpu_model);
573 uint32_t cpu_mips_get_clock (void);
574 int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
576 #endif /* !defined (__MIPS_CPU_H__) */