1 #if !defined (__MIPS_CPU_H__)
9 typedef union fpr_t fpr_t;
16 #if defined(MIPS_USES_R4K_TLB)
17 typedef struct tlb_t tlb_t;
30 typedef struct CPUMIPSState CPUMIPSState;
32 /* General integer registers */
34 /* Special registers */
38 #if defined(MIPS_USES_FPU)
39 /* Floating point registers */
41 /* Floating point special purpose registers */
48 #if defined(MIPS_USES_R4K_TLB)
53 uint32_t CP0_EntryLo0;
54 uint32_t CP0_EntryLo1;
56 uint32_t CP0_PageMask;
58 uint32_t CP0_BadVAddr;
108 uint32_t CP0_WatchLo;
109 uint32_t CP0_WatchHi;
113 #define CP0DB_LSNM 28
114 #define CP0DB_Doze 27
115 #define CP0DB_Halt 26
117 #define CP0DB_IBEP 24
118 #define CP0DB_DBEP 21
119 #define CP0DB_IEXI 20
132 uint32_t CP0_ErrorEPC;
135 #if defined (USE_HOST_FLOAT_REGS) && defined(MIPS_USES_FPU)
136 double ft0, ft1, ft2;
138 struct QEMUTimer *timer; /* Internal timer */
139 int interrupt_request;
143 int user_mode_only; /* user mode only simulation */
144 uint32_t hflags; /* CPU State */
145 /* TMASK defines different execution modes */
146 #define MIPS_HFLAGS_TMASK 0x00FF
147 #define MIPS_HFLAG_MODE 0x001F /* execution modes */
148 #define MIPS_HFLAG_UM 0x0001 /* user mode */
149 #define MIPS_HFLAG_ERL 0x0002 /* Error mode */
150 #define MIPS_HFLAG_EXL 0x0004 /* Exception mode */
151 #define MIPS_HFLAG_DM 0x0008 /* Debug mode */
152 #define MIPS_HFLAG_SM 0x0010 /* Supervisor mode */
153 #define MIPS_HFLAG_RE 0x0040 /* Reversed endianness */
154 #define MIPS_HFLAG_DS 0x0080 /* In / out of delay slot */
155 /* Those flags keep the branch state if the translation is interrupted
156 * between the branch instruction and the delay slot
158 #define MIPS_HFLAG_BMASK 0x0F00
159 #define MIPS_HFLAG_B 0x0100 /* Unconditional branch */
160 #define MIPS_HFLAG_BC 0x0200 /* Conditional branch */
161 #define MIPS_HFLAG_BL 0x0400 /* Likely branch */
162 #define MIPS_HFLAG_BR 0x0800 /* branch to register (can't link TB) */
163 target_ulong btarget; /* Jump / branch target */
164 int bcond; /* Branch condition (if needed) */
165 struct TranslationBlock *current_tb; /* currently executing TB */
166 /* soft mmu support */
167 /* in order to avoid passing too many arguments to the memory
168 write helpers, we store some rarely used information in the CPU
170 target_ulong mem_write_pc; /* host pc at which the memory was
172 unsigned long mem_write_vaddr; /* target virtual addr at which the
173 memory was written */
174 /* 0 = kernel, 1 = user (may have 2 = kernel code, 3 = user code ?) */
175 CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
176 CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
177 /* ice debug support */
178 target_ulong breakpoints[MAX_BREAKPOINTS];
180 int singlestep_enabled; /* XXX: should use CPU single step mode instead */
187 /* Memory access type :
188 * may be needed for precise access rights control and precise exceptions.
191 /* 1 bit to define user level / supervisor access */
194 /* 1 bit to indicate direction */
196 /* Type of instruction that generated the access */
197 ACCESS_CODE = 0x10, /* Code fetch access */
198 ACCESS_INT = 0x20, /* Integer load/store access */
199 ACCESS_FLOAT = 0x30, /* floating point load/store access */
235 EXCP_MTCP0 = 0x104, /* mtmsr instruction: */
236 /* may change privilege level */
237 EXCP_BRANCH = 0x108, /* branch instruction */
238 EXCP_ERET = 0x10C, /* return from interrupt */
239 EXCP_SYSCALL_USER = 0x110, /* System call in user mode only */
243 int cpu_mips_exec(CPUMIPSState *s);
244 CPUMIPSState *cpu_mips_init(void);
245 uint32_t cpu_mips_get_clock (void);
247 #endif /* !defined (__MIPS_CPU_H__) */