1 #if !defined(__QEMU_MIPS_EXEC_H__)
2 #define __QEMU_MIPS_EXEC_H__
8 #include "dyngen-exec.h"
10 #if defined(__sparc__)
11 struct CPUMIPSState *env;
13 register struct CPUMIPSState *env asm(AREG0);
16 #if defined (USE_64BITS_REGS)
17 typedef int64_t host_int_t;
18 typedef uint64_t host_uint_t;
20 typedef int32_t host_int_t;
21 typedef uint32_t host_uint_t;
24 #if defined(__sparc__)
29 #if TARGET_LONG_BITS > HOST_LONG_BITS
34 register host_uint_t T0 asm(AREG1);
35 register host_uint_t T1 asm(AREG2);
36 register host_uint_t T2 asm(AREG3);
40 #if defined (USE_HOST_FLOAT_REGS)
41 #error "implement me."
43 #define FDT0 (env->ft0.fd)
44 #define FDT1 (env->ft1.fd)
45 #define FDT2 (env->ft2.fd)
46 #define FST0 (env->ft0.fs[FP_ENDIAN_IDX])
47 #define FST1 (env->ft1.fs[FP_ENDIAN_IDX])
48 #define FST2 (env->ft2.fs[FP_ENDIAN_IDX])
49 #define DT0 (env->ft0.d)
50 #define DT1 (env->ft1.d)
51 #define DT2 (env->ft2.d)
52 #define WT0 (env->ft0.w[FP_ENDIAN_IDX])
53 #define WT1 (env->ft1.w[FP_ENDIAN_IDX])
54 #define WT2 (env->ft2.w[FP_ENDIAN_IDX])
57 #if defined (DEBUG_OP)
58 # define RETURN() __asm__ __volatile__("nop" : : : "memory");
60 # define RETURN() __asm__ __volatile__("" : : : "memory");
66 #if !defined(CONFIG_USER_ONLY)
67 #include "softmmu_exec.h"
68 #endif /* !defined(CONFIG_USER_ONLY) */
70 static inline void env_to_regs(void)
74 static inline void regs_to_env(void)
78 #ifdef MIPS_HAS_MIPS64
79 #if TARGET_LONG_BITS > HOST_LONG_BITS
81 void do_dsll32 (void);
83 void do_dsra32 (void);
85 void do_dsrl32 (void);
87 void do_drotr32 (void);
91 void do_drotrv (void);
95 #if TARGET_LONG_BITS > HOST_LONG_BITS
101 void do_msubu (void);
103 void do_ddivu (void);
105 #ifdef MIPS_HAS_MIPS64
106 void do_dmult (void);
107 void do_dmultu (void);
109 void do_mfc0_random(void);
110 void do_mfc0_count(void);
111 void do_mtc0_entryhi(uint32_t in);
112 void do_mtc0_status_debug(uint32_t old, uint32_t val);
113 void do_mtc0_status_irqraise_debug(void);
114 void do_tlbwi (void);
115 void do_tlbwr (void);
118 void dump_fpu(CPUState *env);
119 void fpu_dump_state(CPUState *env, FILE *f,
120 int (*fpu_fprintf)(FILE *f, const char *fmt, ...),
123 void do_lwl_raw (uint32_t);
124 void do_lwr_raw (uint32_t);
125 uint32_t do_swl_raw (uint32_t);
126 uint32_t do_swr_raw (uint32_t);
127 #ifdef MIPS_HAS_MIPS64
128 void do_ldl_raw (uint64_t);
129 void do_ldr_raw (uint64_t);
130 uint64_t do_sdl_raw (uint64_t);
131 uint64_t do_sdr_raw (uint64_t);
133 #if !defined(CONFIG_USER_ONLY)
134 void do_lwl_user (uint32_t);
135 void do_lwl_kernel (uint32_t);
136 void do_lwr_user (uint32_t);
137 void do_lwr_kernel (uint32_t);
138 uint32_t do_swl_user (uint32_t);
139 uint32_t do_swl_kernel (uint32_t);
140 uint32_t do_swr_user (uint32_t);
141 uint32_t do_swr_kernel (uint32_t);
142 #ifdef MIPS_HAS_MIPS64
143 void do_ldl_user (uint64_t);
144 void do_ldl_kernel (uint64_t);
145 void do_ldr_user (uint64_t);
146 void do_ldr_kernel (uint64_t);
147 uint64_t do_sdl_user (uint64_t);
148 uint64_t do_sdl_kernel (uint64_t);
149 uint64_t do_sdr_user (uint64_t);
150 uint64_t do_sdr_kernel (uint64_t);
153 void do_pmon (int function);
157 int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
158 int is_user, int is_softmmu);
159 void do_interrupt (CPUState *env);
160 void invalidate_tlb (CPUState *env, int idx, int use_extra);
162 void cpu_loop_exit(void);
163 void do_raise_exception_err (uint32_t exception, int error_code);
164 void do_raise_exception (uint32_t exception);
165 void do_raise_exception_direct (uint32_t exception);
167 void cpu_dump_state(CPUState *env, FILE *f,
168 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
170 void cpu_mips_irqctrl_init (void);
171 uint32_t cpu_mips_get_random (CPUState *env);
172 uint32_t cpu_mips_get_count (CPUState *env);
173 void cpu_mips_store_count (CPUState *env, uint32_t value);
174 void cpu_mips_store_compare (CPUState *env, uint32_t value);
175 void cpu_mips_update_irq(CPUState *env);
176 void cpu_mips_clock_init (CPUState *env);
177 void cpu_mips_tlb_flush (CPUState *env, int flush_global);
179 #endif /* !defined(__QEMU_MIPS_EXEC_H__) */