2 * MIPS emulation helpers for qemu.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
39 /* no MMU emulation */
40 int no_mmu_map_address (CPUState *env, target_ulong *physical, int *prot,
41 target_ulong address, int rw, int access_type)
44 *prot = PAGE_READ | PAGE_WRITE;
48 /* fixed mapping MMU emulation */
49 int fixed_mmu_map_address (CPUState *env, target_ulong *physical, int *prot,
50 target_ulong address, int rw, int access_type)
52 if (address <= (int32_t)0x7FFFFFFFUL) {
53 if (!(env->CP0_Status & (1 << CP0St_ERL)))
54 *physical = address + 0x40000000UL;
57 } else if (address <= (int32_t)0xBFFFFFFFUL)
58 *physical = address & 0x1FFFFFFF;
62 *prot = PAGE_READ | PAGE_WRITE;
66 /* MIPS32/MIPS64 R4000-style MMU emulation */
67 int r4k_map_address (CPUState *env, target_ulong *physical, int *prot,
68 target_ulong address, int rw, int access_type)
70 uint8_t ASID = env->CP0_EntryHi & 0xFF;
73 for (i = 0; i < env->tlb_in_use; i++) {
74 r4k_tlb_t *tlb = &env->mmu.r4k.tlb[i];
75 /* 1k pages are not supported. */
76 target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
77 target_ulong tag = address & ~mask;
78 target_ulong VPN = tlb->VPN & ~mask;
80 tag &= 0xC00000FFFFFFFFFFULL;
83 /* Check ASID, virtual page number & size */
84 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
86 int n = !!(address & mask & ~(mask >> 1));
87 /* Check access rights */
88 if (!(n ? tlb->V1 : tlb->V0))
89 return TLBRET_INVALID;
90 if (rw == 0 || (n ? tlb->D1 : tlb->D0)) {
91 *physical = tlb->PFN[n] | (address & (mask >> 1));
93 if (n ? tlb->D1 : tlb->D0)
100 return TLBRET_NOMATCH;
103 static int get_physical_address (CPUState *env, target_ulong *physical,
104 int *prot, target_ulong address,
105 int rw, int access_type)
107 /* User mode can only access useg/xuseg */
108 int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
110 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
111 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
112 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
114 int ret = TLBRET_MATCH;
118 fprintf(logfile, "user mode %d h %08x\n",
119 user_mode, env->hflags);
124 if (user_mode && address > 0x3FFFFFFFFFFFFFFFULL)
125 return TLBRET_BADADDR;
127 if (user_mode && address > 0x7FFFFFFFUL)
128 return TLBRET_BADADDR;
131 if (address <= (int32_t)0x7FFFFFFFUL) {
133 if (!(env->CP0_Status & (1 << CP0St_ERL) && user_mode)) {
134 ret = env->map_address(env, physical, prot, address, rw, access_type);
136 *physical = address & 0xFFFFFFFF;
137 *prot = PAGE_READ | PAGE_WRITE;
142 - PABITS = 36 (correct for MIPS64R1)
145 } else if (address < 0x3FFFFFFFFFFFFFFFULL) {
147 if (UX && address < 0x000000FFFFFFFFFFULL) {
148 ret = env->map_address(env, physical, prot, address, rw, access_type);
150 ret = TLBRET_BADADDR;
152 } else if (address < 0x7FFFFFFFFFFFFFFFULL) {
154 if (SX && address < 0x400000FFFFFFFFFFULL) {
155 ret = env->map_address(env, physical, prot, address, rw, access_type);
157 ret = TLBRET_BADADDR;
159 } else if (address < 0xBFFFFFFFFFFFFFFFULL) {
161 /* XXX: check supervisor mode */
162 if (KX && (address & 0x03FFFFFFFFFFFFFFULL) < 0X0000000FFFFFFFFFULL)
164 *physical = address & 0X000000FFFFFFFFFFULL;
165 *prot = PAGE_READ | PAGE_WRITE;
167 ret = TLBRET_BADADDR;
169 } else if (address < 0xFFFFFFFF7FFFFFFFULL) {
171 /* XXX: check supervisor mode */
172 if (KX && address < 0xC00000FF7FFFFFFFULL) {
173 ret = env->map_address(env, physical, prot, address, rw, access_type);
175 ret = TLBRET_BADADDR;
178 } else if (address < (int32_t)0xA0000000UL) {
180 /* XXX: check supervisor mode */
181 *physical = address - (int32_t)0x80000000UL;
182 *prot = PAGE_READ | PAGE_WRITE;
183 } else if (address < (int32_t)0xC0000000UL) {
185 /* XXX: check supervisor mode */
186 *physical = address - (int32_t)0xA0000000UL;
187 *prot = PAGE_READ | PAGE_WRITE;
188 } else if (address < (int32_t)0xE0000000UL) {
190 ret = env->map_address(env, physical, prot, address, rw, access_type);
193 /* XXX: check supervisor mode */
194 /* XXX: debug segment is not emulated */
195 ret = env->map_address(env, physical, prot, address, rw, access_type);
199 fprintf(logfile, TARGET_FMT_lx " %d %d => " TARGET_FMT_lx " %d (%d)\n",
200 address, rw, access_type, *physical, *prot, ret);
207 #if defined(CONFIG_USER_ONLY)
208 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
213 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
215 target_ulong phys_addr;
218 if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
223 void cpu_mips_init_mmu (CPUState *env)
226 #endif /* !defined(CONFIG_USER_ONLY) */
228 int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
229 int is_user, int is_softmmu)
231 target_ulong physical;
233 int exception = 0, error_code = 0;
239 cpu_dump_state(env, logfile, fprintf, 0);
241 fprintf(logfile, "%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d is_user %d smmu %d\n",
242 __func__, env->PC, address, rw, is_user, is_softmmu);
248 /* XXX: put correct access by using cpu_restore_state()
250 access_type = ACCESS_INT;
251 if (env->user_mode_only) {
252 /* user mode only emulation */
253 ret = TLBRET_NOMATCH;
256 ret = get_physical_address(env, &physical, &prot,
257 address, rw, access_type);
259 fprintf(logfile, "%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_lx " prot %d\n",
260 __func__, address, ret, physical, prot);
262 if (ret == TLBRET_MATCH) {
263 ret = tlb_set_page(env, address & TARGET_PAGE_MASK,
264 physical & TARGET_PAGE_MASK, prot,
265 is_user, is_softmmu);
266 } else if (ret < 0) {
271 /* Reference to kernel address from user mode or supervisor mode */
272 /* Reference to supervisor address from user mode */
274 exception = EXCP_AdES;
276 exception = EXCP_AdEL;
279 /* No TLB match for a mapped address */
281 exception = EXCP_TLBS;
283 exception = EXCP_TLBL;
287 /* TLB match with no valid bit */
289 exception = EXCP_TLBS;
291 exception = EXCP_TLBL;
294 /* TLB match but 'D' bit is cleared */
295 exception = EXCP_LTLBL;
299 /* Raise exception */
300 env->CP0_BadVAddr = address;
301 env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
302 ((address >> 9) & 0x007ffff0);
304 (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1));
306 env->CP0_EntryHi &= 0xc00000ffffffffffULL;
307 env->CP0_XContext = (env->CP0_XContext & 0xfffffffe00000000ULL) |
308 ((address >> 31) & 0x0000000180000000ULL) |
309 ((address >> 9) & 0x000000007ffffff0ULL);
311 env->exception_index = exception;
312 env->error_code = error_code;
319 #if defined(CONFIG_USER_ONLY)
320 void do_interrupt (CPUState *env)
322 env->exception_index = EXCP_NONE;
325 void do_interrupt (CPUState *env)
330 if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
331 fprintf(logfile, "%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d excp %d\n",
332 __func__, env->PC, env->CP0_EPC, cause, env->exception_index);
334 if (env->exception_index == EXCP_EXT_INTERRUPT &&
335 (env->hflags & MIPS_HFLAG_DM))
336 env->exception_index = EXCP_DINT;
338 switch (env->exception_index) {
340 env->CP0_Debug |= 1 << CP0DB_DSS;
341 /* Debug single step cannot be raised inside a delay slot and
342 * resume will always occur on the next instruction
343 * (but we assume the pc has always been updated during
346 env->CP0_DEPC = env->PC;
347 goto enter_debug_mode;
349 env->CP0_Debug |= 1 << CP0DB_DINT;
352 env->CP0_Debug |= 1 << CP0DB_DIB;
355 env->CP0_Debug |= 1 << CP0DB_DBp;
358 env->CP0_Debug |= 1 << CP0DB_DDBS;
361 env->CP0_Debug |= 1 << CP0DB_DDBL;
363 if (env->hflags & MIPS_HFLAG_BMASK) {
364 /* If the exception was raised from a delay slot,
365 come back to the jump. */
366 env->CP0_DEPC = env->PC - 4;
367 env->hflags &= ~MIPS_HFLAG_BMASK;
369 env->CP0_DEPC = env->PC;
372 env->hflags |= MIPS_HFLAG_DM;
373 env->hflags &= ~MIPS_HFLAG_UM;
374 /* EJTAG probe trap enable is not implemented... */
375 if (!(env->CP0_Status & (1 << CP0St_EXL)))
376 env->CP0_Cause &= ~(1 << CP0Ca_BD);
377 env->PC = (int32_t)0xBFC00480;
383 env->CP0_Status |= (1 << CP0St_SR);
384 env->CP0_WatchLo = 0;
387 env->CP0_Status |= (1 << CP0St_NMI);
389 if (env->hflags & MIPS_HFLAG_BMASK) {
390 /* If the exception was raised from a delay slot,
391 come back to the jump. */
392 env->CP0_ErrorEPC = env->PC - 4;
393 env->hflags &= ~MIPS_HFLAG_BMASK;
395 env->CP0_ErrorEPC = env->PC;
397 env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
398 env->hflags &= ~MIPS_HFLAG_UM;
399 if (!(env->CP0_Status & (1 << CP0St_EXL)))
400 env->CP0_Cause &= ~(1 << CP0Ca_BD);
401 env->PC = (int32_t)0xBFC00000;
406 case EXCP_EXT_INTERRUPT:
408 if (env->CP0_Cause & (1 << CP0Ca_IV))
413 /* XXX: TODO: manage defered watch exceptions */
423 if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
425 int R = env->CP0_BadVAddr >> 62;
426 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
427 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
428 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
430 if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
454 env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
455 (env->error_code << CP0Ca_CE);
471 if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
473 int R = env->CP0_BadVAddr >> 62;
474 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
475 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
476 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
478 if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
485 if (!(env->CP0_Status & (1 << CP0St_EXL))) {
486 if (env->hflags & MIPS_HFLAG_BMASK) {
487 /* If the exception was raised from a delay slot,
488 come back to the jump. */
489 env->CP0_EPC = env->PC - 4;
490 env->CP0_Cause |= (1 << CP0Ca_BD);
492 env->CP0_EPC = env->PC;
493 env->CP0_Cause &= ~(1 << CP0Ca_BD);
495 env->CP0_Status |= (1 << CP0St_EXL);
496 env->hflags &= ~MIPS_HFLAG_UM;
498 env->hflags &= ~MIPS_HFLAG_BMASK;
499 if (env->CP0_Status & (1 << CP0St_BEV)) {
500 env->PC = (int32_t)0xBFC00200;
502 env->PC = (int32_t)(env->CP0_EBase & ~0x3ff);
505 env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
509 fprintf(logfile, "Invalid MIPS exception %d. Exiting\n",
510 env->exception_index);
512 printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
515 if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
516 fprintf(logfile, "%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d excp %d\n"
517 " S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
518 __func__, env->PC, env->CP0_EPC, cause, env->exception_index,
519 env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
522 env->exception_index = EXCP_NONE;
524 #endif /* !defined(CONFIG_USER_ONLY) */
526 void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra)
531 uint8_t ASID = env->CP0_EntryHi & 0xFF;
534 tlb = &env->mmu.r4k.tlb[idx];
535 /* The qemu TLB is flushed when the ASID changes, so no need to
536 flush these entries again. */
537 if (tlb->G == 0 && tlb->ASID != ASID) {
541 if (use_extra && env->tlb_in_use < MIPS_TLB_MAX) {
542 /* For tlbwr, we can shadow the discarded entry into
543 a new (fake) TLB entry, as long as the guest can not
544 tell that it's there. */
545 env->mmu.r4k.tlb[env->tlb_in_use] = *tlb;
550 /* 1k pages are not supported. */
551 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
553 addr = tlb->VPN & ~mask;
555 if (addr >= 0xC00000FF80000000ULL) {
556 addr |= 0x3FFFFF0000000000ULL;
559 end = addr | (mask >> 1);
561 tlb_flush_page (env, addr);
562 addr += TARGET_PAGE_SIZE;
566 addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
568 if (addr >= 0xC00000FF80000000ULL) {
569 addr |= 0x3FFFFF0000000000ULL;
574 tlb_flush_page (env, addr);
575 addr += TARGET_PAGE_SIZE;