2 * MIPS emulation helpers for qemu.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
39 /* no MMU emulation */
40 int no_mmu_map_address (CPUState *env, target_ulong *physical, int *prot,
41 target_ulong address, int rw, int access_type)
44 *prot = PAGE_READ | PAGE_WRITE;
48 /* fixed mapping MMU emulation */
49 int fixed_mmu_map_address (CPUState *env, target_ulong *physical, int *prot,
50 target_ulong address, int rw, int access_type)
52 if (address <= (int32_t)0x7FFFFFFFUL) {
53 if (!(env->CP0_Status & (1 << CP0St_ERL)))
54 *physical = address + 0x40000000UL;
57 } else if (address <= (int32_t)0xBFFFFFFFUL)
58 *physical = address & 0x1FFFFFFF;
62 *prot = PAGE_READ | PAGE_WRITE;
66 /* MIPS32/MIPS64 R4000-style MMU emulation */
67 int r4k_map_address (CPUState *env, target_ulong *physical, int *prot,
68 target_ulong address, int rw, int access_type)
70 uint8_t ASID = env->CP0_EntryHi & 0xFF;
73 for (i = 0; i < env->tlb->tlb_in_use; i++) {
74 r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i];
75 /* 1k pages are not supported. */
76 target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
77 target_ulong tag = address & ~mask;
78 target_ulong VPN = tlb->VPN & ~mask;
83 /* Check ASID, virtual page number & size */
84 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
86 int n = !!(address & mask & ~(mask >> 1));
87 /* Check access rights */
88 if (!(n ? tlb->V1 : tlb->V0))
89 return TLBRET_INVALID;
90 if (rw == 0 || (n ? tlb->D1 : tlb->D0)) {
91 *physical = tlb->PFN[n] | (address & (mask >> 1));
93 if (n ? tlb->D1 : tlb->D0)
100 return TLBRET_NOMATCH;
103 static int get_physical_address (CPUState *env, target_ulong *physical,
104 int *prot, target_ulong address,
105 int rw, int access_type)
107 /* User mode can only access useg/xuseg */
108 int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
110 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
111 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
112 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
114 int ret = TLBRET_MATCH;
118 fprintf(logfile, "user mode %d h %08x\n",
119 user_mode, env->hflags);
124 if (user_mode && address > 0x3FFFFFFFFFFFFFFFULL)
125 return TLBRET_BADADDR;
127 if (user_mode && address > 0x7FFFFFFFUL)
128 return TLBRET_BADADDR;
131 if (address <= (int32_t)0x7FFFFFFFUL) {
133 if (env->CP0_Status & (1 << CP0St_ERL)) {
134 *physical = address & 0xFFFFFFFF;
135 *prot = PAGE_READ | PAGE_WRITE;
137 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
142 - PABITS = 36 (correct for MIPS64R1)
144 } else if (address < 0x3FFFFFFFFFFFFFFFULL) {
146 if (UX && address < (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
147 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
149 ret = TLBRET_BADADDR;
151 } else if (address < 0x7FFFFFFFFFFFFFFFULL) {
153 if (SX && address < (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
154 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
156 ret = TLBRET_BADADDR;
158 } else if (address < 0xBFFFFFFFFFFFFFFFULL) {
160 /* XXX: check supervisor mode */
161 if (KX && (address & 0x07FFFFFFFFFFFFFFULL) < 0X0000000FFFFFFFFFULL)
163 *physical = address & 0X0000000FFFFFFFFFULL;
164 *prot = PAGE_READ | PAGE_WRITE;
166 ret = TLBRET_BADADDR;
168 } else if (address < 0xFFFFFFFF7FFFFFFFULL) {
170 /* XXX: check supervisor mode */
171 if (KX && address < (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
172 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
174 ret = TLBRET_BADADDR;
177 } else if (address < (int32_t)0xA0000000UL) {
179 /* XXX: check supervisor mode */
180 *physical = address - (int32_t)0x80000000UL;
181 *prot = PAGE_READ | PAGE_WRITE;
182 } else if (address < (int32_t)0xC0000000UL) {
184 /* XXX: check supervisor mode */
185 *physical = address - (int32_t)0xA0000000UL;
186 *prot = PAGE_READ | PAGE_WRITE;
187 } else if (address < (int32_t)0xE0000000UL) {
189 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
192 /* XXX: check supervisor mode */
193 /* XXX: debug segment is not emulated */
194 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
198 fprintf(logfile, TARGET_FMT_lx " %d %d => " TARGET_FMT_lx " %d (%d)\n",
199 address, rw, access_type, *physical, *prot, ret);
206 #if defined(CONFIG_USER_ONLY)
207 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
212 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
214 target_ulong phys_addr;
217 if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
222 void cpu_mips_init_mmu (CPUState *env)
225 #endif /* !defined(CONFIG_USER_ONLY) */
227 int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
228 int is_user, int is_softmmu)
230 target_ulong physical;
232 int exception = 0, error_code = 0;
238 cpu_dump_state(env, logfile, fprintf, 0);
240 fprintf(logfile, "%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d is_user %d smmu %d\n",
241 __func__, env->PC[env->current_tc], address, rw, is_user, is_softmmu);
247 /* XXX: put correct access by using cpu_restore_state()
249 access_type = ACCESS_INT;
250 if (env->user_mode_only) {
251 /* user mode only emulation */
252 ret = TLBRET_NOMATCH;
255 ret = get_physical_address(env, &physical, &prot,
256 address, rw, access_type);
258 fprintf(logfile, "%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_lx " prot %d\n",
259 __func__, address, ret, physical, prot);
261 if (ret == TLBRET_MATCH) {
262 ret = tlb_set_page(env, address & TARGET_PAGE_MASK,
263 physical & TARGET_PAGE_MASK, prot,
264 is_user, is_softmmu);
265 } else if (ret < 0) {
270 /* Reference to kernel address from user mode or supervisor mode */
271 /* Reference to supervisor address from user mode */
273 exception = EXCP_AdES;
275 exception = EXCP_AdEL;
278 /* No TLB match for a mapped address */
280 exception = EXCP_TLBS;
282 exception = EXCP_TLBL;
286 /* TLB match with no valid bit */
288 exception = EXCP_TLBS;
290 exception = EXCP_TLBL;
293 /* TLB match but 'D' bit is cleared */
294 exception = EXCP_LTLBL;
298 /* Raise exception */
299 env->CP0_BadVAddr = address;
300 env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
301 ((address >> 9) & 0x007ffff0);
303 (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1));
305 env->CP0_EntryHi &= env->SEGMask;
306 env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) |
307 ((address & 0xC00000000000ULL) >> (env->SEGBITS - 9)) |
308 ((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9);
310 env->exception_index = exception;
311 env->error_code = error_code;
318 #if defined(CONFIG_USER_ONLY)
319 void do_interrupt (CPUState *env)
321 env->exception_index = EXCP_NONE;
324 void do_interrupt (CPUState *env)
329 if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
330 fprintf(logfile, "%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d excp %d\n",
331 __func__, env->PC[env->current_tc], env->CP0_EPC, cause, env->exception_index);
333 if (env->exception_index == EXCP_EXT_INTERRUPT &&
334 (env->hflags & MIPS_HFLAG_DM))
335 env->exception_index = EXCP_DINT;
337 switch (env->exception_index) {
339 env->CP0_Debug |= 1 << CP0DB_DSS;
340 /* Debug single step cannot be raised inside a delay slot and
341 * resume will always occur on the next instruction
342 * (but we assume the pc has always been updated during
345 env->CP0_DEPC = env->PC[env->current_tc];
346 goto enter_debug_mode;
348 env->CP0_Debug |= 1 << CP0DB_DINT;
351 env->CP0_Debug |= 1 << CP0DB_DIB;
354 env->CP0_Debug |= 1 << CP0DB_DBp;
357 env->CP0_Debug |= 1 << CP0DB_DDBS;
360 env->CP0_Debug |= 1 << CP0DB_DDBL;
362 if (env->hflags & MIPS_HFLAG_BMASK) {
363 /* If the exception was raised from a delay slot,
364 come back to the jump. */
365 env->CP0_DEPC = env->PC[env->current_tc] - 4;
366 env->hflags &= ~MIPS_HFLAG_BMASK;
368 env->CP0_DEPC = env->PC[env->current_tc];
371 env->hflags |= MIPS_HFLAG_DM;
372 if ((env->CP0_Config0 & (0x3 << CP0C0_AT)))
373 env->hflags |= MIPS_HFLAG_64;
374 env->hflags &= ~MIPS_HFLAG_UM;
375 /* EJTAG probe trap enable is not implemented... */
376 if (!(env->CP0_Status & (1 << CP0St_EXL)))
377 env->CP0_Cause &= ~(1 << CP0Ca_BD);
378 env->PC[env->current_tc] = (int32_t)0xBFC00480;
384 env->CP0_Status |= (1 << CP0St_SR);
385 memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo));
388 env->CP0_Status |= (1 << CP0St_NMI);
390 if (env->hflags & MIPS_HFLAG_BMASK) {
391 /* If the exception was raised from a delay slot,
392 come back to the jump. */
393 env->CP0_ErrorEPC = env->PC[env->current_tc] - 4;
394 env->hflags &= ~MIPS_HFLAG_BMASK;
396 env->CP0_ErrorEPC = env->PC[env->current_tc];
398 env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
399 if ((env->CP0_Config0 & (0x3 << CP0C0_AT)))
400 env->hflags |= MIPS_HFLAG_64;
401 env->hflags &= ~MIPS_HFLAG_UM;
402 if (!(env->CP0_Status & (1 << CP0St_EXL)))
403 env->CP0_Cause &= ~(1 << CP0Ca_BD);
404 env->PC[env->current_tc] = (int32_t)0xBFC00000;
409 case EXCP_EXT_INTERRUPT:
411 if (env->CP0_Cause & (1 << CP0Ca_IV))
416 /* XXX: TODO: manage defered watch exceptions */
426 if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
428 int R = env->CP0_BadVAddr >> 62;
429 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
430 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
431 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
433 if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
457 env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
458 (env->error_code << CP0Ca_CE);
477 if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
479 int R = env->CP0_BadVAddr >> 62;
480 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
481 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
482 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
484 if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
491 if (!(env->CP0_Status & (1 << CP0St_EXL))) {
492 if (env->hflags & MIPS_HFLAG_BMASK) {
493 /* If the exception was raised from a delay slot,
494 come back to the jump. */
495 env->CP0_EPC = env->PC[env->current_tc] - 4;
496 env->CP0_Cause |= (1 << CP0Ca_BD);
498 env->CP0_EPC = env->PC[env->current_tc];
499 env->CP0_Cause &= ~(1 << CP0Ca_BD);
501 env->CP0_Status |= (1 << CP0St_EXL);
502 if ((env->CP0_Config0 & (0x3 << CP0C0_AT)))
503 env->hflags |= MIPS_HFLAG_64;
504 env->hflags &= ~MIPS_HFLAG_UM;
506 env->hflags &= ~MIPS_HFLAG_BMASK;
507 if (env->CP0_Status & (1 << CP0St_BEV)) {
508 env->PC[env->current_tc] = (int32_t)0xBFC00200;
510 env->PC[env->current_tc] = (int32_t)(env->CP0_EBase & ~0x3ff);
512 env->PC[env->current_tc] += offset;
513 env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
517 fprintf(logfile, "Invalid MIPS exception %d. Exiting\n",
518 env->exception_index);
520 printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
523 if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
524 fprintf(logfile, "%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d excp %d\n"
525 " S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
526 __func__, env->PC[env->current_tc], env->CP0_EPC, cause, env->exception_index,
527 env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
530 env->exception_index = EXCP_NONE;
532 #endif /* !defined(CONFIG_USER_ONLY) */
534 void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra)
539 uint8_t ASID = env->CP0_EntryHi & 0xFF;
542 tlb = &env->tlb->mmu.r4k.tlb[idx];
543 /* The qemu TLB is flushed when the ASID changes, so no need to
544 flush these entries again. */
545 if (tlb->G == 0 && tlb->ASID != ASID) {
549 if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
550 /* For tlbwr, we can shadow the discarded entry into
551 a new (fake) TLB entry, as long as the guest can not
552 tell that it's there. */
553 env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
554 env->tlb->tlb_in_use++;
558 /* 1k pages are not supported. */
559 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
561 addr = tlb->VPN & ~mask;
563 if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
564 addr |= 0x3FFFFF0000000000ULL;
567 end = addr | (mask >> 1);
569 tlb_flush_page (env, addr);
570 addr += TARGET_PAGE_SIZE;
574 addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
576 if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
577 addr |= 0x3FFFFF0000000000ULL;
582 tlb_flush_page (env, addr);
583 addr += TARGET_PAGE_SIZE;