2 * MIPS emulation micro-operations for qemu.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2006 Marius Groeger (FPU operations)
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 #define CALL_FROM_TB0(func) func();
29 #define CALL_FROM_TB1(func, arg0) func(arg0);
31 #ifndef CALL_FROM_TB1_CONST16
32 #define CALL_FROM_TB1_CONST16(func, arg0) CALL_FROM_TB1(func, arg0);
35 #define CALL_FROM_TB2(func, arg0, arg1) func(arg0, arg1);
37 #ifndef CALL_FROM_TB2_CONST16
38 #define CALL_FROM_TB2_CONST16(func, arg0, arg1) \
39 CALL_FROM_TB2(func, arg0, arg1);
42 #define CALL_FROM_TB3(func, arg0, arg1, arg2) func(arg0, arg1, arg2);
45 #define CALL_FROM_TB4(func, arg0, arg1, arg2, arg3) \
46 func(arg0, arg1, arg2, arg3);
50 #include "op_template.c"
53 #include "op_template.c"
56 #include "op_template.c"
59 #include "op_template.c"
62 #include "op_template.c"
65 #include "op_template.c"
68 #include "op_template.c"
71 #include "op_template.c"
74 #include "op_template.c"
77 #include "op_template.c"
80 #include "op_template.c"
83 #include "op_template.c"
86 #include "op_template.c"
89 #include "op_template.c"
92 #include "op_template.c"
95 #include "op_template.c"
98 #include "op_template.c"
101 #include "op_template.c"
104 #include "op_template.c"
107 #include "op_template.c"
110 #include "op_template.c"
113 #include "op_template.c"
116 #include "op_template.c"
119 #include "op_template.c"
122 #include "op_template.c"
125 #include "op_template.c"
128 #include "op_template.c"
131 #include "op_template.c"
134 #include "op_template.c"
137 #include "op_template.c"
140 #include "op_template.c"
144 #include "op_template.c"
151 #include "fop_template.c"
155 #include "fop_template.c"
159 #include "fop_template.c"
163 #include "fop_template.c"
167 #include "fop_template.c"
171 #include "fop_template.c"
175 #include "fop_template.c"
179 #include "fop_template.c"
183 #include "fop_template.c"
187 #include "fop_template.c"
191 #include "fop_template.c"
195 #include "fop_template.c"
199 #include "fop_template.c"
203 #include "fop_template.c"
207 #include "fop_template.c"
211 #include "fop_template.c"
215 #include "fop_template.c"
219 #include "fop_template.c"
223 #include "fop_template.c"
227 #include "fop_template.c"
231 #include "fop_template.c"
235 #include "fop_template.c"
239 #include "fop_template.c"
243 #include "fop_template.c"
247 #include "fop_template.c"
251 #include "fop_template.c"
255 #include "fop_template.c"
259 #include "fop_template.c"
263 #include "fop_template.c"
267 #include "fop_template.c"
271 #include "fop_template.c"
275 #include "fop_template.c"
279 #include "fop_template.c"
284 void op_dup_T0 (void)
290 void op_load_HI (void)
296 void op_store_HI (void)
302 void op_load_LO (void)
308 void op_store_LO (void)
315 #define MEMSUFFIX _raw
318 #if !defined(CONFIG_USER_ONLY)
319 #define MEMSUFFIX _user
323 #define MEMSUFFIX _kernel
331 T0 = (int32_t)((int32_t)T0 + (int32_t)T1);
340 T0 = (int32_t)T0 + (int32_t)T1;
341 if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 31) {
342 /* operands of same sign, result different sign */
343 CALL_FROM_TB1(do_raise_exception_direct, EXCP_OVERFLOW);
351 T0 = (int32_t)((int32_t)T0 - (int32_t)T1);
360 T0 = (int32_t)T0 - (int32_t)T1;
361 if (((tmp ^ T1) & (tmp ^ T0)) >> 31) {
362 /* operands of different sign, first operand and result different sign */
363 CALL_FROM_TB1(do_raise_exception_direct, EXCP_OVERFLOW);
371 T0 = (int32_t)((int32_t)T0 * (int32_t)T1);
378 env->LO = (int32_t)((int32_t)T0 / (int32_t)T1);
379 env->HI = (int32_t)((int32_t)T0 % (int32_t)T1);
387 env->LO = (int32_t)((uint32_t)T0 / (uint32_t)T1);
388 env->HI = (int32_t)((uint32_t)T0 % (uint32_t)T1);
393 #ifdef MIPS_HAS_MIPS64
407 if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 63) {
408 /* operands of same sign, result different sign */
409 CALL_FROM_TB1(do_raise_exception_direct, EXCP_OVERFLOW);
425 T0 = (int64_t)T0 - (int64_t)T1;
426 if (((tmp ^ T1) & (tmp ^ T0)) >> 63) {
427 /* operands of different sign, first operand and result different sign */
428 CALL_FROM_TB1(do_raise_exception_direct, EXCP_OVERFLOW);
435 T0 = (int64_t)T0 * (int64_t)T1;
439 #if TARGET_LONG_BITS > HOST_LONG_BITS
440 /* Those might call libgcc functions. */
456 env->LO = (int64_t)T0 / (int64_t)T1;
457 env->HI = (int64_t)T0 % (int64_t)T1;
471 #endif /* MIPS_HAS_MIPS64 */
500 T0 = (int32_t)((uint32_t)T0 << (uint32_t)T1);
506 T0 = (int32_t)((int32_t)T0 >> (uint32_t)T1);
512 T0 = (int32_t)((uint32_t)T0 >> (uint32_t)T1);
521 tmp = (int32_t)((uint32_t)T0 << (0x20 - (uint32_t)T1));
522 T0 = (int32_t)((uint32_t)T0 >> (uint32_t)T1) | tmp;
530 T0 = (int32_t)((uint32_t)T1 << ((uint32_t)T0 & 0x1F));
536 T0 = (int32_t)((int32_t)T1 >> (T0 & 0x1F));
542 T0 = (int32_t)((uint32_t)T1 >> (T0 & 0x1F));
552 tmp = (int32_t)((uint32_t)T1 << (0x20 - T0));
553 T0 = (int32_t)((uint32_t)T1 >> T0) | tmp;
563 if (T0 == ~((target_ulong)0)) {
566 for (n = 0; n < 32; n++) {
567 if (!(T0 & (1 << 31)))
583 for (n = 0; n < 32; n++) {
593 #ifdef MIPS_HAS_MIPS64
595 #if TARGET_LONG_BITS > HOST_LONG_BITS
596 /* Those might call libgcc functions. */
599 CALL_FROM_TB0(do_dsll);
603 void op_dsll32 (void)
605 CALL_FROM_TB0(do_dsll32);
611 CALL_FROM_TB0(do_dsra);
615 void op_dsra32 (void)
617 CALL_FROM_TB0(do_dsra32);
623 CALL_FROM_TB0(do_dsrl);
627 void op_dsrl32 (void)
629 CALL_FROM_TB0(do_dsrl32);
635 CALL_FROM_TB0(do_drotr);
639 void op_drotr32 (void)
641 CALL_FROM_TB0(do_drotr32);
647 CALL_FROM_TB0(do_dsllv);
653 CALL_FROM_TB0(do_dsrav);
659 CALL_FROM_TB0(do_dsrlv);
663 void op_drotrv (void)
665 CALL_FROM_TB0(do_drotrv);
669 #else /* TARGET_LONG_BITS > HOST_LONG_BITS */
677 void op_dsll32 (void)
679 T0 = T0 << (T1 + 32);
685 T0 = (int64_t)T0 >> T1;
689 void op_dsra32 (void)
691 T0 = (int64_t)T0 >> (T1 + 32);
701 void op_dsrl32 (void)
703 T0 = T0 >> (T1 + 32);
712 tmp = T0 << (0x40 - T1);
713 T0 = (T0 >> T1) | tmp;
719 void op_drotr32 (void)
724 tmp = T0 << (0x40 - (32 + T1));
725 T0 = (T0 >> (32 + T1)) | tmp;
733 T0 = T1 << (T0 & 0x3F);
739 T0 = (int64_t)T1 >> (T0 & 0x3F);
745 T0 = T1 >> (T0 & 0x3F);
749 void op_drotrv (void)
755 tmp = T1 << (0x40 - T0);
756 T0 = (T1 >> T0) | tmp;
761 #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
767 if (T0 == ~((target_ulong)0)) {
770 for (n = 0; n < 64; n++) {
771 if (!(T0 & (1ULL << 63)))
787 for (n = 0; n < 64; n++) {
788 if (T0 & (1ULL << 63))
798 /* 64 bits arithmetic */
799 #if TARGET_LONG_BITS > HOST_LONG_BITS
802 CALL_FROM_TB0(do_mult);
808 CALL_FROM_TB0(do_multu);
814 CALL_FROM_TB0(do_madd);
820 CALL_FROM_TB0(do_maddu);
826 CALL_FROM_TB0(do_msub);
832 CALL_FROM_TB0(do_msubu);
836 #else /* TARGET_LONG_BITS > HOST_LONG_BITS */
838 static inline uint64_t get_HILO (void)
840 return ((uint64_t)env->HI << 32) | ((uint64_t)(uint32_t)env->LO);
843 static inline void set_HILO (uint64_t HILO)
845 env->LO = (int32_t)(HILO & 0xFFFFFFFF);
846 env->HI = (int32_t)(HILO >> 32);
851 set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
857 set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
865 tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
866 set_HILO((int64_t)get_HILO() + tmp);
874 tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
875 set_HILO(get_HILO() + tmp);
883 tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
884 set_HILO((int64_t)get_HILO() - tmp);
892 tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
893 set_HILO(get_HILO() - tmp);
896 #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
898 #ifdef MIPS_HAS_MIPS64
901 CALL_FROM_TB0(do_dmult);
905 void op_dmultu (void)
907 CALL_FROM_TB0(do_dmultu);
912 /* Conditional moves */
916 env->gpr[PARAM1] = T0;
923 env->gpr[PARAM1] = T0;
930 if (!(env->fcr31 & PARAM1))
931 env->gpr[PARAM2] = env->gpr[PARAM3];
937 if (env->fcr31 & PARAM1)
938 env->gpr[PARAM2] = env->gpr[PARAM3];
944 #define OP_COND(name, cond) \
945 void glue(op_, name) (void) \
955 OP_COND(eq, T0 == T1);
956 OP_COND(ne, T0 != T1);
957 OP_COND(ge, (int32_t)T0 >= (int32_t)T1);
958 OP_COND(geu, T0 >= T1);
959 OP_COND(lt, (int32_t)T0 < (int32_t)T1);
960 OP_COND(ltu, T0 < T1);
961 OP_COND(gez, (int32_t)T0 >= 0);
962 OP_COND(gtz, (int32_t)T0 > 0);
963 OP_COND(lez, (int32_t)T0 <= 0);
964 OP_COND(ltz, (int32_t)T0 < 0);
967 //#undef USE_DIRECT_JUMP
969 void OPPROTO op_goto_tb0(void)
971 GOTO_TB(op_goto_tb0, PARAM1, 0);
975 void OPPROTO op_goto_tb1(void)
977 GOTO_TB(op_goto_tb1, PARAM1, 1);
981 /* Branch to register */
982 void op_save_breg_target (void)
988 void op_restore_breg_target (void)
1000 void op_save_btarget (void)
1002 env->btarget = PARAM1;
1006 /* Conditional branch */
1007 void op_set_bcond (void)
1013 void op_save_bcond (void)
1019 void op_restore_bcond (void)
1025 void op_jnz_T2 (void)
1028 GOTO_LABEL_PARAM(1);
1033 void op_mfc0_index (void)
1035 T0 = env->CP0_Index;
1039 void op_mfc0_random (void)
1041 CALL_FROM_TB0(do_mfc0_random);
1045 void op_mfc0_entrylo0 (void)
1047 T0 = (int32_t)env->CP0_EntryLo0;
1051 void op_mfc0_entrylo1 (void)
1053 T0 = (int32_t)env->CP0_EntryLo1;
1057 void op_mfc0_context (void)
1059 T0 = (int32_t)env->CP0_Context;
1063 void op_mfc0_pagemask (void)
1065 T0 = env->CP0_PageMask;
1069 void op_mfc0_pagegrain (void)
1071 T0 = env->CP0_PageGrain;
1075 void op_mfc0_wired (void)
1077 T0 = env->CP0_Wired;
1081 void op_mfc0_hwrena (void)
1083 T0 = env->CP0_HWREna;
1087 void op_mfc0_badvaddr (void)
1089 T0 = (int32_t)env->CP0_BadVAddr;
1093 void op_mfc0_count (void)
1095 CALL_FROM_TB0(do_mfc0_count);
1099 void op_mfc0_entryhi (void)
1101 T0 = (int32_t)env->CP0_EntryHi;
1105 void op_mfc0_compare (void)
1107 T0 = env->CP0_Compare;
1111 void op_mfc0_status (void)
1113 T0 = env->CP0_Status;
1114 if (env->hflags & MIPS_HFLAG_UM)
1115 T0 |= (1 << CP0St_UM);
1116 if (env->hflags & MIPS_HFLAG_ERL)
1117 T0 |= (1 << CP0St_ERL);
1118 if (env->hflags & MIPS_HFLAG_EXL)
1119 T0 |= (1 << CP0St_EXL);
1123 void op_mfc0_intctl (void)
1125 T0 = env->CP0_IntCtl;
1129 void op_mfc0_srsctl (void)
1131 T0 = env->CP0_SRSCtl;
1135 void op_mfc0_srsmap (void)
1137 T0 = env->CP0_SRSMap;
1141 void op_mfc0_cause (void)
1143 T0 = env->CP0_Cause;
1147 void op_mfc0_epc (void)
1149 T0 = (int32_t)env->CP0_EPC;
1153 void op_mfc0_prid (void)
1159 void op_mfc0_ebase (void)
1161 T0 = env->CP0_EBase;
1165 void op_mfc0_config0 (void)
1167 T0 = env->CP0_Config0;
1171 void op_mfc0_config1 (void)
1173 T0 = env->CP0_Config1;
1177 void op_mfc0_config2 (void)
1179 T0 = env->CP0_Config2;
1183 void op_mfc0_config3 (void)
1185 T0 = env->CP0_Config3;
1189 void op_mfc0_lladdr (void)
1191 T0 = (int32_t)env->CP0_LLAddr >> 4;
1195 void op_mfc0_watchlo0 (void)
1197 T0 = (int32_t)env->CP0_WatchLo;
1201 void op_mfc0_watchhi0 (void)
1203 T0 = env->CP0_WatchHi;
1207 void op_mfc0_xcontext (void)
1209 T0 = (int32_t)env->CP0_XContext;
1213 void op_mfc0_framemask (void)
1215 T0 = env->CP0_Framemask;
1219 void op_mfc0_debug (void)
1221 T0 = env->CP0_Debug;
1222 if (env->hflags & MIPS_HFLAG_DM)
1223 T0 |= 1 << CP0DB_DM;
1227 void op_mfc0_depc (void)
1229 T0 = (int32_t)env->CP0_DEPC;
1233 void op_mfc0_performance0 (void)
1235 T0 = env->CP0_Performance0;
1239 void op_mfc0_taglo (void)
1241 T0 = env->CP0_TagLo;
1245 void op_mfc0_datalo (void)
1247 T0 = env->CP0_DataLo;
1251 void op_mfc0_taghi (void)
1253 T0 = env->CP0_TagHi;
1257 void op_mfc0_datahi (void)
1259 T0 = env->CP0_DataHi;
1263 void op_mfc0_errorepc (void)
1265 T0 = (int32_t)env->CP0_ErrorEPC;
1269 void op_mfc0_desave (void)
1271 T0 = env->CP0_DESAVE;
1275 void op_mtc0_index (void)
1277 env->CP0_Index = (env->CP0_Index & 0x80000000) | (T0 & (MIPS_TLB_NB - 1));
1281 void op_mtc0_entrylo0 (void)
1283 /* Large physaddr not implemented */
1284 /* 1k pages not implemented */
1285 env->CP0_EntryLo0 = (int32_t)T0 & 0x3FFFFFFF;
1289 void op_mtc0_entrylo1 (void)
1291 /* Large physaddr not implemented */
1292 /* 1k pages not implemented */
1293 env->CP0_EntryLo1 = (int32_t)T0 & 0x3FFFFFFF;
1297 void op_mtc0_context (void)
1299 env->CP0_Context = (env->CP0_Context & ~0x007FFFFF) | (T0 & 0x007FFFF0);
1303 void op_mtc0_pagemask (void)
1305 /* 1k pages not implemented */
1306 env->CP0_PageMask = T0 & 0x1FFFE000;
1310 void op_mtc0_pagegrain (void)
1312 /* SmartMIPS not implemented */
1313 /* Large physaddr not implemented */
1314 /* 1k pages not implemented */
1315 env->CP0_PageGrain = 0;
1319 void op_mtc0_wired (void)
1321 env->CP0_Wired = T0 & (MIPS_TLB_NB - 1);
1325 void op_mtc0_hwrena (void)
1327 env->CP0_HWREna = T0 & 0x0000000F;
1331 void op_mtc0_count (void)
1333 CALL_FROM_TB2(cpu_mips_store_count, env, T0);
1337 void op_mtc0_entryhi (void)
1339 target_ulong old, val;
1341 /* 1k pages not implemented */
1342 /* Ignore MIPS64 TLB for now */
1343 val = (target_ulong)(int32_t)T0 & ~(target_ulong)0x1F00;
1344 old = env->CP0_EntryHi;
1345 env->CP0_EntryHi = val;
1346 /* If the ASID changes, flush qemu's TLB. */
1347 if ((old & 0xFF) != (val & 0xFF))
1348 CALL_FROM_TB2(cpu_mips_tlb_flush, env, 1);
1352 void op_mtc0_compare (void)
1354 CALL_FROM_TB2(cpu_mips_store_compare, env, T0);
1358 void op_mtc0_status (void)
1362 val = (int32_t)T0 & 0xFA78FF01;
1363 old = env->CP0_Status;
1364 if (T0 & (1 << CP0St_UM))
1365 env->hflags |= MIPS_HFLAG_UM;
1367 env->hflags &= ~MIPS_HFLAG_UM;
1368 if (T0 & (1 << CP0St_ERL))
1369 env->hflags |= MIPS_HFLAG_ERL;
1371 env->hflags &= ~MIPS_HFLAG_ERL;
1372 if (T0 & (1 << CP0St_EXL))
1373 env->hflags |= MIPS_HFLAG_EXL;
1375 env->hflags &= ~MIPS_HFLAG_EXL;
1376 env->CP0_Status = val;
1377 if (loglevel & CPU_LOG_TB_IN_ASM)
1378 CALL_FROM_TB2(do_mtc0_status_debug, old, val);
1379 CALL_FROM_TB1(cpu_mips_update_irq, env);
1383 void op_mtc0_intctl (void)
1385 /* vectored interrupts not implemented */
1386 env->CP0_IntCtl = 0;
1390 void op_mtc0_srsctl (void)
1392 /* shadow registers not implemented */
1393 env->CP0_SRSCtl = 0;
1397 void op_mtc0_srsmap (void)
1399 /* shadow registers not implemented */
1400 env->CP0_SRSMap = 0;
1404 void op_mtc0_cause (void)
1406 env->CP0_Cause = (env->CP0_Cause & 0xB000F87C) | (T0 & 0x00C00300);
1408 /* Handle the software interrupt as an hardware one, as they
1410 if (T0 & CP0Ca_IP_mask) {
1411 CALL_FROM_TB1(cpu_mips_update_irq, env);
1416 void op_mtc0_epc (void)
1418 env->CP0_EPC = (int32_t)T0;
1422 void op_mtc0_ebase (void)
1424 /* vectored interrupts not implemented */
1425 /* Multi-CPU not implemented */
1426 env->CP0_EBase = 0x80000000 | (T0 & 0x3FFFF000);
1430 void op_mtc0_config0 (void)
1432 #if defined(MIPS_USES_R4K_TLB)
1433 /* Fixed mapping MMU not implemented */
1434 env->CP0_Config0 = (env->CP0_Config0 & 0x8017FF88) | (T0 & 0x00000001);
1436 env->CP0_Config0 = (env->CP0_Config0 & 0xFE17FF88) | (T0 & 0x00000001);
1441 void op_mtc0_config2 (void)
1443 /* tertiary/secondary caches not implemented */
1444 env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1448 void op_mtc0_watchlo0 (void)
1450 env->CP0_WatchLo = (int32_t)T0;
1454 void op_mtc0_watchhi0 (void)
1456 env->CP0_WatchHi = T0 & 0x40FF0FF8;
1460 void op_mtc0_xcontext (void)
1462 env->CP0_XContext = (int32_t)T0; /* XXX */
1466 void op_mtc0_framemask (void)
1468 env->CP0_Framemask = T0; /* XXX */
1472 void op_mtc0_debug (void)
1474 env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (T0 & 0x13300120);
1475 if (T0 & (1 << CP0DB_DM))
1476 env->hflags |= MIPS_HFLAG_DM;
1478 env->hflags &= ~MIPS_HFLAG_DM;
1482 void op_mtc0_depc (void)
1484 env->CP0_DEPC = (int32_t)T0;
1488 void op_mtc0_performance0 (void)
1490 env->CP0_Performance0 = T0; /* XXX */
1494 void op_mtc0_taglo (void)
1496 env->CP0_TagLo = T0 & 0xFFFFFCF6;
1500 void op_mtc0_datalo (void)
1502 env->CP0_DataLo = T0; /* XXX */
1506 void op_mtc0_taghi (void)
1508 env->CP0_TagHi = T0; /* XXX */
1512 void op_mtc0_datahi (void)
1514 env->CP0_DataHi = T0; /* XXX */
1518 void op_mtc0_errorepc (void)
1520 env->CP0_ErrorEPC = (int32_t)T0;
1524 void op_mtc0_desave (void)
1526 env->CP0_DESAVE = T0;
1530 void op_dmfc0_entrylo0 (void)
1532 T0 = env->CP0_EntryLo0;
1536 void op_dmfc0_entrylo1 (void)
1538 T0 = env->CP0_EntryLo1;
1542 void op_dmfc0_context (void)
1544 T0 = env->CP0_Context;
1548 void op_dmfc0_badvaddr (void)
1550 T0 = env->CP0_BadVAddr;
1554 void op_dmfc0_entryhi (void)
1556 T0 = env->CP0_EntryHi;
1560 void op_dmfc0_epc (void)
1566 void op_dmfc0_lladdr (void)
1568 T0 = env->CP0_LLAddr >> 4;
1572 void op_dmfc0_watchlo0 (void)
1574 T0 = env->CP0_WatchLo;
1578 void op_dmfc0_xcontext (void)
1580 T0 = env->CP0_XContext;
1584 void op_dmfc0_depc (void)
1590 void op_dmfc0_errorepc (void)
1592 T0 = env->CP0_ErrorEPC;
1596 void op_dmtc0_entrylo0 (void)
1598 /* Large physaddr not implemented */
1599 /* 1k pages not implemented */
1600 env->CP0_EntryLo0 = T0 & 0x3FFFFFFF;
1604 void op_dmtc0_entrylo1 (void)
1606 /* Large physaddr not implemented */
1607 /* 1k pages not implemented */
1608 env->CP0_EntryLo1 = T0 & 0x3FFFFFFF;
1612 void op_dmtc0_context (void)
1614 env->CP0_Context = (env->CP0_Context & ~0x007FFFFF) | (T0 & 0x007FFFF0);
1618 void op_dmtc0_epc (void)
1624 void op_dmtc0_watchlo0 (void)
1626 env->CP0_WatchLo = T0;
1630 void op_dmtc0_xcontext (void)
1632 env->CP0_XContext = T0; /* XXX */
1636 void op_dmtc0_depc (void)
1642 void op_dmtc0_errorepc (void)
1644 env->CP0_ErrorEPC = T0;
1648 #ifdef MIPS_USES_FPU
1651 # define DEBUG_FPU_STATE() CALL_FROM_TB1(dump_fpu, env)
1653 # define DEBUG_FPU_STATE() do { } while(0)
1656 void op_cp1_enabled(void)
1658 if (!(env->CP0_Status & (1 << CP0St_CU1))) {
1659 CALL_FROM_TB2(do_raise_exception_err, EXCP_CpU, 1);
1671 /* fetch fcr31, masking unused bits */
1672 T0 = env->fcr31 & 0x0183FFFF;
1678 /* convert MIPS rounding mode in FCR31 to IEEE library */
1679 unsigned int ieee_rm[] = {
1680 float_round_nearest_even,
1681 float_round_to_zero,
1686 #define RESTORE_ROUNDING_MODE \
1687 set_float_rounding_mode(ieee_rm[env->fcr31 & 3], &env->fp_status)
1692 /* XXX should this throw an exception?
1693 * don't write to FCR0.
1698 /* store new fcr31, masking unused bits */
1699 env->fcr31 = T0 & 0x0183FFFF;
1701 /* set rounding mode */
1702 RESTORE_ROUNDING_MODE;
1704 #ifndef CONFIG_SOFTFLOAT
1705 /* no floating point exception for native float */
1706 SET_FP_ENABLE(env->fcr31, 0);
1728 Single precition routines have a "s" suffix, double precision a
1731 #define FLOAT_OP(name, p) void OPPROTO op_float_##name##_##p(void)
1735 FDT2 = float32_to_float64(FST0, &env->fp_status);
1741 FDT2 = int32_to_float64(WT0, &env->fp_status);
1747 FST2 = float64_to_float32(FDT0, &env->fp_status);
1753 FST2 = int32_to_float32(WT0, &env->fp_status);
1759 WT2 = float32_to_int32(FST0, &env->fp_status);
1765 WT2 = float64_to_int32(FDT0, &env->fp_status);
1772 set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
1773 WT2 = float64_round_to_int(FDT0, &env->fp_status);
1774 RESTORE_ROUNDING_MODE;
1781 set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
1782 WT2 = float32_round_to_int(FST0, &env->fp_status);
1783 RESTORE_ROUNDING_MODE;
1790 WT2 = float64_to_int32_round_to_zero(FDT0, &env->fp_status);
1796 WT2 = float32_to_int32_round_to_zero(FST0, &env->fp_status);
1803 set_float_rounding_mode(float_round_up, &env->fp_status);
1804 WT2 = float64_round_to_int(FDT0, &env->fp_status);
1805 RESTORE_ROUNDING_MODE;
1812 set_float_rounding_mode(float_round_up, &env->fp_status);
1813 WT2 = float32_round_to_int(FST0, &env->fp_status);
1814 RESTORE_ROUNDING_MODE;
1821 set_float_rounding_mode(float_round_down, &env->fp_status);
1822 WT2 = float64_round_to_int(FDT0, &env->fp_status);
1823 RESTORE_ROUNDING_MODE;
1830 set_float_rounding_mode(float_round_down, &env->fp_status);
1831 WT2 = float32_round_to_int(FST0, &env->fp_status);
1832 RESTORE_ROUNDING_MODE;
1837 /* binary operations */
1838 #define FLOAT_BINOP(name) \
1841 FDT2 = float64_ ## name (FDT0, FDT1, &env->fp_status); \
1842 DEBUG_FPU_STATE(); \
1846 FST2 = float32_ ## name (FST0, FST1, &env->fp_status); \
1847 DEBUG_FPU_STATE(); \
1855 /* unary operations, modifying fp status */
1856 #define FLOAT_UNOP(name) \
1859 FDT2 = float64_ ## name(FDT0, &env->fp_status); \
1860 DEBUG_FPU_STATE(); \
1864 FST2 = float32_ ## name(FST0, &env->fp_status); \
1865 DEBUG_FPU_STATE(); \
1870 /* unary operations, not modifying fp status */
1871 #define FLOAT_UNOP(name) \
1874 FDT2 = float64_ ## name(FDT0); \
1875 DEBUG_FPU_STATE(); \
1879 FST2 = float32_ ## name(FST0); \
1880 DEBUG_FPU_STATE(); \
1899 #ifdef CONFIG_SOFTFLOAT
1900 #define clear_invalid() do { \
1901 int flags = get_float_exception_flags(&env->fp_status); \
1902 flags &= ~float_flag_invalid; \
1903 set_float_exception_flags(flags, &env->fp_status); \
1906 #define clear_invalid() do { } while(0)
1909 extern void dump_fpu_s(CPUState *env);
1911 #define FOP_COND(fmt, op, sig, cond) \
1912 void op_cmp_ ## fmt ## _ ## op (void) \
1915 SET_FP_COND(env->fcr31); \
1917 CLEAR_FP_COND(env->fcr31); \
1920 /*CALL_FROM_TB1(dump_fpu_s, env);*/ \
1921 DEBUG_FPU_STATE(); \
1925 int float64_is_unordered(float64 a, float64 b STATUS_PARAM)
1927 if (float64_is_nan(a) || float64_is_nan(b)) {
1928 float_raise(float_flag_invalid, status);
1936 FOP_COND(d, f, 0, 0)
1937 FOP_COND(d, un, 0, float64_is_unordered(FDT1, FDT0, &env->fp_status))
1938 FOP_COND(d, eq, 0, float64_eq(FDT0, FDT1, &env->fp_status))
1939 FOP_COND(d, ueq, 0, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_eq(FDT0, FDT1, &env->fp_status))
1940 FOP_COND(d, olt, 0, float64_lt(FDT0, FDT1, &env->fp_status))
1941 FOP_COND(d, ult, 0, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_lt(FDT0, FDT1, &env->fp_status))
1942 FOP_COND(d, ole, 0, float64_le(FDT0, FDT1, &env->fp_status))
1943 FOP_COND(d, ule, 0, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_le(FDT0, FDT1, &env->fp_status))
1944 /* NOTE: the comma operator will make "cond" to eval to false,
1945 * but float*_is_unordered() is still called
1947 FOP_COND(d, sf, 1, (float64_is_unordered(FDT0, FDT1, &env->fp_status), 0))
1948 FOP_COND(d, ngle,1, float64_is_unordered(FDT1, FDT0, &env->fp_status))
1949 FOP_COND(d, seq, 1, float64_eq(FDT0, FDT1, &env->fp_status))
1950 FOP_COND(d, ngl, 1, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_eq(FDT0, FDT1, &env->fp_status))
1951 FOP_COND(d, lt, 1, float64_lt(FDT0, FDT1, &env->fp_status))
1952 FOP_COND(d, nge, 1, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_lt(FDT0, FDT1, &env->fp_status))
1953 FOP_COND(d, le, 1, float64_le(FDT0, FDT1, &env->fp_status))
1954 FOP_COND(d, ngt, 1, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_le(FDT0, FDT1, &env->fp_status))
1956 flag float32_is_unordered(float32 a, float32 b STATUS_PARAM)
1958 extern flag float32_is_nan( float32 a );
1959 if (float32_is_nan(a) || float32_is_nan(b)) {
1960 float_raise(float_flag_invalid, status);
1968 /* NOTE: the comma operator will make "cond" to eval to false,
1969 * but float*_is_unordered() is still called
1971 FOP_COND(s, f, 0, 0)
1972 FOP_COND(s, un, 0, float32_is_unordered(FST1, FST0, &env->fp_status))
1973 FOP_COND(s, eq, 0, float32_eq(FST0, FST1, &env->fp_status))
1974 FOP_COND(s, ueq, 0, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_eq(FST0, FST1, &env->fp_status))
1975 FOP_COND(s, olt, 0, float32_lt(FST0, FST1, &env->fp_status))
1976 FOP_COND(s, ult, 0, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_lt(FST0, FST1, &env->fp_status))
1977 FOP_COND(s, ole, 0, float32_le(FST0, FST1, &env->fp_status))
1978 FOP_COND(s, ule, 0, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_le(FST0, FST1, &env->fp_status))
1979 /* NOTE: the comma operator will make "cond" to eval to false,
1980 * but float*_is_unordered() is still called
1982 FOP_COND(s, sf, 1, (float32_is_unordered(FST0, FST1, &env->fp_status), 0))
1983 FOP_COND(s, ngle,1, float32_is_unordered(FST1, FST0, &env->fp_status))
1984 FOP_COND(s, seq, 1, float32_eq(FST0, FST1, &env->fp_status))
1985 FOP_COND(s, ngl, 1, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_eq(FST0, FST1, &env->fp_status))
1986 FOP_COND(s, lt, 1, float32_lt(FST0, FST1, &env->fp_status))
1987 FOP_COND(s, nge, 1, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_lt(FST0, FST1, &env->fp_status))
1988 FOP_COND(s, le, 1, float32_le(FST0, FST1, &env->fp_status))
1989 FOP_COND(s, ngt, 1, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_le(FST0, FST1, &env->fp_status))
1993 T0 = ! IS_FP_COND_SET(env->fcr31);
2000 T0 = IS_FP_COND_SET(env->fcr31);
2004 #endif /* MIPS_USES_FPU */
2006 #if defined(MIPS_USES_R4K_TLB)
2007 void op_tlbwi (void)
2009 CALL_FROM_TB0(do_tlbwi);
2013 void op_tlbwr (void)
2015 CALL_FROM_TB0(do_tlbwr);
2021 CALL_FROM_TB0(do_tlbp);
2027 CALL_FROM_TB0(do_tlbr);
2035 CALL_FROM_TB1(do_pmon, PARAM1);
2041 T0 = env->CP0_Status;
2042 env->CP0_Status = T0 & ~(1 << CP0St_IE);
2043 CALL_FROM_TB1(cpu_mips_update_irq, env);
2049 T0 = env->CP0_Status;
2050 env->CP0_Status = T0 | (1 << CP0St_IE);
2051 CALL_FROM_TB1(cpu_mips_update_irq, env);
2058 CALL_FROM_TB1(do_raise_exception_direct, EXCP_TRAP);
2063 void op_debug (void)
2065 CALL_FROM_TB1(do_raise_exception, EXCP_DEBUG);
2069 void op_set_lladdr (void)
2071 env->CP0_LLAddr = T2;
2075 void debug_eret (void);
2078 CALL_FROM_TB0(debug_eret);
2079 if (env->hflags & MIPS_HFLAG_ERL) {
2080 env->PC = env->CP0_ErrorEPC;
2081 env->hflags &= ~MIPS_HFLAG_ERL;
2082 env->CP0_Status &= ~(1 << CP0St_ERL);
2084 env->PC = env->CP0_EPC;
2085 env->hflags &= ~MIPS_HFLAG_EXL;
2086 env->CP0_Status &= ~(1 << CP0St_EXL);
2088 env->CP0_LLAddr = 1;
2092 void op_deret (void)
2094 CALL_FROM_TB0(debug_eret);
2095 env->PC = env->CP0_DEPC;
2099 void op_rdhwr_cpunum(void)
2101 if (env->CP0_HWREna & (1 << 0))
2102 T0 = env->CP0_EBase & 0x2ff;
2104 CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI);
2108 void op_rdhwr_synci_step(void)
2110 if (env->CP0_HWREna & (1 << 1))
2111 T0 = env->SYNCI_Step;
2113 CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI);
2117 void op_rdhwr_cc(void)
2119 if (env->CP0_HWREna & (1 << 2))
2120 T0 = env->CP0_Count;
2122 CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI);
2126 void op_rdhwr_ccres(void)
2128 if (env->CP0_HWREna & (1 << 3))
2131 CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI);
2135 void op_save_state (void)
2137 env->hflags = PARAM1;
2141 void op_save_pc (void)
2147 void op_raise_exception (void)
2149 CALL_FROM_TB1(do_raise_exception, PARAM1);
2153 void op_raise_exception_err (void)
2155 CALL_FROM_TB2(do_raise_exception_err, PARAM1, PARAM2);
2159 void op_exit_tb (void)
2168 CALL_FROM_TB1(do_raise_exception, EXCP_HLT);
2172 /* Bitfield operations. */
2175 unsigned int pos = PARAM1;
2176 unsigned int size = PARAM2;
2178 T0 = ((uint32_t)T1 >> pos) & ((1 << size) - 1);
2184 unsigned int pos = PARAM1;
2185 unsigned int size = PARAM2;
2186 target_ulong mask = ((1 << size) - 1) << pos;
2188 T0 = (T2 & ~mask) | (((uint32_t)T1 << pos) & mask);
2194 T0 = ((T1 << 8) & ~0x00FF00FF) | ((T1 >> 8) & 0x00FF00FF);
2198 #ifdef MIPS_HAS_MIPS64
2201 unsigned int pos = PARAM1;
2202 unsigned int size = PARAM2;
2204 T0 = (T1 >> pos) & ((1 << size) - 1);
2210 unsigned int pos = PARAM1;
2211 unsigned int size = PARAM2;
2212 target_ulong mask = ((1 << size) - 1) << pos;
2214 T0 = (T2 & ~mask) | ((T1 << pos) & mask);
2220 T0 = ((T1 << 8) & ~0x00FF00FF00FF00FFULL) | ((T1 >> 8) & 0x00FF00FF00FF00FFULL);
2226 T0 = ((T1 << 16) & ~0x0000FFFF0000FFFFULL) | ((T1 >> 16) & 0x0000FFFF0000FFFFULL);
2233 T0 = ((T1 & 0xFF) ^ 0x80) - 0x80;
2239 T0 = ((T1 & 0xFFFF) ^ 0x8000) - 0x8000;