2 * MIPS emulation micro-operations for qemu.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2006 Marius Groeger (FPU operations)
6 * Copyright (c) 2007 Thiemo Seufer (64-bit FPU support)
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include "host-utils.h"
28 #define CALL_FROM_TB0(func) func()
31 #define CALL_FROM_TB1(func, arg0) func(arg0)
33 #ifndef CALL_FROM_TB1_CONST16
34 #define CALL_FROM_TB1_CONST16(func, arg0) CALL_FROM_TB1(func, arg0)
37 #define CALL_FROM_TB2(func, arg0, arg1) func(arg0, arg1)
39 #ifndef CALL_FROM_TB2_CONST16
40 #define CALL_FROM_TB2_CONST16(func, arg0, arg1) \
41 CALL_FROM_TB2(func, arg0, arg1)
44 #define CALL_FROM_TB3(func, arg0, arg1, arg2) func(arg0, arg1, arg2)
47 #define CALL_FROM_TB4(func, arg0, arg1, arg2, arg3) \
48 func(arg0, arg1, arg2, arg3)
52 #define MEMSUFFIX _raw
55 #if !defined(CONFIG_USER_ONLY)
56 #define MEMSUFFIX _user
60 #define MEMSUFFIX _super
64 #define MEMSUFFIX _kernel
69 /* 64 bits arithmetic */
70 #if TARGET_LONG_BITS > HOST_LONG_BITS
73 CALL_FROM_TB0(do_mult);
79 CALL_FROM_TB0(do_multu);
85 CALL_FROM_TB0(do_madd);
91 CALL_FROM_TB0(do_maddu);
97 CALL_FROM_TB0(do_msub);
103 CALL_FROM_TB0(do_msubu);
107 /* Multiplication variants of the vr54xx. */
110 CALL_FROM_TB0(do_muls);
116 CALL_FROM_TB0(do_mulsu);
122 CALL_FROM_TB0(do_macc);
126 void op_macchi (void)
128 CALL_FROM_TB0(do_macchi);
134 CALL_FROM_TB0(do_maccu);
137 void op_macchiu (void)
139 CALL_FROM_TB0(do_macchiu);
145 CALL_FROM_TB0(do_msac);
149 void op_msachi (void)
151 CALL_FROM_TB0(do_msachi);
157 CALL_FROM_TB0(do_msacu);
161 void op_msachiu (void)
163 CALL_FROM_TB0(do_msachiu);
169 CALL_FROM_TB0(do_mulhi);
173 void op_mulhiu (void)
175 CALL_FROM_TB0(do_mulhiu);
179 void op_mulshi (void)
181 CALL_FROM_TB0(do_mulshi);
185 void op_mulshiu (void)
187 CALL_FROM_TB0(do_mulshiu);
191 #else /* TARGET_LONG_BITS > HOST_LONG_BITS */
193 static always_inline uint64_t get_HILO (void)
195 return ((uint64_t)env->HI[env->current_tc][0] << 32) |
196 ((uint64_t)(uint32_t)env->LO[env->current_tc][0]);
199 static always_inline void set_HILO (uint64_t HILO)
201 env->LO[env->current_tc][0] = (int32_t)(HILO & 0xFFFFFFFF);
202 env->HI[env->current_tc][0] = (int32_t)(HILO >> 32);
205 static always_inline void set_HIT0_LO (uint64_t HILO)
207 env->LO[env->current_tc][0] = (int32_t)(HILO & 0xFFFFFFFF);
208 T0 = env->HI[env->current_tc][0] = (int32_t)(HILO >> 32);
211 static always_inline void set_HI_LOT0 (uint64_t HILO)
213 T0 = env->LO[env->current_tc][0] = (int32_t)(HILO & 0xFFFFFFFF);
214 env->HI[env->current_tc][0] = (int32_t)(HILO >> 32);
219 set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
225 set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
233 tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
234 set_HILO((int64_t)get_HILO() + tmp);
242 tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
243 set_HILO(get_HILO() + tmp);
251 tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
252 set_HILO((int64_t)get_HILO() - tmp);
260 tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
261 set_HILO(get_HILO() - tmp);
265 /* Multiplication variants of the vr54xx. */
268 set_HI_LOT0(0 - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
274 set_HI_LOT0(0 - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
280 set_HI_LOT0(get_HILO() + ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
284 void op_macchi (void)
286 set_HIT0_LO(get_HILO() + ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
292 set_HI_LOT0(get_HILO() + ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
296 void op_macchiu (void)
298 set_HIT0_LO(get_HILO() + ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
304 set_HI_LOT0(get_HILO() - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
308 void op_msachi (void)
310 set_HIT0_LO(get_HILO() - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
316 set_HI_LOT0(get_HILO() - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
320 void op_msachiu (void)
322 set_HIT0_LO(get_HILO() - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
328 set_HIT0_LO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
332 void op_mulhiu (void)
334 set_HIT0_LO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
338 void op_mulshi (void)
340 set_HIT0_LO(0 - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
344 void op_mulshiu (void)
346 set_HIT0_LO(0 - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
350 #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
352 #if defined(TARGET_MIPS64)
355 CALL_FROM_TB4(muls64, &(env->LO[env->current_tc][0]), &(env->HI[env->current_tc][0]), T0, T1);
359 void op_dmultu (void)
361 CALL_FROM_TB4(mulu64, &(env->LO[env->current_tc][0]), &(env->HI[env->current_tc][0]), T0, T1);
368 # define DEBUG_FPU_STATE() CALL_FROM_TB1(dump_fpu, env)
370 # define DEBUG_FPU_STATE() do { } while(0)
374 Single precition routines have a "s" suffix, double precision a
375 "d" suffix, 32bit integer "w", 64bit integer "l", paired singe "ps",
376 paired single lowwer "pl", paired single upper "pu". */
378 #define FLOAT_OP(name, p) void OPPROTO op_float_##name##_##p(void)
390 DT2 = ((uint64_t)WT0 << 32) | WT1;
396 DT2 = ((uint64_t)WT0 << 32) | WTH1;
402 DT2 = ((uint64_t)WTH0 << 32) | WT1;
408 DT2 = ((uint64_t)WTH0 << 32) | WTH1;
415 if (!(env->fpu->fcr31 & PARAM1))
422 if (!(env->fpu->fcr31 & PARAM1))
429 unsigned int mask = GET_FP_COND (env->fpu) >> PARAM1;
439 if (env->fpu->fcr31 & PARAM1)
446 if (env->fpu->fcr31 & PARAM1)
453 unsigned int mask = GET_FP_COND (env->fpu) >> PARAM1;
508 /* ternary operations */
509 #define FLOAT_TERNOP(name1, name2) \
510 FLOAT_OP(name1 ## name2, d) \
512 FDT0 = float64_ ## name1 (FDT0, FDT1, &env->fpu->fp_status); \
513 FDT2 = float64_ ## name2 (FDT0, FDT2, &env->fpu->fp_status); \
517 FLOAT_OP(name1 ## name2, s) \
519 FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status); \
520 FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status); \
524 FLOAT_OP(name1 ## name2, ps) \
526 FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status); \
527 FSTH0 = float32_ ## name1 (FSTH0, FSTH1, &env->fpu->fp_status); \
528 FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status); \
529 FSTH2 = float32_ ## name2 (FSTH0, FSTH2, &env->fpu->fp_status); \
533 FLOAT_TERNOP(mul, add)
534 FLOAT_TERNOP(mul, sub)
537 /* negated ternary operations */
538 #define FLOAT_NTERNOP(name1, name2) \
539 FLOAT_OP(n ## name1 ## name2, d) \
541 FDT0 = float64_ ## name1 (FDT0, FDT1, &env->fpu->fp_status); \
542 FDT2 = float64_ ## name2 (FDT0, FDT2, &env->fpu->fp_status); \
543 FDT2 = float64_chs(FDT2); \
547 FLOAT_OP(n ## name1 ## name2, s) \
549 FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status); \
550 FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status); \
551 FST2 = float32_chs(FST2); \
555 FLOAT_OP(n ## name1 ## name2, ps) \
557 FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status); \
558 FSTH0 = float32_ ## name1 (FSTH0, FSTH1, &env->fpu->fp_status); \
559 FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status); \
560 FSTH2 = float32_ ## name2 (FSTH0, FSTH2, &env->fpu->fp_status); \
561 FST2 = float32_chs(FST2); \
562 FSTH2 = float32_chs(FSTH2); \
566 FLOAT_NTERNOP(mul, add)
567 FLOAT_NTERNOP(mul, sub)
570 /* unary operations, modifying fp status */
571 #define FLOAT_UNOP(name) \
574 FDT2 = float64_ ## name(FDT0, &env->fpu->fp_status); \
580 FST2 = float32_ ## name(FST0, &env->fpu->fp_status); \
587 /* unary operations, not modifying fp status */
588 #define FLOAT_UNOP(name) \
591 FDT2 = float64_ ## name(FDT0); \
597 FST2 = float32_ ## name(FST0); \
603 FST2 = float32_ ## name(FST0); \
604 FSTH2 = float32_ ## name(FSTH0); \
639 #ifdef TARGET_WORDS_BIGENDIAN
647 default: /* unpredictable */
654 #ifdef CONFIG_SOFTFLOAT
655 #define clear_invalid() do { \
656 int flags = get_float_exception_flags(&env->fpu->fp_status); \
657 flags &= ~float_flag_invalid; \
658 set_float_exception_flags(flags, &env->fpu->fp_status); \
661 #define clear_invalid() do { } while(0)
664 extern void dump_fpu_s(CPUState *env);
668 T0 = !!(~GET_FP_COND(env->fpu) & (0x1 << PARAM1));
672 void op_bc1any2f (void)
674 T0 = !!(~GET_FP_COND(env->fpu) & (0x3 << PARAM1));
678 void op_bc1any4f (void)
680 T0 = !!(~GET_FP_COND(env->fpu) & (0xf << PARAM1));
687 T0 = !!(GET_FP_COND(env->fpu) & (0x1 << PARAM1));
691 void op_bc1any2t (void)
693 T0 = !!(GET_FP_COND(env->fpu) & (0x3 << PARAM1));
697 void op_bc1any4t (void)
699 T0 = !!(GET_FP_COND(env->fpu) & (0xf << PARAM1));
706 CALL_FROM_TB0(env->tlb->do_tlbwi);
712 CALL_FROM_TB0(env->tlb->do_tlbwr);
718 CALL_FROM_TB0(env->tlb->do_tlbp);
724 CALL_FROM_TB0(env->tlb->do_tlbr);
729 #if defined (CONFIG_USER_ONLY)
730 void op_tls_value (void)
738 CALL_FROM_TB1(do_pmon, PARAM1);
744 T0 = env->CP0_Status;
745 env->CP0_Status = T0 & ~(1 << CP0St_IE);
746 CALL_FROM_TB1(cpu_mips_update_irq, env);
752 T0 = env->CP0_Status;
753 env->CP0_Status = T0 | (1 << CP0St_IE);
754 CALL_FROM_TB1(cpu_mips_update_irq, env);
761 CALL_FROM_TB1(do_raise_exception, EXCP_TRAP);
768 CALL_FROM_TB1(do_raise_exception, EXCP_DEBUG);
772 void debug_pre_eret (void);
773 void debug_post_eret (void);
776 if (loglevel & CPU_LOG_EXEC)
777 CALL_FROM_TB0(debug_pre_eret);
778 if (env->CP0_Status & (1 << CP0St_ERL)) {
779 env->PC[env->current_tc] = env->CP0_ErrorEPC;
780 env->CP0_Status &= ~(1 << CP0St_ERL);
782 env->PC[env->current_tc] = env->CP0_EPC;
783 env->CP0_Status &= ~(1 << CP0St_EXL);
785 CALL_FROM_TB1(compute_hflags, env);
786 if (loglevel & CPU_LOG_EXEC)
787 CALL_FROM_TB0(debug_post_eret);
794 if (loglevel & CPU_LOG_EXEC)
795 CALL_FROM_TB0(debug_pre_eret);
796 env->PC[env->current_tc] = env->CP0_DEPC;
797 env->hflags &= MIPS_HFLAG_DM;
798 CALL_FROM_TB1(compute_hflags, env);
799 if (loglevel & CPU_LOG_EXEC)
800 CALL_FROM_TB0(debug_post_eret);
805 void op_rdhwr_cpunum(void)
807 if ((env->hflags & MIPS_HFLAG_CP0) ||
808 (env->CP0_HWREna & (1 << 0)))
809 T0 = env->CP0_EBase & 0x3ff;
811 CALL_FROM_TB1(do_raise_exception, EXCP_RI);
815 void op_rdhwr_synci_step(void)
817 if ((env->hflags & MIPS_HFLAG_CP0) ||
818 (env->CP0_HWREna & (1 << 1)))
819 T0 = env->SYNCI_Step;
821 CALL_FROM_TB1(do_raise_exception, EXCP_RI);
825 void op_rdhwr_cc(void)
827 if ((env->hflags & MIPS_HFLAG_CP0) ||
828 (env->CP0_HWREna & (1 << 2)))
831 CALL_FROM_TB1(do_raise_exception, EXCP_RI);
835 void op_rdhwr_ccres(void)
837 if ((env->hflags & MIPS_HFLAG_CP0) ||
838 (env->CP0_HWREna & (1 << 3)))
841 CALL_FROM_TB1(do_raise_exception, EXCP_RI);
845 void op_save_state (void)
847 env->hflags = PARAM1;
854 CALL_FROM_TB1(do_raise_exception, EXCP_HLT);
858 /* Bitfield operations. */
861 unsigned int pos = PARAM1;
862 unsigned int size = PARAM2;
864 T0 = (int32_t)((T1 >> pos) & ((size < 32) ? ((1 << size) - 1) : ~0));
870 unsigned int pos = PARAM1;
871 unsigned int size = PARAM2;
872 target_ulong mask = ((size < 32) ? ((1 << size) - 1) : ~0) << pos;
874 T0 = (int32_t)((T0 & ~mask) | ((T1 << pos) & mask));
880 T0 = (int32_t)(((T1 << 8) & ~0x00FF00FF) | ((T1 >> 8) & 0x00FF00FF));
884 #if defined(TARGET_MIPS64)
887 unsigned int pos = PARAM1;
888 unsigned int size = PARAM2;
890 T0 = (T1 >> pos) & ((size < 64) ? ((1ULL << size) - 1) : ~0ULL);
896 unsigned int pos = PARAM1;
897 unsigned int size = PARAM2;
898 target_ulong mask = ((size < 64) ? ((1ULL << size) - 1) : ~0ULL) << pos;
900 T0 = (T0 & ~mask) | ((T1 << pos) & mask);
906 T0 = ((T1 << 8) & ~0x00FF00FF00FF00FFULL) | ((T1 >> 8) & 0x00FF00FF00FF00FFULL);
912 T1 = ((T1 << 16) & ~0x0000FFFF0000FFFFULL) | ((T1 >> 16) & 0x0000FFFF0000FFFFULL);
913 T0 = (T1 << 32) | (T1 >> 32);