2 * MIPS emulation helpers for qemu.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #define MIPS_DEBUG_DISAS
25 /*****************************************************************************/
26 /* Exceptions processing helpers */
27 void cpu_loop_exit(void)
29 longjmp(env->jmp_env, 1);
32 void do_raise_exception_err (uint32_t exception, int error_code)
35 if (logfile && exception < 0x100)
36 fprintf(logfile, "%s: %d %d\n", __func__, exception, error_code);
38 env->exception_index = exception;
39 env->error_code = error_code;
44 void do_raise_exception (uint32_t exception)
46 do_raise_exception_err(exception, 0);
49 #define MEMSUFFIX _raw
50 #include "op_helper_mem.c"
52 #if !defined(CONFIG_USER_ONLY)
53 #define MEMSUFFIX _user
54 #include "op_helper_mem.c"
56 #define MEMSUFFIX _kernel
57 #include "op_helper_mem.c"
61 /* 64 bits arithmetic for 32 bits hosts */
62 #if (HOST_LONG_BITS == 32)
63 static inline uint64_t get_HILO (void)
65 return ((uint64_t)env->HI << 32) | (uint64_t)env->LO;
68 static inline void set_HILO (uint64_t HILO)
70 env->LO = HILO & 0xFFFFFFFF;
76 set_HILO((int64_t)T0 * (int64_t)T1);
81 set_HILO((uint64_t)T0 * (uint64_t)T1);
88 tmp = ((int64_t)T0 * (int64_t)T1);
89 set_HILO((int64_t)get_HILO() + tmp);
96 tmp = ((uint64_t)T0 * (uint64_t)T1);
97 set_HILO(get_HILO() + tmp);
104 tmp = ((int64_t)T0 * (int64_t)T1);
105 set_HILO((int64_t)get_HILO() - tmp);
112 tmp = ((uint64_t)T0 * (uint64_t)T1);
113 set_HILO(get_HILO() - tmp);
117 #if defined(CONFIG_USER_ONLY)
118 void do_mfc0 (int reg, int sel)
120 cpu_abort(env, "mfc0 reg=%d sel=%d\n", reg, sel);
122 void do_mtc0 (int reg, int sel)
124 cpu_abort(env, "mtc0 reg=%d sel=%d\n", reg, sel);
129 cpu_abort(env, "tlbwi\n");
134 cpu_abort(env, "tlbwr\n");
139 cpu_abort(env, "tlbp\n");
144 cpu_abort(env, "tlbr\n");
149 void do_mfc0 (int reg, int sel)
151 const unsigned char *rn;
153 if (sel != 0 && reg != 16 && reg != 28) {
163 T0 = cpu_mips_get_random(env);
167 T0 = env->CP0_EntryLo0;
171 T0 = env->CP0_EntryLo1;
175 T0 = env->CP0_Context;
179 T0 = env->CP0_PageMask;
187 T0 = env->CP0_BadVAddr;
191 T0 = cpu_mips_get_count(env);
195 T0 = env->CP0_EntryHi;
199 T0 = env->CP0_Compare;
203 T0 = env->CP0_Status;
204 if (env->hflags & MIPS_HFLAG_UM)
205 T0 |= (1 << CP0St_UM);
206 if (env->hflags & MIPS_HFLAG_ERL)
207 T0 |= (1 << CP0St_ERL);
208 if (env->hflags & MIPS_HFLAG_EXL)
209 T0 |= (1 << CP0St_EXL);
227 T0 = env->CP0_Config0;
231 T0 = env->CP0_Config1;
235 rn = "Unknown config register";
240 T0 = env->CP0_LLAddr >> 4;
244 T0 = env->CP0_WatchLo;
248 T0 = env->CP0_WatchHi;
253 if (env->hflags & MIPS_HFLAG_DM)
268 T0 = env->CP0_DataLo;
277 T0 = env->CP0_ErrorEPC;
281 T0 = env->CP0_DESAVE;
289 #if defined MIPS_DEBUG_DISAS
290 if (loglevel & CPU_LOG_TB_IN_ASM) {
291 fprintf(logfile, "%08x mfc0 %s => %08x (%d %d)\n",
292 env->PC, rn, T0, reg, sel);
298 void do_mtc0 (int reg, int sel)
300 const unsigned char *rn;
301 uint32_t val, old, mask;
303 if (sel != 0 && reg != 16 && reg != 28) {
311 val = (env->CP0_index & 0x80000000) | (T0 & 0x0000000F);
312 old = env->CP0_index;
313 env->CP0_index = val;
317 val = T0 & 0x03FFFFFFF;
318 old = env->CP0_EntryLo0;
319 env->CP0_EntryLo0 = val;
323 val = T0 & 0x03FFFFFFF;
324 old = env->CP0_EntryLo1;
325 env->CP0_EntryLo1 = val;
329 val = (env->CP0_Context & 0xFF000000) | (T0 & 0x00FFFFF0);
330 old = env->CP0_Context;
331 env->CP0_Context = val;
335 val = T0 & 0x01FFE000;
336 old = env->CP0_PageMask;
337 env->CP0_PageMask = val;
341 val = T0 & 0x0000000F;
342 old = env->CP0_Wired;
343 env->CP0_Wired = val;
348 old = cpu_mips_get_count(env);
349 cpu_mips_store_count(env, val);
353 val = T0 & 0xFFFFF0FF;
354 old = env->CP0_EntryHi;
355 env->CP0_EntryHi = val;
360 old = env->CP0_Compare;
361 cpu_mips_store_compare(env, val);
365 val = T0 & 0xFA78FF01;
366 if (T0 & (1 << CP0St_UM))
367 env->hflags |= MIPS_HFLAG_UM;
369 env->hflags &= ~MIPS_HFLAG_UM;
370 if (T0 & (1 << CP0St_ERL))
371 env->hflags |= MIPS_HFLAG_ERL;
373 env->hflags &= ~MIPS_HFLAG_ERL;
374 if (T0 & (1 << CP0St_EXL))
375 env->hflags |= MIPS_HFLAG_EXL;
377 env->hflags &= ~MIPS_HFLAG_EXL;
378 old = env->CP0_Status;
379 env->CP0_Status = val;
380 /* If we unmasked an asserted IRQ, raise it */
382 if (loglevel & CPU_LOG_TB_IN_ASM) {
383 fprintf(logfile, "Status %08x => %08x Cause %08x (%08x %08x %08x)\n",
384 old, val, env->CP0_Cause, old & mask, val & mask,
385 env->CP0_Cause & mask);
388 if ((val & (1 << CP0St_IE)) && !(old & (1 << CP0St_IE)) &&
389 !(env->hflags & MIPS_HFLAG_EXL) &&
390 !(env->hflags & MIPS_HFLAG_ERL) &&
391 !(env->hflags & MIPS_HFLAG_DM) &&
392 (env->CP0_Status & env->CP0_Cause & mask)) {
394 fprintf(logfile, "Raise pending IRQs\n");
395 env->interrupt_request |= CPU_INTERRUPT_HARD;
396 do_raise_exception(EXCP_EXT_INTERRUPT);
397 } else if (!(val & 0x00000001) && (old & 0x00000001)) {
398 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
404 val = (env->CP0_Cause & 0xB000F87C) | (T0 & 0x000C00300);
405 old = env->CP0_Cause;
406 env->CP0_Cause = val;
410 /* Check if we ever asserted a software IRQ */
411 for (i = 0; i < 2; i++) {
413 if ((val & mask) & !(old & mask))
429 #if defined(MIPS_USES_R4K_TLB)
430 val = (env->CP0_Config0 & 0x8017FF80) | (T0 & 0x7E000001);
432 val = (env->CP0_Config0 & 0xFE17FF80) | (T0 & 0x00000001);
434 old = env->CP0_Config0;
435 env->CP0_Config0 = val;
441 rn = "bad config selector";
447 old = env->CP0_WatchLo;
448 env->CP0_WatchLo = val;
452 val = T0 & 0x40FF0FF8;
453 old = env->CP0_WatchHi;
454 env->CP0_WatchHi = val;
458 val = (env->CP0_Debug & 0x8C03FC1F) | (T0 & 0x13300120);
459 if (T0 & (1 << CP0DB_DM))
460 env->hflags |= MIPS_HFLAG_DM;
462 env->hflags &= ~MIPS_HFLAG_DM;
463 old = env->CP0_Debug;
464 env->CP0_Debug = val;
476 val = T0 & 0xFFFFFCF6;
477 old = env->CP0_TagLo;
478 env->CP0_TagLo = val;
490 old = env->CP0_ErrorEPC;
491 env->CP0_ErrorEPC = val;
496 old = env->CP0_DESAVE;
497 env->CP0_DESAVE = val;
507 #if defined MIPS_DEBUG_DISAS
508 if (loglevel & CPU_LOG_TB_IN_ASM) {
509 fprintf(logfile, "%08x mtc0 %s %08x => %08x (%d %d %08x)\n",
510 env->PC, rn, T0, val, reg, sel, old);
517 #if defined(MIPS_USES_R4K_TLB)
518 static void invalidate_tb (int idx)
521 target_ulong addr, end;
523 tlb = &env->tlb[idx];
526 end = addr + (tlb->end - tlb->VPN);
527 tb_invalidate_page_range(addr, end);
531 end = addr + (tlb->end - tlb->VPN);
532 tb_invalidate_page_range(addr, end);
536 static void fill_tb (int idx)
541 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
542 tlb = &env->tlb[idx];
543 tlb->VPN = env->CP0_EntryHi & 0xFFFFE000;
544 tlb->ASID = env->CP0_EntryHi & 0x000000FF;
545 size = env->CP0_PageMask >> 13;
546 size = 4 * (size + 1);
547 tlb->end = tlb->VPN + (1 << (8 + size));
548 tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
549 tlb->V[0] = env->CP0_EntryLo0 & 2;
550 tlb->D[0] = env->CP0_EntryLo0 & 4;
551 tlb->C[0] = (env->CP0_EntryLo0 >> 3) & 0x7;
552 tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
553 tlb->V[1] = env->CP0_EntryLo1 & 2;
554 tlb->D[1] = env->CP0_EntryLo1 & 4;
555 tlb->C[1] = (env->CP0_EntryLo1 >> 3) & 0x7;
556 tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
561 /* Wildly undefined effects for CP0_index containing a too high value and
562 MIPS_TLB_NB not being a power of two. But so does real silicon. */
563 invalidate_tb(env->CP0_index & (MIPS_TLB_NB - 1));
564 fill_tb(env->CP0_index & (MIPS_TLB_NB - 1));
569 int r = cpu_mips_get_random(env);
582 tag = (env->CP0_EntryHi & 0xFFFFE000);
583 ASID = env->CP0_EntryHi & 0x000000FF;
584 for (i = 0; i < MIPS_TLB_NB; i++) {
586 /* Check ASID, virtual page number & size */
587 if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) {
593 if (i == MIPS_TLB_NB) {
594 env->CP0_index |= 0x80000000;
603 tlb = &env->tlb[env->CP0_index & (MIPS_TLB_NB - 1)];
604 env->CP0_EntryHi = tlb->VPN | tlb->ASID;
605 size = (tlb->end - tlb->VPN) >> 12;
606 env->CP0_PageMask = (size - 1) << 13;
607 env->CP0_EntryLo0 = tlb->V[0] | tlb->D[0] | (tlb->C[0] << 3) |
609 env->CP0_EntryLo1 = tlb->V[1] | tlb->D[1] | (tlb->C[1] << 3) |
614 #endif /* !CONFIG_USER_ONLY */
616 void op_dump_ldst (const unsigned char *func)
619 fprintf(logfile, "%s => %08x %08x\n", __func__, T0, T1);
625 fprintf(logfile, "%s %08x at %08x (%08x)\n", __func__,
626 T1, T0, env->CP0_LLAddr);
630 void debug_eret (void)
633 fprintf(logfile, "ERET: pc %08x EPC %08x ErrorEPC %08x (%d)\n",
634 env->PC, env->CP0_EPC, env->CP0_ErrorEPC,
635 env->hflags & MIPS_HFLAG_ERL ? 1 : 0);
639 void do_pmon (int function)
643 case 2: /* TODO: char inbyte(int waitflag); */
644 if (env->gpr[4] == 0)
647 case 11: /* TODO: char inbyte (void); */
652 printf("%c", env->gpr[4] & 0xFF);
658 unsigned char *fmt = (void *)env->gpr[4];
665 #if !defined(CONFIG_USER_ONLY)
667 #define MMUSUFFIX _mmu
668 #define GETPC() (__builtin_return_address(0))
671 #include "softmmu_template.h"
674 #include "softmmu_template.h"
677 #include "softmmu_template.h"
680 #include "softmmu_template.h"
682 void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr)
684 TranslationBlock *tb;
689 /* XXX: hack to restore env in all cases, even if not called from
692 env = cpu_single_env;
693 ret = cpu_mips_handle_mmu_fault(env, addr, is_write, is_user, 1);
696 /* now we have a real cpu fault */
697 pc = (unsigned long)retaddr;
700 /* the PC is inside the translated code. It means that we have
701 a virtual CPU fault */
702 cpu_restore_state(tb, env, pc, NULL);
705 do_raise_exception_err(env->exception_index, env->error_code);