2 * MIPS emulation helpers for qemu.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #include "host-utils.h"
26 # define GETPC() ((void*)((unsigned long)__builtin_return_address(0) & 0x7fffffffUL))
28 # define GETPC() (__builtin_return_address(0))
31 /*****************************************************************************/
32 /* Exceptions processing helpers */
34 void do_raise_exception_err (uint32_t exception, int error_code)
37 if (logfile && exception < 0x100)
38 fprintf(logfile, "%s: %d %d\n", __func__, exception, error_code);
40 env->exception_index = exception;
41 env->error_code = error_code;
46 void do_raise_exception (uint32_t exception)
48 do_raise_exception_err(exception, 0);
51 void do_restore_state (void *pc_ptr)
54 unsigned long pc = (unsigned long) pc_ptr;
57 cpu_restore_state (tb, env, pc, NULL);
60 void do_raise_exception_direct_err (uint32_t exception, int error_code)
62 do_restore_state (GETPC ());
63 do_raise_exception_err (exception, error_code);
66 void do_raise_exception_direct (uint32_t exception)
68 do_raise_exception_direct_err (exception, 0);
71 #if defined(TARGET_MIPS64)
72 #if TARGET_LONG_BITS > HOST_LONG_BITS
73 /* Those might call libgcc functions. */
86 T0 = (int64_t)T0 >> T1;
91 T0 = (int64_t)T0 >> (T1 + 32);
101 T0 = T0 >> (T1 + 32);
109 tmp = T0 << (0x40 - T1);
110 T0 = (T0 >> T1) | tmp;
114 void do_drotr32 (void)
119 tmp = T0 << (0x40 - (32 + T1));
120 T0 = (T0 >> (32 + T1)) | tmp;
126 T0 = T1 << (T0 & 0x3F);
131 T0 = (int64_t)T1 >> (T0 & 0x3F);
136 T0 = T1 >> (T0 & 0x3F);
139 void do_drotrv (void)
145 tmp = T1 << (0x40 - T0);
146 T0 = (T1 >> T0) | tmp;
161 #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
162 #endif /* TARGET_MIPS64 */
164 /* 64 bits arithmetic for 32 bits hosts */
165 #if TARGET_LONG_BITS > HOST_LONG_BITS
166 static always_inline uint64_t get_HILO (void)
168 return (env->HI[0][env->current_tc] << 32) | (uint32_t)env->LO[0][env->current_tc];
171 static always_inline void set_HILO (uint64_t HILO)
173 env->LO[0][env->current_tc] = (int32_t)HILO;
174 env->HI[0][env->current_tc] = (int32_t)(HILO >> 32);
179 set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
184 set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
191 tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
192 set_HILO((int64_t)get_HILO() + tmp);
199 tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
200 set_HILO(get_HILO() + tmp);
207 tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
208 set_HILO((int64_t)get_HILO() - tmp);
215 tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
216 set_HILO(get_HILO() - tmp);
220 #if HOST_LONG_BITS < 64
223 /* 64bit datatypes because we may see overflow/underflow. */
225 env->LO[0][env->current_tc] = (int32_t)((int64_t)(int32_t)T0 / (int32_t)T1);
226 env->HI[0][env->current_tc] = (int32_t)((int64_t)(int32_t)T0 % (int32_t)T1);
231 #if defined(TARGET_MIPS64)
235 lldiv_t res = lldiv((int64_t)T0, (int64_t)T1);
236 env->LO[0][env->current_tc] = res.quot;
237 env->HI[0][env->current_tc] = res.rem;
241 #if TARGET_LONG_BITS > HOST_LONG_BITS
245 env->LO[0][env->current_tc] = T0 / T1;
246 env->HI[0][env->current_tc] = T0 % T1;
250 #endif /* TARGET_MIPS64 */
252 #if defined(CONFIG_USER_ONLY)
253 void do_mfc0_random (void)
255 cpu_abort(env, "mfc0 random\n");
258 void do_mfc0_count (void)
260 cpu_abort(env, "mfc0 count\n");
263 void cpu_mips_store_count(CPUState *env, uint32_t value)
265 cpu_abort(env, "mtc0 count\n");
268 void cpu_mips_store_compare(CPUState *env, uint32_t value)
270 cpu_abort(env, "mtc0 compare\n");
273 void cpu_mips_start_count(CPUState *env)
275 cpu_abort(env, "start count\n");
278 void cpu_mips_stop_count(CPUState *env)
280 cpu_abort(env, "stop count\n");
283 void cpu_mips_update_irq(CPUState *env)
285 cpu_abort(env, "mtc0 status / mtc0 cause\n");
288 void do_mtc0_status_debug(uint32_t old, uint32_t val)
290 cpu_abort(env, "mtc0 status debug\n");
293 void do_mtc0_status_irqraise_debug (void)
295 cpu_abort(env, "mtc0 status irqraise debug\n");
298 void cpu_mips_tlb_flush (CPUState *env, int flush_global)
300 cpu_abort(env, "mips_tlb_flush\n");
306 void do_mfc0_random (void)
308 T0 = (int32_t)cpu_mips_get_random(env);
311 void do_mfc0_count (void)
313 T0 = (int32_t)cpu_mips_get_count(env);
316 void do_mtc0_status_debug(uint32_t old, uint32_t val)
318 fprintf(logfile, "Status %08x (%08x) => %08x (%08x) Cause %08x",
319 old, old & env->CP0_Cause & CP0Ca_IP_mask,
320 val, val & env->CP0_Cause & CP0Ca_IP_mask,
322 switch (env->hflags & MIPS_HFLAG_KSU) {
323 case MIPS_HFLAG_UM: fputs(", UM\n", logfile); break;
324 case MIPS_HFLAG_SM: fputs(", SM\n", logfile); break;
325 case MIPS_HFLAG_KM: fputs("\n", logfile); break;
326 default: cpu_abort(env, "Invalid MMU mode!\n"); break;
330 void do_mtc0_status_irqraise_debug(void)
332 fprintf(logfile, "Raise pending IRQs\n");
335 void fpu_handle_exception(void)
337 #ifdef CONFIG_SOFTFLOAT
338 int flags = get_float_exception_flags(&env->fpu->fp_status);
339 unsigned int cpuflags = 0, enable, cause = 0;
341 enable = GET_FP_ENABLE(env->fpu->fcr31);
343 /* determine current flags */
344 if (flags & float_flag_invalid) {
345 cpuflags |= FP_INVALID;
346 cause |= FP_INVALID & enable;
348 if (flags & float_flag_divbyzero) {
350 cause |= FP_DIV0 & enable;
352 if (flags & float_flag_overflow) {
353 cpuflags |= FP_OVERFLOW;
354 cause |= FP_OVERFLOW & enable;
356 if (flags & float_flag_underflow) {
357 cpuflags |= FP_UNDERFLOW;
358 cause |= FP_UNDERFLOW & enable;
360 if (flags & float_flag_inexact) {
361 cpuflags |= FP_INEXACT;
362 cause |= FP_INEXACT & enable;
364 SET_FP_FLAGS(env->fpu->fcr31, cpuflags);
365 SET_FP_CAUSE(env->fpu->fcr31, cause);
367 SET_FP_FLAGS(env->fpu->fcr31, 0);
368 SET_FP_CAUSE(env->fpu->fcr31, 0);
373 void cpu_mips_tlb_flush (CPUState *env, int flush_global)
375 /* Flush qemu's TLB and discard all shadowed entries. */
376 tlb_flush (env, flush_global);
377 env->tlb->tlb_in_use = env->tlb->nb_tlb;
380 static void r4k_mips_tlb_flush_extra (CPUState *env, int first)
382 /* Discard entries from env->tlb[first] onwards. */
383 while (env->tlb->tlb_in_use > first) {
384 r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
388 static void r4k_fill_tlb (int idx)
392 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
393 tlb = &env->tlb->mmu.r4k.tlb[idx];
394 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
395 #if defined(TARGET_MIPS64)
396 tlb->VPN &= env->SEGMask;
398 tlb->ASID = env->CP0_EntryHi & 0xFF;
399 tlb->PageMask = env->CP0_PageMask;
400 tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
401 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
402 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
403 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
404 tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
405 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
406 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
407 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
408 tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
411 void r4k_do_tlbwi (void)
413 /* Discard cached TLB entries. We could avoid doing this if the
414 tlbwi is just upgrading access permissions on the current entry;
415 that might be a further win. */
416 r4k_mips_tlb_flush_extra (env, env->tlb->nb_tlb);
418 r4k_invalidate_tlb(env, env->CP0_Index % env->tlb->nb_tlb, 0);
419 r4k_fill_tlb(env->CP0_Index % env->tlb->nb_tlb);
422 void r4k_do_tlbwr (void)
424 int r = cpu_mips_get_random(env);
426 r4k_invalidate_tlb(env, r, 1);
430 void r4k_do_tlbp (void)
439 ASID = env->CP0_EntryHi & 0xFF;
440 for (i = 0; i < env->tlb->nb_tlb; i++) {
441 tlb = &env->tlb->mmu.r4k.tlb[i];
442 /* 1k pages are not supported. */
443 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
444 tag = env->CP0_EntryHi & ~mask;
445 VPN = tlb->VPN & ~mask;
446 /* Check ASID, virtual page number & size */
447 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
453 if (i == env->tlb->nb_tlb) {
454 /* No match. Discard any shadow entries, if any of them match. */
455 for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
456 tlb = &env->tlb->mmu.r4k.tlb[i];
457 /* 1k pages are not supported. */
458 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
459 tag = env->CP0_EntryHi & ~mask;
460 VPN = tlb->VPN & ~mask;
461 /* Check ASID, virtual page number & size */
462 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
463 r4k_mips_tlb_flush_extra (env, i);
468 env->CP0_Index |= 0x80000000;
472 void r4k_do_tlbr (void)
477 ASID = env->CP0_EntryHi & 0xFF;
478 tlb = &env->tlb->mmu.r4k.tlb[env->CP0_Index % env->tlb->nb_tlb];
480 /* If this will change the current ASID, flush qemu's TLB. */
481 if (ASID != tlb->ASID)
482 cpu_mips_tlb_flush (env, 1);
484 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
486 env->CP0_EntryHi = tlb->VPN | tlb->ASID;
487 env->CP0_PageMask = tlb->PageMask;
488 env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
489 (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
490 env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
491 (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
494 #endif /* !CONFIG_USER_ONLY */
496 void dump_ldst (const unsigned char *func)
499 fprintf(logfile, "%s => " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__, T0, T1);
505 fprintf(logfile, "%s " TARGET_FMT_lx " at " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", __func__,
506 T1, T0, env->CP0_LLAddr);
510 void debug_pre_eret (void)
512 fprintf(logfile, "ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
513 env->PC[env->current_tc], env->CP0_EPC);
514 if (env->CP0_Status & (1 << CP0St_ERL))
515 fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
516 if (env->hflags & MIPS_HFLAG_DM)
517 fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
518 fputs("\n", logfile);
521 void debug_post_eret (void)
523 fprintf(logfile, " => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
524 env->PC[env->current_tc], env->CP0_EPC);
525 if (env->CP0_Status & (1 << CP0St_ERL))
526 fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
527 if (env->hflags & MIPS_HFLAG_DM)
528 fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
529 switch (env->hflags & MIPS_HFLAG_KSU) {
530 case MIPS_HFLAG_UM: fputs(", UM\n", logfile); break;
531 case MIPS_HFLAG_SM: fputs(", SM\n", logfile); break;
532 case MIPS_HFLAG_KM: fputs("\n", logfile); break;
533 default: cpu_abort(env, "Invalid MMU mode!\n"); break;
537 void do_pmon (int function)
541 case 2: /* TODO: char inbyte(int waitflag); */
542 if (env->gpr[4][env->current_tc] == 0)
543 env->gpr[2][env->current_tc] = -1;
545 case 11: /* TODO: char inbyte (void); */
546 env->gpr[2][env->current_tc] = -1;
550 printf("%c", (char)(env->gpr[4][env->current_tc] & 0xFF));
556 unsigned char *fmt = (void *)(unsigned long)env->gpr[4][env->current_tc];
563 #if !defined(CONFIG_USER_ONLY)
565 static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr);
567 #define MMUSUFFIX _mmu
571 #include "softmmu_template.h"
574 #include "softmmu_template.h"
577 #include "softmmu_template.h"
580 #include "softmmu_template.h"
582 static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr)
584 env->CP0_BadVAddr = addr;
585 do_restore_state (retaddr);
586 do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
589 void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
591 TranslationBlock *tb;
596 /* XXX: hack to restore env in all cases, even if not called from
599 env = cpu_single_env;
600 ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
603 /* now we have a real cpu fault */
604 pc = (unsigned long)retaddr;
607 /* the PC is inside the translated code. It means that we have
608 a virtual CPU fault */
609 cpu_restore_state(tb, env, pc, NULL);
612 do_raise_exception_err(env->exception_index, env->error_code);
617 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
621 do_raise_exception(EXCP_IBE);
623 do_raise_exception(EXCP_DBE);
627 /* Complex FPU operations which may need stack space. */
629 #define FLOAT_ONE32 (0x3f8 << 20)
630 #define FLOAT_ONE64 (0x3ffULL << 52)
631 #define FLOAT_TWO32 (1 << 30)
632 #define FLOAT_TWO64 (1ULL << 62)
633 #define FLOAT_QNAN32 0x7fbfffff
634 #define FLOAT_QNAN64 0x7ff7ffffffffffffULL
635 #define FLOAT_SNAN32 0x7fffffff
636 #define FLOAT_SNAN64 0x7fffffffffffffffULL
638 /* convert MIPS rounding mode in FCR31 to IEEE library */
639 unsigned int ieee_rm[] = {
640 float_round_nearest_even,
646 #define RESTORE_ROUNDING_MODE \
647 set_float_rounding_mode(ieee_rm[env->fpu->fcr31 & 3], &env->fpu->fp_status)
649 void do_cfc1 (int reg)
653 T0 = (int32_t)env->fpu->fcr0;
656 T0 = ((env->fpu->fcr31 >> 24) & 0xfe) | ((env->fpu->fcr31 >> 23) & 0x1);
659 T0 = env->fpu->fcr31 & 0x0003f07c;
662 T0 = (env->fpu->fcr31 & 0x00000f83) | ((env->fpu->fcr31 >> 22) & 0x4);
665 T0 = (int32_t)env->fpu->fcr31;
670 void do_ctc1 (int reg)
676 env->fpu->fcr31 = (env->fpu->fcr31 & 0x017fffff) | ((T0 & 0xfe) << 24) |
682 env->fpu->fcr31 = (env->fpu->fcr31 & 0xfffc0f83) | (T0 & 0x0003f07c);
687 env->fpu->fcr31 = (env->fpu->fcr31 & 0xfefff07c) | (T0 & 0x00000f83) |
693 env->fpu->fcr31 = T0;
698 /* set rounding mode */
699 RESTORE_ROUNDING_MODE;
700 set_float_exception_flags(0, &env->fpu->fp_status);
701 if ((GET_FP_ENABLE(env->fpu->fcr31) | 0x20) & GET_FP_CAUSE(env->fpu->fcr31))
702 do_raise_exception(EXCP_FPE);
705 static always_inline char ieee_ex_to_mips(char xcpt)
707 return (xcpt & float_flag_inexact) >> 5 |
708 (xcpt & float_flag_underflow) >> 3 |
709 (xcpt & float_flag_overflow) >> 1 |
710 (xcpt & float_flag_divbyzero) << 1 |
711 (xcpt & float_flag_invalid) << 4;
714 static always_inline char mips_ex_to_ieee(char xcpt)
716 return (xcpt & FP_INEXACT) << 5 |
717 (xcpt & FP_UNDERFLOW) << 3 |
718 (xcpt & FP_OVERFLOW) << 1 |
719 (xcpt & FP_DIV0) >> 1 |
720 (xcpt & FP_INVALID) >> 4;
723 static always_inline void update_fcr31(void)
725 int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->fpu->fp_status));
727 SET_FP_CAUSE(env->fpu->fcr31, tmp);
728 if (GET_FP_ENABLE(env->fpu->fcr31) & tmp)
729 do_raise_exception(EXCP_FPE);
731 UPDATE_FP_FLAGS(env->fpu->fcr31, tmp);
734 #define FLOAT_OP(name, p) void do_float_##name##_##p(void)
738 set_float_exception_flags(0, &env->fpu->fp_status);
739 FDT2 = float32_to_float64(FST0, &env->fpu->fp_status);
744 set_float_exception_flags(0, &env->fpu->fp_status);
745 FDT2 = int32_to_float64(WT0, &env->fpu->fp_status);
750 set_float_exception_flags(0, &env->fpu->fp_status);
751 FDT2 = int64_to_float64(DT0, &env->fpu->fp_status);
756 set_float_exception_flags(0, &env->fpu->fp_status);
757 DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
759 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
764 set_float_exception_flags(0, &env->fpu->fp_status);
765 DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
767 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
773 set_float_exception_flags(0, &env->fpu->fp_status);
774 FST2 = int32_to_float32(WT0, &env->fpu->fp_status);
775 FSTH2 = int32_to_float32(WTH0, &env->fpu->fp_status);
780 set_float_exception_flags(0, &env->fpu->fp_status);
781 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
782 WTH2 = float32_to_int32(FSTH0, &env->fpu->fp_status);
784 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
789 set_float_exception_flags(0, &env->fpu->fp_status);
790 FST2 = float64_to_float32(FDT0, &env->fpu->fp_status);
795 set_float_exception_flags(0, &env->fpu->fp_status);
796 FST2 = int32_to_float32(WT0, &env->fpu->fp_status);
801 set_float_exception_flags(0, &env->fpu->fp_status);
802 FST2 = int64_to_float32(DT0, &env->fpu->fp_status);
807 set_float_exception_flags(0, &env->fpu->fp_status);
813 set_float_exception_flags(0, &env->fpu->fp_status);
819 set_float_exception_flags(0, &env->fpu->fp_status);
820 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
822 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
827 set_float_exception_flags(0, &env->fpu->fp_status);
828 WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
830 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
836 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
837 DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
838 RESTORE_ROUNDING_MODE;
840 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
845 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
846 DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
847 RESTORE_ROUNDING_MODE;
849 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
854 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
855 WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
856 RESTORE_ROUNDING_MODE;
858 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
863 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
864 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
865 RESTORE_ROUNDING_MODE;
867 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
873 DT2 = float64_to_int64_round_to_zero(FDT0, &env->fpu->fp_status);
875 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
880 DT2 = float32_to_int64_round_to_zero(FST0, &env->fpu->fp_status);
882 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
887 WT2 = float64_to_int32_round_to_zero(FDT0, &env->fpu->fp_status);
889 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
894 WT2 = float32_to_int32_round_to_zero(FST0, &env->fpu->fp_status);
896 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
902 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
903 DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
904 RESTORE_ROUNDING_MODE;
906 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
911 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
912 DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
913 RESTORE_ROUNDING_MODE;
915 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
920 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
921 WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
922 RESTORE_ROUNDING_MODE;
924 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
929 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
930 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
931 RESTORE_ROUNDING_MODE;
933 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
939 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
940 DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
941 RESTORE_ROUNDING_MODE;
943 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
948 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
949 DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
950 RESTORE_ROUNDING_MODE;
952 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
957 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
958 WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
959 RESTORE_ROUNDING_MODE;
961 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
966 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
967 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
968 RESTORE_ROUNDING_MODE;
970 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
974 /* MIPS specific unary operations */
977 set_float_exception_flags(0, &env->fpu->fp_status);
978 FDT2 = float64_div(FLOAT_ONE64, FDT0, &env->fpu->fp_status);
983 set_float_exception_flags(0, &env->fpu->fp_status);
984 FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status);
990 set_float_exception_flags(0, &env->fpu->fp_status);
991 FDT2 = float64_sqrt(FDT0, &env->fpu->fp_status);
992 FDT2 = float64_div(FLOAT_ONE64, FDT2, &env->fpu->fp_status);
997 set_float_exception_flags(0, &env->fpu->fp_status);
998 FST2 = float32_sqrt(FST0, &env->fpu->fp_status);
999 FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status);
1005 set_float_exception_flags(0, &env->fpu->fp_status);
1006 FDT2 = float64_div(FLOAT_ONE64, FDT0, &env->fpu->fp_status);
1011 set_float_exception_flags(0, &env->fpu->fp_status);
1012 FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status);
1015 FLOAT_OP(recip1, ps)
1017 set_float_exception_flags(0, &env->fpu->fp_status);
1018 FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status);
1019 FSTH2 = float32_div(FLOAT_ONE32, FSTH0, &env->fpu->fp_status);
1025 set_float_exception_flags(0, &env->fpu->fp_status);
1026 FDT2 = float64_sqrt(FDT0, &env->fpu->fp_status);
1027 FDT2 = float64_div(FLOAT_ONE64, FDT2, &env->fpu->fp_status);
1032 set_float_exception_flags(0, &env->fpu->fp_status);
1033 FST2 = float32_sqrt(FST0, &env->fpu->fp_status);
1034 FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status);
1037 FLOAT_OP(rsqrt1, ps)
1039 set_float_exception_flags(0, &env->fpu->fp_status);
1040 FST2 = float32_sqrt(FST0, &env->fpu->fp_status);
1041 FSTH2 = float32_sqrt(FSTH0, &env->fpu->fp_status);
1042 FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status);
1043 FSTH2 = float32_div(FLOAT_ONE32, FSTH2, &env->fpu->fp_status);
1047 /* binary operations */
1048 #define FLOAT_BINOP(name) \
1051 set_float_exception_flags(0, &env->fpu->fp_status); \
1052 FDT2 = float64_ ## name (FDT0, FDT1, &env->fpu->fp_status); \
1054 if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \
1055 DT2 = FLOAT_QNAN64; \
1059 set_float_exception_flags(0, &env->fpu->fp_status); \
1060 FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status); \
1062 if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \
1063 WT2 = FLOAT_QNAN32; \
1065 FLOAT_OP(name, ps) \
1067 set_float_exception_flags(0, &env->fpu->fp_status); \
1068 FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status); \
1069 FSTH2 = float32_ ## name (FSTH0, FSTH1, &env->fpu->fp_status); \
1071 if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) { \
1072 WT2 = FLOAT_QNAN32; \
1073 WTH2 = FLOAT_QNAN32; \
1082 /* MIPS specific binary operations */
1085 set_float_exception_flags(0, &env->fpu->fp_status);
1086 FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status);
1087 FDT2 = float64_chs(float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status));
1092 set_float_exception_flags(0, &env->fpu->fp_status);
1093 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
1094 FST2 = float32_chs(float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status));
1097 FLOAT_OP(recip2, ps)
1099 set_float_exception_flags(0, &env->fpu->fp_status);
1100 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
1101 FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status);
1102 FST2 = float32_chs(float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status));
1103 FSTH2 = float32_chs(float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status));
1109 set_float_exception_flags(0, &env->fpu->fp_status);
1110 FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status);
1111 FDT2 = float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status);
1112 FDT2 = float64_chs(float64_div(FDT2, FLOAT_TWO64, &env->fpu->fp_status));
1117 set_float_exception_flags(0, &env->fpu->fp_status);
1118 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
1119 FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status);
1120 FST2 = float32_chs(float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status));
1123 FLOAT_OP(rsqrt2, ps)
1125 set_float_exception_flags(0, &env->fpu->fp_status);
1126 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
1127 FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status);
1128 FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status);
1129 FSTH2 = float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status);
1130 FST2 = float32_chs(float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status));
1131 FSTH2 = float32_chs(float32_div(FSTH2, FLOAT_TWO32, &env->fpu->fp_status));
1137 set_float_exception_flags(0, &env->fpu->fp_status);
1138 FST2 = float32_add (FST0, FSTH0, &env->fpu->fp_status);
1139 FSTH2 = float32_add (FST1, FSTH1, &env->fpu->fp_status);
1145 set_float_exception_flags(0, &env->fpu->fp_status);
1146 FST2 = float32_mul (FST0, FSTH0, &env->fpu->fp_status);
1147 FSTH2 = float32_mul (FST1, FSTH1, &env->fpu->fp_status);
1151 /* compare operations */
1152 #define FOP_COND_D(op, cond) \
1153 void do_cmp_d_ ## op (long cc) \
1158 SET_FP_COND(cc, env->fpu); \
1160 CLEAR_FP_COND(cc, env->fpu); \
1162 void do_cmpabs_d_ ## op (long cc) \
1165 FDT0 = float64_chs(FDT0); \
1166 FDT1 = float64_chs(FDT1); \
1170 SET_FP_COND(cc, env->fpu); \
1172 CLEAR_FP_COND(cc, env->fpu); \
1175 int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM)
1177 if (float64_is_signaling_nan(a) ||
1178 float64_is_signaling_nan(b) ||
1179 (sig && (float64_is_nan(a) || float64_is_nan(b)))) {
1180 float_raise(float_flag_invalid, status);
1182 } else if (float64_is_nan(a) || float64_is_nan(b)) {
1189 /* NOTE: the comma operator will make "cond" to eval to false,
1190 * but float*_is_unordered() is still called. */
1191 FOP_COND_D(f, (float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status), 0))
1192 FOP_COND_D(un, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status))
1193 FOP_COND_D(eq, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_eq(FDT0, FDT1, &env->fpu->fp_status))
1194 FOP_COND_D(ueq, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_eq(FDT0, FDT1, &env->fpu->fp_status))
1195 FOP_COND_D(olt, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_lt(FDT0, FDT1, &env->fpu->fp_status))
1196 FOP_COND_D(ult, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_lt(FDT0, FDT1, &env->fpu->fp_status))
1197 FOP_COND_D(ole, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_le(FDT0, FDT1, &env->fpu->fp_status))
1198 FOP_COND_D(ule, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_le(FDT0, FDT1, &env->fpu->fp_status))
1199 /* NOTE: the comma operator will make "cond" to eval to false,
1200 * but float*_is_unordered() is still called. */
1201 FOP_COND_D(sf, (float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status), 0))
1202 FOP_COND_D(ngle,float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status))
1203 FOP_COND_D(seq, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_eq(FDT0, FDT1, &env->fpu->fp_status))
1204 FOP_COND_D(ngl, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_eq(FDT0, FDT1, &env->fpu->fp_status))
1205 FOP_COND_D(lt, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_lt(FDT0, FDT1, &env->fpu->fp_status))
1206 FOP_COND_D(nge, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_lt(FDT0, FDT1, &env->fpu->fp_status))
1207 FOP_COND_D(le, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_le(FDT0, FDT1, &env->fpu->fp_status))
1208 FOP_COND_D(ngt, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_le(FDT0, FDT1, &env->fpu->fp_status))
1210 #define FOP_COND_S(op, cond) \
1211 void do_cmp_s_ ## op (long cc) \
1216 SET_FP_COND(cc, env->fpu); \
1218 CLEAR_FP_COND(cc, env->fpu); \
1220 void do_cmpabs_s_ ## op (long cc) \
1223 FST0 = float32_abs(FST0); \
1224 FST1 = float32_abs(FST1); \
1228 SET_FP_COND(cc, env->fpu); \
1230 CLEAR_FP_COND(cc, env->fpu); \
1233 flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM)
1235 if (float32_is_signaling_nan(a) ||
1236 float32_is_signaling_nan(b) ||
1237 (sig && (float32_is_nan(a) || float32_is_nan(b)))) {
1238 float_raise(float_flag_invalid, status);
1240 } else if (float32_is_nan(a) || float32_is_nan(b)) {
1247 /* NOTE: the comma operator will make "cond" to eval to false,
1248 * but float*_is_unordered() is still called. */
1249 FOP_COND_S(f, (float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status), 0))
1250 FOP_COND_S(un, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status))
1251 FOP_COND_S(eq, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status))
1252 FOP_COND_S(ueq, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status))
1253 FOP_COND_S(olt, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status))
1254 FOP_COND_S(ult, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status))
1255 FOP_COND_S(ole, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status))
1256 FOP_COND_S(ule, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status))
1257 /* NOTE: the comma operator will make "cond" to eval to false,
1258 * but float*_is_unordered() is still called. */
1259 FOP_COND_S(sf, (float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status), 0))
1260 FOP_COND_S(ngle,float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status))
1261 FOP_COND_S(seq, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status))
1262 FOP_COND_S(ngl, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status))
1263 FOP_COND_S(lt, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status))
1264 FOP_COND_S(nge, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status))
1265 FOP_COND_S(le, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status))
1266 FOP_COND_S(ngt, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status))
1268 #define FOP_COND_PS(op, condl, condh) \
1269 void do_cmp_ps_ ## op (long cc) \
1275 SET_FP_COND(cc, env->fpu); \
1277 CLEAR_FP_COND(cc, env->fpu); \
1279 SET_FP_COND(cc + 1, env->fpu); \
1281 CLEAR_FP_COND(cc + 1, env->fpu); \
1283 void do_cmpabs_ps_ ## op (long cc) \
1286 FST0 = float32_abs(FST0); \
1287 FSTH0 = float32_abs(FSTH0); \
1288 FST1 = float32_abs(FST1); \
1289 FSTH1 = float32_abs(FSTH1); \
1294 SET_FP_COND(cc, env->fpu); \
1296 CLEAR_FP_COND(cc, env->fpu); \
1298 SET_FP_COND(cc + 1, env->fpu); \
1300 CLEAR_FP_COND(cc + 1, env->fpu); \
1303 /* NOTE: the comma operator will make "cond" to eval to false,
1304 * but float*_is_unordered() is still called. */
1305 FOP_COND_PS(f, (float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status), 0),
1306 (float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status), 0))
1307 FOP_COND_PS(un, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status),
1308 float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status))
1309 FOP_COND_PS(eq, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status),
1310 !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
1311 FOP_COND_PS(ueq, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status),
1312 float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
1313 FOP_COND_PS(olt, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status),
1314 !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
1315 FOP_COND_PS(ult, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status),
1316 float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
1317 FOP_COND_PS(ole, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status),
1318 !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
1319 FOP_COND_PS(ule, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status),
1320 float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
1321 /* NOTE: the comma operator will make "cond" to eval to false,
1322 * but float*_is_unordered() is still called. */
1323 FOP_COND_PS(sf, (float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status), 0),
1324 (float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status), 0))
1325 FOP_COND_PS(ngle,float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status),
1326 float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status))
1327 FOP_COND_PS(seq, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status),
1328 !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
1329 FOP_COND_PS(ngl, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status),
1330 float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
1331 FOP_COND_PS(lt, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status),
1332 !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
1333 FOP_COND_PS(nge, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status),
1334 float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
1335 FOP_COND_PS(le, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status),
1336 !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
1337 FOP_COND_PS(ngt, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status),
1338 float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_le(FSTH0, FSTH1, &env->fpu->fp_status))