2 * MIPS emulation helpers for qemu.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #define GETPC() (__builtin_return_address(0))
25 /*****************************************************************************/
26 /* Exceptions processing helpers */
28 void do_raise_exception_err (uint32_t exception, int error_code)
31 if (logfile && exception < 0x100)
32 fprintf(logfile, "%s: %d %d\n", __func__, exception, error_code);
34 env->exception_index = exception;
35 env->error_code = error_code;
40 void do_raise_exception (uint32_t exception)
42 do_raise_exception_err(exception, 0);
45 void do_restore_state (void *pc_ptr)
48 unsigned long pc = (unsigned long) pc_ptr;
51 cpu_restore_state (tb, env, pc, NULL);
54 void do_raise_exception_direct_err (uint32_t exception, int error_code)
56 do_restore_state (GETPC ());
57 do_raise_exception_err (exception, error_code);
60 void do_raise_exception_direct (uint32_t exception)
62 do_raise_exception_direct_err (exception, 0);
65 #define MEMSUFFIX _raw
66 #include "op_helper_mem.c"
68 #if !defined(CONFIG_USER_ONLY)
69 #define MEMSUFFIX _user
70 #include "op_helper_mem.c"
72 #define MEMSUFFIX _kernel
73 #include "op_helper_mem.c"
78 #if TARGET_LONG_BITS > HOST_LONG_BITS
79 /* Those might call libgcc functions. */
92 T0 = (int64_t)T0 >> T1;
97 T0 = (int64_t)T0 >> (T1 + 32);
105 void do_dsrl32 (void)
107 T0 = T0 >> (T1 + 32);
115 tmp = T0 << (0x40 - T1);
116 T0 = (T0 >> T1) | tmp;
120 void do_drotr32 (void)
125 tmp = T0 << (0x40 - (32 + T1));
126 T0 = (T0 >> (32 + T1)) | tmp;
132 T0 = T1 << (T0 & 0x3F);
137 T0 = (int64_t)T1 >> (T0 & 0x3F);
142 T0 = T1 >> (T0 & 0x3F);
145 void do_drotrv (void)
151 tmp = T1 << (0x40 - T0);
152 T0 = (T1 >> T0) | tmp;
156 #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
157 #endif /* TARGET_MIPS64 */
159 /* 64 bits arithmetic for 32 bits hosts */
160 #if TARGET_LONG_BITS > HOST_LONG_BITS
161 static inline uint64_t get_HILO (void)
163 return (env->HI[0][env->current_tc] << 32) | (uint32_t)env->LO[0][env->current_tc];
166 static inline void set_HILO (uint64_t HILO)
168 env->LO[0][env->current_tc] = (int32_t)HILO;
169 env->HI[0][env->current_tc] = (int32_t)(HILO >> 32);
174 set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
179 set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
186 tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
187 set_HILO((int64_t)get_HILO() + tmp);
194 tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
195 set_HILO(get_HILO() + tmp);
202 tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
203 set_HILO((int64_t)get_HILO() - tmp);
210 tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
211 set_HILO(get_HILO() - tmp);
215 #if HOST_LONG_BITS < 64
218 /* 64bit datatypes because we may see overflow/underflow. */
220 env->LO[0][env->current_tc] = (int32_t)((int64_t)(int32_t)T0 / (int32_t)T1);
221 env->HI[0][env->current_tc] = (int32_t)((int64_t)(int32_t)T0 % (int32_t)T1);
230 lldiv_t res = lldiv((int64_t)T0, (int64_t)T1);
231 env->LO[0][env->current_tc] = res.quot;
232 env->HI[0][env->current_tc] = res.rem;
236 #if TARGET_LONG_BITS > HOST_LONG_BITS
240 env->LO[0][env->current_tc] = T0 / T1;
241 env->HI[0][env->current_tc] = T0 % T1;
245 #endif /* TARGET_MIPS64 */
247 #if defined(CONFIG_USER_ONLY)
248 void do_mfc0_random (void)
250 cpu_abort(env, "mfc0 random\n");
253 void do_mfc0_count (void)
255 cpu_abort(env, "mfc0 count\n");
258 void cpu_mips_store_count(CPUState *env, uint32_t value)
260 cpu_abort(env, "mtc0 count\n");
263 void cpu_mips_store_compare(CPUState *env, uint32_t value)
265 cpu_abort(env, "mtc0 compare\n");
268 void cpu_mips_update_irq(CPUState *env)
270 cpu_abort(env, "mtc0 status / mtc0 cause\n");
273 void do_mtc0_status_debug(uint32_t old, uint32_t val)
275 cpu_abort(env, "mtc0 status debug\n");
278 void do_mtc0_status_irqraise_debug (void)
280 cpu_abort(env, "mtc0 status irqraise debug\n");
283 void cpu_mips_tlb_flush (CPUState *env, int flush_global)
285 cpu_abort(env, "mips_tlb_flush\n");
291 void do_mfc0_random (void)
293 T0 = (int32_t)cpu_mips_get_random(env);
296 void do_mfc0_count (void)
298 T0 = (int32_t)cpu_mips_get_count(env);
301 void do_mtc0_status_debug(uint32_t old, uint32_t val)
303 fprintf(logfile, "Status %08x (%08x) => %08x (%08x) Cause %08x",
304 old, old & env->CP0_Cause & CP0Ca_IP_mask,
305 val, val & env->CP0_Cause & CP0Ca_IP_mask,
307 (env->hflags & MIPS_HFLAG_UM) ? fputs(", UM\n", logfile)
308 : fputs("\n", logfile);
311 void do_mtc0_status_irqraise_debug(void)
313 fprintf(logfile, "Raise pending IRQs\n");
316 void fpu_handle_exception(void)
318 #ifdef CONFIG_SOFTFLOAT
319 int flags = get_float_exception_flags(&env->fpu->fp_status);
320 unsigned int cpuflags = 0, enable, cause = 0;
322 enable = GET_FP_ENABLE(env->fpu->fcr31);
324 /* determine current flags */
325 if (flags & float_flag_invalid) {
326 cpuflags |= FP_INVALID;
327 cause |= FP_INVALID & enable;
329 if (flags & float_flag_divbyzero) {
331 cause |= FP_DIV0 & enable;
333 if (flags & float_flag_overflow) {
334 cpuflags |= FP_OVERFLOW;
335 cause |= FP_OVERFLOW & enable;
337 if (flags & float_flag_underflow) {
338 cpuflags |= FP_UNDERFLOW;
339 cause |= FP_UNDERFLOW & enable;
341 if (flags & float_flag_inexact) {
342 cpuflags |= FP_INEXACT;
343 cause |= FP_INEXACT & enable;
345 SET_FP_FLAGS(env->fpu->fcr31, cpuflags);
346 SET_FP_CAUSE(env->fpu->fcr31, cause);
348 SET_FP_FLAGS(env->fpu->fcr31, 0);
349 SET_FP_CAUSE(env->fpu->fcr31, 0);
354 void cpu_mips_tlb_flush (CPUState *env, int flush_global)
356 /* Flush qemu's TLB and discard all shadowed entries. */
357 tlb_flush (env, flush_global);
358 env->tlb->tlb_in_use = env->tlb->nb_tlb;
361 static void r4k_mips_tlb_flush_extra (CPUState *env, int first)
363 /* Discard entries from env->tlb[first] onwards. */
364 while (env->tlb->tlb_in_use > first) {
365 r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
369 static void r4k_fill_tlb (int idx)
373 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
374 tlb = &env->tlb->mmu.r4k.tlb[idx];
375 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
377 tlb->VPN &= env->SEGMask;
379 tlb->ASID = env->CP0_EntryHi & 0xFF;
380 tlb->PageMask = env->CP0_PageMask;
381 tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
382 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
383 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
384 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
385 tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
386 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
387 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
388 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
389 tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
392 void r4k_do_tlbwi (void)
394 /* Discard cached TLB entries. We could avoid doing this if the
395 tlbwi is just upgrading access permissions on the current entry;
396 that might be a further win. */
397 r4k_mips_tlb_flush_extra (env, env->tlb->nb_tlb);
399 r4k_invalidate_tlb(env, env->CP0_Index % env->tlb->nb_tlb, 0);
400 r4k_fill_tlb(env->CP0_Index % env->tlb->nb_tlb);
403 void r4k_do_tlbwr (void)
405 int r = cpu_mips_get_random(env);
407 r4k_invalidate_tlb(env, r, 1);
411 void r4k_do_tlbp (void)
420 ASID = env->CP0_EntryHi & 0xFF;
421 for (i = 0; i < env->tlb->nb_tlb; i++) {
422 tlb = &env->tlb->mmu.r4k.tlb[i];
423 /* 1k pages are not supported. */
424 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
425 tag = env->CP0_EntryHi & ~mask;
426 VPN = tlb->VPN & ~mask;
427 /* Check ASID, virtual page number & size */
428 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
434 if (i == env->tlb->nb_tlb) {
435 /* No match. Discard any shadow entries, if any of them match. */
436 for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
437 tlb = &env->tlb->mmu.r4k.tlb[i];
438 /* 1k pages are not supported. */
439 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
440 tag = env->CP0_EntryHi & ~mask;
441 VPN = tlb->VPN & ~mask;
442 /* Check ASID, virtual page number & size */
443 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
444 r4k_mips_tlb_flush_extra (env, i);
449 env->CP0_Index |= 0x80000000;
453 void r4k_do_tlbr (void)
458 ASID = env->CP0_EntryHi & 0xFF;
459 tlb = &env->tlb->mmu.r4k.tlb[env->CP0_Index % env->tlb->nb_tlb];
461 /* If this will change the current ASID, flush qemu's TLB. */
462 if (ASID != tlb->ASID)
463 cpu_mips_tlb_flush (env, 1);
465 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
467 env->CP0_EntryHi = tlb->VPN | tlb->ASID;
468 env->CP0_PageMask = tlb->PageMask;
469 env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
470 (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
471 env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
472 (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
475 #endif /* !CONFIG_USER_ONLY */
477 void dump_ldst (const unsigned char *func)
480 fprintf(logfile, "%s => " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__, T0, T1);
486 fprintf(logfile, "%s " TARGET_FMT_lx " at " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", __func__,
487 T1, T0, env->CP0_LLAddr);
491 void debug_pre_eret (void)
493 fprintf(logfile, "ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
494 env->PC[env->current_tc], env->CP0_EPC);
495 if (env->CP0_Status & (1 << CP0St_ERL))
496 fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
497 if (env->hflags & MIPS_HFLAG_DM)
498 fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
499 fputs("\n", logfile);
502 void debug_post_eret (void)
504 fprintf(logfile, " => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
505 env->PC[env->current_tc], env->CP0_EPC);
506 if (env->CP0_Status & (1 << CP0St_ERL))
507 fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
508 if (env->hflags & MIPS_HFLAG_DM)
509 fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
510 if (env->hflags & MIPS_HFLAG_UM)
511 fputs(", UM\n", logfile);
513 fputs("\n", logfile);
516 void do_pmon (int function)
520 case 2: /* TODO: char inbyte(int waitflag); */
521 if (env->gpr[4][env->current_tc] == 0)
522 env->gpr[2][env->current_tc] = -1;
524 case 11: /* TODO: char inbyte (void); */
525 env->gpr[2][env->current_tc] = -1;
529 printf("%c", (char)(env->gpr[4][env->current_tc] & 0xFF));
535 unsigned char *fmt = (void *)(unsigned long)env->gpr[4][env->current_tc];
542 #if !defined(CONFIG_USER_ONLY)
544 static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr);
546 #define MMUSUFFIX _mmu
550 #include "softmmu_template.h"
553 #include "softmmu_template.h"
556 #include "softmmu_template.h"
559 #include "softmmu_template.h"
561 static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr)
563 env->CP0_BadVAddr = addr;
564 do_restore_state (retaddr);
565 do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
568 void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr)
570 TranslationBlock *tb;
575 /* XXX: hack to restore env in all cases, even if not called from
578 env = cpu_single_env;
579 ret = cpu_mips_handle_mmu_fault(env, addr, is_write, is_user, 1);
582 /* now we have a real cpu fault */
583 pc = (unsigned long)retaddr;
586 /* the PC is inside the translated code. It means that we have
587 a virtual CPU fault */
588 cpu_restore_state(tb, env, pc, NULL);
591 do_raise_exception_err(env->exception_index, env->error_code);
598 /* Complex FPU operations which may need stack space. */
600 #define FLOAT_SIGN32 (1 << 31)
601 #define FLOAT_SIGN64 (1ULL << 63)
602 #define FLOAT_ONE32 (0x3f8 << 20)
603 #define FLOAT_ONE64 (0x3ffULL << 52)
604 #define FLOAT_TWO32 (1 << 30)
605 #define FLOAT_TWO64 (1ULL << 62)
607 /* convert MIPS rounding mode in FCR31 to IEEE library */
608 unsigned int ieee_rm[] = {
609 float_round_nearest_even,
615 #define RESTORE_ROUNDING_MODE \
616 set_float_rounding_mode(ieee_rm[env->fpu->fcr31 & 3], &env->fpu->fp_status)
618 void do_cfc1 (int reg)
622 T0 = (int32_t)env->fpu->fcr0;
625 T0 = ((env->fpu->fcr31 >> 24) & 0xfe) | ((env->fpu->fcr31 >> 23) & 0x1);
628 T0 = env->fpu->fcr31 & 0x0003f07c;
631 T0 = (env->fpu->fcr31 & 0x00000f83) | ((env->fpu->fcr31 >> 22) & 0x4);
634 T0 = (int32_t)env->fpu->fcr31;
639 void do_ctc1 (int reg)
645 env->fpu->fcr31 = (env->fpu->fcr31 & 0x017fffff) | ((T0 & 0xfe) << 24) |
651 env->fpu->fcr31 = (env->fpu->fcr31 & 0xfffc0f83) | (T0 & 0x0003f07c);
656 env->fpu->fcr31 = (env->fpu->fcr31 & 0xfefff07c) | (T0 & 0x00000f83) |
662 env->fpu->fcr31 = T0;
667 /* set rounding mode */
668 RESTORE_ROUNDING_MODE;
669 set_float_exception_flags(0, &env->fpu->fp_status);
670 if ((GET_FP_ENABLE(env->fpu->fcr31) | 0x20) & GET_FP_CAUSE(env->fpu->fcr31))
671 do_raise_exception(EXCP_FPE);
674 inline char ieee_ex_to_mips(char xcpt)
676 return (xcpt & float_flag_inexact) >> 5 |
677 (xcpt & float_flag_underflow) >> 3 |
678 (xcpt & float_flag_overflow) >> 1 |
679 (xcpt & float_flag_divbyzero) << 1 |
680 (xcpt & float_flag_invalid) << 4;
683 inline char mips_ex_to_ieee(char xcpt)
685 return (xcpt & FP_INEXACT) << 5 |
686 (xcpt & FP_UNDERFLOW) << 3 |
687 (xcpt & FP_OVERFLOW) << 1 |
688 (xcpt & FP_DIV0) >> 1 |
689 (xcpt & FP_INVALID) >> 4;
692 inline void update_fcr31(void)
694 int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->fpu->fp_status));
696 SET_FP_CAUSE(env->fpu->fcr31, tmp);
697 if (GET_FP_ENABLE(env->fpu->fcr31) & tmp)
698 do_raise_exception(EXCP_FPE);
700 UPDATE_FP_FLAGS(env->fpu->fcr31, tmp);
703 #define FLOAT_OP(name, p) void do_float_##name##_##p(void)
707 set_float_exception_flags(0, &env->fpu->fp_status);
708 FDT2 = float32_to_float64(FST0, &env->fpu->fp_status);
713 set_float_exception_flags(0, &env->fpu->fp_status);
714 FDT2 = int32_to_float64(WT0, &env->fpu->fp_status);
719 set_float_exception_flags(0, &env->fpu->fp_status);
720 FDT2 = int64_to_float64(DT0, &env->fpu->fp_status);
725 set_float_exception_flags(0, &env->fpu->fp_status);
726 DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
728 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
729 DT2 = 0x7fffffffffffffffULL;
733 set_float_exception_flags(0, &env->fpu->fp_status);
734 DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
736 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
737 DT2 = 0x7fffffffffffffffULL;
742 set_float_exception_flags(0, &env->fpu->fp_status);
743 FST2 = int32_to_float32(WT0, &env->fpu->fp_status);
744 FSTH2 = int32_to_float32(WTH0, &env->fpu->fp_status);
749 set_float_exception_flags(0, &env->fpu->fp_status);
750 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
751 WTH2 = float32_to_int32(FSTH0, &env->fpu->fp_status);
753 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
758 set_float_exception_flags(0, &env->fpu->fp_status);
759 FST2 = float64_to_float32(FDT0, &env->fpu->fp_status);
764 set_float_exception_flags(0, &env->fpu->fp_status);
765 FST2 = int32_to_float32(WT0, &env->fpu->fp_status);
770 set_float_exception_flags(0, &env->fpu->fp_status);
771 FST2 = int64_to_float32(DT0, &env->fpu->fp_status);
776 set_float_exception_flags(0, &env->fpu->fp_status);
782 set_float_exception_flags(0, &env->fpu->fp_status);
788 set_float_exception_flags(0, &env->fpu->fp_status);
789 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
791 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
796 set_float_exception_flags(0, &env->fpu->fp_status);
797 WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
799 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
805 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
806 DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
807 RESTORE_ROUNDING_MODE;
809 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
810 DT2 = 0x7fffffffffffffffULL;
814 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
815 DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
816 RESTORE_ROUNDING_MODE;
818 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
819 DT2 = 0x7fffffffffffffffULL;
823 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
824 WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
825 RESTORE_ROUNDING_MODE;
827 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
832 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
833 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
834 RESTORE_ROUNDING_MODE;
836 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
842 DT2 = float64_to_int64_round_to_zero(FDT0, &env->fpu->fp_status);
844 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
845 DT2 = 0x7fffffffffffffffULL;
849 DT2 = float32_to_int64_round_to_zero(FST0, &env->fpu->fp_status);
851 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
852 DT2 = 0x7fffffffffffffffULL;
856 WT2 = float64_to_int32_round_to_zero(FDT0, &env->fpu->fp_status);
858 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
863 WT2 = float32_to_int32_round_to_zero(FST0, &env->fpu->fp_status);
865 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
871 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
872 DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
873 RESTORE_ROUNDING_MODE;
875 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
876 DT2 = 0x7fffffffffffffffULL;
880 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
881 DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
882 RESTORE_ROUNDING_MODE;
884 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
885 DT2 = 0x7fffffffffffffffULL;
889 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
890 WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
891 RESTORE_ROUNDING_MODE;
893 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
898 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
899 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
900 RESTORE_ROUNDING_MODE;
902 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
908 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
909 DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
910 RESTORE_ROUNDING_MODE;
912 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
913 DT2 = 0x7fffffffffffffffULL;
917 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
918 DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
919 RESTORE_ROUNDING_MODE;
921 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
922 DT2 = 0x7fffffffffffffffULL;
926 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
927 WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
928 RESTORE_ROUNDING_MODE;
930 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
935 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
936 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
937 RESTORE_ROUNDING_MODE;
939 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
943 /* MIPS specific unary operations */
946 set_float_exception_flags(0, &env->fpu->fp_status);
947 FDT2 = float64_div(FLOAT_ONE64, FDT0, &env->fpu->fp_status);
952 set_float_exception_flags(0, &env->fpu->fp_status);
953 FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status);
959 set_float_exception_flags(0, &env->fpu->fp_status);
960 FDT2 = float64_sqrt(FDT0, &env->fpu->fp_status);
961 FDT2 = float64_div(FLOAT_ONE64, FDT2, &env->fpu->fp_status);
966 set_float_exception_flags(0, &env->fpu->fp_status);
967 FST2 = float32_sqrt(FST0, &env->fpu->fp_status);
968 FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status);
974 set_float_exception_flags(0, &env->fpu->fp_status);
975 FDT2 = float64_div(FLOAT_ONE64, FDT0, &env->fpu->fp_status);
980 set_float_exception_flags(0, &env->fpu->fp_status);
981 FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status);
986 set_float_exception_flags(0, &env->fpu->fp_status);
987 FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status);
988 FSTH2 = float32_div(FLOAT_ONE32, FSTH0, &env->fpu->fp_status);
994 set_float_exception_flags(0, &env->fpu->fp_status);
995 FDT2 = float64_sqrt(FDT0, &env->fpu->fp_status);
996 FDT2 = float64_div(FLOAT_ONE64, FDT2, &env->fpu->fp_status);
1001 set_float_exception_flags(0, &env->fpu->fp_status);
1002 FST2 = float32_sqrt(FST0, &env->fpu->fp_status);
1003 FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status);
1006 FLOAT_OP(rsqrt1, ps)
1008 set_float_exception_flags(0, &env->fpu->fp_status);
1009 FST2 = float32_sqrt(FST0, &env->fpu->fp_status);
1010 FSTH2 = float32_sqrt(FSTH0, &env->fpu->fp_status);
1011 FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status);
1012 FSTH2 = float32_div(FLOAT_ONE32, FSTH2, &env->fpu->fp_status);
1016 /* binary operations */
1017 #define FLOAT_BINOP(name) \
1020 set_float_exception_flags(0, &env->fpu->fp_status); \
1021 FDT2 = float64_ ## name (FDT0, FDT1, &env->fpu->fp_status); \
1023 if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \
1024 FDT2 = 0x7ff7ffffffffffffULL; \
1025 else if (GET_FP_CAUSE(env->fpu->fcr31) & FP_UNDERFLOW) { \
1026 if ((env->fpu->fcr31 & 0x3) == 0) \
1027 FDT2 &= FLOAT_SIGN64; \
1032 set_float_exception_flags(0, &env->fpu->fp_status); \
1033 FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status); \
1035 if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \
1036 FST2 = 0x7fbfffff; \
1037 else if (GET_FP_CAUSE(env->fpu->fcr31) & FP_UNDERFLOW) { \
1038 if ((env->fpu->fcr31 & 0x3) == 0) \
1039 FST2 &= FLOAT_SIGN32; \
1042 FLOAT_OP(name, ps) \
1044 set_float_exception_flags(0, &env->fpu->fp_status); \
1045 FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status); \
1046 FSTH2 = float32_ ## name (FSTH0, FSTH1, &env->fpu->fp_status); \
1048 if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) { \
1049 FST2 = 0x7fbfffff; \
1050 FSTH2 = 0x7fbfffff; \
1051 } else if (GET_FP_CAUSE(env->fpu->fcr31) & FP_UNDERFLOW) { \
1052 if ((env->fpu->fcr31 & 0x3) == 0) { \
1053 FST2 &= FLOAT_SIGN32; \
1054 FSTH2 &= FLOAT_SIGN32; \
1064 /* MIPS specific binary operations */
1067 set_float_exception_flags(0, &env->fpu->fp_status);
1068 FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status);
1069 FDT2 = float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status) ^ FLOAT_SIGN64;
1074 set_float_exception_flags(0, &env->fpu->fp_status);
1075 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
1076 FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
1079 FLOAT_OP(recip2, ps)
1081 set_float_exception_flags(0, &env->fpu->fp_status);
1082 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
1083 FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status);
1084 FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
1085 FSTH2 = float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
1091 set_float_exception_flags(0, &env->fpu->fp_status);
1092 FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status);
1093 FDT2 = float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status);
1094 FDT2 = float64_div(FDT2, FLOAT_TWO64, &env->fpu->fp_status) ^ FLOAT_SIGN64;
1099 set_float_exception_flags(0, &env->fpu->fp_status);
1100 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
1101 FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status);
1102 FST2 = float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
1105 FLOAT_OP(rsqrt2, ps)
1107 set_float_exception_flags(0, &env->fpu->fp_status);
1108 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
1109 FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status);
1110 FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status);
1111 FSTH2 = float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status);
1112 FST2 = float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
1113 FSTH2 = float32_div(FSTH2, FLOAT_TWO32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
1119 set_float_exception_flags(0, &env->fpu->fp_status);
1120 FST2 = float32_add (FST0, FSTH0, &env->fpu->fp_status);
1121 FSTH2 = float32_add (FST1, FSTH1, &env->fpu->fp_status);
1127 set_float_exception_flags(0, &env->fpu->fp_status);
1128 FST2 = float32_mul (FST0, FSTH0, &env->fpu->fp_status);
1129 FSTH2 = float32_mul (FST1, FSTH1, &env->fpu->fp_status);
1133 /* compare operations */
1134 #define FOP_COND_D(op, cond) \
1135 void do_cmp_d_ ## op (long cc) \
1140 SET_FP_COND(cc, env->fpu); \
1142 CLEAR_FP_COND(cc, env->fpu); \
1144 void do_cmpabs_d_ ## op (long cc) \
1147 FDT0 &= ~FLOAT_SIGN64; \
1148 FDT1 &= ~FLOAT_SIGN64; \
1152 SET_FP_COND(cc, env->fpu); \
1154 CLEAR_FP_COND(cc, env->fpu); \
1157 int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM)
1159 if (float64_is_signaling_nan(a) ||
1160 float64_is_signaling_nan(b) ||
1161 (sig && (float64_is_nan(a) || float64_is_nan(b)))) {
1162 float_raise(float_flag_invalid, status);
1164 } else if (float64_is_nan(a) || float64_is_nan(b)) {
1171 /* NOTE: the comma operator will make "cond" to eval to false,
1172 * but float*_is_unordered() is still called. */
1173 FOP_COND_D(f, (float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status), 0))
1174 FOP_COND_D(un, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status))
1175 FOP_COND_D(eq, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_eq(FDT0, FDT1, &env->fpu->fp_status))
1176 FOP_COND_D(ueq, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_eq(FDT0, FDT1, &env->fpu->fp_status))
1177 FOP_COND_D(olt, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_lt(FDT0, FDT1, &env->fpu->fp_status))
1178 FOP_COND_D(ult, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_lt(FDT0, FDT1, &env->fpu->fp_status))
1179 FOP_COND_D(ole, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_le(FDT0, FDT1, &env->fpu->fp_status))
1180 FOP_COND_D(ule, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_le(FDT0, FDT1, &env->fpu->fp_status))
1181 /* NOTE: the comma operator will make "cond" to eval to false,
1182 * but float*_is_unordered() is still called. */
1183 FOP_COND_D(sf, (float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status), 0))
1184 FOP_COND_D(ngle,float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status))
1185 FOP_COND_D(seq, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_eq(FDT0, FDT1, &env->fpu->fp_status))
1186 FOP_COND_D(ngl, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_eq(FDT0, FDT1, &env->fpu->fp_status))
1187 FOP_COND_D(lt, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_lt(FDT0, FDT1, &env->fpu->fp_status))
1188 FOP_COND_D(nge, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_lt(FDT0, FDT1, &env->fpu->fp_status))
1189 FOP_COND_D(le, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_le(FDT0, FDT1, &env->fpu->fp_status))
1190 FOP_COND_D(ngt, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_le(FDT0, FDT1, &env->fpu->fp_status))
1192 #define FOP_COND_S(op, cond) \
1193 void do_cmp_s_ ## op (long cc) \
1198 SET_FP_COND(cc, env->fpu); \
1200 CLEAR_FP_COND(cc, env->fpu); \
1202 void do_cmpabs_s_ ## op (long cc) \
1205 FST0 &= ~FLOAT_SIGN32; \
1206 FST1 &= ~FLOAT_SIGN32; \
1210 SET_FP_COND(cc, env->fpu); \
1212 CLEAR_FP_COND(cc, env->fpu); \
1215 flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM)
1217 if (float32_is_signaling_nan(a) ||
1218 float32_is_signaling_nan(b) ||
1219 (sig && (float32_is_nan(a) || float32_is_nan(b)))) {
1220 float_raise(float_flag_invalid, status);
1222 } else if (float32_is_nan(a) || float32_is_nan(b)) {
1229 /* NOTE: the comma operator will make "cond" to eval to false,
1230 * but float*_is_unordered() is still called. */
1231 FOP_COND_S(f, (float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status), 0))
1232 FOP_COND_S(un, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status))
1233 FOP_COND_S(eq, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status))
1234 FOP_COND_S(ueq, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status))
1235 FOP_COND_S(olt, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status))
1236 FOP_COND_S(ult, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status))
1237 FOP_COND_S(ole, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status))
1238 FOP_COND_S(ule, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status))
1239 /* NOTE: the comma operator will make "cond" to eval to false,
1240 * but float*_is_unordered() is still called. */
1241 FOP_COND_S(sf, (float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status), 0))
1242 FOP_COND_S(ngle,float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status))
1243 FOP_COND_S(seq, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status))
1244 FOP_COND_S(ngl, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status))
1245 FOP_COND_S(lt, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status))
1246 FOP_COND_S(nge, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status))
1247 FOP_COND_S(le, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status))
1248 FOP_COND_S(ngt, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status))
1250 #define FOP_COND_PS(op, condl, condh) \
1251 void do_cmp_ps_ ## op (long cc) \
1257 SET_FP_COND(cc, env->fpu); \
1259 CLEAR_FP_COND(cc, env->fpu); \
1261 SET_FP_COND(cc + 1, env->fpu); \
1263 CLEAR_FP_COND(cc + 1, env->fpu); \
1265 void do_cmpabs_ps_ ## op (long cc) \
1268 FST0 &= ~FLOAT_SIGN32; \
1269 FSTH0 &= ~FLOAT_SIGN32; \
1270 FST1 &= ~FLOAT_SIGN32; \
1271 FSTH1 &= ~FLOAT_SIGN32; \
1276 SET_FP_COND(cc, env->fpu); \
1278 CLEAR_FP_COND(cc, env->fpu); \
1280 SET_FP_COND(cc + 1, env->fpu); \
1282 CLEAR_FP_COND(cc + 1, env->fpu); \
1285 /* NOTE: the comma operator will make "cond" to eval to false,
1286 * but float*_is_unordered() is still called. */
1287 FOP_COND_PS(f, (float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status), 0),
1288 (float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status), 0))
1289 FOP_COND_PS(un, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status),
1290 float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status))
1291 FOP_COND_PS(eq, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status),
1292 !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
1293 FOP_COND_PS(ueq, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status),
1294 float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
1295 FOP_COND_PS(olt, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status),
1296 !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
1297 FOP_COND_PS(ult, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status),
1298 float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
1299 FOP_COND_PS(ole, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status),
1300 !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
1301 FOP_COND_PS(ule, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status),
1302 float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
1303 /* NOTE: the comma operator will make "cond" to eval to false,
1304 * but float*_is_unordered() is still called. */
1305 FOP_COND_PS(sf, (float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status), 0),
1306 (float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status), 0))
1307 FOP_COND_PS(ngle,float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status),
1308 float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status))
1309 FOP_COND_PS(seq, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status),
1310 !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
1311 FOP_COND_PS(ngl, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status),
1312 float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
1313 FOP_COND_PS(lt, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status),
1314 !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
1315 FOP_COND_PS(nge, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status),
1316 float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
1317 FOP_COND_PS(le, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status),
1318 !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
1319 FOP_COND_PS(ngt, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status),
1320 float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_le(FSTH0, FSTH1, &env->fpu->fp_status))