2 * MIPS emulation helpers for qemu.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #include "host-utils.h"
26 # define GETPC() ((void*)((unsigned long)__builtin_return_address(0) & 0x7fffffffUL))
28 # define GETPC() (__builtin_return_address(0))
31 /*****************************************************************************/
32 /* Exceptions processing helpers */
34 void do_raise_exception_err (uint32_t exception, int error_code)
37 if (logfile && exception < 0x100)
38 fprintf(logfile, "%s: %d %d\n", __func__, exception, error_code);
40 env->exception_index = exception;
41 env->error_code = error_code;
46 void do_raise_exception (uint32_t exception)
48 do_raise_exception_err(exception, 0);
51 void do_restore_state (void *pc_ptr)
54 unsigned long pc = (unsigned long) pc_ptr;
57 cpu_restore_state (tb, env, pc, NULL);
60 void do_raise_exception_direct_err (uint32_t exception, int error_code)
62 do_restore_state (GETPC ());
63 do_raise_exception_err (exception, error_code);
66 void do_raise_exception_direct (uint32_t exception)
68 do_raise_exception_direct_err (exception, 0);
71 #if defined(TARGET_MIPS64)
72 #if TARGET_LONG_BITS > HOST_LONG_BITS
73 /* Those might call libgcc functions. */
86 T0 = (int64_t)T0 >> T1;
91 T0 = (int64_t)T0 >> (T1 + 32);
101 T0 = T0 >> (T1 + 32);
109 tmp = T0 << (0x40 - T1);
110 T0 = (T0 >> T1) | tmp;
114 void do_drotr32 (void)
118 tmp = T0 << (0x40 - (32 + T1));
119 T0 = (T0 >> (32 + T1)) | tmp;
124 T0 = T1 << (T0 & 0x3F);
129 T0 = (int64_t)T1 >> (T0 & 0x3F);
134 T0 = T1 >> (T0 & 0x3F);
137 void do_drotrv (void)
143 tmp = T1 << (0x40 - T0);
144 T0 = (T1 >> T0) | tmp;
159 #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
160 #endif /* TARGET_MIPS64 */
162 /* 64 bits arithmetic for 32 bits hosts */
163 #if TARGET_LONG_BITS > HOST_LONG_BITS
164 static always_inline uint64_t get_HILO (void)
166 return (env->HI[0][env->current_tc] << 32) | (uint32_t)env->LO[0][env->current_tc];
169 static always_inline void set_HILO (uint64_t HILO)
171 env->LO[0][env->current_tc] = (int32_t)HILO;
172 env->HI[0][env->current_tc] = (int32_t)(HILO >> 32);
175 static always_inline void set_HIT0_LO (uint64_t HILO)
177 env->LO[0][env->current_tc] = (int32_t)(HILO & 0xFFFFFFFF);
178 T0 = env->HI[0][env->current_tc] = (int32_t)(HILO >> 32);
181 static always_inline void set_HI_LOT0 (uint64_t HILO)
183 T0 = env->LO[0][env->current_tc] = (int32_t)(HILO & 0xFFFFFFFF);
184 env->HI[0][env->current_tc] = (int32_t)(HILO >> 32);
189 set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
194 set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
201 tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
202 set_HILO((int64_t)get_HILO() + tmp);
209 tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
210 set_HILO(get_HILO() + tmp);
217 tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
218 set_HILO((int64_t)get_HILO() - tmp);
225 tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
226 set_HILO(get_HILO() - tmp);
229 /* Multiplication variants of the vr54xx. */
232 set_HI_LOT0(0 - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
237 set_HI_LOT0(0 - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
242 set_HI_LOT0(((int64_t)get_HILO()) + ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
245 void do_macchi (void)
247 set_HIT0_LO(((int64_t)get_HILO()) + ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
252 set_HI_LOT0(((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
255 void do_macchiu (void)
257 set_HIT0_LO(((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
262 set_HI_LOT0(((int64_t)get_HILO()) - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
265 void do_msachi (void)
267 set_HIT0_LO(((int64_t)get_HILO()) - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
272 set_HI_LOT0(((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
275 void do_msachiu (void)
277 set_HIT0_LO(((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
282 set_HIT0_LO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
285 void do_mulhiu (void)
287 set_HIT0_LO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
290 void do_mulshi (void)
292 set_HIT0_LO(0 - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
295 void do_mulshiu (void)
297 set_HIT0_LO(0 - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
299 #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
301 #if HOST_LONG_BITS < 64
304 /* 64bit datatypes because we may see overflow/underflow. */
306 env->LO[0][env->current_tc] = (int32_t)((int64_t)(int32_t)T0 / (int32_t)T1);
307 env->HI[0][env->current_tc] = (int32_t)((int64_t)(int32_t)T0 % (int32_t)T1);
312 #if defined(TARGET_MIPS64)
316 int64_t arg0 = (int64_t)T0;
317 int64_t arg1 = (int64_t)T1;
318 if (arg0 == ((int64_t)-1 << 63) && arg1 == (int64_t)-1) {
319 env->LO[0][env->current_tc] = arg0;
320 env->HI[0][env->current_tc] = 0;
322 lldiv_t res = lldiv(arg0, arg1);
323 env->LO[0][env->current_tc] = res.quot;
324 env->HI[0][env->current_tc] = res.rem;
329 #if TARGET_LONG_BITS > HOST_LONG_BITS
333 env->LO[0][env->current_tc] = T0 / T1;
334 env->HI[0][env->current_tc] = T0 % T1;
338 #endif /* TARGET_MIPS64 */
340 #if defined(CONFIG_USER_ONLY)
341 void do_mfc0_random (void)
343 cpu_abort(env, "mfc0 random\n");
346 void do_mfc0_count (void)
348 cpu_abort(env, "mfc0 count\n");
351 void cpu_mips_store_count(CPUState *env, uint32_t value)
353 cpu_abort(env, "mtc0 count\n");
356 void cpu_mips_store_compare(CPUState *env, uint32_t value)
358 cpu_abort(env, "mtc0 compare\n");
361 void cpu_mips_start_count(CPUState *env)
363 cpu_abort(env, "start count\n");
366 void cpu_mips_stop_count(CPUState *env)
368 cpu_abort(env, "stop count\n");
371 void cpu_mips_update_irq(CPUState *env)
373 cpu_abort(env, "mtc0 status / mtc0 cause\n");
376 void do_mtc0_status_debug(uint32_t old, uint32_t val)
378 cpu_abort(env, "mtc0 status debug\n");
381 void do_mtc0_status_irqraise_debug (void)
383 cpu_abort(env, "mtc0 status irqraise debug\n");
386 void cpu_mips_tlb_flush (CPUState *env, int flush_global)
388 cpu_abort(env, "mips_tlb_flush\n");
394 void do_mfc0_random (void)
396 T0 = (int32_t)cpu_mips_get_random(env);
399 void do_mfc0_count (void)
401 T0 = (int32_t)cpu_mips_get_count(env);
404 void do_mtc0_status_debug(uint32_t old, uint32_t val)
406 fprintf(logfile, "Status %08x (%08x) => %08x (%08x) Cause %08x",
407 old, old & env->CP0_Cause & CP0Ca_IP_mask,
408 val, val & env->CP0_Cause & CP0Ca_IP_mask,
410 switch (env->hflags & MIPS_HFLAG_KSU) {
411 case MIPS_HFLAG_UM: fputs(", UM\n", logfile); break;
412 case MIPS_HFLAG_SM: fputs(", SM\n", logfile); break;
413 case MIPS_HFLAG_KM: fputs("\n", logfile); break;
414 default: cpu_abort(env, "Invalid MMU mode!\n"); break;
418 void do_mtc0_status_irqraise_debug(void)
420 fprintf(logfile, "Raise pending IRQs\n");
423 void fpu_handle_exception(void)
425 #ifdef CONFIG_SOFTFLOAT
426 int flags = get_float_exception_flags(&env->fpu->fp_status);
427 unsigned int cpuflags = 0, enable, cause = 0;
429 enable = GET_FP_ENABLE(env->fpu->fcr31);
431 /* determine current flags */
432 if (flags & float_flag_invalid) {
433 cpuflags |= FP_INVALID;
434 cause |= FP_INVALID & enable;
436 if (flags & float_flag_divbyzero) {
438 cause |= FP_DIV0 & enable;
440 if (flags & float_flag_overflow) {
441 cpuflags |= FP_OVERFLOW;
442 cause |= FP_OVERFLOW & enable;
444 if (flags & float_flag_underflow) {
445 cpuflags |= FP_UNDERFLOW;
446 cause |= FP_UNDERFLOW & enable;
448 if (flags & float_flag_inexact) {
449 cpuflags |= FP_INEXACT;
450 cause |= FP_INEXACT & enable;
452 SET_FP_FLAGS(env->fpu->fcr31, cpuflags);
453 SET_FP_CAUSE(env->fpu->fcr31, cause);
455 SET_FP_FLAGS(env->fpu->fcr31, 0);
456 SET_FP_CAUSE(env->fpu->fcr31, 0);
461 void cpu_mips_tlb_flush (CPUState *env, int flush_global)
463 /* Flush qemu's TLB and discard all shadowed entries. */
464 tlb_flush (env, flush_global);
465 env->tlb->tlb_in_use = env->tlb->nb_tlb;
468 static void r4k_mips_tlb_flush_extra (CPUState *env, int first)
470 /* Discard entries from env->tlb[first] onwards. */
471 while (env->tlb->tlb_in_use > first) {
472 r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
476 static void r4k_fill_tlb (int idx)
480 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
481 tlb = &env->tlb->mmu.r4k.tlb[idx];
482 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
483 #if defined(TARGET_MIPS64)
484 tlb->VPN &= env->SEGMask;
486 tlb->ASID = env->CP0_EntryHi & 0xFF;
487 tlb->PageMask = env->CP0_PageMask;
488 tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
489 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
490 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
491 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
492 tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
493 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
494 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
495 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
496 tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
499 void r4k_do_tlbwi (void)
501 /* Discard cached TLB entries. We could avoid doing this if the
502 tlbwi is just upgrading access permissions on the current entry;
503 that might be a further win. */
504 r4k_mips_tlb_flush_extra (env, env->tlb->nb_tlb);
506 r4k_invalidate_tlb(env, env->CP0_Index % env->tlb->nb_tlb, 0);
507 r4k_fill_tlb(env->CP0_Index % env->tlb->nb_tlb);
510 void r4k_do_tlbwr (void)
512 int r = cpu_mips_get_random(env);
514 r4k_invalidate_tlb(env, r, 1);
518 void r4k_do_tlbp (void)
527 ASID = env->CP0_EntryHi & 0xFF;
528 for (i = 0; i < env->tlb->nb_tlb; i++) {
529 tlb = &env->tlb->mmu.r4k.tlb[i];
530 /* 1k pages are not supported. */
531 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
532 tag = env->CP0_EntryHi & ~mask;
533 VPN = tlb->VPN & ~mask;
534 /* Check ASID, virtual page number & size */
535 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
541 if (i == env->tlb->nb_tlb) {
542 /* No match. Discard any shadow entries, if any of them match. */
543 for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
544 tlb = &env->tlb->mmu.r4k.tlb[i];
545 /* 1k pages are not supported. */
546 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
547 tag = env->CP0_EntryHi & ~mask;
548 VPN = tlb->VPN & ~mask;
549 /* Check ASID, virtual page number & size */
550 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
551 r4k_mips_tlb_flush_extra (env, i);
556 env->CP0_Index |= 0x80000000;
560 void r4k_do_tlbr (void)
565 ASID = env->CP0_EntryHi & 0xFF;
566 tlb = &env->tlb->mmu.r4k.tlb[env->CP0_Index % env->tlb->nb_tlb];
568 /* If this will change the current ASID, flush qemu's TLB. */
569 if (ASID != tlb->ASID)
570 cpu_mips_tlb_flush (env, 1);
572 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
574 env->CP0_EntryHi = tlb->VPN | tlb->ASID;
575 env->CP0_PageMask = tlb->PageMask;
576 env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
577 (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
578 env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
579 (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
582 #endif /* !CONFIG_USER_ONLY */
584 void dump_ldst (const unsigned char *func)
587 fprintf(logfile, "%s => " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__, T0, T1);
593 fprintf(logfile, "%s " TARGET_FMT_lx " at " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", __func__,
594 T1, T0, env->CP0_LLAddr);
598 void debug_pre_eret (void)
600 fprintf(logfile, "ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
601 env->PC[env->current_tc], env->CP0_EPC);
602 if (env->CP0_Status & (1 << CP0St_ERL))
603 fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
604 if (env->hflags & MIPS_HFLAG_DM)
605 fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
606 fputs("\n", logfile);
609 void debug_post_eret (void)
611 fprintf(logfile, " => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
612 env->PC[env->current_tc], env->CP0_EPC);
613 if (env->CP0_Status & (1 << CP0St_ERL))
614 fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
615 if (env->hflags & MIPS_HFLAG_DM)
616 fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
617 switch (env->hflags & MIPS_HFLAG_KSU) {
618 case MIPS_HFLAG_UM: fputs(", UM\n", logfile); break;
619 case MIPS_HFLAG_SM: fputs(", SM\n", logfile); break;
620 case MIPS_HFLAG_KM: fputs("\n", logfile); break;
621 default: cpu_abort(env, "Invalid MMU mode!\n"); break;
625 void do_pmon (int function)
629 case 2: /* TODO: char inbyte(int waitflag); */
630 if (env->gpr[4][env->current_tc] == 0)
631 env->gpr[2][env->current_tc] = -1;
633 case 11: /* TODO: char inbyte (void); */
634 env->gpr[2][env->current_tc] = -1;
638 printf("%c", (char)(env->gpr[4][env->current_tc] & 0xFF));
644 unsigned char *fmt = (void *)(unsigned long)env->gpr[4][env->current_tc];
651 #if !defined(CONFIG_USER_ONLY)
653 static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr);
655 #define MMUSUFFIX _mmu
659 #include "softmmu_template.h"
662 #include "softmmu_template.h"
665 #include "softmmu_template.h"
668 #include "softmmu_template.h"
670 static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr)
672 env->CP0_BadVAddr = addr;
673 do_restore_state (retaddr);
674 do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
677 void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
679 TranslationBlock *tb;
684 /* XXX: hack to restore env in all cases, even if not called from
687 env = cpu_single_env;
688 ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
691 /* now we have a real cpu fault */
692 pc = (unsigned long)retaddr;
695 /* the PC is inside the translated code. It means that we have
696 a virtual CPU fault */
697 cpu_restore_state(tb, env, pc, NULL);
700 do_raise_exception_err(env->exception_index, env->error_code);
705 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
709 do_raise_exception(EXCP_IBE);
711 do_raise_exception(EXCP_DBE);
715 /* Complex FPU operations which may need stack space. */
717 #define FLOAT_ONE32 make_float32(0x3f8 << 20)
718 #define FLOAT_ONE64 make_float64(0x3ffULL << 52)
719 #define FLOAT_TWO32 make_float32(1 << 30)
720 #define FLOAT_TWO64 make_float64(1ULL << 62)
721 #define FLOAT_QNAN32 0x7fbfffff
722 #define FLOAT_QNAN64 0x7ff7ffffffffffffULL
723 #define FLOAT_SNAN32 0x7fffffff
724 #define FLOAT_SNAN64 0x7fffffffffffffffULL
726 /* convert MIPS rounding mode in FCR31 to IEEE library */
727 unsigned int ieee_rm[] = {
728 float_round_nearest_even,
734 #define RESTORE_ROUNDING_MODE \
735 set_float_rounding_mode(ieee_rm[env->fpu->fcr31 & 3], &env->fpu->fp_status)
737 void do_cfc1 (int reg)
741 T0 = (int32_t)env->fpu->fcr0;
744 T0 = ((env->fpu->fcr31 >> 24) & 0xfe) | ((env->fpu->fcr31 >> 23) & 0x1);
747 T0 = env->fpu->fcr31 & 0x0003f07c;
750 T0 = (env->fpu->fcr31 & 0x00000f83) | ((env->fpu->fcr31 >> 22) & 0x4);
753 T0 = (int32_t)env->fpu->fcr31;
758 void do_ctc1 (int reg)
764 env->fpu->fcr31 = (env->fpu->fcr31 & 0x017fffff) | ((T0 & 0xfe) << 24) |
770 env->fpu->fcr31 = (env->fpu->fcr31 & 0xfffc0f83) | (T0 & 0x0003f07c);
775 env->fpu->fcr31 = (env->fpu->fcr31 & 0xfefff07c) | (T0 & 0x00000f83) |
781 env->fpu->fcr31 = T0;
786 /* set rounding mode */
787 RESTORE_ROUNDING_MODE;
788 set_float_exception_flags(0, &env->fpu->fp_status);
789 if ((GET_FP_ENABLE(env->fpu->fcr31) | 0x20) & GET_FP_CAUSE(env->fpu->fcr31))
790 do_raise_exception(EXCP_FPE);
793 static always_inline char ieee_ex_to_mips(char xcpt)
795 return (xcpt & float_flag_inexact) >> 5 |
796 (xcpt & float_flag_underflow) >> 3 |
797 (xcpt & float_flag_overflow) >> 1 |
798 (xcpt & float_flag_divbyzero) << 1 |
799 (xcpt & float_flag_invalid) << 4;
802 static always_inline char mips_ex_to_ieee(char xcpt)
804 return (xcpt & FP_INEXACT) << 5 |
805 (xcpt & FP_UNDERFLOW) << 3 |
806 (xcpt & FP_OVERFLOW) << 1 |
807 (xcpt & FP_DIV0) >> 1 |
808 (xcpt & FP_INVALID) >> 4;
811 static always_inline void update_fcr31(void)
813 int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->fpu->fp_status));
815 SET_FP_CAUSE(env->fpu->fcr31, tmp);
816 if (GET_FP_ENABLE(env->fpu->fcr31) & tmp)
817 do_raise_exception(EXCP_FPE);
819 UPDATE_FP_FLAGS(env->fpu->fcr31, tmp);
822 #define FLOAT_OP(name, p) void do_float_##name##_##p(void)
826 set_float_exception_flags(0, &env->fpu->fp_status);
827 FDT2 = float32_to_float64(FST0, &env->fpu->fp_status);
832 set_float_exception_flags(0, &env->fpu->fp_status);
833 FDT2 = int32_to_float64(WT0, &env->fpu->fp_status);
838 set_float_exception_flags(0, &env->fpu->fp_status);
839 FDT2 = int64_to_float64(DT0, &env->fpu->fp_status);
844 set_float_exception_flags(0, &env->fpu->fp_status);
845 DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
847 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
852 set_float_exception_flags(0, &env->fpu->fp_status);
853 DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
855 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
861 set_float_exception_flags(0, &env->fpu->fp_status);
862 FST2 = int32_to_float32(WT0, &env->fpu->fp_status);
863 FSTH2 = int32_to_float32(WTH0, &env->fpu->fp_status);
868 set_float_exception_flags(0, &env->fpu->fp_status);
869 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
870 WTH2 = float32_to_int32(FSTH0, &env->fpu->fp_status);
872 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
877 set_float_exception_flags(0, &env->fpu->fp_status);
878 FST2 = float64_to_float32(FDT0, &env->fpu->fp_status);
883 set_float_exception_flags(0, &env->fpu->fp_status);
884 FST2 = int32_to_float32(WT0, &env->fpu->fp_status);
889 set_float_exception_flags(0, &env->fpu->fp_status);
890 FST2 = int64_to_float32(DT0, &env->fpu->fp_status);
895 set_float_exception_flags(0, &env->fpu->fp_status);
901 set_float_exception_flags(0, &env->fpu->fp_status);
907 set_float_exception_flags(0, &env->fpu->fp_status);
908 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
910 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
915 set_float_exception_flags(0, &env->fpu->fp_status);
916 WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
918 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
924 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
925 DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
926 RESTORE_ROUNDING_MODE;
928 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
933 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
934 DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
935 RESTORE_ROUNDING_MODE;
937 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
942 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
943 WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
944 RESTORE_ROUNDING_MODE;
946 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
951 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
952 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
953 RESTORE_ROUNDING_MODE;
955 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
961 DT2 = float64_to_int64_round_to_zero(FDT0, &env->fpu->fp_status);
963 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
968 DT2 = float32_to_int64_round_to_zero(FST0, &env->fpu->fp_status);
970 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
975 WT2 = float64_to_int32_round_to_zero(FDT0, &env->fpu->fp_status);
977 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
982 WT2 = float32_to_int32_round_to_zero(FST0, &env->fpu->fp_status);
984 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
990 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
991 DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
992 RESTORE_ROUNDING_MODE;
994 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
999 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
1000 DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
1001 RESTORE_ROUNDING_MODE;
1003 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
1008 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
1009 WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
1010 RESTORE_ROUNDING_MODE;
1012 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
1017 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
1018 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
1019 RESTORE_ROUNDING_MODE;
1021 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
1027 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
1028 DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
1029 RESTORE_ROUNDING_MODE;
1031 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
1036 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
1037 DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
1038 RESTORE_ROUNDING_MODE;
1040 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
1045 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
1046 WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
1047 RESTORE_ROUNDING_MODE;
1049 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
1054 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
1055 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
1056 RESTORE_ROUNDING_MODE;
1058 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
1062 /* MIPS specific unary operations */
1065 set_float_exception_flags(0, &env->fpu->fp_status);
1066 FDT2 = float64_div(FLOAT_ONE64, FDT0, &env->fpu->fp_status);
1071 set_float_exception_flags(0, &env->fpu->fp_status);
1072 FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status);
1078 set_float_exception_flags(0, &env->fpu->fp_status);
1079 FDT2 = float64_sqrt(FDT0, &env->fpu->fp_status);
1080 FDT2 = float64_div(FLOAT_ONE64, FDT2, &env->fpu->fp_status);
1085 set_float_exception_flags(0, &env->fpu->fp_status);
1086 FST2 = float32_sqrt(FST0, &env->fpu->fp_status);
1087 FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status);
1093 set_float_exception_flags(0, &env->fpu->fp_status);
1094 FDT2 = float64_div(FLOAT_ONE64, FDT0, &env->fpu->fp_status);
1099 set_float_exception_flags(0, &env->fpu->fp_status);
1100 FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status);
1103 FLOAT_OP(recip1, ps)
1105 set_float_exception_flags(0, &env->fpu->fp_status);
1106 FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status);
1107 FSTH2 = float32_div(FLOAT_ONE32, FSTH0, &env->fpu->fp_status);
1113 set_float_exception_flags(0, &env->fpu->fp_status);
1114 FDT2 = float64_sqrt(FDT0, &env->fpu->fp_status);
1115 FDT2 = float64_div(FLOAT_ONE64, FDT2, &env->fpu->fp_status);
1120 set_float_exception_flags(0, &env->fpu->fp_status);
1121 FST2 = float32_sqrt(FST0, &env->fpu->fp_status);
1122 FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status);
1125 FLOAT_OP(rsqrt1, ps)
1127 set_float_exception_flags(0, &env->fpu->fp_status);
1128 FST2 = float32_sqrt(FST0, &env->fpu->fp_status);
1129 FSTH2 = float32_sqrt(FSTH0, &env->fpu->fp_status);
1130 FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status);
1131 FSTH2 = float32_div(FLOAT_ONE32, FSTH2, &env->fpu->fp_status);
1135 /* binary operations */
1136 #define FLOAT_BINOP(name) \
1139 set_float_exception_flags(0, &env->fpu->fp_status); \
1140 FDT2 = float64_ ## name (FDT0, FDT1, &env->fpu->fp_status); \
1142 if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \
1143 DT2 = FLOAT_QNAN64; \
1147 set_float_exception_flags(0, &env->fpu->fp_status); \
1148 FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status); \
1150 if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \
1151 WT2 = FLOAT_QNAN32; \
1153 FLOAT_OP(name, ps) \
1155 set_float_exception_flags(0, &env->fpu->fp_status); \
1156 FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status); \
1157 FSTH2 = float32_ ## name (FSTH0, FSTH1, &env->fpu->fp_status); \
1159 if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) { \
1160 WT2 = FLOAT_QNAN32; \
1161 WTH2 = FLOAT_QNAN32; \
1170 /* MIPS specific binary operations */
1173 set_float_exception_flags(0, &env->fpu->fp_status);
1174 FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status);
1175 FDT2 = float64_chs(float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status));
1180 set_float_exception_flags(0, &env->fpu->fp_status);
1181 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
1182 FST2 = float32_chs(float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status));
1185 FLOAT_OP(recip2, ps)
1187 set_float_exception_flags(0, &env->fpu->fp_status);
1188 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
1189 FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status);
1190 FST2 = float32_chs(float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status));
1191 FSTH2 = float32_chs(float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status));
1197 set_float_exception_flags(0, &env->fpu->fp_status);
1198 FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status);
1199 FDT2 = float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status);
1200 FDT2 = float64_chs(float64_div(FDT2, FLOAT_TWO64, &env->fpu->fp_status));
1205 set_float_exception_flags(0, &env->fpu->fp_status);
1206 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
1207 FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status);
1208 FST2 = float32_chs(float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status));
1211 FLOAT_OP(rsqrt2, ps)
1213 set_float_exception_flags(0, &env->fpu->fp_status);
1214 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
1215 FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status);
1216 FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status);
1217 FSTH2 = float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status);
1218 FST2 = float32_chs(float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status));
1219 FSTH2 = float32_chs(float32_div(FSTH2, FLOAT_TWO32, &env->fpu->fp_status));
1225 set_float_exception_flags(0, &env->fpu->fp_status);
1226 FST2 = float32_add (FST0, FSTH0, &env->fpu->fp_status);
1227 FSTH2 = float32_add (FST1, FSTH1, &env->fpu->fp_status);
1233 set_float_exception_flags(0, &env->fpu->fp_status);
1234 FST2 = float32_mul (FST0, FSTH0, &env->fpu->fp_status);
1235 FSTH2 = float32_mul (FST1, FSTH1, &env->fpu->fp_status);
1239 /* compare operations */
1240 #define FOP_COND_D(op, cond) \
1241 void do_cmp_d_ ## op (long cc) \
1246 SET_FP_COND(cc, env->fpu); \
1248 CLEAR_FP_COND(cc, env->fpu); \
1250 void do_cmpabs_d_ ## op (long cc) \
1253 FDT0 = float64_abs(FDT0); \
1254 FDT1 = float64_abs(FDT1); \
1258 SET_FP_COND(cc, env->fpu); \
1260 CLEAR_FP_COND(cc, env->fpu); \
1263 int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM)
1265 if (float64_is_signaling_nan(a) ||
1266 float64_is_signaling_nan(b) ||
1267 (sig && (float64_is_nan(a) || float64_is_nan(b)))) {
1268 float_raise(float_flag_invalid, status);
1270 } else if (float64_is_nan(a) || float64_is_nan(b)) {
1277 /* NOTE: the comma operator will make "cond" to eval to false,
1278 * but float*_is_unordered() is still called. */
1279 FOP_COND_D(f, (float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status), 0))
1280 FOP_COND_D(un, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status))
1281 FOP_COND_D(eq, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_eq(FDT0, FDT1, &env->fpu->fp_status))
1282 FOP_COND_D(ueq, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_eq(FDT0, FDT1, &env->fpu->fp_status))
1283 FOP_COND_D(olt, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_lt(FDT0, FDT1, &env->fpu->fp_status))
1284 FOP_COND_D(ult, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_lt(FDT0, FDT1, &env->fpu->fp_status))
1285 FOP_COND_D(ole, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_le(FDT0, FDT1, &env->fpu->fp_status))
1286 FOP_COND_D(ule, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_le(FDT0, FDT1, &env->fpu->fp_status))
1287 /* NOTE: the comma operator will make "cond" to eval to false,
1288 * but float*_is_unordered() is still called. */
1289 FOP_COND_D(sf, (float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status), 0))
1290 FOP_COND_D(ngle,float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status))
1291 FOP_COND_D(seq, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_eq(FDT0, FDT1, &env->fpu->fp_status))
1292 FOP_COND_D(ngl, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_eq(FDT0, FDT1, &env->fpu->fp_status))
1293 FOP_COND_D(lt, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_lt(FDT0, FDT1, &env->fpu->fp_status))
1294 FOP_COND_D(nge, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_lt(FDT0, FDT1, &env->fpu->fp_status))
1295 FOP_COND_D(le, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_le(FDT0, FDT1, &env->fpu->fp_status))
1296 FOP_COND_D(ngt, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_le(FDT0, FDT1, &env->fpu->fp_status))
1298 #define FOP_COND_S(op, cond) \
1299 void do_cmp_s_ ## op (long cc) \
1304 SET_FP_COND(cc, env->fpu); \
1306 CLEAR_FP_COND(cc, env->fpu); \
1308 void do_cmpabs_s_ ## op (long cc) \
1311 FST0 = float32_abs(FST0); \
1312 FST1 = float32_abs(FST1); \
1316 SET_FP_COND(cc, env->fpu); \
1318 CLEAR_FP_COND(cc, env->fpu); \
1321 flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM)
1323 if (float32_is_signaling_nan(a) ||
1324 float32_is_signaling_nan(b) ||
1325 (sig && (float32_is_nan(a) || float32_is_nan(b)))) {
1326 float_raise(float_flag_invalid, status);
1328 } else if (float32_is_nan(a) || float32_is_nan(b)) {
1335 /* NOTE: the comma operator will make "cond" to eval to false,
1336 * but float*_is_unordered() is still called. */
1337 FOP_COND_S(f, (float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status), 0))
1338 FOP_COND_S(un, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status))
1339 FOP_COND_S(eq, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status))
1340 FOP_COND_S(ueq, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status))
1341 FOP_COND_S(olt, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status))
1342 FOP_COND_S(ult, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status))
1343 FOP_COND_S(ole, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status))
1344 FOP_COND_S(ule, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status))
1345 /* NOTE: the comma operator will make "cond" to eval to false,
1346 * but float*_is_unordered() is still called. */
1347 FOP_COND_S(sf, (float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status), 0))
1348 FOP_COND_S(ngle,float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status))
1349 FOP_COND_S(seq, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status))
1350 FOP_COND_S(ngl, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status))
1351 FOP_COND_S(lt, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status))
1352 FOP_COND_S(nge, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status))
1353 FOP_COND_S(le, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status))
1354 FOP_COND_S(ngt, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status))
1356 #define FOP_COND_PS(op, condl, condh) \
1357 void do_cmp_ps_ ## op (long cc) \
1363 SET_FP_COND(cc, env->fpu); \
1365 CLEAR_FP_COND(cc, env->fpu); \
1367 SET_FP_COND(cc + 1, env->fpu); \
1369 CLEAR_FP_COND(cc + 1, env->fpu); \
1371 void do_cmpabs_ps_ ## op (long cc) \
1374 FST0 = float32_abs(FST0); \
1375 FSTH0 = float32_abs(FSTH0); \
1376 FST1 = float32_abs(FST1); \
1377 FSTH1 = float32_abs(FSTH1); \
1382 SET_FP_COND(cc, env->fpu); \
1384 CLEAR_FP_COND(cc, env->fpu); \
1386 SET_FP_COND(cc + 1, env->fpu); \
1388 CLEAR_FP_COND(cc + 1, env->fpu); \
1391 /* NOTE: the comma operator will make "cond" to eval to false,
1392 * but float*_is_unordered() is still called. */
1393 FOP_COND_PS(f, (float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status), 0),
1394 (float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status), 0))
1395 FOP_COND_PS(un, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status),
1396 float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status))
1397 FOP_COND_PS(eq, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status),
1398 !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
1399 FOP_COND_PS(ueq, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status),
1400 float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
1401 FOP_COND_PS(olt, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status),
1402 !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
1403 FOP_COND_PS(ult, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status),
1404 float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
1405 FOP_COND_PS(ole, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status),
1406 !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
1407 FOP_COND_PS(ule, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status),
1408 float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
1409 /* NOTE: the comma operator will make "cond" to eval to false,
1410 * but float*_is_unordered() is still called. */
1411 FOP_COND_PS(sf, (float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status), 0),
1412 (float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status), 0))
1413 FOP_COND_PS(ngle,float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status),
1414 float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status))
1415 FOP_COND_PS(seq, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status),
1416 !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
1417 FOP_COND_PS(ngl, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status),
1418 float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
1419 FOP_COND_PS(lt, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status),
1420 !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
1421 FOP_COND_PS(nge, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status),
1422 float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
1423 FOP_COND_PS(le, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status),
1424 !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
1425 FOP_COND_PS(ngt, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status),
1426 float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_le(FSTH0, FSTH1, &env->fpu->fp_status))