2 * MIPS emulation helpers for qemu.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #define MIPS_DEBUG_DISAS
25 #define GETPC() (__builtin_return_address(0))
27 /*****************************************************************************/
28 /* Exceptions processing helpers */
29 void cpu_loop_exit(void)
31 longjmp(env->jmp_env, 1);
34 void do_raise_exception_err (uint32_t exception, int error_code)
37 if (logfile && exception < 0x100)
38 fprintf(logfile, "%s: %d %d\n", __func__, exception, error_code);
40 env->exception_index = exception;
41 env->error_code = error_code;
46 void do_raise_exception (uint32_t exception)
48 do_raise_exception_err(exception, 0);
51 void do_restore_state (void *pc_ptr)
54 unsigned long pc = (unsigned long) pc_ptr;
57 cpu_restore_state (tb, env, pc, NULL);
60 void do_raise_exception_direct_err (uint32_t exception, int error_code)
62 do_restore_state (GETPC ());
63 do_raise_exception_err (exception, error_code);
66 void do_raise_exception_direct (uint32_t exception)
68 do_raise_exception_direct_err (exception, 0);
71 #define MEMSUFFIX _raw
72 #include "op_helper_mem.c"
74 #if !defined(CONFIG_USER_ONLY)
75 #define MEMSUFFIX _user
76 #include "op_helper_mem.c"
78 #define MEMSUFFIX _kernel
79 #include "op_helper_mem.c"
84 #if TARGET_LONG_BITS > HOST_LONG_BITS
85 /* Those might call libgcc functions. */
98 T0 = (int64_t)T0 >> T1;
101 void do_dsra32 (void)
103 T0 = (int64_t)T0 >> (T1 + 32);
111 void do_dsrl32 (void)
113 T0 = T0 >> (T1 + 32);
121 tmp = T0 << (0x40 - T1);
122 T0 = (T0 >> T1) | tmp;
126 void do_drotr32 (void)
131 tmp = T0 << (0x40 - (32 + T1));
132 T0 = (T0 >> (32 + T1)) | tmp;
138 T0 = T1 << (T0 & 0x3F);
143 T0 = (int64_t)T1 >> (T0 & 0x3F);
148 T0 = T1 >> (T0 & 0x3F);
151 void do_drotrv (void)
157 tmp = T1 << (0x40 - T0);
158 T0 = (T1 >> T0) | tmp;
162 #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
163 #endif /* TARGET_MIPS64 */
165 /* 64 bits arithmetic for 32 bits hosts */
166 #if TARGET_LONG_BITS > HOST_LONG_BITS
167 static inline uint64_t get_HILO (void)
169 return (env->HI << 32) | (uint32_t)env->LO;
172 static inline void set_HILO (uint64_t HILO)
174 env->LO = (int32_t)HILO;
175 env->HI = (int32_t)(HILO >> 32);
180 set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
185 set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
192 tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
193 set_HILO((int64_t)get_HILO() + tmp);
200 tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
201 set_HILO(get_HILO() + tmp);
208 tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
209 set_HILO((int64_t)get_HILO() - tmp);
216 tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
217 set_HILO(get_HILO() - tmp);
224 env->LO = (int64_t)T0 * (int64_t)T1;
226 env->HI = (env->LO | (1ULL << 63)) ? ~0ULL : 0ULL;
229 void do_dmultu (void)
239 lldiv_t res = lldiv((int64_t)T0, (int64_t)T1);
249 lldiv_t res = lldiv(T0, T1);
250 env->LO = (uint64_t)res.quot;
251 env->HI = (uint64_t)res.rem;
256 #if defined(CONFIG_USER_ONLY)
257 void do_mfc0_random (void)
259 cpu_abort(env, "mfc0 random\n");
262 void do_mfc0_count (void)
264 cpu_abort(env, "mfc0 count\n");
267 void cpu_mips_store_count(CPUState *env, uint32_t value)
269 cpu_abort(env, "mtc0 count\n");
272 void cpu_mips_store_compare(CPUState *env, uint32_t value)
274 cpu_abort(env, "mtc0 compare\n");
277 void cpu_mips_update_irq(CPUState *env)
279 cpu_abort(env, "mtc0 status / mtc0 cause\n");
282 void do_mtc0_status_debug(uint32_t old, uint32_t val)
284 cpu_abort(env, "mtc0 status debug\n");
287 void do_mtc0_status_irqraise_debug (void)
289 cpu_abort(env, "mtc0 status irqraise debug\n");
294 cpu_abort(env, "tlbwi\n");
299 cpu_abort(env, "tlbwr\n");
304 cpu_abort(env, "tlbp\n");
309 cpu_abort(env, "tlbr\n");
312 void cpu_mips_tlb_flush (CPUState *env, int flush_global)
314 cpu_abort(env, "mips_tlb_flush\n");
320 void do_mfc0_random (void)
322 T0 = (int32_t)cpu_mips_get_random(env);
325 void do_mfc0_count (void)
327 T0 = (int32_t)cpu_mips_get_count(env);
330 void do_mtc0_status_debug(uint32_t old, uint32_t val)
332 fprintf(logfile, "Status %08x (%08x) => %08x (%08x) Cause %08x",
333 old, old & env->CP0_Cause & CP0Ca_IP_mask,
334 val, val & env->CP0_Cause & CP0Ca_IP_mask,
336 (env->hflags & MIPS_HFLAG_UM) ? fputs(", UM\n", logfile)
337 : fputs("\n", logfile);
340 void do_mtc0_status_irqraise_debug(void)
342 fprintf(logfile, "Raise pending IRQs\n");
345 void fpu_handle_exception(void)
347 #ifdef CONFIG_SOFTFLOAT
348 int flags = get_float_exception_flags(&env->fp_status);
349 unsigned int cpuflags = 0, enable, cause = 0;
351 enable = GET_FP_ENABLE(env->fcr31);
353 /* determine current flags */
354 if (flags & float_flag_invalid) {
355 cpuflags |= FP_INVALID;
356 cause |= FP_INVALID & enable;
358 if (flags & float_flag_divbyzero) {
360 cause |= FP_DIV0 & enable;
362 if (flags & float_flag_overflow) {
363 cpuflags |= FP_OVERFLOW;
364 cause |= FP_OVERFLOW & enable;
366 if (flags & float_flag_underflow) {
367 cpuflags |= FP_UNDERFLOW;
368 cause |= FP_UNDERFLOW & enable;
370 if (flags & float_flag_inexact) {
371 cpuflags |= FP_INEXACT;
372 cause |= FP_INEXACT & enable;
374 SET_FP_FLAGS(env->fcr31, cpuflags);
375 SET_FP_CAUSE(env->fcr31, cause);
377 SET_FP_FLAGS(env->fcr31, 0);
378 SET_FP_CAUSE(env->fcr31, 0);
383 #if defined(MIPS_USES_R4K_TLB)
384 void cpu_mips_tlb_flush (CPUState *env, int flush_global)
386 /* Flush qemu's TLB and discard all shadowed entries. */
387 tlb_flush (env, flush_global);
388 env->tlb_in_use = MIPS_TLB_NB;
391 static void mips_tlb_flush_extra (CPUState *env, int first)
393 /* Discard entries from env->tlb[first] onwards. */
394 while (env->tlb_in_use > first) {
395 invalidate_tlb(env, --env->tlb_in_use, 0);
399 static void fill_tlb (int idx)
403 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
404 tlb = &env->tlb[idx];
405 tlb->VPN = env->CP0_EntryHi & ~(target_ulong)0x1FFF;
406 tlb->ASID = env->CP0_EntryHi & 0xFF;
407 tlb->PageMask = env->CP0_PageMask;
408 tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
409 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
410 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
411 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
412 tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
413 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
414 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
415 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
416 tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
421 /* Discard cached TLB entries. We could avoid doing this if the
422 tlbwi is just upgrading access permissions on the current entry;
423 that might be a further win. */
424 mips_tlb_flush_extra (env, MIPS_TLB_NB);
426 /* Wildly undefined effects for CP0_Index containing a too high value and
427 MIPS_TLB_NB not being a power of two. But so does real silicon. */
428 invalidate_tlb(env, env->CP0_Index & (MIPS_TLB_NB - 1), 0);
429 fill_tlb(env->CP0_Index & (MIPS_TLB_NB - 1));
434 int r = cpu_mips_get_random(env);
436 invalidate_tlb(env, r, 1);
447 tag = env->CP0_EntryHi & (int32_t)0xFFFFE000;
448 ASID = env->CP0_EntryHi & 0xFF;
449 for (i = 0; i < MIPS_TLB_NB; i++) {
451 /* Check ASID, virtual page number & size */
452 if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) {
458 if (i == MIPS_TLB_NB) {
459 /* No match. Discard any shadow entries, if any of them match. */
460 for (i = MIPS_TLB_NB; i < env->tlb_in_use; i++) {
463 /* Check ASID, virtual page number & size */
464 if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) {
465 mips_tlb_flush_extra (env, i);
470 env->CP0_Index |= 0x80000000;
479 ASID = env->CP0_EntryHi & 0xFF;
480 tlb = &env->tlb[env->CP0_Index & (MIPS_TLB_NB - 1)];
482 /* If this will change the current ASID, flush qemu's TLB. */
483 if (ASID != tlb->ASID)
484 cpu_mips_tlb_flush (env, 1);
486 mips_tlb_flush_extra(env, MIPS_TLB_NB);
488 env->CP0_EntryHi = tlb->VPN | tlb->ASID;
489 env->CP0_PageMask = tlb->PageMask;
490 env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
491 (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
492 env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
493 (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
497 #endif /* !CONFIG_USER_ONLY */
499 void dump_ldst (const unsigned char *func)
502 fprintf(logfile, "%s => " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__, T0, T1);
508 fprintf(logfile, "%s " TARGET_FMT_lx " at " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", __func__,
509 T1, T0, env->CP0_LLAddr);
513 void debug_pre_eret (void)
515 fprintf(logfile, "ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
516 env->PC, env->CP0_EPC);
517 if (env->CP0_Status & (1 << CP0St_ERL))
518 fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
519 if (env->hflags & MIPS_HFLAG_DM)
520 fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
521 fputs("\n", logfile);
524 void debug_post_eret (void)
526 fprintf(logfile, " => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
527 env->PC, env->CP0_EPC);
528 if (env->CP0_Status & (1 << CP0St_ERL))
529 fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
530 if (env->hflags & MIPS_HFLAG_DM)
531 fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
532 if (env->hflags & MIPS_HFLAG_UM)
533 fputs(", UM\n", logfile);
535 fputs("\n", logfile);
538 void do_pmon (int function)
542 case 2: /* TODO: char inbyte(int waitflag); */
543 if (env->gpr[4] == 0)
546 case 11: /* TODO: char inbyte (void); */
551 printf("%c", (char)(env->gpr[4] & 0xFF));
557 unsigned char *fmt = (void *)(unsigned long)env->gpr[4];
564 #if !defined(CONFIG_USER_ONLY)
566 static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr);
568 #define MMUSUFFIX _mmu
572 #include "softmmu_template.h"
575 #include "softmmu_template.h"
578 #include "softmmu_template.h"
581 #include "softmmu_template.h"
583 static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr)
585 env->CP0_BadVAddr = addr;
586 do_restore_state (retaddr);
587 do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
590 void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr)
592 TranslationBlock *tb;
597 /* XXX: hack to restore env in all cases, even if not called from
600 env = cpu_single_env;
601 ret = cpu_mips_handle_mmu_fault(env, addr, is_write, is_user, 1);
604 /* now we have a real cpu fault */
605 pc = (unsigned long)retaddr;
608 /* the PC is inside the translated code. It means that we have
609 a virtual CPU fault */
610 cpu_restore_state(tb, env, pc, NULL);
613 do_raise_exception_err(env->exception_index, env->error_code);