2 * MIPS emulation helpers for qemu.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #define MIPS_DEBUG_DISAS
24 #define GETPC() (__builtin_return_address(0))
26 /*****************************************************************************/
27 /* Exceptions processing helpers */
28 void cpu_loop_exit(void)
30 longjmp(env->jmp_env, 1);
33 void do_raise_exception_err (uint32_t exception, int error_code)
36 if (logfile && exception < 0x100)
37 fprintf(logfile, "%s: %d %d\n", __func__, exception, error_code);
39 env->exception_index = exception;
40 env->error_code = error_code;
45 void do_raise_exception (uint32_t exception)
47 do_raise_exception_err(exception, 0);
50 void do_restore_state (void *pc_ptr)
53 unsigned long pc = (unsigned long) pc_ptr;
56 cpu_restore_state (tb, env, pc, NULL);
59 void do_raise_exception_direct (uint32_t exception)
61 do_restore_state (GETPC ());
62 do_raise_exception_err (exception, 0);
65 #define MEMSUFFIX _raw
66 #include "op_helper_mem.c"
68 #if !defined(CONFIG_USER_ONLY)
69 #define MEMSUFFIX _user
70 #include "op_helper_mem.c"
72 #define MEMSUFFIX _kernel
73 #include "op_helper_mem.c"
77 #ifdef MIPS_HAS_MIPS64
78 #if TARGET_LONG_BITS > HOST_LONG_BITS
79 /* Those might call libgcc functions. */
92 T0 = (int64_t)T0 >> T1;
97 T0 = (int64_t)T0 >> (T1 + 32);
105 void do_dsrl32 (void)
107 T0 = T0 >> (T1 + 32);
115 tmp = T0 << (0x40 - T1);
116 T0 = (T0 >> T1) | tmp;
121 void do_drotr32 (void)
126 tmp = T0 << (0x40 - (32 + T1));
127 T0 = (T0 >> (32 + T1)) | tmp;
134 T0 = T1 << (T0 & 0x3F);
139 T0 = (int64_t)T1 >> (T0 & 0x3F);
144 T0 = T1 >> (T0 & 0x3F);
147 void do_drotrv (void)
153 tmp = T1 << (0x40 - T0);
154 T0 = (T1 >> T0) | tmp;
158 #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
159 #endif /* MIPS_HAS_MIPS64 */
161 /* 64 bits arithmetic for 32 bits hosts */
162 #if TARGET_LONG_BITS > HOST_LONG_BITS
163 static inline uint64_t get_HILO (void)
165 return (env->HI << 32) | (uint32_t)env->LO;
168 static inline void set_HILO (uint64_t HILO)
170 env->LO = (int32_t)HILO;
171 env->HI = (int32_t)(HILO >> 32);
176 set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
181 set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
188 tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
189 set_HILO((int64_t)get_HILO() + tmp);
196 tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
197 set_HILO(get_HILO() + tmp);
204 tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
205 set_HILO((int64_t)get_HILO() - tmp);
212 tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
213 set_HILO(get_HILO() - tmp);
217 #ifdef MIPS_HAS_MIPS64
221 set_HILO((int64_t)T0 * (int64_t)T1);
224 void do_dmultu (void)
227 set_HILO((uint64_t)T0 * (uint64_t)T1);
233 env->LO = (int64_t)T0 / (int64_t)T1;
234 env->HI = (int64_t)T0 % (int64_t)T1;
247 #if defined(CONFIG_USER_ONLY)
248 void do_mfc0_random (void)
250 cpu_abort(env, "mfc0 random\n");
253 void do_mfc0_count (void)
255 cpu_abort(env, "mfc0 count\n");
258 void cpu_mips_store_count(CPUState *env, uint32_t value)
260 cpu_abort(env, "mtc0 count\n");
263 void cpu_mips_store_compare(CPUState *env, uint32_t value)
265 cpu_abort(env, "mtc0 compare\n");
268 void do_mtc0_status_debug(uint32_t old, uint32_t val)
270 cpu_abort(env, "mtc0 status debug\n");
273 void do_mtc0_status_irqraise_debug (void)
275 cpu_abort(env, "mtc0 status irqraise debug\n");
280 cpu_abort(env, "tlbwi\n");
285 cpu_abort(env, "tlbwr\n");
290 cpu_abort(env, "tlbp\n");
295 cpu_abort(env, "tlbr\n");
298 void cpu_mips_tlb_flush (CPUState *env, int flush_global)
300 cpu_abort(env, "mips_tlb_flush\n");
306 void do_mfc0_random (void)
308 T0 = (int32_t)cpu_mips_get_random(env);
311 void do_mfc0_count (void)
313 T0 = (int32_t)cpu_mips_get_count(env);
316 void do_mtc0_status_debug(uint32_t old, uint32_t val)
318 const uint32_t mask = 0x0000FF00;
319 fprintf(logfile, "Status %08x => %08x Cause %08x (%08x %08x %08x)\n",
320 old, val, env->CP0_Cause, old & mask, val & mask,
321 env->CP0_Cause & mask);
324 void do_mtc0_status_irqraise_debug(void)
326 fprintf(logfile, "Raise pending IRQs\n");
330 #include "softfloat.h"
332 void fpu_handle_exception(void)
334 #ifdef CONFIG_SOFTFLOAT
335 int flags = get_float_exception_flags(&env->fp_status);
336 unsigned int cpuflags = 0, enable, cause = 0;
338 enable = GET_FP_ENABLE(env->fcr31);
340 /* determine current flags */
341 if (flags & float_flag_invalid) {
342 cpuflags |= FP_INVALID;
343 cause |= FP_INVALID & enable;
345 if (flags & float_flag_divbyzero) {
347 cause |= FP_DIV0 & enable;
349 if (flags & float_flag_overflow) {
350 cpuflags |= FP_OVERFLOW;
351 cause |= FP_OVERFLOW & enable;
353 if (flags & float_flag_underflow) {
354 cpuflags |= FP_UNDERFLOW;
355 cause |= FP_UNDERFLOW & enable;
357 if (flags & float_flag_inexact) {
358 cpuflags |= FP_INEXACT;
359 cause |= FP_INEXACT & enable;
361 SET_FP_FLAGS(env->fcr31, cpuflags);
362 SET_FP_CAUSE(env->fcr31, cause);
364 SET_FP_FLAGS(env->fcr31, 0);
365 SET_FP_CAUSE(env->fcr31, 0);
368 #endif /* MIPS_USES_FPU */
371 #if defined(MIPS_USES_R4K_TLB)
372 void cpu_mips_tlb_flush (CPUState *env, int flush_global)
374 /* Flush qemu's TLB and discard all shadowed entries. */
375 tlb_flush (env, flush_global);
376 env->tlb_in_use = MIPS_TLB_NB;
379 static void invalidate_tlb (int idx, int use_extra)
385 ASID = env->CP0_EntryHi & 0xFF;
387 tlb = &env->tlb[idx];
388 /* The qemu TLB is flushed then the ASID changes, so no need to
389 flush these entries again. */
390 if (tlb->G == 0 && tlb->ASID != ASID) {
394 if (use_extra && env->tlb_in_use < MIPS_TLB_MAX) {
395 /* For tlbwr, we can shadow the discarded entry into
396 a new (fake) TLB entry, as long as the guest can not
397 tell that it's there. */
398 env->tlb[env->tlb_in_use] = *tlb;
404 tb_invalidate_page_range(tlb->PFN[0], tlb->end - tlb->VPN);
406 while (addr < tlb->end) {
407 tlb_flush_page (env, addr);
408 addr += TARGET_PAGE_SIZE;
412 tb_invalidate_page_range(tlb->PFN[1], tlb->end2 - tlb->end);
414 while (addr < tlb->end2) {
415 tlb_flush_page (env, addr);
416 addr += TARGET_PAGE_SIZE;
421 static void mips_tlb_flush_extra (CPUState *env, int first)
423 /* Discard entries from env->tlb[first] onwards. */
424 while (env->tlb_in_use > first) {
425 invalidate_tlb(--env->tlb_in_use, 0);
429 static void fill_tlb (int idx)
434 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
435 tlb = &env->tlb[idx];
436 tlb->VPN = env->CP0_EntryHi & (int32_t)0xFFFFE000;
437 tlb->ASID = env->CP0_EntryHi & 0xFF;
438 size = env->CP0_PageMask >> 13;
439 size = 4 * (size + 1);
440 tlb->end = tlb->VPN + (1 << (8 + size));
441 tlb->end2 = tlb->end + (1 << (8 + size));
442 tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
443 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
444 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
445 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
446 tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
447 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
448 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
449 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
450 tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
455 /* Discard cached TLB entries. We could avoid doing this if the
456 tlbwi is just upgrading access permissions on the current entry;
457 that might be a further win. */
458 mips_tlb_flush_extra (env, MIPS_TLB_NB);
460 /* Wildly undefined effects for CP0_index containing a too high value and
461 MIPS_TLB_NB not being a power of two. But so does real silicon. */
462 invalidate_tlb(env->CP0_index & (MIPS_TLB_NB - 1), 0);
463 fill_tlb(env->CP0_index & (MIPS_TLB_NB - 1));
468 int r = cpu_mips_get_random(env);
470 invalidate_tlb(r, 1);
481 tag = env->CP0_EntryHi & (int32_t)0xFFFFE000;
482 ASID = env->CP0_EntryHi & 0xFF;
483 for (i = 0; i < MIPS_TLB_NB; i++) {
485 /* Check ASID, virtual page number & size */
486 if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) {
492 if (i == MIPS_TLB_NB) {
493 /* No match. Discard any shadow entries, if any of them match. */
494 for (i = MIPS_TLB_NB; i < env->tlb_in_use; i++) {
497 /* Check ASID, virtual page number & size */
498 if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) {
499 mips_tlb_flush_extra (env, i);
504 env->CP0_index |= 0x80000000;
514 ASID = env->CP0_EntryHi & 0xFF;
515 tlb = &env->tlb[env->CP0_index & (MIPS_TLB_NB - 1)];
517 /* If this will change the current ASID, flush qemu's TLB. */
518 if (ASID != tlb->ASID)
519 cpu_mips_tlb_flush (env, 1);
521 mips_tlb_flush_extra(env, MIPS_TLB_NB);
523 env->CP0_EntryHi = tlb->VPN | tlb->ASID;
524 size = (tlb->end - tlb->VPN) >> 12;
525 env->CP0_PageMask = (size - 1) << 13;
526 env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
527 (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
528 env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
529 (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
533 #endif /* !CONFIG_USER_ONLY */
535 void dump_ldst (const unsigned char *func)
538 fprintf(logfile, "%s => " TLSZ " " TLSZ "\n", __func__, T0, T1);
544 fprintf(logfile, "%s " TLSZ " at " TLSZ " (" TLSZ ")\n", __func__,
545 T1, T0, env->CP0_LLAddr);
549 void debug_eret (void)
552 fprintf(logfile, "ERET: pc " TLSZ " EPC " TLSZ " ErrorEPC " TLSZ " (%d)\n",
553 env->PC, env->CP0_EPC, env->CP0_ErrorEPC,
554 env->hflags & MIPS_HFLAG_ERL ? 1 : 0);
558 void do_pmon (int function)
562 case 2: /* TODO: char inbyte(int waitflag); */
563 if (env->gpr[4] == 0)
566 case 11: /* TODO: char inbyte (void); */
571 printf("%c", (char)(env->gpr[4] & 0xFF));
577 unsigned char *fmt = (void *)(unsigned long)env->gpr[4];
584 #if !defined(CONFIG_USER_ONLY)
586 static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr);
588 #define MMUSUFFIX _mmu
592 #include "softmmu_template.h"
595 #include "softmmu_template.h"
598 #include "softmmu_template.h"
601 #include "softmmu_template.h"
603 static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr)
605 env->CP0_BadVAddr = addr;
606 do_restore_state (retaddr);
607 do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
610 void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr)
612 TranslationBlock *tb;
617 /* XXX: hack to restore env in all cases, even if not called from
620 env = cpu_single_env;
621 ret = cpu_mips_handle_mmu_fault(env, addr, is_write, is_user, 1);
624 /* now we have a real cpu fault */
625 pc = (unsigned long)retaddr;
628 /* the PC is inside the translated code. It means that we have
629 a virtual CPU fault */
630 cpu_restore_state(tb, env, pc, NULL);
633 do_raise_exception_err(env->exception_index, env->error_code);