2 * MIPS emulation helpers for qemu.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #include "host-utils.h"
26 # define GETPC() ((void*)((unsigned long)__builtin_return_address(0) & 0x7fffffffUL))
28 # define GETPC() (__builtin_return_address(0))
31 /*****************************************************************************/
32 /* Exceptions processing helpers */
34 void do_raise_exception_err (uint32_t exception, int error_code)
37 if (logfile && exception < 0x100)
38 fprintf(logfile, "%s: %d %d\n", __func__, exception, error_code);
40 env->exception_index = exception;
41 env->error_code = error_code;
46 void do_raise_exception (uint32_t exception)
48 do_raise_exception_err(exception, 0);
51 void do_interrupt_restart (void)
53 if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
54 !(env->CP0_Status & (1 << CP0St_ERL)) &&
55 !(env->hflags & MIPS_HFLAG_DM) &&
56 (env->CP0_Status & (1 << CP0St_IE)) &&
57 (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask)) {
58 env->CP0_Cause &= ~(0x1f << CP0Ca_EC);
59 do_raise_exception(EXCP_EXT_INTERRUPT);
63 void do_restore_state (void *pc_ptr)
66 unsigned long pc = (unsigned long) pc_ptr;
70 cpu_restore_state (tb, env, pc, NULL);
84 #if defined(TARGET_MIPS64)
85 #if TARGET_LONG_BITS > HOST_LONG_BITS
86 /* Those might call libgcc functions. */
99 T0 = (int64_t)T0 >> T1;
102 void do_dsra32 (void)
104 T0 = (int64_t)T0 >> (T1 + 32);
112 void do_dsrl32 (void)
114 T0 = T0 >> (T1 + 32);
122 tmp = T0 << (0x40 - T1);
123 T0 = (T0 >> T1) | tmp;
127 void do_drotr32 (void)
131 tmp = T0 << (0x40 - (32 + T1));
132 T0 = (T0 >> (32 + T1)) | tmp;
137 T0 = T1 << (T0 & 0x3F);
142 T0 = (int64_t)T1 >> (T0 & 0x3F);
147 T0 = T1 >> (T0 & 0x3F);
150 void do_drotrv (void)
156 tmp = T1 << (0x40 - T0);
157 T0 = (T1 >> T0) | tmp;
162 #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
174 #endif /* TARGET_MIPS64 */
176 /* 64 bits arithmetic for 32 bits hosts */
177 #if TARGET_LONG_BITS > HOST_LONG_BITS
178 static always_inline uint64_t get_HILO (void)
180 return (env->HI[env->current_tc][0] << 32) | (uint32_t)env->LO[env->current_tc][0];
183 static always_inline void set_HILO (uint64_t HILO)
185 env->LO[env->current_tc][0] = (int32_t)HILO;
186 env->HI[env->current_tc][0] = (int32_t)(HILO >> 32);
189 static always_inline void set_HIT0_LO (uint64_t HILO)
191 env->LO[env->current_tc][0] = (int32_t)(HILO & 0xFFFFFFFF);
192 T0 = env->HI[env->current_tc][0] = (int32_t)(HILO >> 32);
195 static always_inline void set_HI_LOT0 (uint64_t HILO)
197 T0 = env->LO[env->current_tc][0] = (int32_t)(HILO & 0xFFFFFFFF);
198 env->HI[env->current_tc][0] = (int32_t)(HILO >> 32);
203 set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
208 set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
215 tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
216 set_HILO((int64_t)get_HILO() + tmp);
223 tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
224 set_HILO(get_HILO() + tmp);
231 tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
232 set_HILO((int64_t)get_HILO() - tmp);
239 tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
240 set_HILO(get_HILO() - tmp);
243 /* Multiplication variants of the vr54xx. */
246 set_HI_LOT0(0 - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
251 set_HI_LOT0(0 - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
256 set_HI_LOT0(((int64_t)get_HILO()) + ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
259 void do_macchi (void)
261 set_HIT0_LO(((int64_t)get_HILO()) + ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
266 set_HI_LOT0(((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
269 void do_macchiu (void)
271 set_HIT0_LO(((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
276 set_HI_LOT0(((int64_t)get_HILO()) - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
279 void do_msachi (void)
281 set_HIT0_LO(((int64_t)get_HILO()) - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
286 set_HI_LOT0(((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
289 void do_msachiu (void)
291 set_HIT0_LO(((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
296 set_HIT0_LO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
299 void do_mulhiu (void)
301 set_HIT0_LO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
304 void do_mulshi (void)
306 set_HIT0_LO(0 - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
309 void do_mulshiu (void)
311 set_HIT0_LO(0 - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
313 #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
315 #if defined(CONFIG_USER_ONLY)
316 void do_mfc0_random (void)
318 cpu_abort(env, "mfc0 random\n");
321 void do_mfc0_count (void)
323 cpu_abort(env, "mfc0 count\n");
326 void cpu_mips_store_count(CPUState *env, uint32_t value)
328 cpu_abort(env, "mtc0 count\n");
331 void cpu_mips_store_compare(CPUState *env, uint32_t value)
333 cpu_abort(env, "mtc0 compare\n");
336 void cpu_mips_start_count(CPUState *env)
338 cpu_abort(env, "start count\n");
341 void cpu_mips_stop_count(CPUState *env)
343 cpu_abort(env, "stop count\n");
346 void cpu_mips_update_irq(CPUState *env)
348 cpu_abort(env, "mtc0 status / mtc0 cause\n");
351 void do_mtc0_status_debug(uint32_t old, uint32_t val)
353 cpu_abort(env, "mtc0 status debug\n");
356 void do_mtc0_status_irqraise_debug (void)
358 cpu_abort(env, "mtc0 status irqraise debug\n");
361 void cpu_mips_tlb_flush (CPUState *env, int flush_global)
363 cpu_abort(env, "mips_tlb_flush\n");
369 void do_mfc0_random (void)
371 T0 = (int32_t)cpu_mips_get_random(env);
374 void do_mfc0_count (void)
376 T0 = (int32_t)cpu_mips_get_count(env);
379 void do_mtc0_status_debug(uint32_t old, uint32_t val)
381 fprintf(logfile, "Status %08x (%08x) => %08x (%08x) Cause %08x",
382 old, old & env->CP0_Cause & CP0Ca_IP_mask,
383 val, val & env->CP0_Cause & CP0Ca_IP_mask,
385 switch (env->hflags & MIPS_HFLAG_KSU) {
386 case MIPS_HFLAG_UM: fputs(", UM\n", logfile); break;
387 case MIPS_HFLAG_SM: fputs(", SM\n", logfile); break;
388 case MIPS_HFLAG_KM: fputs("\n", logfile); break;
389 default: cpu_abort(env, "Invalid MMU mode!\n"); break;
393 void do_mtc0_status_irqraise_debug(void)
395 fprintf(logfile, "Raise pending IRQs\n");
398 void fpu_handle_exception(void)
400 #ifdef CONFIG_SOFTFLOAT
401 int flags = get_float_exception_flags(&env->fpu->fp_status);
402 unsigned int cpuflags = 0, enable, cause = 0;
404 enable = GET_FP_ENABLE(env->fpu->fcr31);
406 /* determine current flags */
407 if (flags & float_flag_invalid) {
408 cpuflags |= FP_INVALID;
409 cause |= FP_INVALID & enable;
411 if (flags & float_flag_divbyzero) {
413 cause |= FP_DIV0 & enable;
415 if (flags & float_flag_overflow) {
416 cpuflags |= FP_OVERFLOW;
417 cause |= FP_OVERFLOW & enable;
419 if (flags & float_flag_underflow) {
420 cpuflags |= FP_UNDERFLOW;
421 cause |= FP_UNDERFLOW & enable;
423 if (flags & float_flag_inexact) {
424 cpuflags |= FP_INEXACT;
425 cause |= FP_INEXACT & enable;
427 SET_FP_FLAGS(env->fpu->fcr31, cpuflags);
428 SET_FP_CAUSE(env->fpu->fcr31, cause);
430 SET_FP_FLAGS(env->fpu->fcr31, 0);
431 SET_FP_CAUSE(env->fpu->fcr31, 0);
436 void cpu_mips_tlb_flush (CPUState *env, int flush_global)
438 /* Flush qemu's TLB and discard all shadowed entries. */
439 tlb_flush (env, flush_global);
440 env->tlb->tlb_in_use = env->tlb->nb_tlb;
443 static void r4k_mips_tlb_flush_extra (CPUState *env, int first)
445 /* Discard entries from env->tlb[first] onwards. */
446 while (env->tlb->tlb_in_use > first) {
447 r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
451 static void r4k_fill_tlb (int idx)
455 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
456 tlb = &env->tlb->mmu.r4k.tlb[idx];
457 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
458 #if defined(TARGET_MIPS64)
459 tlb->VPN &= env->SEGMask;
461 tlb->ASID = env->CP0_EntryHi & 0xFF;
462 tlb->PageMask = env->CP0_PageMask;
463 tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
464 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
465 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
466 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
467 tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
468 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
469 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
470 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
471 tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
474 void r4k_do_tlbwi (void)
476 /* Discard cached TLB entries. We could avoid doing this if the
477 tlbwi is just upgrading access permissions on the current entry;
478 that might be a further win. */
479 r4k_mips_tlb_flush_extra (env, env->tlb->nb_tlb);
481 r4k_invalidate_tlb(env, env->CP0_Index % env->tlb->nb_tlb, 0);
482 r4k_fill_tlb(env->CP0_Index % env->tlb->nb_tlb);
485 void r4k_do_tlbwr (void)
487 int r = cpu_mips_get_random(env);
489 r4k_invalidate_tlb(env, r, 1);
493 void r4k_do_tlbp (void)
502 ASID = env->CP0_EntryHi & 0xFF;
503 for (i = 0; i < env->tlb->nb_tlb; i++) {
504 tlb = &env->tlb->mmu.r4k.tlb[i];
505 /* 1k pages are not supported. */
506 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
507 tag = env->CP0_EntryHi & ~mask;
508 VPN = tlb->VPN & ~mask;
509 /* Check ASID, virtual page number & size */
510 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
516 if (i == env->tlb->nb_tlb) {
517 /* No match. Discard any shadow entries, if any of them match. */
518 for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
519 tlb = &env->tlb->mmu.r4k.tlb[i];
520 /* 1k pages are not supported. */
521 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
522 tag = env->CP0_EntryHi & ~mask;
523 VPN = tlb->VPN & ~mask;
524 /* Check ASID, virtual page number & size */
525 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
526 r4k_mips_tlb_flush_extra (env, i);
531 env->CP0_Index |= 0x80000000;
535 void r4k_do_tlbr (void)
540 ASID = env->CP0_EntryHi & 0xFF;
541 tlb = &env->tlb->mmu.r4k.tlb[env->CP0_Index % env->tlb->nb_tlb];
543 /* If this will change the current ASID, flush qemu's TLB. */
544 if (ASID != tlb->ASID)
545 cpu_mips_tlb_flush (env, 1);
547 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
549 env->CP0_EntryHi = tlb->VPN | tlb->ASID;
550 env->CP0_PageMask = tlb->PageMask;
551 env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
552 (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
553 env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
554 (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
557 #endif /* !CONFIG_USER_ONLY */
559 void dump_ldst (const unsigned char *func)
562 fprintf(logfile, "%s => " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__, T0, T1);
568 fprintf(logfile, "%s " TARGET_FMT_lx " at " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", __func__,
569 T1, T0, env->CP0_LLAddr);
573 void debug_pre_eret (void)
575 fprintf(logfile, "ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
576 env->PC[env->current_tc], env->CP0_EPC);
577 if (env->CP0_Status & (1 << CP0St_ERL))
578 fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
579 if (env->hflags & MIPS_HFLAG_DM)
580 fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
581 fputs("\n", logfile);
584 void debug_post_eret (void)
586 fprintf(logfile, " => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
587 env->PC[env->current_tc], env->CP0_EPC);
588 if (env->CP0_Status & (1 << CP0St_ERL))
589 fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
590 if (env->hflags & MIPS_HFLAG_DM)
591 fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
592 switch (env->hflags & MIPS_HFLAG_KSU) {
593 case MIPS_HFLAG_UM: fputs(", UM\n", logfile); break;
594 case MIPS_HFLAG_SM: fputs(", SM\n", logfile); break;
595 case MIPS_HFLAG_KM: fputs("\n", logfile); break;
596 default: cpu_abort(env, "Invalid MMU mode!\n"); break;
600 void do_pmon (int function)
604 case 2: /* TODO: char inbyte(int waitflag); */
605 if (env->gpr[env->current_tc][4] == 0)
606 env->gpr[env->current_tc][2] = -1;
608 case 11: /* TODO: char inbyte (void); */
609 env->gpr[env->current_tc][2] = -1;
613 printf("%c", (char)(env->gpr[env->current_tc][4] & 0xFF));
619 unsigned char *fmt = (void *)(unsigned long)env->gpr[env->current_tc][4];
626 #if !defined(CONFIG_USER_ONLY)
628 static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr);
630 #define MMUSUFFIX _mmu
634 #include "softmmu_template.h"
637 #include "softmmu_template.h"
640 #include "softmmu_template.h"
643 #include "softmmu_template.h"
645 static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr)
647 env->CP0_BadVAddr = addr;
648 do_restore_state (retaddr);
649 do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
652 void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
654 TranslationBlock *tb;
659 /* XXX: hack to restore env in all cases, even if not called from
662 env = cpu_single_env;
663 ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
666 /* now we have a real cpu fault */
667 pc = (unsigned long)retaddr;
670 /* the PC is inside the translated code. It means that we have
671 a virtual CPU fault */
672 cpu_restore_state(tb, env, pc, NULL);
675 do_raise_exception_err(env->exception_index, env->error_code);
680 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
684 do_raise_exception(EXCP_IBE);
686 do_raise_exception(EXCP_DBE);
690 /* Complex FPU operations which may need stack space. */
692 #define FLOAT_ONE32 make_float32(0x3f8 << 20)
693 #define FLOAT_ONE64 make_float64(0x3ffULL << 52)
694 #define FLOAT_TWO32 make_float32(1 << 30)
695 #define FLOAT_TWO64 make_float64(1ULL << 62)
696 #define FLOAT_QNAN32 0x7fbfffff
697 #define FLOAT_QNAN64 0x7ff7ffffffffffffULL
698 #define FLOAT_SNAN32 0x7fffffff
699 #define FLOAT_SNAN64 0x7fffffffffffffffULL
701 /* convert MIPS rounding mode in FCR31 to IEEE library */
702 unsigned int ieee_rm[] = {
703 float_round_nearest_even,
709 #define RESTORE_ROUNDING_MODE \
710 set_float_rounding_mode(ieee_rm[env->fpu->fcr31 & 3], &env->fpu->fp_status)
712 void do_cfc1 (int reg)
716 T0 = (int32_t)env->fpu->fcr0;
719 T0 = ((env->fpu->fcr31 >> 24) & 0xfe) | ((env->fpu->fcr31 >> 23) & 0x1);
722 T0 = env->fpu->fcr31 & 0x0003f07c;
725 T0 = (env->fpu->fcr31 & 0x00000f83) | ((env->fpu->fcr31 >> 22) & 0x4);
728 T0 = (int32_t)env->fpu->fcr31;
733 void do_ctc1 (int reg)
739 env->fpu->fcr31 = (env->fpu->fcr31 & 0x017fffff) | ((T0 & 0xfe) << 24) |
745 env->fpu->fcr31 = (env->fpu->fcr31 & 0xfffc0f83) | (T0 & 0x0003f07c);
750 env->fpu->fcr31 = (env->fpu->fcr31 & 0xfefff07c) | (T0 & 0x00000f83) |
756 env->fpu->fcr31 = T0;
761 /* set rounding mode */
762 RESTORE_ROUNDING_MODE;
763 set_float_exception_flags(0, &env->fpu->fp_status);
764 if ((GET_FP_ENABLE(env->fpu->fcr31) | 0x20) & GET_FP_CAUSE(env->fpu->fcr31))
765 do_raise_exception(EXCP_FPE);
768 static always_inline char ieee_ex_to_mips(char xcpt)
770 return (xcpt & float_flag_inexact) >> 5 |
771 (xcpt & float_flag_underflow) >> 3 |
772 (xcpt & float_flag_overflow) >> 1 |
773 (xcpt & float_flag_divbyzero) << 1 |
774 (xcpt & float_flag_invalid) << 4;
777 static always_inline char mips_ex_to_ieee(char xcpt)
779 return (xcpt & FP_INEXACT) << 5 |
780 (xcpt & FP_UNDERFLOW) << 3 |
781 (xcpt & FP_OVERFLOW) << 1 |
782 (xcpt & FP_DIV0) >> 1 |
783 (xcpt & FP_INVALID) >> 4;
786 static always_inline void update_fcr31(void)
788 int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->fpu->fp_status));
790 SET_FP_CAUSE(env->fpu->fcr31, tmp);
791 if (GET_FP_ENABLE(env->fpu->fcr31) & tmp)
792 do_raise_exception(EXCP_FPE);
794 UPDATE_FP_FLAGS(env->fpu->fcr31, tmp);
797 #define FLOAT_OP(name, p) void do_float_##name##_##p(void)
801 set_float_exception_flags(0, &env->fpu->fp_status);
802 FDT2 = float32_to_float64(FST0, &env->fpu->fp_status);
807 set_float_exception_flags(0, &env->fpu->fp_status);
808 FDT2 = int32_to_float64(WT0, &env->fpu->fp_status);
813 set_float_exception_flags(0, &env->fpu->fp_status);
814 FDT2 = int64_to_float64(DT0, &env->fpu->fp_status);
819 set_float_exception_flags(0, &env->fpu->fp_status);
820 DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
822 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
827 set_float_exception_flags(0, &env->fpu->fp_status);
828 DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
830 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
836 set_float_exception_flags(0, &env->fpu->fp_status);
837 FST2 = int32_to_float32(WT0, &env->fpu->fp_status);
838 FSTH2 = int32_to_float32(WTH0, &env->fpu->fp_status);
843 set_float_exception_flags(0, &env->fpu->fp_status);
844 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
845 WTH2 = float32_to_int32(FSTH0, &env->fpu->fp_status);
847 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
852 set_float_exception_flags(0, &env->fpu->fp_status);
853 FST2 = float64_to_float32(FDT0, &env->fpu->fp_status);
858 set_float_exception_flags(0, &env->fpu->fp_status);
859 FST2 = int32_to_float32(WT0, &env->fpu->fp_status);
864 set_float_exception_flags(0, &env->fpu->fp_status);
865 FST2 = int64_to_float32(DT0, &env->fpu->fp_status);
870 set_float_exception_flags(0, &env->fpu->fp_status);
876 set_float_exception_flags(0, &env->fpu->fp_status);
882 set_float_exception_flags(0, &env->fpu->fp_status);
883 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
885 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
890 set_float_exception_flags(0, &env->fpu->fp_status);
891 WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
893 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
899 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
900 DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
901 RESTORE_ROUNDING_MODE;
903 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
908 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
909 DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
910 RESTORE_ROUNDING_MODE;
912 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
917 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
918 WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
919 RESTORE_ROUNDING_MODE;
921 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
926 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
927 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
928 RESTORE_ROUNDING_MODE;
930 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
936 DT2 = float64_to_int64_round_to_zero(FDT0, &env->fpu->fp_status);
938 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
943 DT2 = float32_to_int64_round_to_zero(FST0, &env->fpu->fp_status);
945 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
950 WT2 = float64_to_int32_round_to_zero(FDT0, &env->fpu->fp_status);
952 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
957 WT2 = float32_to_int32_round_to_zero(FST0, &env->fpu->fp_status);
959 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
965 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
966 DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
967 RESTORE_ROUNDING_MODE;
969 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
974 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
975 DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
976 RESTORE_ROUNDING_MODE;
978 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
983 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
984 WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
985 RESTORE_ROUNDING_MODE;
987 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
992 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
993 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
994 RESTORE_ROUNDING_MODE;
996 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
1002 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
1003 DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
1004 RESTORE_ROUNDING_MODE;
1006 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
1011 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
1012 DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
1013 RESTORE_ROUNDING_MODE;
1015 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
1020 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
1021 WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
1022 RESTORE_ROUNDING_MODE;
1024 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
1029 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
1030 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
1031 RESTORE_ROUNDING_MODE;
1033 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
1037 /* MIPS specific unary operations */
1040 set_float_exception_flags(0, &env->fpu->fp_status);
1041 FDT2 = float64_div(FLOAT_ONE64, FDT0, &env->fpu->fp_status);
1046 set_float_exception_flags(0, &env->fpu->fp_status);
1047 FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status);
1053 set_float_exception_flags(0, &env->fpu->fp_status);
1054 FDT2 = float64_sqrt(FDT0, &env->fpu->fp_status);
1055 FDT2 = float64_div(FLOAT_ONE64, FDT2, &env->fpu->fp_status);
1060 set_float_exception_flags(0, &env->fpu->fp_status);
1061 FST2 = float32_sqrt(FST0, &env->fpu->fp_status);
1062 FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status);
1068 set_float_exception_flags(0, &env->fpu->fp_status);
1069 FDT2 = float64_div(FLOAT_ONE64, FDT0, &env->fpu->fp_status);
1074 set_float_exception_flags(0, &env->fpu->fp_status);
1075 FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status);
1078 FLOAT_OP(recip1, ps)
1080 set_float_exception_flags(0, &env->fpu->fp_status);
1081 FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status);
1082 FSTH2 = float32_div(FLOAT_ONE32, FSTH0, &env->fpu->fp_status);
1088 set_float_exception_flags(0, &env->fpu->fp_status);
1089 FDT2 = float64_sqrt(FDT0, &env->fpu->fp_status);
1090 FDT2 = float64_div(FLOAT_ONE64, FDT2, &env->fpu->fp_status);
1095 set_float_exception_flags(0, &env->fpu->fp_status);
1096 FST2 = float32_sqrt(FST0, &env->fpu->fp_status);
1097 FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status);
1100 FLOAT_OP(rsqrt1, ps)
1102 set_float_exception_flags(0, &env->fpu->fp_status);
1103 FST2 = float32_sqrt(FST0, &env->fpu->fp_status);
1104 FSTH2 = float32_sqrt(FSTH0, &env->fpu->fp_status);
1105 FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status);
1106 FSTH2 = float32_div(FLOAT_ONE32, FSTH2, &env->fpu->fp_status);
1110 /* binary operations */
1111 #define FLOAT_BINOP(name) \
1114 set_float_exception_flags(0, &env->fpu->fp_status); \
1115 FDT2 = float64_ ## name (FDT0, FDT1, &env->fpu->fp_status); \
1117 if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \
1118 DT2 = FLOAT_QNAN64; \
1122 set_float_exception_flags(0, &env->fpu->fp_status); \
1123 FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status); \
1125 if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \
1126 WT2 = FLOAT_QNAN32; \
1128 FLOAT_OP(name, ps) \
1130 set_float_exception_flags(0, &env->fpu->fp_status); \
1131 FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status); \
1132 FSTH2 = float32_ ## name (FSTH0, FSTH1, &env->fpu->fp_status); \
1134 if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) { \
1135 WT2 = FLOAT_QNAN32; \
1136 WTH2 = FLOAT_QNAN32; \
1145 /* MIPS specific binary operations */
1148 set_float_exception_flags(0, &env->fpu->fp_status);
1149 FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status);
1150 FDT2 = float64_chs(float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status));
1155 set_float_exception_flags(0, &env->fpu->fp_status);
1156 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
1157 FST2 = float32_chs(float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status));
1160 FLOAT_OP(recip2, ps)
1162 set_float_exception_flags(0, &env->fpu->fp_status);
1163 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
1164 FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status);
1165 FST2 = float32_chs(float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status));
1166 FSTH2 = float32_chs(float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status));
1172 set_float_exception_flags(0, &env->fpu->fp_status);
1173 FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status);
1174 FDT2 = float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status);
1175 FDT2 = float64_chs(float64_div(FDT2, FLOAT_TWO64, &env->fpu->fp_status));
1180 set_float_exception_flags(0, &env->fpu->fp_status);
1181 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
1182 FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status);
1183 FST2 = float32_chs(float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status));
1186 FLOAT_OP(rsqrt2, ps)
1188 set_float_exception_flags(0, &env->fpu->fp_status);
1189 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
1190 FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status);
1191 FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status);
1192 FSTH2 = float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status);
1193 FST2 = float32_chs(float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status));
1194 FSTH2 = float32_chs(float32_div(FSTH2, FLOAT_TWO32, &env->fpu->fp_status));
1200 set_float_exception_flags(0, &env->fpu->fp_status);
1201 FST2 = float32_add (FST0, FSTH0, &env->fpu->fp_status);
1202 FSTH2 = float32_add (FST1, FSTH1, &env->fpu->fp_status);
1208 set_float_exception_flags(0, &env->fpu->fp_status);
1209 FST2 = float32_mul (FST0, FSTH0, &env->fpu->fp_status);
1210 FSTH2 = float32_mul (FST1, FSTH1, &env->fpu->fp_status);
1214 /* compare operations */
1215 #define FOP_COND_D(op, cond) \
1216 void do_cmp_d_ ## op (long cc) \
1221 SET_FP_COND(cc, env->fpu); \
1223 CLEAR_FP_COND(cc, env->fpu); \
1225 void do_cmpabs_d_ ## op (long cc) \
1228 FDT0 = float64_abs(FDT0); \
1229 FDT1 = float64_abs(FDT1); \
1233 SET_FP_COND(cc, env->fpu); \
1235 CLEAR_FP_COND(cc, env->fpu); \
1238 int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM)
1240 if (float64_is_signaling_nan(a) ||
1241 float64_is_signaling_nan(b) ||
1242 (sig && (float64_is_nan(a) || float64_is_nan(b)))) {
1243 float_raise(float_flag_invalid, status);
1245 } else if (float64_is_nan(a) || float64_is_nan(b)) {
1252 /* NOTE: the comma operator will make "cond" to eval to false,
1253 * but float*_is_unordered() is still called. */
1254 FOP_COND_D(f, (float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status), 0))
1255 FOP_COND_D(un, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status))
1256 FOP_COND_D(eq, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_eq(FDT0, FDT1, &env->fpu->fp_status))
1257 FOP_COND_D(ueq, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_eq(FDT0, FDT1, &env->fpu->fp_status))
1258 FOP_COND_D(olt, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_lt(FDT0, FDT1, &env->fpu->fp_status))
1259 FOP_COND_D(ult, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_lt(FDT0, FDT1, &env->fpu->fp_status))
1260 FOP_COND_D(ole, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_le(FDT0, FDT1, &env->fpu->fp_status))
1261 FOP_COND_D(ule, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_le(FDT0, FDT1, &env->fpu->fp_status))
1262 /* NOTE: the comma operator will make "cond" to eval to false,
1263 * but float*_is_unordered() is still called. */
1264 FOP_COND_D(sf, (float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status), 0))
1265 FOP_COND_D(ngle,float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status))
1266 FOP_COND_D(seq, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_eq(FDT0, FDT1, &env->fpu->fp_status))
1267 FOP_COND_D(ngl, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_eq(FDT0, FDT1, &env->fpu->fp_status))
1268 FOP_COND_D(lt, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_lt(FDT0, FDT1, &env->fpu->fp_status))
1269 FOP_COND_D(nge, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_lt(FDT0, FDT1, &env->fpu->fp_status))
1270 FOP_COND_D(le, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_le(FDT0, FDT1, &env->fpu->fp_status))
1271 FOP_COND_D(ngt, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_le(FDT0, FDT1, &env->fpu->fp_status))
1273 #define FOP_COND_S(op, cond) \
1274 void do_cmp_s_ ## op (long cc) \
1279 SET_FP_COND(cc, env->fpu); \
1281 CLEAR_FP_COND(cc, env->fpu); \
1283 void do_cmpabs_s_ ## op (long cc) \
1286 FST0 = float32_abs(FST0); \
1287 FST1 = float32_abs(FST1); \
1291 SET_FP_COND(cc, env->fpu); \
1293 CLEAR_FP_COND(cc, env->fpu); \
1296 flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM)
1298 if (float32_is_signaling_nan(a) ||
1299 float32_is_signaling_nan(b) ||
1300 (sig && (float32_is_nan(a) || float32_is_nan(b)))) {
1301 float_raise(float_flag_invalid, status);
1303 } else if (float32_is_nan(a) || float32_is_nan(b)) {
1310 /* NOTE: the comma operator will make "cond" to eval to false,
1311 * but float*_is_unordered() is still called. */
1312 FOP_COND_S(f, (float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status), 0))
1313 FOP_COND_S(un, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status))
1314 FOP_COND_S(eq, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status))
1315 FOP_COND_S(ueq, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status))
1316 FOP_COND_S(olt, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status))
1317 FOP_COND_S(ult, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status))
1318 FOP_COND_S(ole, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status))
1319 FOP_COND_S(ule, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status))
1320 /* NOTE: the comma operator will make "cond" to eval to false,
1321 * but float*_is_unordered() is still called. */
1322 FOP_COND_S(sf, (float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status), 0))
1323 FOP_COND_S(ngle,float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status))
1324 FOP_COND_S(seq, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status))
1325 FOP_COND_S(ngl, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status))
1326 FOP_COND_S(lt, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status))
1327 FOP_COND_S(nge, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status))
1328 FOP_COND_S(le, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status))
1329 FOP_COND_S(ngt, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status))
1331 #define FOP_COND_PS(op, condl, condh) \
1332 void do_cmp_ps_ ## op (long cc) \
1338 SET_FP_COND(cc, env->fpu); \
1340 CLEAR_FP_COND(cc, env->fpu); \
1342 SET_FP_COND(cc + 1, env->fpu); \
1344 CLEAR_FP_COND(cc + 1, env->fpu); \
1346 void do_cmpabs_ps_ ## op (long cc) \
1349 FST0 = float32_abs(FST0); \
1350 FSTH0 = float32_abs(FSTH0); \
1351 FST1 = float32_abs(FST1); \
1352 FSTH1 = float32_abs(FSTH1); \
1357 SET_FP_COND(cc, env->fpu); \
1359 CLEAR_FP_COND(cc, env->fpu); \
1361 SET_FP_COND(cc + 1, env->fpu); \
1363 CLEAR_FP_COND(cc + 1, env->fpu); \
1366 /* NOTE: the comma operator will make "cond" to eval to false,
1367 * but float*_is_unordered() is still called. */
1368 FOP_COND_PS(f, (float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status), 0),
1369 (float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status), 0))
1370 FOP_COND_PS(un, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status),
1371 float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status))
1372 FOP_COND_PS(eq, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status),
1373 !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
1374 FOP_COND_PS(ueq, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status),
1375 float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
1376 FOP_COND_PS(olt, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status),
1377 !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
1378 FOP_COND_PS(ult, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status),
1379 float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
1380 FOP_COND_PS(ole, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status),
1381 !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
1382 FOP_COND_PS(ule, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status),
1383 float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
1384 /* NOTE: the comma operator will make "cond" to eval to false,
1385 * but float*_is_unordered() is still called. */
1386 FOP_COND_PS(sf, (float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status), 0),
1387 (float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status), 0))
1388 FOP_COND_PS(ngle,float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status),
1389 float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status))
1390 FOP_COND_PS(seq, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status),
1391 !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
1392 FOP_COND_PS(ngl, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status),
1393 float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
1394 FOP_COND_PS(lt, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status),
1395 !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
1396 FOP_COND_PS(nge, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status),
1397 float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
1398 FOP_COND_PS(le, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status),
1399 !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
1400 FOP_COND_PS(ngt, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status),
1401 float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_le(FSTH0, FSTH1, &env->fpu->fp_status))