2 * MIPS32 emulation for qemu: main translation routines.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2006 Marius Groeger (FPU operations)
6 * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
33 #include "qemu-common.h"
39 //#define MIPS_DEBUG_DISAS
40 //#define MIPS_DEBUG_SIGN_EXTENSIONS
42 /* MIPS major opcodes */
43 #define MASK_OP_MAJOR(op) (op & (0x3F << 26))
46 /* indirect opcode tables */
47 OPC_SPECIAL = (0x00 << 26),
48 OPC_REGIMM = (0x01 << 26),
49 OPC_CP0 = (0x10 << 26),
50 OPC_CP1 = (0x11 << 26),
51 OPC_CP2 = (0x12 << 26),
52 OPC_CP3 = (0x13 << 26),
53 OPC_SPECIAL2 = (0x1C << 26),
54 OPC_SPECIAL3 = (0x1F << 26),
55 /* arithmetic with immediate */
56 OPC_ADDI = (0x08 << 26),
57 OPC_ADDIU = (0x09 << 26),
58 OPC_SLTI = (0x0A << 26),
59 OPC_SLTIU = (0x0B << 26),
60 /* logic with immediate */
61 OPC_ANDI = (0x0C << 26),
62 OPC_ORI = (0x0D << 26),
63 OPC_XORI = (0x0E << 26),
64 OPC_LUI = (0x0F << 26),
65 /* arithmetic with immediate */
66 OPC_DADDI = (0x18 << 26),
67 OPC_DADDIU = (0x19 << 26),
68 /* Jump and branches */
70 OPC_JAL = (0x03 << 26),
71 OPC_BEQ = (0x04 << 26), /* Unconditional if rs = rt = 0 (B) */
72 OPC_BEQL = (0x14 << 26),
73 OPC_BNE = (0x05 << 26),
74 OPC_BNEL = (0x15 << 26),
75 OPC_BLEZ = (0x06 << 26),
76 OPC_BLEZL = (0x16 << 26),
77 OPC_BGTZ = (0x07 << 26),
78 OPC_BGTZL = (0x17 << 26),
79 OPC_JALX = (0x1D << 26), /* MIPS 16 only */
81 OPC_LDL = (0x1A << 26),
82 OPC_LDR = (0x1B << 26),
83 OPC_LB = (0x20 << 26),
84 OPC_LH = (0x21 << 26),
85 OPC_LWL = (0x22 << 26),
86 OPC_LW = (0x23 << 26),
87 OPC_LBU = (0x24 << 26),
88 OPC_LHU = (0x25 << 26),
89 OPC_LWR = (0x26 << 26),
90 OPC_LWU = (0x27 << 26),
91 OPC_SB = (0x28 << 26),
92 OPC_SH = (0x29 << 26),
93 OPC_SWL = (0x2A << 26),
94 OPC_SW = (0x2B << 26),
95 OPC_SDL = (0x2C << 26),
96 OPC_SDR = (0x2D << 26),
97 OPC_SWR = (0x2E << 26),
98 OPC_LL = (0x30 << 26),
99 OPC_LLD = (0x34 << 26),
100 OPC_LD = (0x37 << 26),
101 OPC_SC = (0x38 << 26),
102 OPC_SCD = (0x3C << 26),
103 OPC_SD = (0x3F << 26),
104 /* Floating point load/store */
105 OPC_LWC1 = (0x31 << 26),
106 OPC_LWC2 = (0x32 << 26),
107 OPC_LDC1 = (0x35 << 26),
108 OPC_LDC2 = (0x36 << 26),
109 OPC_SWC1 = (0x39 << 26),
110 OPC_SWC2 = (0x3A << 26),
111 OPC_SDC1 = (0x3D << 26),
112 OPC_SDC2 = (0x3E << 26),
113 /* MDMX ASE specific */
114 OPC_MDMX = (0x1E << 26),
115 /* Cache and prefetch */
116 OPC_CACHE = (0x2F << 26),
117 OPC_PREF = (0x33 << 26),
118 /* Reserved major opcode */
119 OPC_MAJOR3B_RESERVED = (0x3B << 26),
122 /* MIPS special opcodes */
123 #define MASK_SPECIAL(op) MASK_OP_MAJOR(op) | (op & 0x3F)
127 OPC_SLL = 0x00 | OPC_SPECIAL,
128 /* NOP is SLL r0, r0, 0 */
129 /* SSNOP is SLL r0, r0, 1 */
130 /* EHB is SLL r0, r0, 3 */
131 OPC_SRL = 0x02 | OPC_SPECIAL, /* also ROTR */
132 OPC_SRA = 0x03 | OPC_SPECIAL,
133 OPC_SLLV = 0x04 | OPC_SPECIAL,
134 OPC_SRLV = 0x06 | OPC_SPECIAL, /* also ROTRV */
135 OPC_SRAV = 0x07 | OPC_SPECIAL,
136 OPC_DSLLV = 0x14 | OPC_SPECIAL,
137 OPC_DSRLV = 0x16 | OPC_SPECIAL, /* also DROTRV */
138 OPC_DSRAV = 0x17 | OPC_SPECIAL,
139 OPC_DSLL = 0x38 | OPC_SPECIAL,
140 OPC_DSRL = 0x3A | OPC_SPECIAL, /* also DROTR */
141 OPC_DSRA = 0x3B | OPC_SPECIAL,
142 OPC_DSLL32 = 0x3C | OPC_SPECIAL,
143 OPC_DSRL32 = 0x3E | OPC_SPECIAL, /* also DROTR32 */
144 OPC_DSRA32 = 0x3F | OPC_SPECIAL,
145 /* Multiplication / division */
146 OPC_MULT = 0x18 | OPC_SPECIAL,
147 OPC_MULTU = 0x19 | OPC_SPECIAL,
148 OPC_DIV = 0x1A | OPC_SPECIAL,
149 OPC_DIVU = 0x1B | OPC_SPECIAL,
150 OPC_DMULT = 0x1C | OPC_SPECIAL,
151 OPC_DMULTU = 0x1D | OPC_SPECIAL,
152 OPC_DDIV = 0x1E | OPC_SPECIAL,
153 OPC_DDIVU = 0x1F | OPC_SPECIAL,
154 /* 2 registers arithmetic / logic */
155 OPC_ADD = 0x20 | OPC_SPECIAL,
156 OPC_ADDU = 0x21 | OPC_SPECIAL,
157 OPC_SUB = 0x22 | OPC_SPECIAL,
158 OPC_SUBU = 0x23 | OPC_SPECIAL,
159 OPC_AND = 0x24 | OPC_SPECIAL,
160 OPC_OR = 0x25 | OPC_SPECIAL,
161 OPC_XOR = 0x26 | OPC_SPECIAL,
162 OPC_NOR = 0x27 | OPC_SPECIAL,
163 OPC_SLT = 0x2A | OPC_SPECIAL,
164 OPC_SLTU = 0x2B | OPC_SPECIAL,
165 OPC_DADD = 0x2C | OPC_SPECIAL,
166 OPC_DADDU = 0x2D | OPC_SPECIAL,
167 OPC_DSUB = 0x2E | OPC_SPECIAL,
168 OPC_DSUBU = 0x2F | OPC_SPECIAL,
170 OPC_JR = 0x08 | OPC_SPECIAL, /* Also JR.HB */
171 OPC_JALR = 0x09 | OPC_SPECIAL, /* Also JALR.HB */
173 OPC_TGE = 0x30 | OPC_SPECIAL,
174 OPC_TGEU = 0x31 | OPC_SPECIAL,
175 OPC_TLT = 0x32 | OPC_SPECIAL,
176 OPC_TLTU = 0x33 | OPC_SPECIAL,
177 OPC_TEQ = 0x34 | OPC_SPECIAL,
178 OPC_TNE = 0x36 | OPC_SPECIAL,
179 /* HI / LO registers load & stores */
180 OPC_MFHI = 0x10 | OPC_SPECIAL,
181 OPC_MTHI = 0x11 | OPC_SPECIAL,
182 OPC_MFLO = 0x12 | OPC_SPECIAL,
183 OPC_MTLO = 0x13 | OPC_SPECIAL,
184 /* Conditional moves */
185 OPC_MOVZ = 0x0A | OPC_SPECIAL,
186 OPC_MOVN = 0x0B | OPC_SPECIAL,
188 OPC_MOVCI = 0x01 | OPC_SPECIAL,
191 OPC_PMON = 0x05 | OPC_SPECIAL, /* inofficial */
192 OPC_SYSCALL = 0x0C | OPC_SPECIAL,
193 OPC_BREAK = 0x0D | OPC_SPECIAL,
194 OPC_SPIM = 0x0E | OPC_SPECIAL, /* inofficial */
195 OPC_SYNC = 0x0F | OPC_SPECIAL,
197 OPC_SPECIAL15_RESERVED = 0x15 | OPC_SPECIAL,
198 OPC_SPECIAL28_RESERVED = 0x28 | OPC_SPECIAL,
199 OPC_SPECIAL29_RESERVED = 0x29 | OPC_SPECIAL,
200 OPC_SPECIAL35_RESERVED = 0x35 | OPC_SPECIAL,
201 OPC_SPECIAL37_RESERVED = 0x37 | OPC_SPECIAL,
202 OPC_SPECIAL39_RESERVED = 0x39 | OPC_SPECIAL,
203 OPC_SPECIAL3D_RESERVED = 0x3D | OPC_SPECIAL,
206 /* Multiplication variants of the vr54xx. */
207 #define MASK_MUL_VR54XX(op) MASK_SPECIAL(op) | (op & (0x1F << 6))
210 OPC_VR54XX_MULS = (0x03 << 6) | OPC_MULT,
211 OPC_VR54XX_MULSU = (0x03 << 6) | OPC_MULTU,
212 OPC_VR54XX_MACC = (0x05 << 6) | OPC_MULT,
213 OPC_VR54XX_MACCU = (0x05 << 6) | OPC_MULTU,
214 OPC_VR54XX_MSAC = (0x07 << 6) | OPC_MULT,
215 OPC_VR54XX_MSACU = (0x07 << 6) | OPC_MULTU,
216 OPC_VR54XX_MULHI = (0x09 << 6) | OPC_MULT,
217 OPC_VR54XX_MULHIU = (0x09 << 6) | OPC_MULTU,
218 OPC_VR54XX_MULSHI = (0x0B << 6) | OPC_MULT,
219 OPC_VR54XX_MULSHIU = (0x0B << 6) | OPC_MULTU,
220 OPC_VR54XX_MACCHI = (0x0D << 6) | OPC_MULT,
221 OPC_VR54XX_MACCHIU = (0x0D << 6) | OPC_MULTU,
222 OPC_VR54XX_MSACHI = (0x0F << 6) | OPC_MULT,
223 OPC_VR54XX_MSACHIU = (0x0F << 6) | OPC_MULTU,
226 /* REGIMM (rt field) opcodes */
227 #define MASK_REGIMM(op) MASK_OP_MAJOR(op) | (op & (0x1F << 16))
230 OPC_BLTZ = (0x00 << 16) | OPC_REGIMM,
231 OPC_BLTZL = (0x02 << 16) | OPC_REGIMM,
232 OPC_BGEZ = (0x01 << 16) | OPC_REGIMM,
233 OPC_BGEZL = (0x03 << 16) | OPC_REGIMM,
234 OPC_BLTZAL = (0x10 << 16) | OPC_REGIMM,
235 OPC_BLTZALL = (0x12 << 16) | OPC_REGIMM,
236 OPC_BGEZAL = (0x11 << 16) | OPC_REGIMM,
237 OPC_BGEZALL = (0x13 << 16) | OPC_REGIMM,
238 OPC_TGEI = (0x08 << 16) | OPC_REGIMM,
239 OPC_TGEIU = (0x09 << 16) | OPC_REGIMM,
240 OPC_TLTI = (0x0A << 16) | OPC_REGIMM,
241 OPC_TLTIU = (0x0B << 16) | OPC_REGIMM,
242 OPC_TEQI = (0x0C << 16) | OPC_REGIMM,
243 OPC_TNEI = (0x0E << 16) | OPC_REGIMM,
244 OPC_SYNCI = (0x1F << 16) | OPC_REGIMM,
247 /* Special2 opcodes */
248 #define MASK_SPECIAL2(op) MASK_OP_MAJOR(op) | (op & 0x3F)
251 /* Multiply & xxx operations */
252 OPC_MADD = 0x00 | OPC_SPECIAL2,
253 OPC_MADDU = 0x01 | OPC_SPECIAL2,
254 OPC_MUL = 0x02 | OPC_SPECIAL2,
255 OPC_MSUB = 0x04 | OPC_SPECIAL2,
256 OPC_MSUBU = 0x05 | OPC_SPECIAL2,
258 OPC_CLZ = 0x20 | OPC_SPECIAL2,
259 OPC_CLO = 0x21 | OPC_SPECIAL2,
260 OPC_DCLZ = 0x24 | OPC_SPECIAL2,
261 OPC_DCLO = 0x25 | OPC_SPECIAL2,
263 OPC_SDBBP = 0x3F | OPC_SPECIAL2,
266 /* Special3 opcodes */
267 #define MASK_SPECIAL3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
270 OPC_EXT = 0x00 | OPC_SPECIAL3,
271 OPC_DEXTM = 0x01 | OPC_SPECIAL3,
272 OPC_DEXTU = 0x02 | OPC_SPECIAL3,
273 OPC_DEXT = 0x03 | OPC_SPECIAL3,
274 OPC_INS = 0x04 | OPC_SPECIAL3,
275 OPC_DINSM = 0x05 | OPC_SPECIAL3,
276 OPC_DINSU = 0x06 | OPC_SPECIAL3,
277 OPC_DINS = 0x07 | OPC_SPECIAL3,
278 OPC_FORK = 0x08 | OPC_SPECIAL3,
279 OPC_YIELD = 0x09 | OPC_SPECIAL3,
280 OPC_BSHFL = 0x20 | OPC_SPECIAL3,
281 OPC_DBSHFL = 0x24 | OPC_SPECIAL3,
282 OPC_RDHWR = 0x3B | OPC_SPECIAL3,
286 #define MASK_BSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
289 OPC_WSBH = (0x02 << 6) | OPC_BSHFL,
290 OPC_SEB = (0x10 << 6) | OPC_BSHFL,
291 OPC_SEH = (0x18 << 6) | OPC_BSHFL,
295 #define MASK_DBSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
298 OPC_DSBH = (0x02 << 6) | OPC_DBSHFL,
299 OPC_DSHD = (0x05 << 6) | OPC_DBSHFL,
302 /* Coprocessor 0 (rs field) */
303 #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
306 OPC_MFC0 = (0x00 << 21) | OPC_CP0,
307 OPC_DMFC0 = (0x01 << 21) | OPC_CP0,
308 OPC_MTC0 = (0x04 << 21) | OPC_CP0,
309 OPC_DMTC0 = (0x05 << 21) | OPC_CP0,
310 OPC_MFTR = (0x08 << 21) | OPC_CP0,
311 OPC_RDPGPR = (0x0A << 21) | OPC_CP0,
312 OPC_MFMC0 = (0x0B << 21) | OPC_CP0,
313 OPC_MTTR = (0x0C << 21) | OPC_CP0,
314 OPC_WRPGPR = (0x0E << 21) | OPC_CP0,
315 OPC_C0 = (0x10 << 21) | OPC_CP0,
316 OPC_C0_FIRST = (0x10 << 21) | OPC_CP0,
317 OPC_C0_LAST = (0x1F << 21) | OPC_CP0,
321 #define MASK_MFMC0(op) MASK_CP0(op) | (op & 0xFFFF)
324 OPC_DMT = 0x01 | (0 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0,
325 OPC_EMT = 0x01 | (1 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0,
326 OPC_DVPE = 0x01 | (0 << 5) | OPC_MFMC0,
327 OPC_EVPE = 0x01 | (1 << 5) | OPC_MFMC0,
328 OPC_DI = (0 << 5) | (0x0C << 11) | OPC_MFMC0,
329 OPC_EI = (1 << 5) | (0x0C << 11) | OPC_MFMC0,
332 /* Coprocessor 0 (with rs == C0) */
333 #define MASK_C0(op) MASK_CP0(op) | (op & 0x3F)
336 OPC_TLBR = 0x01 | OPC_C0,
337 OPC_TLBWI = 0x02 | OPC_C0,
338 OPC_TLBWR = 0x06 | OPC_C0,
339 OPC_TLBP = 0x08 | OPC_C0,
340 OPC_RFE = 0x10 | OPC_C0,
341 OPC_ERET = 0x18 | OPC_C0,
342 OPC_DERET = 0x1F | OPC_C0,
343 OPC_WAIT = 0x20 | OPC_C0,
346 /* Coprocessor 1 (rs field) */
347 #define MASK_CP1(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
350 OPC_MFC1 = (0x00 << 21) | OPC_CP1,
351 OPC_DMFC1 = (0x01 << 21) | OPC_CP1,
352 OPC_CFC1 = (0x02 << 21) | OPC_CP1,
353 OPC_MFHC1 = (0x03 << 21) | OPC_CP1,
354 OPC_MTC1 = (0x04 << 21) | OPC_CP1,
355 OPC_DMTC1 = (0x05 << 21) | OPC_CP1,
356 OPC_CTC1 = (0x06 << 21) | OPC_CP1,
357 OPC_MTHC1 = (0x07 << 21) | OPC_CP1,
358 OPC_BC1 = (0x08 << 21) | OPC_CP1, /* bc */
359 OPC_BC1ANY2 = (0x09 << 21) | OPC_CP1,
360 OPC_BC1ANY4 = (0x0A << 21) | OPC_CP1,
361 OPC_S_FMT = (0x10 << 21) | OPC_CP1, /* 16: fmt=single fp */
362 OPC_D_FMT = (0x11 << 21) | OPC_CP1, /* 17: fmt=double fp */
363 OPC_E_FMT = (0x12 << 21) | OPC_CP1, /* 18: fmt=extended fp */
364 OPC_Q_FMT = (0x13 << 21) | OPC_CP1, /* 19: fmt=quad fp */
365 OPC_W_FMT = (0x14 << 21) | OPC_CP1, /* 20: fmt=32bit fixed */
366 OPC_L_FMT = (0x15 << 21) | OPC_CP1, /* 21: fmt=64bit fixed */
367 OPC_PS_FMT = (0x16 << 21) | OPC_CP1, /* 22: fmt=paired single fp */
370 #define MASK_CP1_FUNC(op) MASK_CP1(op) | (op & 0x3F)
371 #define MASK_BC1(op) MASK_CP1(op) | (op & (0x3 << 16))
374 OPC_BC1F = (0x00 << 16) | OPC_BC1,
375 OPC_BC1T = (0x01 << 16) | OPC_BC1,
376 OPC_BC1FL = (0x02 << 16) | OPC_BC1,
377 OPC_BC1TL = (0x03 << 16) | OPC_BC1,
381 OPC_BC1FANY2 = (0x00 << 16) | OPC_BC1ANY2,
382 OPC_BC1TANY2 = (0x01 << 16) | OPC_BC1ANY2,
386 OPC_BC1FANY4 = (0x00 << 16) | OPC_BC1ANY4,
387 OPC_BC1TANY4 = (0x01 << 16) | OPC_BC1ANY4,
390 #define MASK_CP2(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
393 OPC_MFC2 = (0x00 << 21) | OPC_CP2,
394 OPC_DMFC2 = (0x01 << 21) | OPC_CP2,
395 OPC_CFC2 = (0x02 << 21) | OPC_CP2,
396 OPC_MFHC2 = (0x03 << 21) | OPC_CP2,
397 OPC_MTC2 = (0x04 << 21) | OPC_CP2,
398 OPC_DMTC2 = (0x05 << 21) | OPC_CP2,
399 OPC_CTC2 = (0x06 << 21) | OPC_CP2,
400 OPC_MTHC2 = (0x07 << 21) | OPC_CP2,
401 OPC_BC2 = (0x08 << 21) | OPC_CP2,
404 #define MASK_CP3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
407 OPC_LWXC1 = 0x00 | OPC_CP3,
408 OPC_LDXC1 = 0x01 | OPC_CP3,
409 OPC_LUXC1 = 0x05 | OPC_CP3,
410 OPC_SWXC1 = 0x08 | OPC_CP3,
411 OPC_SDXC1 = 0x09 | OPC_CP3,
412 OPC_SUXC1 = 0x0D | OPC_CP3,
413 OPC_PREFX = 0x0F | OPC_CP3,
414 OPC_ALNV_PS = 0x1E | OPC_CP3,
415 OPC_MADD_S = 0x20 | OPC_CP3,
416 OPC_MADD_D = 0x21 | OPC_CP3,
417 OPC_MADD_PS = 0x26 | OPC_CP3,
418 OPC_MSUB_S = 0x28 | OPC_CP3,
419 OPC_MSUB_D = 0x29 | OPC_CP3,
420 OPC_MSUB_PS = 0x2E | OPC_CP3,
421 OPC_NMADD_S = 0x30 | OPC_CP3,
422 OPC_NMADD_D = 0x31 | OPC_CP3,
423 OPC_NMADD_PS= 0x36 | OPC_CP3,
424 OPC_NMSUB_S = 0x38 | OPC_CP3,
425 OPC_NMSUB_D = 0x39 | OPC_CP3,
426 OPC_NMSUB_PS= 0x3E | OPC_CP3,
429 /* global register indices */
430 static TCGv_ptr cpu_env;
431 static TCGv cpu_gpr[32], cpu_PC;
432 static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC], cpu_ACX[MIPS_DSP_ACC];
433 static TCGv cpu_dspctrl, btarget, bcond;
434 static TCGv_i32 hflags;
435 static TCGv_i32 fpu_fcr0, fpu_fcr31;
437 #include "gen-icount.h"
439 #define gen_helper_0i(name, arg) do { \
440 TCGv_i32 helper_tmp = tcg_const_i32(arg); \
441 gen_helper_##name(helper_tmp); \
442 tcg_temp_free_i32(helper_tmp); \
445 #define gen_helper_1i(name, arg1, arg2) do { \
446 TCGv_i32 helper_tmp = tcg_const_i32(arg2); \
447 gen_helper_##name(arg1, helper_tmp); \
448 tcg_temp_free_i32(helper_tmp); \
451 #define gen_helper_2i(name, arg1, arg2, arg3) do { \
452 TCGv_i32 helper_tmp = tcg_const_i32(arg3); \
453 gen_helper_##name(arg1, arg2, helper_tmp); \
454 tcg_temp_free_i32(helper_tmp); \
457 #define gen_helper_3i(name, arg1, arg2, arg3, arg4) do { \
458 TCGv_i32 helper_tmp = tcg_const_i32(arg4); \
459 gen_helper_##name(arg1, arg2, arg3, helper_tmp); \
460 tcg_temp_free_i32(helper_tmp); \
463 typedef struct DisasContext {
464 struct TranslationBlock *tb;
465 target_ulong pc, saved_pc;
467 /* Routine used to access memory */
469 uint32_t hflags, saved_hflags;
471 target_ulong btarget;
475 BS_NONE = 0, /* We go out of the TB without reaching a branch or an
476 * exception condition */
477 BS_STOP = 1, /* We want to stop translation for any reason */
478 BS_BRANCH = 2, /* We reached a branch condition */
479 BS_EXCP = 3, /* We reached an exception condition */
482 static const char *regnames[] =
483 { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
484 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
485 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
486 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", };
488 static const char *regnames_HI[] =
489 { "HI0", "HI1", "HI2", "HI3", };
491 static const char *regnames_LO[] =
492 { "LO0", "LO1", "LO2", "LO3", };
494 static const char *regnames_ACX[] =
495 { "ACX0", "ACX1", "ACX2", "ACX3", };
497 static const char *fregnames[] =
498 { "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
499 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
500 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
501 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", };
503 #ifdef MIPS_DEBUG_DISAS
504 #define MIPS_DEBUG(fmt, ...) \
505 qemu_log_mask(CPU_LOG_TB_IN_ASM, \
506 TARGET_FMT_lx ": %08x " fmt "\n", \
507 ctx->pc, ctx->opcode , ## __VA_ARGS__)
508 #define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
510 #define MIPS_DEBUG(fmt, ...) do { } while(0)
511 #define LOG_DISAS(...) do { } while (0)
514 #define MIPS_INVAL(op) \
516 MIPS_DEBUG("Invalid %s %03x %03x %03x", op, ctx->opcode >> 26, \
517 ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \
520 /* General purpose registers moves. */
521 static inline void gen_load_gpr (TCGv t, int reg)
524 tcg_gen_movi_tl(t, 0);
526 tcg_gen_mov_tl(t, cpu_gpr[reg]);
529 static inline void gen_store_gpr (TCGv t, int reg)
532 tcg_gen_mov_tl(cpu_gpr[reg], t);
535 /* Moves to/from ACX register. */
536 static inline void gen_load_ACX (TCGv t, int reg)
538 tcg_gen_mov_tl(t, cpu_ACX[reg]);
541 static inline void gen_store_ACX (TCGv t, int reg)
543 tcg_gen_mov_tl(cpu_ACX[reg], t);
546 /* Moves to/from shadow registers. */
547 static inline void gen_load_srsgpr (int from, int to)
549 TCGv t0 = tcg_temp_new();
552 tcg_gen_movi_tl(t0, 0);
554 TCGv_i32 t2 = tcg_temp_new_i32();
555 TCGv_ptr addr = tcg_temp_new_ptr();
557 tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUState, CP0_SRSCtl));
558 tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS);
559 tcg_gen_andi_i32(t2, t2, 0xf);
560 tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32);
561 tcg_gen_ext_i32_ptr(addr, t2);
562 tcg_gen_add_ptr(addr, cpu_env, addr);
564 tcg_gen_ld_tl(t0, addr, sizeof(target_ulong) * from);
565 tcg_temp_free_ptr(addr);
566 tcg_temp_free_i32(t2);
568 gen_store_gpr(t0, to);
572 static inline void gen_store_srsgpr (int from, int to)
575 TCGv t0 = tcg_temp_new();
576 TCGv_i32 t2 = tcg_temp_new_i32();
577 TCGv_ptr addr = tcg_temp_new_ptr();
579 gen_load_gpr(t0, from);
580 tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUState, CP0_SRSCtl));
581 tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS);
582 tcg_gen_andi_i32(t2, t2, 0xf);
583 tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32);
584 tcg_gen_ext_i32_ptr(addr, t2);
585 tcg_gen_add_ptr(addr, cpu_env, addr);
587 tcg_gen_st_tl(t0, addr, sizeof(target_ulong) * to);
588 tcg_temp_free_ptr(addr);
589 tcg_temp_free_i32(t2);
594 /* Floating point register moves. */
595 static inline void gen_load_fpr32 (TCGv_i32 t, int reg)
597 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX]));
600 static inline void gen_store_fpr32 (TCGv_i32 t, int reg)
602 tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX]));
605 static inline void gen_load_fpr32h (TCGv_i32 t, int reg)
607 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX]));
610 static inline void gen_store_fpr32h (TCGv_i32 t, int reg)
612 tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX]));
615 static inline void gen_load_fpr64 (DisasContext *ctx, TCGv_i64 t, int reg)
617 if (ctx->hflags & MIPS_HFLAG_F64) {
618 tcg_gen_ld_i64(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].d));
620 TCGv_i32 t0 = tcg_temp_new_i32();
621 TCGv_i32 t1 = tcg_temp_new_i32();
622 gen_load_fpr32(t0, reg & ~1);
623 gen_load_fpr32(t1, reg | 1);
624 tcg_gen_concat_i32_i64(t, t0, t1);
625 tcg_temp_free_i32(t0);
626 tcg_temp_free_i32(t1);
630 static inline void gen_store_fpr64 (DisasContext *ctx, TCGv_i64 t, int reg)
632 if (ctx->hflags & MIPS_HFLAG_F64) {
633 tcg_gen_st_i64(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].d));
635 TCGv_i64 t0 = tcg_temp_new_i64();
636 TCGv_i32 t1 = tcg_temp_new_i32();
637 tcg_gen_trunc_i64_i32(t1, t);
638 gen_store_fpr32(t1, reg & ~1);
639 tcg_gen_shri_i64(t0, t, 32);
640 tcg_gen_trunc_i64_i32(t1, t0);
641 gen_store_fpr32(t1, reg | 1);
642 tcg_temp_free_i32(t1);
643 tcg_temp_free_i64(t0);
647 static inline int get_fp_bit (int cc)
655 #define FOP_CONDS(type, fmt, bits) \
656 static inline void gen_cmp ## type ## _ ## fmt(int n, TCGv_i##bits a, \
657 TCGv_i##bits b, int cc) \
660 case 0: gen_helper_2i(cmp ## type ## _ ## fmt ## _f, a, b, cc); break;\
661 case 1: gen_helper_2i(cmp ## type ## _ ## fmt ## _un, a, b, cc); break;\
662 case 2: gen_helper_2i(cmp ## type ## _ ## fmt ## _eq, a, b, cc); break;\
663 case 3: gen_helper_2i(cmp ## type ## _ ## fmt ## _ueq, a, b, cc); break;\
664 case 4: gen_helper_2i(cmp ## type ## _ ## fmt ## _olt, a, b, cc); break;\
665 case 5: gen_helper_2i(cmp ## type ## _ ## fmt ## _ult, a, b, cc); break;\
666 case 6: gen_helper_2i(cmp ## type ## _ ## fmt ## _ole, a, b, cc); break;\
667 case 7: gen_helper_2i(cmp ## type ## _ ## fmt ## _ule, a, b, cc); break;\
668 case 8: gen_helper_2i(cmp ## type ## _ ## fmt ## _sf, a, b, cc); break;\
669 case 9: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngle, a, b, cc); break;\
670 case 10: gen_helper_2i(cmp ## type ## _ ## fmt ## _seq, a, b, cc); break;\
671 case 11: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngl, a, b, cc); break;\
672 case 12: gen_helper_2i(cmp ## type ## _ ## fmt ## _lt, a, b, cc); break;\
673 case 13: gen_helper_2i(cmp ## type ## _ ## fmt ## _nge, a, b, cc); break;\
674 case 14: gen_helper_2i(cmp ## type ## _ ## fmt ## _le, a, b, cc); break;\
675 case 15: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngt, a, b, cc); break;\
681 FOP_CONDS(abs, d, 64)
683 FOP_CONDS(abs, s, 32)
685 FOP_CONDS(abs, ps, 64)
689 #define OP_COND(name, cond) \
690 static inline void glue(gen_op_, name) (TCGv ret, TCGv t0, TCGv t1) \
692 int l1 = gen_new_label(); \
693 int l2 = gen_new_label(); \
695 tcg_gen_brcond_tl(cond, t0, t1, l1); \
696 tcg_gen_movi_tl(ret, 0); \
699 tcg_gen_movi_tl(ret, 1); \
702 OP_COND(eq, TCG_COND_EQ);
703 OP_COND(ne, TCG_COND_NE);
704 OP_COND(ge, TCG_COND_GE);
705 OP_COND(geu, TCG_COND_GEU);
706 OP_COND(lt, TCG_COND_LT);
707 OP_COND(ltu, TCG_COND_LTU);
710 #define OP_CONDI(name, cond) \
711 static inline void glue(gen_op_, name) (TCGv ret, TCGv t0, target_ulong val) \
713 int l1 = gen_new_label(); \
714 int l2 = gen_new_label(); \
716 tcg_gen_brcondi_tl(cond, t0, val, l1); \
717 tcg_gen_movi_tl(ret, 0); \
720 tcg_gen_movi_tl(ret, 1); \
723 OP_CONDI(lti, TCG_COND_LT);
724 OP_CONDI(ltiu, TCG_COND_LTU);
727 #define OP_CONDZ(name, cond) \
728 static inline void glue(gen_op_, name) (TCGv ret, TCGv t0) \
730 int l1 = gen_new_label(); \
731 int l2 = gen_new_label(); \
733 tcg_gen_brcondi_tl(cond, t0, 0, l1); \
734 tcg_gen_movi_tl(ret, 0); \
737 tcg_gen_movi_tl(ret, 1); \
740 OP_CONDZ(gez, TCG_COND_GE);
741 OP_CONDZ(gtz, TCG_COND_GT);
742 OP_CONDZ(lez, TCG_COND_LE);
743 OP_CONDZ(ltz, TCG_COND_LT);
746 static inline void gen_save_pc(target_ulong pc)
748 tcg_gen_movi_tl(cpu_PC, pc);
751 static inline void save_cpu_state (DisasContext *ctx, int do_save_pc)
753 LOG_DISAS("hflags %08x saved %08x\n", ctx->hflags, ctx->saved_hflags);
754 if (do_save_pc && ctx->pc != ctx->saved_pc) {
755 gen_save_pc(ctx->pc);
756 ctx->saved_pc = ctx->pc;
758 if (ctx->hflags != ctx->saved_hflags) {
759 tcg_gen_movi_i32(hflags, ctx->hflags);
760 ctx->saved_hflags = ctx->hflags;
761 switch (ctx->hflags & MIPS_HFLAG_BMASK) {
767 tcg_gen_movi_tl(btarget, ctx->btarget);
773 static inline void restore_cpu_state (CPUState *env, DisasContext *ctx)
775 ctx->saved_hflags = ctx->hflags;
776 switch (ctx->hflags & MIPS_HFLAG_BMASK) {
782 ctx->btarget = env->btarget;
788 generate_exception_err (DisasContext *ctx, int excp, int err)
790 TCGv_i32 texcp = tcg_const_i32(excp);
791 TCGv_i32 terr = tcg_const_i32(err);
792 save_cpu_state(ctx, 1);
793 gen_helper_raise_exception_err(texcp, terr);
794 tcg_temp_free_i32(terr);
795 tcg_temp_free_i32(texcp);
799 generate_exception (DisasContext *ctx, int excp)
801 save_cpu_state(ctx, 1);
802 gen_helper_0i(raise_exception, excp);
805 /* Addresses computation */
806 static inline void gen_op_addr_add (DisasContext *ctx, TCGv t0, TCGv t1)
808 tcg_gen_add_tl(t0, t0, t1);
810 #if defined(TARGET_MIPS64)
811 /* For compatibility with 32-bit code, data reference in user mode
812 with Status_UX = 0 should be casted to 32-bit and sign extended.
813 See the MIPS64 PRA manual, section 4.10. */
814 if (((ctx->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
815 !(ctx->hflags & MIPS_HFLAG_UX)) {
816 tcg_gen_ext32s_i64(t0, t0);
821 static inline void check_cp0_enabled(DisasContext *ctx)
823 if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0)))
824 generate_exception_err(ctx, EXCP_CpU, 1);
827 static inline void check_cp1_enabled(DisasContext *ctx)
829 if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU)))
830 generate_exception_err(ctx, EXCP_CpU, 1);
833 /* Verify that the processor is running with COP1X instructions enabled.
834 This is associated with the nabla symbol in the MIPS32 and MIPS64
837 static inline void check_cop1x(DisasContext *ctx)
839 if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X)))
840 generate_exception(ctx, EXCP_RI);
843 /* Verify that the processor is running with 64-bit floating-point
844 operations enabled. */
846 static inline void check_cp1_64bitmode(DisasContext *ctx)
848 if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X)))
849 generate_exception(ctx, EXCP_RI);
853 * Verify if floating point register is valid; an operation is not defined
854 * if bit 0 of any register specification is set and the FR bit in the
855 * Status register equals zero, since the register numbers specify an
856 * even-odd pair of adjacent coprocessor general registers. When the FR bit
857 * in the Status register equals one, both even and odd register numbers
858 * are valid. This limitation exists only for 64 bit wide (d,l,ps) registers.
860 * Multiple 64 bit wide registers can be checked by calling
861 * gen_op_cp1_registers(freg1 | freg2 | ... | fregN);
863 static inline void check_cp1_registers(DisasContext *ctx, int regs)
865 if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1)))
866 generate_exception(ctx, EXCP_RI);
869 /* This code generates a "reserved instruction" exception if the
870 CPU does not support the instruction set corresponding to flags. */
871 static inline void check_insn(CPUState *env, DisasContext *ctx, int flags)
873 if (unlikely(!(env->insn_flags & flags)))
874 generate_exception(ctx, EXCP_RI);
877 /* This code generates a "reserved instruction" exception if 64-bit
878 instructions are not enabled. */
879 static inline void check_mips_64(DisasContext *ctx)
881 if (unlikely(!(ctx->hflags & MIPS_HFLAG_64)))
882 generate_exception(ctx, EXCP_RI);
885 /* load/store instructions. */
886 #define OP_LD(insn,fname) \
887 static inline void op_ldst_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
889 tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \
896 #if defined(TARGET_MIPS64)
902 #define OP_ST(insn,fname) \
903 static inline void op_ldst_##insn(TCGv arg1, TCGv arg2, DisasContext *ctx) \
905 tcg_gen_qemu_##fname(arg1, arg2, ctx->mem_idx); \
910 #if defined(TARGET_MIPS64)
915 #define OP_LD_ATOMIC(insn,fname) \
916 static inline void op_ldst_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
918 TCGv t0 = tcg_temp_new(); \
919 tcg_gen_mov_tl(t0, arg1); \
920 tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \
921 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_LLAddr)); \
924 OP_LD_ATOMIC(ll,ld32s);
925 #if defined(TARGET_MIPS64)
926 OP_LD_ATOMIC(lld,ld64);
930 #define OP_ST_ATOMIC(insn,fname,almask) \
931 static inline void op_ldst_##insn(TCGv ret, TCGv arg1, TCGv arg2, DisasContext *ctx) \
933 TCGv t0 = tcg_temp_new(); \
934 int l1 = gen_new_label(); \
935 int l2 = gen_new_label(); \
936 int l3 = gen_new_label(); \
938 tcg_gen_andi_tl(t0, arg2, almask); \
939 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); \
940 tcg_gen_st_tl(arg2, cpu_env, offsetof(CPUState, CP0_BadVAddr)); \
941 generate_exception(ctx, EXCP_AdES); \
943 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_LLAddr)); \
944 tcg_gen_brcond_tl(TCG_COND_NE, arg2, t0, l2); \
946 tcg_gen_qemu_##fname(arg1, arg2, ctx->mem_idx); \
947 tcg_gen_movi_tl(ret, 1); \
950 tcg_gen_movi_tl(ret, 0); \
953 OP_ST_ATOMIC(sc,st32,0x3);
954 #if defined(TARGET_MIPS64)
955 OP_ST_ATOMIC(scd,st64,0x7);
960 static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
961 int base, int16_t offset)
963 const char *opn = "ldst";
964 TCGv t0 = tcg_temp_new();
965 TCGv t1 = tcg_temp_new();
968 tcg_gen_movi_tl(t0, offset);
969 } else if (offset == 0) {
970 gen_load_gpr(t0, base);
972 tcg_gen_movi_tl(t0, offset);
973 gen_op_addr_add(ctx, t0, cpu_gpr[base]);
975 /* Don't do NOP if destination is zero: we must perform the actual
978 #if defined(TARGET_MIPS64)
980 save_cpu_state(ctx, 0);
981 op_ldst_lwu(t0, t0, ctx);
982 gen_store_gpr(t0, rt);
986 save_cpu_state(ctx, 0);
987 op_ldst_ld(t0, t0, ctx);
988 gen_store_gpr(t0, rt);
992 save_cpu_state(ctx, 0);
993 op_ldst_lld(t0, t0, ctx);
994 gen_store_gpr(t0, rt);
998 save_cpu_state(ctx, 0);
999 gen_load_gpr(t1, rt);
1000 op_ldst_sd(t1, t0, ctx);
1004 save_cpu_state(ctx, 1);
1005 gen_load_gpr(t1, rt);
1006 gen_helper_3i(ldl, t1, t1, t0, ctx->mem_idx);
1007 gen_store_gpr(t1, rt);
1011 save_cpu_state(ctx, 1);
1012 gen_load_gpr(t1, rt);
1013 gen_helper_2i(sdl, t1, t0, ctx->mem_idx);
1017 save_cpu_state(ctx, 1);
1018 gen_load_gpr(t1, rt);
1019 gen_helper_3i(ldr, t1, t1, t0, ctx->mem_idx);
1020 gen_store_gpr(t1, rt);
1024 save_cpu_state(ctx, 1);
1025 gen_load_gpr(t1, rt);
1026 gen_helper_2i(sdr, t1, t0, ctx->mem_idx);
1031 save_cpu_state(ctx, 0);
1032 op_ldst_lw(t0, t0, ctx);
1033 gen_store_gpr(t0, rt);
1037 save_cpu_state(ctx, 0);
1038 gen_load_gpr(t1, rt);
1039 op_ldst_sw(t1, t0, ctx);
1043 save_cpu_state(ctx, 0);
1044 op_ldst_lh(t0, t0, ctx);
1045 gen_store_gpr(t0, rt);
1049 save_cpu_state(ctx, 0);
1050 gen_load_gpr(t1, rt);
1051 op_ldst_sh(t1, t0, ctx);
1055 save_cpu_state(ctx, 0);
1056 op_ldst_lhu(t0, t0, ctx);
1057 gen_store_gpr(t0, rt);
1061 save_cpu_state(ctx, 0);
1062 op_ldst_lb(t0, t0, ctx);
1063 gen_store_gpr(t0, rt);
1067 save_cpu_state(ctx, 0);
1068 gen_load_gpr(t1, rt);
1069 op_ldst_sb(t1, t0, ctx);
1073 save_cpu_state(ctx, 0);
1074 op_ldst_lbu(t0, t0, ctx);
1075 gen_store_gpr(t0, rt);
1079 save_cpu_state(ctx, 1);
1080 gen_load_gpr(t1, rt);
1081 gen_helper_3i(lwl, t1, t1, t0, ctx->mem_idx);
1082 gen_store_gpr(t1, rt);
1086 save_cpu_state(ctx, 1);
1087 gen_load_gpr(t1, rt);
1088 gen_helper_2i(swl, t1, t0, ctx->mem_idx);
1092 save_cpu_state(ctx, 1);
1093 gen_load_gpr(t1, rt);
1094 gen_helper_3i(lwr, t1, t1, t0, ctx->mem_idx);
1095 gen_store_gpr(t1, rt);
1099 save_cpu_state(ctx, 1);
1100 gen_load_gpr(t1, rt);
1101 gen_helper_2i(swr, t1, t0, ctx->mem_idx);
1105 save_cpu_state(ctx, 0);
1106 op_ldst_ll(t0, t0, ctx);
1107 gen_store_gpr(t0, rt);
1111 MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]);
1116 /* Store conditional */
1117 static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt,
1118 int base, int16_t offset)
1120 const char *opn = "st_cond";
1123 t0 = tcg_temp_local_new();
1126 tcg_gen_movi_tl(t0, offset);
1127 } else if (offset == 0) {
1128 gen_load_gpr(t0, base);
1130 tcg_gen_movi_tl(t0, offset);
1131 gen_op_addr_add(ctx, t0, cpu_gpr[base]);
1133 /* Don't do NOP if destination is zero: we must perform the actual
1136 t1 = tcg_temp_local_new();
1137 gen_load_gpr(t1, rt);
1139 #if defined(TARGET_MIPS64)
1141 save_cpu_state(ctx, 0);
1142 op_ldst_scd(t0, t1, t0, ctx);
1147 save_cpu_state(ctx, 0);
1148 op_ldst_sc(t0, t1, t0, ctx);
1152 MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]);
1154 gen_store_gpr(t0, rt);
1158 /* Load and store */
1159 static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
1160 int base, int16_t offset)
1162 const char *opn = "flt_ldst";
1163 TCGv t0 = tcg_temp_new();
1166 tcg_gen_movi_tl(t0, offset);
1167 } else if (offset == 0) {
1168 gen_load_gpr(t0, base);
1170 tcg_gen_movi_tl(t0, offset);
1171 gen_op_addr_add(ctx, t0, cpu_gpr[base]);
1173 /* Don't do NOP if destination is zero: we must perform the actual
1178 TCGv_i32 fp0 = tcg_temp_new_i32();
1180 tcg_gen_qemu_ld32s(t0, t0, ctx->mem_idx);
1181 tcg_gen_trunc_tl_i32(fp0, t0);
1182 gen_store_fpr32(fp0, ft);
1183 tcg_temp_free_i32(fp0);
1189 TCGv_i32 fp0 = tcg_temp_new_i32();
1190 TCGv t1 = tcg_temp_new();
1192 gen_load_fpr32(fp0, ft);
1193 tcg_gen_extu_i32_tl(t1, fp0);
1194 tcg_gen_qemu_st32(t1, t0, ctx->mem_idx);
1196 tcg_temp_free_i32(fp0);
1202 TCGv_i64 fp0 = tcg_temp_new_i64();
1204 tcg_gen_qemu_ld64(fp0, t0, ctx->mem_idx);
1205 gen_store_fpr64(ctx, fp0, ft);
1206 tcg_temp_free_i64(fp0);
1212 TCGv_i64 fp0 = tcg_temp_new_i64();
1214 gen_load_fpr64(ctx, fp0, ft);
1215 tcg_gen_qemu_st64(fp0, t0, ctx->mem_idx);
1216 tcg_temp_free_i64(fp0);
1222 generate_exception(ctx, EXCP_RI);
1225 MIPS_DEBUG("%s %s, %d(%s)", opn, fregnames[ft], offset, regnames[base]);
1230 /* Arithmetic with immediate operand */
1231 static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
1232 int rt, int rs, int16_t imm)
1234 target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */
1235 const char *opn = "imm arith";
1237 if (rt == 0 && opc != OPC_ADDI && opc != OPC_DADDI) {
1238 /* If no destination, treat it as a NOP.
1239 For addi, we must generate the overflow exception when needed. */
1246 TCGv t0 = tcg_temp_local_new();
1247 TCGv t1 = tcg_temp_new();
1248 TCGv t2 = tcg_temp_new();
1249 int l1 = gen_new_label();
1251 gen_load_gpr(t1, rs);
1252 tcg_gen_addi_tl(t0, t1, uimm);
1253 tcg_gen_ext32s_tl(t0, t0);
1255 tcg_gen_xori_tl(t1, t1, ~uimm);
1256 tcg_gen_xori_tl(t2, t0, uimm);
1257 tcg_gen_and_tl(t1, t1, t2);
1259 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
1261 /* operands of same sign, result different sign */
1262 generate_exception(ctx, EXCP_OVERFLOW);
1264 tcg_gen_ext32s_tl(t0, t0);
1265 gen_store_gpr(t0, rt);
1272 tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
1273 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
1275 tcg_gen_movi_tl(cpu_gpr[rt], uimm);
1279 #if defined(TARGET_MIPS64)
1282 TCGv t0 = tcg_temp_local_new();
1283 TCGv t1 = tcg_temp_new();
1284 TCGv t2 = tcg_temp_new();
1285 int l1 = gen_new_label();
1287 gen_load_gpr(t1, rs);
1288 tcg_gen_addi_tl(t0, t1, uimm);
1290 tcg_gen_xori_tl(t1, t1, ~uimm);
1291 tcg_gen_xori_tl(t2, t0, uimm);
1292 tcg_gen_and_tl(t1, t1, t2);
1294 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
1296 /* operands of same sign, result different sign */
1297 generate_exception(ctx, EXCP_OVERFLOW);
1299 gen_store_gpr(t0, rt);
1306 tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
1308 tcg_gen_movi_tl(cpu_gpr[rt], uimm);
1314 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt], regnames[rs], uimm);
1317 /* Logic with immediate operand */
1318 static void gen_logic_imm (CPUState *env, uint32_t opc, int rt, int rs, int16_t imm)
1321 const char *opn = "imm logic";
1324 /* If no destination, treat it as a NOP. */
1328 uimm = (uint16_t)imm;
1331 if (likely(rs != 0))
1332 tcg_gen_andi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
1334 tcg_gen_movi_tl(cpu_gpr[rt], 0);
1339 tcg_gen_ori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
1341 tcg_gen_movi_tl(cpu_gpr[rt], uimm);
1345 if (likely(rs != 0))
1346 tcg_gen_xori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
1348 tcg_gen_movi_tl(cpu_gpr[rt], uimm);
1352 tcg_gen_movi_tl(cpu_gpr[rt], imm << 16);
1356 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt], regnames[rs], uimm);
1359 /* Set on less than with immediate operand */
1360 static void gen_slt_imm (CPUState *env, uint32_t opc, int rt, int rs, int16_t imm)
1362 target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */
1363 const char *opn = "imm arith";
1367 /* If no destination, treat it as a NOP. */
1371 t0 = tcg_temp_new();
1372 gen_load_gpr(t0, rs);
1375 gen_op_lti(cpu_gpr[rt], t0, uimm);
1379 gen_op_ltiu(cpu_gpr[rt], t0, uimm);
1383 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt], regnames[rs], uimm);
1387 /* Shifts with immediate operand */
1388 static void gen_shift_imm(CPUState *env, DisasContext *ctx, uint32_t opc,
1389 int rt, int rs, int16_t imm)
1391 target_ulong uimm = ((uint16_t)imm) & 0x1f;
1392 const char *opn = "imm shift";
1396 /* If no destination, treat it as a NOP. */
1401 t0 = tcg_temp_new();
1402 gen_load_gpr(t0, rs);
1405 tcg_gen_shli_tl(t0, t0, uimm);
1406 tcg_gen_ext32s_tl(cpu_gpr[rt], t0);
1410 tcg_gen_ext32s_tl(t0, t0);
1411 tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm);
1415 switch ((ctx->opcode >> 21) & 0x1f) {
1418 tcg_gen_ext32u_tl(t0, t0);
1419 tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm);
1421 tcg_gen_ext32s_tl(cpu_gpr[rt], t0);
1426 /* rotr is decoded as srl on non-R2 CPUs */
1427 if (env->insn_flags & ISA_MIPS32R2) {
1429 TCGv_i32 t1 = tcg_temp_new_i32();
1431 tcg_gen_trunc_tl_i32(t1, t0);
1432 tcg_gen_rotri_i32(t1, t1, uimm);
1433 tcg_gen_ext_i32_tl(cpu_gpr[rt], t1);
1434 tcg_temp_free_i32(t1);
1439 tcg_gen_ext32u_tl(t0, t0);
1440 tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm);
1442 tcg_gen_ext32s_tl(cpu_gpr[rt], t0);
1448 MIPS_INVAL("invalid srl flag");
1449 generate_exception(ctx, EXCP_RI);
1453 #if defined(TARGET_MIPS64)
1455 tcg_gen_shli_tl(cpu_gpr[rt], t0, uimm);
1459 tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm);
1463 switch ((ctx->opcode >> 21) & 0x1f) {
1465 tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm);
1469 /* drotr is decoded as dsrl on non-R2 CPUs */
1470 if (env->insn_flags & ISA_MIPS32R2) {
1472 tcg_gen_rotri_tl(cpu_gpr[rt], t0, uimm);
1476 tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm);
1481 MIPS_INVAL("invalid dsrl flag");
1482 generate_exception(ctx, EXCP_RI);
1487 tcg_gen_shli_tl(cpu_gpr[rt], t0, uimm + 32);
1491 tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm + 32);
1495 switch ((ctx->opcode >> 21) & 0x1f) {
1497 tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm + 32);
1501 /* drotr32 is decoded as dsrl32 on non-R2 CPUs */
1502 if (env->insn_flags & ISA_MIPS32R2) {
1503 tcg_gen_rotri_tl(cpu_gpr[rt], t0, uimm + 32);
1506 tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm + 32);
1511 MIPS_INVAL("invalid dsrl32 flag");
1512 generate_exception(ctx, EXCP_RI);
1518 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt], regnames[rs], uimm);
1523 static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
1524 int rd, int rs, int rt)
1526 const char *opn = "arith";
1528 if (rd == 0 && opc != OPC_ADD && opc != OPC_SUB
1529 && opc != OPC_DADD && opc != OPC_DSUB) {
1530 /* If no destination, treat it as a NOP.
1531 For add & sub, we must generate the overflow exception when needed. */
1539 TCGv t0 = tcg_temp_local_new();
1540 TCGv t1 = tcg_temp_new();
1541 TCGv t2 = tcg_temp_new();
1542 int l1 = gen_new_label();
1544 gen_load_gpr(t1, rs);
1545 gen_load_gpr(t2, rt);
1546 tcg_gen_add_tl(t0, t1, t2);
1547 tcg_gen_ext32s_tl(t0, t0);
1548 tcg_gen_xor_tl(t1, t1, t2);
1549 tcg_gen_not_tl(t1, t1);
1550 tcg_gen_xor_tl(t2, t0, t2);
1551 tcg_gen_and_tl(t1, t1, t2);
1553 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
1555 /* operands of same sign, result different sign */
1556 generate_exception(ctx, EXCP_OVERFLOW);
1558 gen_store_gpr(t0, rd);
1564 if (rs != 0 && rt != 0) {
1565 tcg_gen_add_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
1566 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
1567 } else if (rs == 0 && rt != 0) {
1568 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]);
1569 } else if (rs != 0 && rt == 0) {
1570 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
1572 tcg_gen_movi_tl(cpu_gpr[rd], 0);
1578 TCGv t0 = tcg_temp_local_new();
1579 TCGv t1 = tcg_temp_new();
1580 TCGv t2 = tcg_temp_new();
1581 int l1 = gen_new_label();
1583 gen_load_gpr(t1, rs);
1584 gen_load_gpr(t2, rt);
1585 tcg_gen_sub_tl(t0, t1, t2);
1586 tcg_gen_ext32s_tl(t0, t0);
1587 tcg_gen_xor_tl(t2, t1, t2);
1588 tcg_gen_xor_tl(t1, t0, t1);
1589 tcg_gen_and_tl(t1, t1, t2);
1591 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
1593 /* operands of different sign, first operand and result different sign */
1594 generate_exception(ctx, EXCP_OVERFLOW);
1596 gen_store_gpr(t0, rd);
1602 if (rs != 0 && rt != 0) {
1603 tcg_gen_sub_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
1604 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
1605 } else if (rs == 0 && rt != 0) {
1606 tcg_gen_neg_tl(cpu_gpr[rd], cpu_gpr[rt]);
1607 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
1608 } else if (rs != 0 && rt == 0) {
1609 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
1611 tcg_gen_movi_tl(cpu_gpr[rd], 0);
1615 #if defined(TARGET_MIPS64)
1618 TCGv t0 = tcg_temp_local_new();
1619 TCGv t1 = tcg_temp_new();
1620 TCGv t2 = tcg_temp_new();
1621 int l1 = gen_new_label();
1623 gen_load_gpr(t1, rs);
1624 gen_load_gpr(t2, rt);
1625 tcg_gen_add_tl(t0, t1, t2);
1626 tcg_gen_xor_tl(t1, t1, t2);
1627 tcg_gen_not_tl(t1, t1);
1628 tcg_gen_xor_tl(t2, t0, t2);
1629 tcg_gen_and_tl(t1, t1, t2);
1631 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
1633 /* operands of same sign, result different sign */
1634 generate_exception(ctx, EXCP_OVERFLOW);
1636 gen_store_gpr(t0, rd);
1642 if (rs != 0 && rt != 0) {
1643 tcg_gen_add_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
1644 } else if (rs == 0 && rt != 0) {
1645 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]);
1646 } else if (rs != 0 && rt == 0) {
1647 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
1649 tcg_gen_movi_tl(cpu_gpr[rd], 0);
1655 TCGv t0 = tcg_temp_local_new();
1656 TCGv t1 = tcg_temp_new();
1657 TCGv t2 = tcg_temp_new();
1658 int l1 = gen_new_label();
1660 gen_load_gpr(t1, rs);
1661 gen_load_gpr(t2, rt);
1662 tcg_gen_sub_tl(t0, t1, t2);
1663 tcg_gen_xor_tl(t2, t1, t2);
1664 tcg_gen_xor_tl(t1, t0, t1);
1665 tcg_gen_and_tl(t1, t1, t2);
1667 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
1669 /* operands of different sign, first operand and result different sign */
1670 generate_exception(ctx, EXCP_OVERFLOW);
1672 gen_store_gpr(t0, rd);
1678 if (rs != 0 && rt != 0) {
1679 tcg_gen_sub_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
1680 } else if (rs == 0 && rt != 0) {
1681 tcg_gen_neg_tl(cpu_gpr[rd], cpu_gpr[rt]);
1682 } else if (rs != 0 && rt == 0) {
1683 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
1685 tcg_gen_movi_tl(cpu_gpr[rd], 0);
1691 if (likely(rs != 0 && rt != 0)) {
1692 tcg_gen_mul_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
1693 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
1695 tcg_gen_movi_tl(cpu_gpr[rd], 0);
1700 MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]);
1703 /* Conditional move */
1704 static void gen_cond_move (CPUState *env, uint32_t opc, int rd, int rs, int rt)
1706 const char *opn = "cond move";
1710 /* If no destination, treat it as a NOP.
1711 For add & sub, we must generate the overflow exception when needed. */
1716 l1 = gen_new_label();
1719 if (likely(rt != 0))
1720 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rt], 0, l1);
1726 if (likely(rt != 0))
1727 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rt], 0, l1);
1732 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
1734 tcg_gen_movi_tl(cpu_gpr[rd], 0);
1737 MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]);
1741 static void gen_logic (CPUState *env, uint32_t opc, int rd, int rs, int rt)
1743 const char *opn = "logic";
1746 /* If no destination, treat it as a NOP. */
1753 if (likely(rs != 0 && rt != 0)) {
1754 tcg_gen_and_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
1756 tcg_gen_movi_tl(cpu_gpr[rd], 0);
1761 if (rs != 0 && rt != 0) {
1762 tcg_gen_nor_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
1763 } else if (rs == 0 && rt != 0) {
1764 tcg_gen_not_tl(cpu_gpr[rd], cpu_gpr[rt]);
1765 } else if (rs != 0 && rt == 0) {
1766 tcg_gen_not_tl(cpu_gpr[rd], cpu_gpr[rs]);
1768 tcg_gen_movi_tl(cpu_gpr[rd], ~((target_ulong)0));
1773 if (likely(rs != 0 && rt != 0)) {
1774 tcg_gen_or_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
1775 } else if (rs == 0 && rt != 0) {
1776 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]);
1777 } else if (rs != 0 && rt == 0) {
1778 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
1780 tcg_gen_movi_tl(cpu_gpr[rd], 0);
1785 if (likely(rs != 0 && rt != 0)) {
1786 tcg_gen_xor_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
1787 } else if (rs == 0 && rt != 0) {
1788 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]);
1789 } else if (rs != 0 && rt == 0) {
1790 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
1792 tcg_gen_movi_tl(cpu_gpr[rd], 0);
1797 MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]);
1800 /* Set on lower than */
1801 static void gen_slt (CPUState *env, uint32_t opc, int rd, int rs, int rt)
1803 const char *opn = "slt";
1807 /* If no destination, treat it as a NOP. */
1812 t0 = tcg_temp_new();
1813 t1 = tcg_temp_new();
1814 gen_load_gpr(t0, rs);
1815 gen_load_gpr(t1, rt);
1818 gen_op_lt(cpu_gpr[rd], t0, t1);
1822 gen_op_ltu(cpu_gpr[rd], t0, t1);
1826 MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]);
1832 static void gen_shift (CPUState *env, DisasContext *ctx, uint32_t opc,
1833 int rd, int rs, int rt)
1835 const char *opn = "shifts";
1839 /* If no destination, treat it as a NOP.
1840 For add & sub, we must generate the overflow exception when needed. */
1845 t0 = tcg_temp_new();
1846 t1 = tcg_temp_new();
1847 gen_load_gpr(t0, rs);
1848 gen_load_gpr(t1, rt);
1851 tcg_gen_andi_tl(t0, t0, 0x1f);
1852 tcg_gen_shl_tl(t0, t1, t0);
1853 tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
1857 tcg_gen_ext32s_tl(t1, t1);
1858 tcg_gen_andi_tl(t0, t0, 0x1f);
1859 tcg_gen_sar_tl(cpu_gpr[rd], t1, t0);
1863 switch ((ctx->opcode >> 6) & 0x1f) {
1865 tcg_gen_ext32u_tl(t1, t1);
1866 tcg_gen_andi_tl(t0, t0, 0x1f);
1867 tcg_gen_shr_tl(t0, t1, t0);
1868 tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
1872 /* rotrv is decoded as srlv on non-R2 CPUs */
1873 if (env->insn_flags & ISA_MIPS32R2) {
1874 TCGv_i32 t2 = tcg_temp_new_i32();
1875 TCGv_i32 t3 = tcg_temp_new_i32();
1877 tcg_gen_trunc_tl_i32(t2, t0);
1878 tcg_gen_trunc_tl_i32(t3, t1);
1879 tcg_gen_andi_i32(t2, t2, 0x1f);
1880 tcg_gen_rotr_i32(t2, t3, t2);
1881 tcg_gen_ext_i32_tl(cpu_gpr[rd], t2);
1882 tcg_temp_free_i32(t2);
1883 tcg_temp_free_i32(t3);
1886 tcg_gen_ext32u_tl(t1, t1);
1887 tcg_gen_andi_tl(t0, t0, 0x1f);
1888 tcg_gen_shr_tl(t0, t1, t0);
1889 tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
1894 MIPS_INVAL("invalid srlv flag");
1895 generate_exception(ctx, EXCP_RI);
1899 #if defined(TARGET_MIPS64)
1901 tcg_gen_andi_tl(t0, t0, 0x3f);
1902 tcg_gen_shl_tl(cpu_gpr[rd], t1, t0);
1906 tcg_gen_andi_tl(t0, t0, 0x3f);
1907 tcg_gen_sar_tl(cpu_gpr[rd], t1, t0);
1911 switch ((ctx->opcode >> 6) & 0x1f) {
1913 tcg_gen_andi_tl(t0, t0, 0x3f);
1914 tcg_gen_shr_tl(cpu_gpr[rd], t1, t0);
1918 /* drotrv is decoded as dsrlv on non-R2 CPUs */
1919 if (env->insn_flags & ISA_MIPS32R2) {
1920 tcg_gen_andi_tl(t0, t0, 0x3f);
1921 tcg_gen_rotr_tl(cpu_gpr[rd], t1, t0);
1924 tcg_gen_andi_tl(t0, t0, 0x3f);
1925 tcg_gen_shr_tl(t0, t1, t0);
1930 MIPS_INVAL("invalid dsrlv flag");
1931 generate_exception(ctx, EXCP_RI);
1937 MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]);
1942 /* Arithmetic on HI/LO registers */
1943 static void gen_HILO (DisasContext *ctx, uint32_t opc, int reg)
1945 const char *opn = "hilo";
1947 if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) {
1954 tcg_gen_mov_tl(cpu_gpr[reg], cpu_HI[0]);
1958 tcg_gen_mov_tl(cpu_gpr[reg], cpu_LO[0]);
1963 tcg_gen_mov_tl(cpu_HI[0], cpu_gpr[reg]);
1965 tcg_gen_movi_tl(cpu_HI[0], 0);
1970 tcg_gen_mov_tl(cpu_LO[0], cpu_gpr[reg]);
1972 tcg_gen_movi_tl(cpu_LO[0], 0);
1976 MIPS_DEBUG("%s %s", opn, regnames[reg]);
1979 static void gen_muldiv (DisasContext *ctx, uint32_t opc,
1982 const char *opn = "mul/div";
1988 #if defined(TARGET_MIPS64)
1992 t0 = tcg_temp_local_new();
1993 t1 = tcg_temp_local_new();
1996 t0 = tcg_temp_new();
1997 t1 = tcg_temp_new();
2001 gen_load_gpr(t0, rs);
2002 gen_load_gpr(t1, rt);
2006 int l1 = gen_new_label();
2007 int l2 = gen_new_label();
2009 tcg_gen_ext32s_tl(t0, t0);
2010 tcg_gen_ext32s_tl(t1, t1);
2011 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
2012 tcg_gen_brcondi_tl(TCG_COND_NE, t0, INT_MIN, l2);
2013 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1, l2);
2015 tcg_gen_mov_tl(cpu_LO[0], t0);
2016 tcg_gen_movi_tl(cpu_HI[0], 0);
2019 tcg_gen_div_tl(cpu_LO[0], t0, t1);
2020 tcg_gen_rem_tl(cpu_HI[0], t0, t1);
2021 tcg_gen_ext32s_tl(cpu_LO[0], cpu_LO[0]);
2022 tcg_gen_ext32s_tl(cpu_HI[0], cpu_HI[0]);
2029 int l1 = gen_new_label();
2031 tcg_gen_ext32u_tl(t0, t0);
2032 tcg_gen_ext32u_tl(t1, t1);
2033 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
2034 tcg_gen_divu_tl(cpu_LO[0], t0, t1);
2035 tcg_gen_remu_tl(cpu_HI[0], t0, t1);
2036 tcg_gen_ext32s_tl(cpu_LO[0], cpu_LO[0]);
2037 tcg_gen_ext32s_tl(cpu_HI[0], cpu_HI[0]);
2044 TCGv_i64 t2 = tcg_temp_new_i64();
2045 TCGv_i64 t3 = tcg_temp_new_i64();
2047 tcg_gen_ext_tl_i64(t2, t0);
2048 tcg_gen_ext_tl_i64(t3, t1);
2049 tcg_gen_mul_i64(t2, t2, t3);
2050 tcg_temp_free_i64(t3);
2051 tcg_gen_trunc_i64_tl(t0, t2);
2052 tcg_gen_shri_i64(t2, t2, 32);
2053 tcg_gen_trunc_i64_tl(t1, t2);
2054 tcg_temp_free_i64(t2);
2055 tcg_gen_ext32s_tl(cpu_LO[0], t0);
2056 tcg_gen_ext32s_tl(cpu_HI[0], t1);
2062 TCGv_i64 t2 = tcg_temp_new_i64();
2063 TCGv_i64 t3 = tcg_temp_new_i64();
2065 tcg_gen_ext32u_tl(t0, t0);
2066 tcg_gen_ext32u_tl(t1, t1);
2067 tcg_gen_extu_tl_i64(t2, t0);
2068 tcg_gen_extu_tl_i64(t3, t1);
2069 tcg_gen_mul_i64(t2, t2, t3);
2070 tcg_temp_free_i64(t3);
2071 tcg_gen_trunc_i64_tl(t0, t2);
2072 tcg_gen_shri_i64(t2, t2, 32);
2073 tcg_gen_trunc_i64_tl(t1, t2);
2074 tcg_temp_free_i64(t2);
2075 tcg_gen_ext32s_tl(cpu_LO[0], t0);
2076 tcg_gen_ext32s_tl(cpu_HI[0], t1);
2080 #if defined(TARGET_MIPS64)
2083 int l1 = gen_new_label();
2084 int l2 = gen_new_label();
2086 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
2087 tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2);
2088 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2);
2089 tcg_gen_mov_tl(cpu_LO[0], t0);
2090 tcg_gen_movi_tl(cpu_HI[0], 0);
2093 tcg_gen_div_i64(cpu_LO[0], t0, t1);
2094 tcg_gen_rem_i64(cpu_HI[0], t0, t1);
2101 int l1 = gen_new_label();
2103 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
2104 tcg_gen_divu_i64(cpu_LO[0], t0, t1);
2105 tcg_gen_remu_i64(cpu_HI[0], t0, t1);
2111 gen_helper_dmult(t0, t1);
2115 gen_helper_dmultu(t0, t1);
2121 TCGv_i64 t2 = tcg_temp_new_i64();
2122 TCGv_i64 t3 = tcg_temp_new_i64();
2124 tcg_gen_ext_tl_i64(t2, t0);
2125 tcg_gen_ext_tl_i64(t3, t1);
2126 tcg_gen_mul_i64(t2, t2, t3);
2127 tcg_gen_concat_tl_i64(t3, cpu_LO[0], cpu_HI[0]);
2128 tcg_gen_add_i64(t2, t2, t3);
2129 tcg_temp_free_i64(t3);
2130 tcg_gen_trunc_i64_tl(t0, t2);
2131 tcg_gen_shri_i64(t2, t2, 32);
2132 tcg_gen_trunc_i64_tl(t1, t2);
2133 tcg_temp_free_i64(t2);
2134 tcg_gen_ext32s_tl(cpu_LO[0], t0);
2135 tcg_gen_ext32s_tl(cpu_LO[1], t1);
2141 TCGv_i64 t2 = tcg_temp_new_i64();
2142 TCGv_i64 t3 = tcg_temp_new_i64();
2144 tcg_gen_ext32u_tl(t0, t0);
2145 tcg_gen_ext32u_tl(t1, t1);
2146 tcg_gen_extu_tl_i64(t2, t0);
2147 tcg_gen_extu_tl_i64(t3, t1);
2148 tcg_gen_mul_i64(t2, t2, t3);
2149 tcg_gen_concat_tl_i64(t3, cpu_LO[0], cpu_HI[0]);
2150 tcg_gen_add_i64(t2, t2, t3);
2151 tcg_temp_free_i64(t3);
2152 tcg_gen_trunc_i64_tl(t0, t2);
2153 tcg_gen_shri_i64(t2, t2, 32);
2154 tcg_gen_trunc_i64_tl(t1, t2);
2155 tcg_temp_free_i64(t2);
2156 tcg_gen_ext32s_tl(cpu_LO[0], t0);
2157 tcg_gen_ext32s_tl(cpu_HI[0], t1);
2163 TCGv_i64 t2 = tcg_temp_new_i64();
2164 TCGv_i64 t3 = tcg_temp_new_i64();
2166 tcg_gen_ext_tl_i64(t2, t0);
2167 tcg_gen_ext_tl_i64(t3, t1);
2168 tcg_gen_mul_i64(t2, t2, t3);
2169 tcg_gen_concat_tl_i64(t3, cpu_LO[0], cpu_HI[0]);
2170 tcg_gen_sub_i64(t2, t2, t3);
2171 tcg_temp_free_i64(t3);
2172 tcg_gen_trunc_i64_tl(t0, t2);
2173 tcg_gen_shri_i64(t2, t2, 32);
2174 tcg_gen_trunc_i64_tl(t1, t2);
2175 tcg_temp_free_i64(t2);
2176 tcg_gen_ext32s_tl(cpu_LO[0], t0);
2177 tcg_gen_ext32s_tl(cpu_HI[0], t1);
2183 TCGv_i64 t2 = tcg_temp_new_i64();
2184 TCGv_i64 t3 = tcg_temp_new_i64();
2186 tcg_gen_ext32u_tl(t0, t0);
2187 tcg_gen_ext32u_tl(t1, t1);
2188 tcg_gen_extu_tl_i64(t2, t0);
2189 tcg_gen_extu_tl_i64(t3, t1);
2190 tcg_gen_mul_i64(t2, t2, t3);
2191 tcg_gen_concat_tl_i64(t3, cpu_LO[0], cpu_HI[0]);
2192 tcg_gen_sub_i64(t2, t2, t3);
2193 tcg_temp_free_i64(t3);
2194 tcg_gen_trunc_i64_tl(t0, t2);
2195 tcg_gen_shri_i64(t2, t2, 32);
2196 tcg_gen_trunc_i64_tl(t1, t2);
2197 tcg_temp_free_i64(t2);
2198 tcg_gen_ext32s_tl(cpu_LO[0], t0);
2199 tcg_gen_ext32s_tl(cpu_HI[0], t1);
2205 generate_exception(ctx, EXCP_RI);
2208 MIPS_DEBUG("%s %s %s", opn, regnames[rs], regnames[rt]);
2214 static void gen_mul_vr54xx (DisasContext *ctx, uint32_t opc,
2215 int rd, int rs, int rt)
2217 const char *opn = "mul vr54xx";
2218 TCGv t0 = tcg_temp_new();
2219 TCGv t1 = tcg_temp_new();
2221 gen_load_gpr(t0, rs);
2222 gen_load_gpr(t1, rt);
2225 case OPC_VR54XX_MULS:
2226 gen_helper_muls(t0, t0, t1);
2229 case OPC_VR54XX_MULSU:
2230 gen_helper_mulsu(t0, t0, t1);
2233 case OPC_VR54XX_MACC:
2234 gen_helper_macc(t0, t0, t1);
2237 case OPC_VR54XX_MACCU:
2238 gen_helper_maccu(t0, t0, t1);
2241 case OPC_VR54XX_MSAC:
2242 gen_helper_msac(t0, t0, t1);
2245 case OPC_VR54XX_MSACU:
2246 gen_helper_msacu(t0, t0, t1);
2249 case OPC_VR54XX_MULHI:
2250 gen_helper_mulhi(t0, t0, t1);
2253 case OPC_VR54XX_MULHIU:
2254 gen_helper_mulhiu(t0, t0, t1);
2257 case OPC_VR54XX_MULSHI:
2258 gen_helper_mulshi(t0, t0, t1);
2261 case OPC_VR54XX_MULSHIU:
2262 gen_helper_mulshiu(t0, t0, t1);
2265 case OPC_VR54XX_MACCHI:
2266 gen_helper_macchi(t0, t0, t1);
2269 case OPC_VR54XX_MACCHIU:
2270 gen_helper_macchiu(t0, t0, t1);
2273 case OPC_VR54XX_MSACHI:
2274 gen_helper_msachi(t0, t0, t1);
2277 case OPC_VR54XX_MSACHIU:
2278 gen_helper_msachiu(t0, t0, t1);
2282 MIPS_INVAL("mul vr54xx");
2283 generate_exception(ctx, EXCP_RI);
2286 gen_store_gpr(t0, rd);
2287 MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]);
2294 static void gen_cl (DisasContext *ctx, uint32_t opc,
2297 const char *opn = "CLx";
2305 t0 = tcg_temp_new();
2306 gen_load_gpr(t0, rs);
2309 gen_helper_clo(cpu_gpr[rd], t0);
2313 gen_helper_clz(cpu_gpr[rd], t0);
2316 #if defined(TARGET_MIPS64)
2318 gen_helper_dclo(cpu_gpr[rd], t0);
2322 gen_helper_dclz(cpu_gpr[rd], t0);
2327 MIPS_DEBUG("%s %s, %s", opn, regnames[rd], regnames[rs]);
2332 static void gen_trap (DisasContext *ctx, uint32_t opc,
2333 int rs, int rt, int16_t imm)
2336 TCGv t0 = tcg_temp_new();
2337 TCGv t1 = tcg_temp_new();
2340 /* Load needed operands */
2348 /* Compare two registers */
2350 gen_load_gpr(t0, rs);
2351 gen_load_gpr(t1, rt);
2361 /* Compare register to immediate */
2362 if (rs != 0 || imm != 0) {
2363 gen_load_gpr(t0, rs);
2364 tcg_gen_movi_tl(t1, (int32_t)imm);
2371 case OPC_TEQ: /* rs == rs */
2372 case OPC_TEQI: /* r0 == 0 */
2373 case OPC_TGE: /* rs >= rs */
2374 case OPC_TGEI: /* r0 >= 0 */
2375 case OPC_TGEU: /* rs >= rs unsigned */
2376 case OPC_TGEIU: /* r0 >= 0 unsigned */
2378 generate_exception(ctx, EXCP_TRAP);
2380 case OPC_TLT: /* rs < rs */
2381 case OPC_TLTI: /* r0 < 0 */
2382 case OPC_TLTU: /* rs < rs unsigned */
2383 case OPC_TLTIU: /* r0 < 0 unsigned */
2384 case OPC_TNE: /* rs != rs */
2385 case OPC_TNEI: /* r0 != 0 */
2386 /* Never trap: treat as NOP. */
2390 int l1 = gen_new_label();
2395 tcg_gen_brcond_tl(TCG_COND_NE, t0, t1, l1);
2399 tcg_gen_brcond_tl(TCG_COND_LT, t0, t1, l1);
2403 tcg_gen_brcond_tl(TCG_COND_LTU, t0, t1, l1);
2407 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
2411 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
2415 tcg_gen_brcond_tl(TCG_COND_EQ, t0, t1, l1);
2418 generate_exception(ctx, EXCP_TRAP);
2425 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
2427 TranslationBlock *tb;
2429 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
2432 tcg_gen_exit_tb((long)tb + n);
2439 /* Branches (before delay slot) */
2440 static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
2441 int rs, int rt, int32_t offset)
2443 target_ulong btgt = -1;
2445 int bcond_compute = 0;
2446 TCGv t0 = tcg_temp_new();
2447 TCGv t1 = tcg_temp_new();
2449 if (ctx->hflags & MIPS_HFLAG_BMASK) {
2450 #ifdef MIPS_DEBUG_DISAS
2451 LOG_DISAS("Branch in delay slot at PC 0x" TARGET_FMT_lx "\n", ctx->pc);
2453 generate_exception(ctx, EXCP_RI);
2457 /* Load needed operands */
2463 /* Compare two registers */
2465 gen_load_gpr(t0, rs);
2466 gen_load_gpr(t1, rt);
2469 btgt = ctx->pc + 4 + offset;
2483 /* Compare to zero */
2485 gen_load_gpr(t0, rs);
2488 btgt = ctx->pc + 4 + offset;
2492 /* Jump to immediate */
2493 btgt = ((ctx->pc + 4) & (int32_t)0xF0000000) | (uint32_t)offset;
2497 /* Jump to register */
2498 if (offset != 0 && offset != 16) {
2499 /* Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the
2500 others are reserved. */
2501 MIPS_INVAL("jump hint");
2502 generate_exception(ctx, EXCP_RI);
2505 gen_load_gpr(btarget, rs);
2508 MIPS_INVAL("branch/jump");
2509 generate_exception(ctx, EXCP_RI);
2512 if (bcond_compute == 0) {
2513 /* No condition to be computed */
2515 case OPC_BEQ: /* rx == rx */
2516 case OPC_BEQL: /* rx == rx likely */
2517 case OPC_BGEZ: /* 0 >= 0 */
2518 case OPC_BGEZL: /* 0 >= 0 likely */
2519 case OPC_BLEZ: /* 0 <= 0 */
2520 case OPC_BLEZL: /* 0 <= 0 likely */
2522 ctx->hflags |= MIPS_HFLAG_B;
2523 MIPS_DEBUG("balways");
2525 case OPC_BGEZAL: /* 0 >= 0 */
2526 case OPC_BGEZALL: /* 0 >= 0 likely */
2527 /* Always take and link */
2529 ctx->hflags |= MIPS_HFLAG_B;
2530 MIPS_DEBUG("balways and link");
2532 case OPC_BNE: /* rx != rx */
2533 case OPC_BGTZ: /* 0 > 0 */
2534 case OPC_BLTZ: /* 0 < 0 */
2536 MIPS_DEBUG("bnever (NOP)");
2538 case OPC_BLTZAL: /* 0 < 0 */
2539 tcg_gen_movi_tl(cpu_gpr[31], ctx->pc + 8);
2540 MIPS_DEBUG("bnever and link");
2542 case OPC_BLTZALL: /* 0 < 0 likely */
2543 tcg_gen_movi_tl(cpu_gpr[31], ctx->pc + 8);
2544 /* Skip the instruction in the delay slot */
2545 MIPS_DEBUG("bnever, link and skip");
2548 case OPC_BNEL: /* rx != rx likely */
2549 case OPC_BGTZL: /* 0 > 0 likely */
2550 case OPC_BLTZL: /* 0 < 0 likely */
2551 /* Skip the instruction in the delay slot */
2552 MIPS_DEBUG("bnever and skip");
2556 ctx->hflags |= MIPS_HFLAG_B;
2557 MIPS_DEBUG("j " TARGET_FMT_lx, btgt);
2561 ctx->hflags |= MIPS_HFLAG_B;
2562 MIPS_DEBUG("jal " TARGET_FMT_lx, btgt);
2565 ctx->hflags |= MIPS_HFLAG_BR;
2566 MIPS_DEBUG("jr %s", regnames[rs]);
2570 ctx->hflags |= MIPS_HFLAG_BR;
2571 MIPS_DEBUG("jalr %s, %s", regnames[rt], regnames[rs]);
2574 MIPS_INVAL("branch/jump");
2575 generate_exception(ctx, EXCP_RI);
2581 gen_op_eq(bcond, t0, t1);
2582 MIPS_DEBUG("beq %s, %s, " TARGET_FMT_lx,
2583 regnames[rs], regnames[rt], btgt);
2586 gen_op_eq(bcond, t0, t1);
2587 MIPS_DEBUG("beql %s, %s, " TARGET_FMT_lx,
2588 regnames[rs], regnames[rt], btgt);
2591 gen_op_ne(bcond, t0, t1);
2592 MIPS_DEBUG("bne %s, %s, " TARGET_FMT_lx,
2593 regnames[rs], regnames[rt], btgt);
2596 gen_op_ne(bcond, t0, t1);
2597 MIPS_DEBUG("bnel %s, %s, " TARGET_FMT_lx,
2598 regnames[rs], regnames[rt], btgt);
2601 gen_op_gez(bcond, t0);
2602 MIPS_DEBUG("bgez %s, " TARGET_FMT_lx, regnames[rs], btgt);
2605 gen_op_gez(bcond, t0);
2606 MIPS_DEBUG("bgezl %s, " TARGET_FMT_lx, regnames[rs], btgt);
2609 gen_op_gez(bcond, t0);
2610 MIPS_DEBUG("bgezal %s, " TARGET_FMT_lx, regnames[rs], btgt);
2614 gen_op_gez(bcond, t0);
2616 MIPS_DEBUG("bgezall %s, " TARGET_FMT_lx, regnames[rs], btgt);
2619 gen_op_gtz(bcond, t0);
2620 MIPS_DEBUG("bgtz %s, " TARGET_FMT_lx, regnames[rs], btgt);
2623 gen_op_gtz(bcond, t0);
2624 MIPS_DEBUG("bgtzl %s, " TARGET_FMT_lx, regnames[rs], btgt);
2627 gen_op_lez(bcond, t0);
2628 MIPS_DEBUG("blez %s, " TARGET_FMT_lx, regnames[rs], btgt);
2631 gen_op_lez(bcond, t0);
2632 MIPS_DEBUG("blezl %s, " TARGET_FMT_lx, regnames[rs], btgt);
2635 gen_op_ltz(bcond, t0);
2636 MIPS_DEBUG("bltz %s, " TARGET_FMT_lx, regnames[rs], btgt);
2639 gen_op_ltz(bcond, t0);
2640 MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx, regnames[rs], btgt);
2643 gen_op_ltz(bcond, t0);
2645 MIPS_DEBUG("bltzal %s, " TARGET_FMT_lx, regnames[rs], btgt);
2647 ctx->hflags |= MIPS_HFLAG_BC;
2650 gen_op_ltz(bcond, t0);
2652 MIPS_DEBUG("bltzall %s, " TARGET_FMT_lx, regnames[rs], btgt);
2654 ctx->hflags |= MIPS_HFLAG_BL;
2657 MIPS_INVAL("conditional branch/jump");
2658 generate_exception(ctx, EXCP_RI);
2662 MIPS_DEBUG("enter ds: link %d cond %02x target " TARGET_FMT_lx,
2663 blink, ctx->hflags, btgt);
2665 ctx->btarget = btgt;
2667 tcg_gen_movi_tl(cpu_gpr[blink], ctx->pc + 8);
2675 /* special3 bitfield operations */
2676 static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt,
2677 int rs, int lsb, int msb)
2679 TCGv t0 = tcg_temp_new();
2680 TCGv t1 = tcg_temp_new();
2683 gen_load_gpr(t1, rs);
2688 tcg_gen_shri_tl(t0, t1, lsb);
2690 tcg_gen_andi_tl(t0, t0, (1 << (msb + 1)) - 1);
2692 tcg_gen_ext32s_tl(t0, t0);
2695 #if defined(TARGET_MIPS64)
2697 tcg_gen_shri_tl(t0, t1, lsb);
2699 tcg_gen_andi_tl(t0, t0, (1ULL << (msb + 1 + 32)) - 1);
2703 tcg_gen_shri_tl(t0, t1, lsb + 32);
2704 tcg_gen_andi_tl(t0, t0, (1ULL << (msb + 1)) - 1);
2707 tcg_gen_shri_tl(t0, t1, lsb);
2708 tcg_gen_andi_tl(t0, t0, (1ULL << (msb + 1)) - 1);
2714 mask = ((msb - lsb + 1 < 32) ? ((1 << (msb - lsb + 1)) - 1) : ~0) << lsb;
2715 gen_load_gpr(t0, rt);
2716 tcg_gen_andi_tl(t0, t0, ~mask);
2717 tcg_gen_shli_tl(t1, t1, lsb);
2718 tcg_gen_andi_tl(t1, t1, mask);
2719 tcg_gen_or_tl(t0, t0, t1);
2720 tcg_gen_ext32s_tl(t0, t0);
2722 #if defined(TARGET_MIPS64)
2726 mask = ((msb - lsb + 1 + 32 < 64) ? ((1ULL << (msb - lsb + 1 + 32)) - 1) : ~0ULL) << lsb;
2727 gen_load_gpr(t0, rt);
2728 tcg_gen_andi_tl(t0, t0, ~mask);
2729 tcg_gen_shli_tl(t1, t1, lsb);
2730 tcg_gen_andi_tl(t1, t1, mask);
2731 tcg_gen_or_tl(t0, t0, t1);
2736 mask = ((1ULL << (msb - lsb + 1)) - 1) << lsb;
2737 gen_load_gpr(t0, rt);
2738 tcg_gen_andi_tl(t0, t0, ~mask);
2739 tcg_gen_shli_tl(t1, t1, lsb + 32);
2740 tcg_gen_andi_tl(t1, t1, mask);
2741 tcg_gen_or_tl(t0, t0, t1);
2746 gen_load_gpr(t0, rt);
2747 mask = ((1ULL << (msb - lsb + 1)) - 1) << lsb;
2748 gen_load_gpr(t0, rt);
2749 tcg_gen_andi_tl(t0, t0, ~mask);
2750 tcg_gen_shli_tl(t1, t1, lsb);
2751 tcg_gen_andi_tl(t1, t1, mask);
2752 tcg_gen_or_tl(t0, t0, t1);
2757 MIPS_INVAL("bitops");
2758 generate_exception(ctx, EXCP_RI);
2763 gen_store_gpr(t0, rt);
2768 static void gen_bshfl (DisasContext *ctx, uint32_t op2, int rt, int rd)
2773 /* If no destination, treat it as a NOP. */
2778 t0 = tcg_temp_new();
2779 gen_load_gpr(t0, rt);
2783 TCGv t1 = tcg_temp_new();
2785 tcg_gen_shri_tl(t1, t0, 8);
2786 tcg_gen_andi_tl(t1, t1, 0x00FF00FF);
2787 tcg_gen_shli_tl(t0, t0, 8);
2788 tcg_gen_andi_tl(t0, t0, ~0x00FF00FF);
2789 tcg_gen_or_tl(t0, t0, t1);
2791 tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
2795 tcg_gen_ext8s_tl(cpu_gpr[rd], t0);
2798 tcg_gen_ext16s_tl(cpu_gpr[rd], t0);
2800 #if defined(TARGET_MIPS64)
2803 TCGv t1 = tcg_temp_new();
2805 tcg_gen_shri_tl(t1, t0, 8);
2806 tcg_gen_andi_tl(t1, t1, 0x00FF00FF00FF00FFULL);
2807 tcg_gen_shli_tl(t0, t0, 8);
2808 tcg_gen_andi_tl(t0, t0, ~0x00FF00FF00FF00FFULL);
2809 tcg_gen_or_tl(cpu_gpr[rd], t0, t1);
2815 TCGv t1 = tcg_temp_new();
2817 tcg_gen_shri_tl(t1, t0, 16);
2818 tcg_gen_andi_tl(t1, t1, 0x0000FFFF0000FFFFULL);
2819 tcg_gen_shli_tl(t0, t0, 16);
2820 tcg_gen_andi_tl(t0, t0, ~0x0000FFFF0000FFFFULL);
2821 tcg_gen_or_tl(t0, t0, t1);
2822 tcg_gen_shri_tl(t1, t0, 32);
2823 tcg_gen_shli_tl(t0, t0, 32);
2824 tcg_gen_or_tl(cpu_gpr[rd], t0, t1);
2830 MIPS_INVAL("bsfhl");
2831 generate_exception(ctx, EXCP_RI);
2838 #ifndef CONFIG_USER_ONLY
2839 /* CP0 (MMU and control) */
2840 static inline void gen_mfc0_load32 (TCGv arg, target_ulong off)
2842 TCGv_i32 t0 = tcg_temp_new_i32();
2844 tcg_gen_ld_i32(t0, cpu_env, off);
2845 tcg_gen_ext_i32_tl(arg, t0);
2846 tcg_temp_free_i32(t0);
2849 static inline void gen_mfc0_load64 (TCGv arg, target_ulong off)
2851 tcg_gen_ld_tl(arg, cpu_env, off);
2852 tcg_gen_ext32s_tl(arg, arg);
2855 static inline void gen_mtc0_store32 (TCGv arg, target_ulong off)
2857 TCGv_i32 t0 = tcg_temp_new_i32();
2859 tcg_gen_trunc_tl_i32(t0, arg);
2860 tcg_gen_st_i32(t0, cpu_env, off);
2861 tcg_temp_free_i32(t0);
2864 static inline void gen_mtc0_store64 (TCGv arg, target_ulong off)
2866 tcg_gen_ext32s_tl(arg, arg);
2867 tcg_gen_st_tl(arg, cpu_env, off);
2870 static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel)
2872 const char *rn = "invalid";
2875 check_insn(env, ctx, ISA_MIPS32);
2881 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Index));
2885 check_insn(env, ctx, ASE_MT);
2886 gen_helper_mfc0_mvpcontrol(arg);
2890 check_insn(env, ctx, ASE_MT);
2891 gen_helper_mfc0_mvpconf0(arg);
2895 check_insn(env, ctx, ASE_MT);
2896 gen_helper_mfc0_mvpconf1(arg);
2906 gen_helper_mfc0_random(arg);
2910 check_insn(env, ctx, ASE_MT);
2911 gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEControl));
2915 check_insn(env, ctx, ASE_MT);
2916 gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf0));
2920 check_insn(env, ctx, ASE_MT);
2921 gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf1));
2925 check_insn(env, ctx, ASE_MT);
2926 gen_mfc0_load64(arg, offsetof(CPUState, CP0_YQMask));
2930 check_insn(env, ctx, ASE_MT);
2931 gen_mfc0_load64(arg, offsetof(CPUState, CP0_VPESchedule));
2935 check_insn(env, ctx, ASE_MT);
2936 gen_mfc0_load64(arg, offsetof(CPUState, CP0_VPEScheFBack));
2937 rn = "VPEScheFBack";
2940 check_insn(env, ctx, ASE_MT);
2941 gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEOpt));
2951 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo0));
2952 tcg_gen_ext32s_tl(arg, arg);
2956 check_insn(env, ctx, ASE_MT);
2957 gen_helper_mfc0_tcstatus(arg);
2961 check_insn(env, ctx, ASE_MT);
2962 gen_helper_mfc0_tcbind(arg);
2966 check_insn(env, ctx, ASE_MT);
2967 gen_helper_mfc0_tcrestart(arg);
2971 check_insn(env, ctx, ASE_MT);
2972 gen_helper_mfc0_tchalt(arg);
2976 check_insn(env, ctx, ASE_MT);
2977 gen_helper_mfc0_tccontext(arg);
2981 check_insn(env, ctx, ASE_MT);
2982 gen_helper_mfc0_tcschedule(arg);
2986 check_insn(env, ctx, ASE_MT);
2987 gen_helper_mfc0_tcschefback(arg);
2997 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo1));
2998 tcg_gen_ext32s_tl(arg, arg);
3008 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_Context));
3009 tcg_gen_ext32s_tl(arg, arg);
3013 // gen_helper_mfc0_contextconfig(arg); /* SmartMIPS ASE */
3014 rn = "ContextConfig";
3023 gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageMask));
3027 check_insn(env, ctx, ISA_MIPS32R2);
3028 gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageGrain));
3038 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Wired));
3042 check_insn(env, ctx, ISA_MIPS32R2);
3043 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf0));
3047 check_insn(env, ctx, ISA_MIPS32R2);
3048 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf1));
3052 check_insn(env, ctx, ISA_MIPS32R2);
3053 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf2));
3057 check_insn(env, ctx, ISA_MIPS32R2);
3058 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf3));
3062 check_insn(env, ctx, ISA_MIPS32R2);
3063 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf4));
3073 check_insn(env, ctx, ISA_MIPS32R2);
3074 gen_mfc0_load32(arg, offsetof(CPUState, CP0_HWREna));
3084 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_BadVAddr));
3085 tcg_gen_ext32s_tl(arg, arg);
3095 /* Mark as an IO operation because we read the time. */
3098 gen_helper_mfc0_count(arg);
3101 ctx->bstate = BS_STOP;
3105 /* 6,7 are implementation dependent */
3113 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryHi));
3114 tcg_gen_ext32s_tl(arg, arg);
3124 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Compare));
3127 /* 6,7 are implementation dependent */
3135 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Status));
3139 check_insn(env, ctx, ISA_MIPS32R2);
3140 gen_mfc0_load32(arg, offsetof(CPUState, CP0_IntCtl));
3144 check_insn(env, ctx, ISA_MIPS32R2);
3145 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSCtl));
3149 check_insn(env, ctx, ISA_MIPS32R2);
3150 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSMap));
3160 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Cause));
3170 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EPC));
3171 tcg_gen_ext32s_tl(arg, arg);
3181 gen_mfc0_load32(arg, offsetof(CPUState, CP0_PRid));
3185 check_insn(env, ctx, ISA_MIPS32R2);
3186 gen_mfc0_load32(arg, offsetof(CPUState, CP0_EBase));
3196 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config0));
3200 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config1));
3204 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config2));
3208 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config3));
3211 /* 4,5 are reserved */
3212 /* 6,7 are implementation dependent */
3214 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config6));
3218 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config7));
3228 gen_helper_mfc0_lladdr(arg);
3238 gen_helper_1i(mfc0_watchlo, arg, sel);
3248 gen_helper_1i(mfc0_watchhi, arg, sel);
3258 #if defined(TARGET_MIPS64)
3259 check_insn(env, ctx, ISA_MIPS3);
3260 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_XContext));
3261 tcg_gen_ext32s_tl(arg, arg);
3270 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3273 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Framemask));
3281 tcg_gen_movi_tl(arg, 0); /* unimplemented */
3282 rn = "'Diagnostic"; /* implementation dependent */
3287 gen_helper_mfc0_debug(arg); /* EJTAG support */
3291 // gen_helper_mfc0_tracecontrol(arg); /* PDtrace support */
3292 rn = "TraceControl";
3295 // gen_helper_mfc0_tracecontrol2(arg); /* PDtrace support */
3296 rn = "TraceControl2";
3299 // gen_helper_mfc0_usertracedata(arg); /* PDtrace support */
3300 rn = "UserTraceData";
3303 // gen_helper_mfc0_tracebpc(arg); /* PDtrace support */
3314 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_DEPC));
3315 tcg_gen_ext32s_tl(arg, arg);
3325 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Performance0));
3326 rn = "Performance0";
3329 // gen_helper_mfc0_performance1(arg);
3330 rn = "Performance1";
3333 // gen_helper_mfc0_performance2(arg);
3334 rn = "Performance2";
3337 // gen_helper_mfc0_performance3(arg);
3338 rn = "Performance3";
3341 // gen_helper_mfc0_performance4(arg);
3342 rn = "Performance4";
3345 // gen_helper_mfc0_performance5(arg);
3346 rn = "Performance5";
3349 // gen_helper_mfc0_performance6(arg);
3350 rn = "Performance6";
3353 // gen_helper_mfc0_performance7(arg);
3354 rn = "Performance7";
3361 tcg_gen_movi_tl(arg, 0); /* unimplemented */
3367 tcg_gen_movi_tl(arg, 0); /* unimplemented */
3380 gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagLo));
3387 gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataLo));
3400 gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagHi));
3407 gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataHi));
3417 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
3418 tcg_gen_ext32s_tl(arg, arg);
3429 gen_mfc0_load32(arg, offsetof(CPUState, CP0_DESAVE));
3439 LOG_DISAS("mfc0 %s (reg %d sel %d)\n", rn, reg, sel);
3443 LOG_DISAS("mfc0 %s (reg %d sel %d)\n", rn, reg, sel);
3444 generate_exception(ctx, EXCP_RI);
3447 static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel)
3449 const char *rn = "invalid";
3452 check_insn(env, ctx, ISA_MIPS32);
3461 gen_helper_mtc0_index(arg);
3465 check_insn(env, ctx, ASE_MT);
3466 gen_helper_mtc0_mvpcontrol(arg);
3470 check_insn(env, ctx, ASE_MT);
3475 check_insn(env, ctx, ASE_MT);
3490 check_insn(env, ctx, ASE_MT);
3491 gen_helper_mtc0_vpecontrol(arg);
3495 check_insn(env, ctx, ASE_MT);
3496 gen_helper_mtc0_vpeconf0(arg);
3500 check_insn(env, ctx, ASE_MT);
3501 gen_helper_mtc0_vpeconf1(arg);
3505 check_insn(env, ctx, ASE_MT);
3506 gen_helper_mtc0_yqmask(arg);
3510 check_insn(env, ctx, ASE_MT);
3511 gen_mtc0_store64(arg, offsetof(CPUState, CP0_VPESchedule));
3515 check_insn(env, ctx, ASE_MT);
3516 gen_mtc0_store64(arg, offsetof(CPUState, CP0_VPEScheFBack));
3517 rn = "VPEScheFBack";
3520 check_insn(env, ctx, ASE_MT);
3521 gen_helper_mtc0_vpeopt(arg);
3531 gen_helper_mtc0_entrylo0(arg);
3535 check_insn(env, ctx, ASE_MT);
3536 gen_helper_mtc0_tcstatus(arg);
3540 check_insn(env, ctx, ASE_MT);
3541 gen_helper_mtc0_tcbind(arg);
3545 check_insn(env, ctx, ASE_MT);
3546 gen_helper_mtc0_tcrestart(arg);
3550 check_insn(env, ctx, ASE_MT);
3551 gen_helper_mtc0_tchalt(arg);
3555 check_insn(env, ctx, ASE_MT);
3556 gen_helper_mtc0_tccontext(arg);
3560 check_insn(env, ctx, ASE_MT);
3561 gen_helper_mtc0_tcschedule(arg);
3565 check_insn(env, ctx, ASE_MT);
3566 gen_helper_mtc0_tcschefback(arg);
3576 gen_helper_mtc0_entrylo1(arg);
3586 gen_helper_mtc0_context(arg);
3590 // gen_helper_mtc0_contextconfig(arg); /* SmartMIPS ASE */
3591 rn = "ContextConfig";
3600 gen_helper_mtc0_pagemask(arg);
3604 check_insn(env, ctx, ISA_MIPS32R2);
3605 gen_helper_mtc0_pagegrain(arg);
3615 gen_helper_mtc0_wired(arg);
3619 check_insn(env, ctx, ISA_MIPS32R2);
3620 gen_helper_mtc0_srsconf0(arg);
3624 check_insn(env, ctx, ISA_MIPS32R2);
3625 gen_helper_mtc0_srsconf1(arg);
3629 check_insn(env, ctx, ISA_MIPS32R2);
3630 gen_helper_mtc0_srsconf2(arg);
3634 check_insn(env, ctx, ISA_MIPS32R2);
3635 gen_helper_mtc0_srsconf3(arg);
3639 check_insn(env, ctx, ISA_MIPS32R2);
3640 gen_helper_mtc0_srsconf4(arg);
3650 check_insn(env, ctx, ISA_MIPS32R2);
3651 gen_helper_mtc0_hwrena(arg);
3665 gen_helper_mtc0_count(arg);
3668 /* 6,7 are implementation dependent */
3676 gen_helper_mtc0_entryhi(arg);
3686 gen_helper_mtc0_compare(arg);
3689 /* 6,7 are implementation dependent */
3697 save_cpu_state(ctx, 1);
3698 gen_helper_mtc0_status(arg);
3699 /* BS_STOP isn't good enough here, hflags may have changed. */
3700 gen_save_pc(ctx->pc + 4);
3701 ctx->bstate = BS_EXCP;
3705 check_insn(env, ctx, ISA_MIPS32R2);
3706 gen_helper_mtc0_intctl(arg);
3707 /* Stop translation as we may have switched the execution mode */
3708 ctx->bstate = BS_STOP;
3712 check_insn(env, ctx, ISA_MIPS32R2);
3713 gen_helper_mtc0_srsctl(arg);
3714 /* Stop translation as we may have switched the execution mode */
3715 ctx->bstate = BS_STOP;
3719 check_insn(env, ctx, ISA_MIPS32R2);
3720 gen_mtc0_store32(arg, offsetof(CPUState, CP0_SRSMap));
3721 /* Stop translation as we may have switched the execution mode */
3722 ctx->bstate = BS_STOP;
3732 save_cpu_state(ctx, 1);
3733 gen_helper_mtc0_cause(arg);
3743 gen_mtc0_store64(arg, offsetof(CPUState, CP0_EPC));
3757 check_insn(env, ctx, ISA_MIPS32R2);
3758 gen_helper_mtc0_ebase(arg);
3768 gen_helper_mtc0_config0(arg);
3770 /* Stop translation as we may have switched the execution mode */
3771 ctx->bstate = BS_STOP;
3774 /* ignored, read only */
3778 gen_helper_mtc0_config2(arg);
3780 /* Stop translation as we may have switched the execution mode */
3781 ctx->bstate = BS_STOP;
3784 /* ignored, read only */
3787 /* 4,5 are reserved */
3788 /* 6,7 are implementation dependent */
3798 rn = "Invalid config selector";
3815 gen_helper_1i(mtc0_watchlo, arg, sel);
3825 gen_helper_1i(mtc0_watchhi, arg, sel);
3835 #if defined(TARGET_MIPS64)
3836 check_insn(env, ctx, ISA_MIPS3);
3837 gen_helper_mtc0_xcontext(arg);
3846 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3849 gen_helper_mtc0_framemask(arg);
3858 rn = "Diagnostic"; /* implementation dependent */
3863 gen_helper_mtc0_debug(arg); /* EJTAG support */
3864 /* BS_STOP isn't good enough here, hflags may have changed. */
3865 gen_save_pc(ctx->pc + 4);
3866 ctx->bstate = BS_EXCP;
3870 // gen_helper_mtc0_tracecontrol(arg); /* PDtrace support */
3871 rn = "TraceControl";
3872 /* Stop translation as we may have switched the execution mode */
3873 ctx->bstate = BS_STOP;
3876 // gen_helper_mtc0_tracecontrol2(arg); /* PDtrace support */
3877 rn = "TraceControl2";
3878 /* Stop translation as we may have switched the execution mode */
3879 ctx->bstate = BS_STOP;
3882 /* Stop translation as we may have switched the execution mode */
3883 ctx->bstate = BS_STOP;
3884 // gen_helper_mtc0_usertracedata(arg); /* PDtrace support */
3885 rn = "UserTraceData";
3886 /* Stop translation as we may have switched the execution mode */
3887 ctx->bstate = BS_STOP;
3890 // gen_helper_mtc0_tracebpc(arg); /* PDtrace support */
3891 /* Stop translation as we may have switched the execution mode */
3892 ctx->bstate = BS_STOP;
3903 gen_mtc0_store64(arg, offsetof(CPUState, CP0_DEPC));
3913 gen_helper_mtc0_performance0(arg);
3914 rn = "Performance0";
3917 // gen_helper_mtc0_performance1(arg);
3918 rn = "Performance1";
3921 // gen_helper_mtc0_performance2(arg);
3922 rn = "Performance2";
3925 // gen_helper_mtc0_performance3(arg);
3926 rn = "Performance3";
3929 // gen_helper_mtc0_performance4(arg);
3930 rn = "Performance4";
3933 // gen_helper_mtc0_performance5(arg);
3934 rn = "Performance5";
3937 // gen_helper_mtc0_performance6(arg);
3938 rn = "Performance6";
3941 // gen_helper_mtc0_performance7(arg);
3942 rn = "Performance7";
3968 gen_helper_mtc0_taglo(arg);
3975 gen_helper_mtc0_datalo(arg);
3988 gen_helper_mtc0_taghi(arg);
3995 gen_helper_mtc0_datahi(arg);
4006 gen_mtc0_store64(arg, offsetof(CPUState, CP0_ErrorEPC));
4017 gen_mtc0_store32(arg, offsetof(CPUState, CP0_DESAVE));
4023 /* Stop translation as we may have switched the execution mode */
4024 ctx->bstate = BS_STOP;
4029 LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn, reg, sel);
4030 /* For simplicity assume that all writes can cause interrupts. */
4033 ctx->bstate = BS_STOP;
4038 LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn, reg, sel);
4039 generate_exception(ctx, EXCP_RI);
4042 #if defined(TARGET_MIPS64)
4043 static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel)
4045 const char *rn = "invalid";
4048 check_insn(env, ctx, ISA_MIPS64);
4054 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Index));
4058 check_insn(env, ctx, ASE_MT);
4059 gen_helper_mfc0_mvpcontrol(arg);
4063 check_insn(env, ctx, ASE_MT);
4064 gen_helper_mfc0_mvpconf0(arg);
4068 check_insn(env, ctx, ASE_MT);
4069 gen_helper_mfc0_mvpconf1(arg);
4079 gen_helper_mfc0_random(arg);
4083 check_insn(env, ctx, ASE_MT);
4084 gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEControl));
4088 check_insn(env, ctx, ASE_MT);
4089 gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf0));
4093 check_insn(env, ctx, ASE_MT);
4094 gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf1));
4098 check_insn(env, ctx, ASE_MT);
4099 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_YQMask));
4103 check_insn(env, ctx, ASE_MT);
4104 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_VPESchedule));
4108 check_insn(env, ctx, ASE_MT);
4109 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_VPEScheFBack));
4110 rn = "VPEScheFBack";
4113 check_insn(env, ctx, ASE_MT);
4114 gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEOpt));
4124 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo0));
4128 check_insn(env, ctx, ASE_MT);
4129 gen_helper_mfc0_tcstatus(arg);
4133 check_insn(env, ctx, ASE_MT);
4134 gen_helper_mfc0_tcbind(arg);
4138 check_insn(env, ctx, ASE_MT);
4139 gen_helper_dmfc0_tcrestart(arg);
4143 check_insn(env, ctx, ASE_MT);
4144 gen_helper_dmfc0_tchalt(arg);
4148 check_insn(env, ctx, ASE_MT);
4149 gen_helper_dmfc0_tccontext(arg);
4153 check_insn(env, ctx, ASE_MT);
4154 gen_helper_dmfc0_tcschedule(arg);
4158 check_insn(env, ctx, ASE_MT);
4159 gen_helper_dmfc0_tcschefback(arg);
4169 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo1));
4179 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_Context));
4183 // gen_helper_dmfc0_contextconfig(arg); /* SmartMIPS ASE */
4184 rn = "ContextConfig";
4193 gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageMask));
4197 check_insn(env, ctx, ISA_MIPS32R2);
4198 gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageGrain));
4208 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Wired));
4212 check_insn(env, ctx, ISA_MIPS32R2);
4213 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf0));
4217 check_insn(env, ctx, ISA_MIPS32R2);
4218 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf1));
4222 check_insn(env, ctx, ISA_MIPS32R2);
4223 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf2));
4227 check_insn(env, ctx, ISA_MIPS32R2);
4228 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf3));
4232 check_insn(env, ctx, ISA_MIPS32R2);
4233 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf4));
4243 check_insn(env, ctx, ISA_MIPS32R2);
4244 gen_mfc0_load32(arg, offsetof(CPUState, CP0_HWREna));
4254 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_BadVAddr));
4264 /* Mark as an IO operation because we read the time. */
4267 gen_helper_mfc0_count(arg);
4270 ctx->bstate = BS_STOP;
4274 /* 6,7 are implementation dependent */
4282 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryHi));
4292 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Compare));
4295 /* 6,7 are implementation dependent */
4303 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Status));
4307 check_insn(env, ctx, ISA_MIPS32R2);
4308 gen_mfc0_load32(arg, offsetof(CPUState, CP0_IntCtl));
4312 check_insn(env, ctx, ISA_MIPS32R2);
4313 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSCtl));
4317 check_insn(env, ctx, ISA_MIPS32R2);
4318 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSMap));
4328 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Cause));
4338 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EPC));
4348 gen_mfc0_load32(arg, offsetof(CPUState, CP0_PRid));
4352 check_insn(env, ctx, ISA_MIPS32R2);
4353 gen_mfc0_load32(arg, offsetof(CPUState, CP0_EBase));
4363 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config0));
4367 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config1));
4371 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config2));
4375 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config3));
4378 /* 6,7 are implementation dependent */
4380 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config6));
4384 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config7));
4394 gen_helper_dmfc0_lladdr(arg);
4404 gen_helper_1i(dmfc0_watchlo, arg, sel);
4414 gen_helper_1i(mfc0_watchhi, arg, sel);
4424 check_insn(env, ctx, ISA_MIPS3);
4425 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_XContext));
4433 /* Officially reserved, but sel 0 is used for R1x000 framemask */
4436 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Framemask));
4444 tcg_gen_movi_tl(arg, 0); /* unimplemented */
4445 rn = "'Diagnostic"; /* implementation dependent */
4450 gen_helper_mfc0_debug(arg); /* EJTAG support */
4454 // gen_helper_dmfc0_tracecontrol(arg); /* PDtrace support */
4455 rn = "TraceControl";
4458 // gen_helper_dmfc0_tracecontrol2(arg); /* PDtrace support */
4459 rn = "TraceControl2";
4462 // gen_helper_dmfc0_usertracedata(arg); /* PDtrace support */
4463 rn = "UserTraceData";
4466 // gen_helper_dmfc0_tracebpc(arg); /* PDtrace support */
4477 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_DEPC));
4487 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Performance0));
4488 rn = "Performance0";
4491 // gen_helper_dmfc0_performance1(arg);
4492 rn = "Performance1";
4495 // gen_helper_dmfc0_performance2(arg);
4496 rn = "Performance2";
4499 // gen_helper_dmfc0_performance3(arg);
4500 rn = "Performance3";
4503 // gen_helper_dmfc0_performance4(arg);
4504 rn = "Performance4";
4507 // gen_helper_dmfc0_performance5(arg);
4508 rn = "Performance5";
4511 // gen_helper_dmfc0_performance6(arg);
4512 rn = "Performance6";
4515 // gen_helper_dmfc0_performance7(arg);
4516 rn = "Performance7";
4523 tcg_gen_movi_tl(arg, 0); /* unimplemented */
4530 tcg_gen_movi_tl(arg, 0); /* unimplemented */
4543 gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagLo));
4550 gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataLo));
4563 gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagHi));
4570 gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataHi));
4580 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
4591 gen_mfc0_load32(arg, offsetof(CPUState, CP0_DESAVE));
4601 LOG_DISAS("dmfc0 %s (reg %d sel %d)\n", rn, reg, sel);
4605 LOG_DISAS("dmfc0 %s (reg %d sel %d)\n", rn, reg, sel);
4606 generate_exception(ctx, EXCP_RI);
4609 static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel)
4611 const char *rn = "invalid";
4614 check_insn(env, ctx, ISA_MIPS64);
4623 gen_helper_mtc0_index(arg);
4627 check_insn(env, ctx, ASE_MT);
4628 gen_helper_mtc0_mvpcontrol(arg);
4632 check_insn(env, ctx, ASE_MT);
4637 check_insn(env, ctx, ASE_MT);
4652 check_insn(env, ctx, ASE_MT);
4653 gen_helper_mtc0_vpecontrol(arg);
4657 check_insn(env, ctx, ASE_MT);
4658 gen_helper_mtc0_vpeconf0(arg);
4662 check_insn(env, ctx, ASE_MT);
4663 gen_helper_mtc0_vpeconf1(arg);
4667 check_insn(env, ctx, ASE_MT);
4668 gen_helper_mtc0_yqmask(arg);
4672 check_insn(env, ctx, ASE_MT);
4673 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_VPESchedule));
4677 check_insn(env, ctx, ASE_MT);
4678 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_VPEScheFBack));
4679 rn = "VPEScheFBack";
4682 check_insn(env, ctx, ASE_MT);
4683 gen_helper_mtc0_vpeopt(arg);
4693 gen_helper_mtc0_entrylo0(arg);
4697 check_insn(env, ctx, ASE_MT);
4698 gen_helper_mtc0_tcstatus(arg);
4702 check_insn(env, ctx, ASE_MT);
4703 gen_helper_mtc0_tcbind(arg);
4707 check_insn(env, ctx, ASE_MT);
4708 gen_helper_mtc0_tcrestart(arg);
4712 check_insn(env, ctx, ASE_MT);
4713 gen_helper_mtc0_tchalt(arg);
4717 check_insn(env, ctx, ASE_MT);
4718 gen_helper_mtc0_tccontext(arg);
4722 check_insn(env, ctx, ASE_MT);
4723 gen_helper_mtc0_tcschedule(arg);
4727 check_insn(env, ctx, ASE_MT);
4728 gen_helper_mtc0_tcschefback(arg);
4738 gen_helper_mtc0_entrylo1(arg);
4748 gen_helper_mtc0_context(arg);
4752 // gen_helper_mtc0_contextconfig(arg); /* SmartMIPS ASE */
4753 rn = "ContextConfig";
4762 gen_helper_mtc0_pagemask(arg);
4766 check_insn(env, ctx, ISA_MIPS32R2);
4767 gen_helper_mtc0_pagegrain(arg);
4777 gen_helper_mtc0_wired(arg);
4781 check_insn(env, ctx, ISA_MIPS32R2);
4782 gen_helper_mtc0_srsconf0(arg);
4786 check_insn(env, ctx, ISA_MIPS32R2);
4787 gen_helper_mtc0_srsconf1(arg);
4791 check_insn(env, ctx, ISA_MIPS32R2);
4792 gen_helper_mtc0_srsconf2(arg);
4796 check_insn(env, ctx, ISA_MIPS32R2);
4797 gen_helper_mtc0_srsconf3(arg);
4801 check_insn(env, ctx, ISA_MIPS32R2);
4802 gen_helper_mtc0_srsconf4(arg);
4812 check_insn(env, ctx, ISA_MIPS32R2);
4813 gen_helper_mtc0_hwrena(arg);
4827 gen_helper_mtc0_count(arg);
4830 /* 6,7 are implementation dependent */
4834 /* Stop translation as we may have switched the execution mode */
4835 ctx->bstate = BS_STOP;
4840 gen_helper_mtc0_entryhi(arg);
4850 gen_helper_mtc0_compare(arg);
4853 /* 6,7 are implementation dependent */
4857 /* Stop translation as we may have switched the execution mode */
4858 ctx->bstate = BS_STOP;
4863 save_cpu_state(ctx, 1);
4864 gen_helper_mtc0_status(arg);
4865 /* BS_STOP isn't good enough here, hflags may have changed. */
4866 gen_save_pc(ctx->pc + 4);
4867 ctx->bstate = BS_EXCP;
4871 check_insn(env, ctx, ISA_MIPS32R2);
4872 gen_helper_mtc0_intctl(arg);
4873 /* Stop translation as we may have switched the execution mode */
4874 ctx->bstate = BS_STOP;
4878 check_insn(env, ctx, ISA_MIPS32R2);
4879 gen_helper_mtc0_srsctl(arg);
4880 /* Stop translation as we may have switched the execution mode */
4881 ctx->bstate = BS_STOP;
4885 check_insn(env, ctx, ISA_MIPS32R2);
4886 gen_mtc0_store32(arg, offsetof(CPUState, CP0_SRSMap));
4887 /* Stop translation as we may have switched the execution mode */
4888 ctx->bstate = BS_STOP;
4898 save_cpu_state(ctx, 1);
4899 gen_helper_mtc0_cause(arg);
4909 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_EPC));
4923 check_insn(env, ctx, ISA_MIPS32R2);
4924 gen_helper_mtc0_ebase(arg);
4934 gen_helper_mtc0_config0(arg);
4936 /* Stop translation as we may have switched the execution mode */
4937 ctx->bstate = BS_STOP;
4940 /* ignored, read only */
4944 gen_helper_mtc0_config2(arg);
4946 /* Stop translation as we may have switched the execution mode */
4947 ctx->bstate = BS_STOP;
4953 /* 6,7 are implementation dependent */
4955 rn = "Invalid config selector";
4972 gen_helper_1i(mtc0_watchlo, arg, sel);
4982 gen_helper_1i(mtc0_watchhi, arg, sel);
4992 check_insn(env, ctx, ISA_MIPS3);
4993 gen_helper_mtc0_xcontext(arg);
5001 /* Officially reserved, but sel 0 is used for R1x000 framemask */
5004 gen_helper_mtc0_framemask(arg);
5013 rn = "Diagnostic"; /* implementation dependent */
5018 gen_helper_mtc0_debug(arg); /* EJTAG support */
5019 /* BS_STOP isn't good enough here, hflags may have changed. */
5020 gen_save_pc(ctx->pc + 4);
5021 ctx->bstate = BS_EXCP;
5025 // gen_helper_mtc0_tracecontrol(arg); /* PDtrace support */
5026 /* Stop translation as we may have switched the execution mode */
5027 ctx->bstate = BS_STOP;
5028 rn = "TraceControl";
5031 // gen_helper_mtc0_tracecontrol2(arg); /* PDtrace support */
5032 /* Stop translation as we may have switched the execution mode */
5033 ctx->bstate = BS_STOP;
5034 rn = "TraceControl2";
5037 // gen_helper_mtc0_usertracedata(arg); /* PDtrace support */
5038 /* Stop translation as we may have switched the execution mode */
5039 ctx->bstate = BS_STOP;
5040 rn = "UserTraceData";
5043 // gen_helper_mtc0_tracebpc(arg); /* PDtrace support */
5044 /* Stop translation as we may have switched the execution mode */
5045 ctx->bstate = BS_STOP;
5056 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_DEPC));
5066 gen_helper_mtc0_performance0(arg);
5067 rn = "Performance0";
5070 // gen_helper_mtc0_performance1(arg);
5071 rn = "Performance1";
5074 // gen_helper_mtc0_performance2(arg);
5075 rn = "Performance2";
5078 // gen_helper_mtc0_performance3(arg);
5079 rn = "Performance3";
5082 // gen_helper_mtc0_performance4(arg);
5083 rn = "Performance4";
5086 // gen_helper_mtc0_performance5(arg);
5087 rn = "Performance5";
5090 // gen_helper_mtc0_performance6(arg);
5091 rn = "Performance6";
5094 // gen_helper_mtc0_performance7(arg);
5095 rn = "Performance7";
5121 gen_helper_mtc0_taglo(arg);
5128 gen_helper_mtc0_datalo(arg);
5141 gen_helper_mtc0_taghi(arg);
5148 gen_helper_mtc0_datahi(arg);
5159 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
5170 gen_mtc0_store32(arg, offsetof(CPUState, CP0_DESAVE));
5176 /* Stop translation as we may have switched the execution mode */
5177 ctx->bstate = BS_STOP;
5182 LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn, reg, sel);
5183 /* For simplicity assume that all writes can cause interrupts. */
5186 ctx->bstate = BS_STOP;
5191 LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn, reg, sel);
5192 generate_exception(ctx, EXCP_RI);
5194 #endif /* TARGET_MIPS64 */
5196 static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, int rd,
5197 int u, int sel, int h)
5199 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
5200 TCGv t0 = tcg_temp_local_new();
5202 if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 &&
5203 ((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) !=
5204 (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE))))
5205 tcg_gen_movi_tl(t0, -1);
5206 else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
5207 (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC)))
5208 tcg_gen_movi_tl(t0, -1);
5214 gen_helper_mftc0_tcstatus(t0);
5217 gen_helper_mftc0_tcbind(t0);
5220 gen_helper_mftc0_tcrestart(t0);
5223 gen_helper_mftc0_tchalt(t0);
5226 gen_helper_mftc0_tccontext(t0);
5229 gen_helper_mftc0_tcschedule(t0);
5232 gen_helper_mftc0_tcschefback(t0);
5235 gen_mfc0(env, ctx, t0, rt, sel);
5242 gen_helper_mftc0_entryhi(t0);
5245 gen_mfc0(env, ctx, t0, rt, sel);
5251 gen_helper_mftc0_status(t0);
5254 gen_mfc0(env, ctx, t0, rt, sel);
5260 gen_helper_mftc0_debug(t0);
5263 gen_mfc0(env, ctx, t0, rt, sel);
5268 gen_mfc0(env, ctx, t0, rt, sel);
5270 } else switch (sel) {
5271 /* GPR registers. */
5273 gen_helper_1i(mftgpr, t0, rt);
5275 /* Auxiliary CPU registers */
5279 gen_helper_1i(mftlo, t0, 0);
5282 gen_helper_1i(mfthi, t0, 0);
5285 gen_helper_1i(mftacx, t0, 0);
5288 gen_helper_1i(mftlo, t0, 1);
5291 gen_helper_1i(mfthi, t0, 1);
5294 gen_helper_1i(mftacx, t0, 1);
5297 gen_helper_1i(mftlo, t0, 2);
5300 gen_helper_1i(mfthi, t0, 2);
5303 gen_helper_1i(mftacx, t0, 2);
5306 gen_helper_1i(mftlo, t0, 3);
5309 gen_helper_1i(mfthi, t0, 3);
5312 gen_helper_1i(mftacx, t0, 3);
5315 gen_helper_mftdsp(t0);
5321 /* Floating point (COP1). */
5323 /* XXX: For now we support only a single FPU context. */
5325 TCGv_i32 fp0 = tcg_temp_new_i32();
5327 gen_load_fpr32(fp0, rt);
5328 tcg_gen_ext_i32_tl(t0, fp0);
5329 tcg_temp_free_i32(fp0);
5331 TCGv_i32 fp0 = tcg_temp_new_i32();
5333 gen_load_fpr32h(fp0, rt);
5334 tcg_gen_ext_i32_tl(t0, fp0);
5335 tcg_temp_free_i32(fp0);
5339 /* XXX: For now we support only a single FPU context. */
5340 gen_helper_1i(cfc1, t0, rt);
5342 /* COP2: Not implemented. */
5349 LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt, u, sel, h);
5350 gen_store_gpr(t0, rd);
5356 LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt, u, sel, h);
5357 generate_exception(ctx, EXCP_RI);
5360 static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, int rt,
5361 int u, int sel, int h)
5363 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
5364 TCGv t0 = tcg_temp_local_new();
5366 gen_load_gpr(t0, rt);
5367 if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 &&
5368 ((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) !=
5369 (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE))))
5371 else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
5372 (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC)))
5379 gen_helper_mttc0_tcstatus(t0);
5382 gen_helper_mttc0_tcbind(t0);
5385 gen_helper_mttc0_tcrestart(t0);
5388 gen_helper_mttc0_tchalt(t0);
5391 gen_helper_mttc0_tccontext(t0);
5394 gen_helper_mttc0_tcschedule(t0);
5397 gen_helper_mttc0_tcschefback(t0);
5400 gen_mtc0(env, ctx, t0, rd, sel);
5407 gen_helper_mttc0_entryhi(t0);
5410 gen_mtc0(env, ctx, t0, rd, sel);
5416 gen_helper_mttc0_status(t0);
5419 gen_mtc0(env, ctx, t0, rd, sel);
5425 gen_helper_mttc0_debug(t0);
5428 gen_mtc0(env, ctx, t0, rd, sel);
5433 gen_mtc0(env, ctx, t0, rd, sel);
5435 } else switch (sel) {
5436 /* GPR registers. */
5438 gen_helper_1i(mttgpr, t0, rd);
5440 /* Auxiliary CPU registers */
5444 gen_helper_1i(mttlo, t0, 0);
5447 gen_helper_1i(mtthi, t0, 0);
5450 gen_helper_1i(mttacx, t0, 0);
5453 gen_helper_1i(mttlo, t0, 1);
5456 gen_helper_1i(mtthi, t0, 1);
5459 gen_helper_1i(mttacx, t0, 1);
5462 gen_helper_1i(mttlo, t0, 2);
5465 gen_helper_1i(mtthi, t0, 2);
5468 gen_helper_1i(mttacx, t0, 2);
5471 gen_helper_1i(mttlo, t0, 3);
5474 gen_helper_1i(mtthi, t0, 3);
5477 gen_helper_1i(mttacx, t0, 3);
5480 gen_helper_mttdsp(t0);
5486 /* Floating point (COP1). */
5488 /* XXX: For now we support only a single FPU context. */
5490 TCGv_i32 fp0 = tcg_temp_new_i32();
5492 tcg_gen_trunc_tl_i32(fp0, t0);
5493 gen_store_fpr32(fp0, rd);
5494 tcg_temp_free_i32(fp0);
5496 TCGv_i32 fp0 = tcg_temp_new_i32();
5498 tcg_gen_trunc_tl_i32(fp0, t0);
5499 gen_store_fpr32h(fp0, rd);
5500 tcg_temp_free_i32(fp0);
5504 /* XXX: For now we support only a single FPU context. */
5505 gen_helper_1i(ctc1, t0, rd);
5507 /* COP2: Not implemented. */
5514 LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h);
5520 LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h);
5521 generate_exception(ctx, EXCP_RI);
5524 static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int rd)
5526 const char *opn = "ldst";
5534 gen_mfc0(env, ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7);
5539 TCGv t0 = tcg_temp_new();
5541 gen_load_gpr(t0, rt);
5542 gen_mtc0(env, ctx, t0, rd, ctx->opcode & 0x7);
5547 #if defined(TARGET_MIPS64)
5549 check_insn(env, ctx, ISA_MIPS3);
5554 gen_dmfc0(env, ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7);
5558 check_insn(env, ctx, ISA_MIPS3);
5560 TCGv t0 = tcg_temp_new();
5562 gen_load_gpr(t0, rt);
5563 gen_dmtc0(env, ctx, t0, rd, ctx->opcode & 0x7);
5570 check_insn(env, ctx, ASE_MT);
5575 gen_mftr(env, ctx, rt, rd, (ctx->opcode >> 5) & 1,
5576 ctx->opcode & 0x7, (ctx->opcode >> 4) & 1);
5580 check_insn(env, ctx, ASE_MT);
5581 gen_mttr(env, ctx, rd, rt, (ctx->opcode >> 5) & 1,
5582 ctx->opcode & 0x7, (ctx->opcode >> 4) & 1);
5587 if (!env->tlb->helper_tlbwi)
5593 if (!env->tlb->helper_tlbwr)
5599 if (!env->tlb->helper_tlbp)
5605 if (!env->tlb->helper_tlbr)
5611 check_insn(env, ctx, ISA_MIPS2);
5613 ctx->bstate = BS_EXCP;
5617 check_insn(env, ctx, ISA_MIPS32);
5618 if (!(ctx->hflags & MIPS_HFLAG_DM)) {
5620 generate_exception(ctx, EXCP_RI);
5623 ctx->bstate = BS_EXCP;
5628 check_insn(env, ctx, ISA_MIPS3 | ISA_MIPS32);
5629 /* If we get an exception, we want to restart at next instruction */
5631 save_cpu_state(ctx, 1);
5634 ctx->bstate = BS_EXCP;
5639 generate_exception(ctx, EXCP_RI);
5642 MIPS_DEBUG("%s %s %d", opn, regnames[rt], rd);
5644 #endif /* !CONFIG_USER_ONLY */
5646 /* CP1 Branches (before delay slot) */
5647 static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,
5648 int32_t cc, int32_t offset)
5650 target_ulong btarget;
5651 const char *opn = "cp1 cond branch";
5652 TCGv_i32 t0 = tcg_temp_new_i32();
5655 check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32);
5657 btarget = ctx->pc + 4 + offset;
5661 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
5662 tcg_gen_not_i32(t0, t0);
5663 tcg_gen_andi_i32(t0, t0, 1);
5664 tcg_gen_extu_i32_tl(bcond, t0);
5668 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
5669 tcg_gen_not_i32(t0, t0);
5670 tcg_gen_andi_i32(t0, t0, 1);
5671 tcg_gen_extu_i32_tl(bcond, t0);
5675 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
5676 tcg_gen_andi_i32(t0, t0, 1);
5677 tcg_gen_extu_i32_tl(bcond, t0);
5681 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
5682 tcg_gen_andi_i32(t0, t0, 1);
5683 tcg_gen_extu_i32_tl(bcond, t0);
5686 ctx->hflags |= MIPS_HFLAG_BL;
5690 TCGv_i32 t1 = tcg_temp_new_i32();
5691 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
5692 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1));
5693 tcg_gen_or_i32(t0, t0, t1);
5694 tcg_temp_free_i32(t1);
5695 tcg_gen_not_i32(t0, t0);
5696 tcg_gen_andi_i32(t0, t0, 1);
5697 tcg_gen_extu_i32_tl(bcond, t0);
5703 TCGv_i32 t1 = tcg_temp_new_i32();
5704 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
5705 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1));
5706 tcg_gen_or_i32(t0, t0, t1);
5707 tcg_temp_free_i32(t1);
5708 tcg_gen_andi_i32(t0, t0, 1);
5709 tcg_gen_extu_i32_tl(bcond, t0);
5715 TCGv_i32 t1 = tcg_temp_new_i32();
5716 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
5717 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1));
5718 tcg_gen_or_i32(t0, t0, t1);
5719 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+2));
5720 tcg_gen_or_i32(t0, t0, t1);
5721 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+3));
5722 tcg_gen_or_i32(t0, t0, t1);
5723 tcg_temp_free_i32(t1);
5724 tcg_gen_not_i32(t0, t0);
5725 tcg_gen_andi_i32(t0, t0, 1);
5726 tcg_gen_extu_i32_tl(bcond, t0);
5732 TCGv_i32 t1 = tcg_temp_new_i32();
5733 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
5734 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1));
5735 tcg_gen_or_i32(t0, t0, t1);
5736 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+2));
5737 tcg_gen_or_i32(t0, t0, t1);
5738 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+3));
5739 tcg_gen_or_i32(t0, t0, t1);
5740 tcg_temp_free_i32(t1);
5741 tcg_gen_andi_i32(t0, t0, 1);
5742 tcg_gen_extu_i32_tl(bcond, t0);
5746 ctx->hflags |= MIPS_HFLAG_BC;
5750 generate_exception (ctx, EXCP_RI);
5753 MIPS_DEBUG("%s: cond %02x target " TARGET_FMT_lx, opn,
5754 ctx->hflags, btarget);
5755 ctx->btarget = btarget;
5758 tcg_temp_free_i32(t0);
5761 /* Coprocessor 1 (FPU) */
5763 #define FOP(func, fmt) (((fmt) << 21) | (func))
5765 static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
5767 const char *opn = "cp1 move";
5768 TCGv t0 = tcg_temp_new();
5773 TCGv_i32 fp0 = tcg_temp_new_i32();
5775 gen_load_fpr32(fp0, fs);
5776 tcg_gen_ext_i32_tl(t0, fp0);
5777 tcg_temp_free_i32(fp0);
5779 gen_store_gpr(t0, rt);
5783 gen_load_gpr(t0, rt);
5785 TCGv_i32 fp0 = tcg_temp_new_i32();
5787 tcg_gen_trunc_tl_i32(fp0, t0);
5788 gen_store_fpr32(fp0, fs);
5789 tcg_temp_free_i32(fp0);
5794 gen_helper_1i(cfc1, t0, fs);
5795 gen_store_gpr(t0, rt);
5799 gen_load_gpr(t0, rt);
5800 gen_helper_1i(ctc1, t0, fs);
5803 #if defined(TARGET_MIPS64)
5805 gen_load_fpr64(ctx, t0, fs);
5806 gen_store_gpr(t0, rt);
5810 gen_load_gpr(t0, rt);
5811 gen_store_fpr64(ctx, t0, fs);
5817 TCGv_i32 fp0 = tcg_temp_new_i32();
5819 gen_load_fpr32h(fp0, fs);
5820 tcg_gen_ext_i32_tl(t0, fp0);
5821 tcg_temp_free_i32(fp0);
5823 gen_store_gpr(t0, rt);
5827 gen_load_gpr(t0, rt);
5829 TCGv_i32 fp0 = tcg_temp_new_i32();
5831 tcg_gen_trunc_tl_i32(fp0, t0);
5832 gen_store_fpr32h(fp0, fs);
5833 tcg_temp_free_i32(fp0);
5839 generate_exception (ctx, EXCP_RI);
5842 MIPS_DEBUG("%s %s %s", opn, regnames[rt], fregnames[fs]);
5848 static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf)
5864 l1 = gen_new_label();
5865 t0 = tcg_temp_new_i32();
5866 tcg_gen_andi_i32(t0, fpu_fcr31, get_fp_bit(cc));
5867 tcg_gen_brcondi_i32(cond, t0, 0, l1);
5868 tcg_temp_free_i32(t0);
5870 tcg_gen_movi_tl(cpu_gpr[rd], 0);
5872 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
5877 static inline void gen_movcf_s (int fs, int fd, int cc, int tf)
5880 TCGv_i32 t0 = tcg_temp_new_i32();
5881 int l1 = gen_new_label();
5888 tcg_gen_andi_i32(t0, fpu_fcr31, get_fp_bit(cc));
5889 tcg_gen_brcondi_i32(cond, t0, 0, l1);
5890 gen_load_fpr32(t0, fs);
5891 gen_store_fpr32(t0, fd);
5893 tcg_temp_free_i32(t0);
5896 static inline void gen_movcf_d (DisasContext *ctx, int fs, int fd, int cc, int tf)
5899 TCGv_i32 t0 = tcg_temp_new_i32();
5901 int l1 = gen_new_label();
5908 tcg_gen_andi_i32(t0, fpu_fcr31, get_fp_bit(cc));
5909 tcg_gen_brcondi_i32(cond, t0, 0, l1);
5910 tcg_temp_free_i32(t0);
5911 fp0 = tcg_temp_new_i64();
5912 gen_load_fpr64(ctx, fp0, fs);
5913 gen_store_fpr64(ctx, fp0, fd);
5914 tcg_temp_free_i64(fp0);
5918 static inline void gen_movcf_ps (int fs, int fd, int cc, int tf)
5921 TCGv_i32 t0 = tcg_temp_new_i32();
5922 int l1 = gen_new_label();
5923 int l2 = gen_new_label();
5930 tcg_gen_andi_i32(t0, fpu_fcr31, get_fp_bit(cc));
5931 tcg_gen_brcondi_i32(cond, t0, 0, l1);
5932 gen_load_fpr32(t0, fs);
5933 gen_store_fpr32(t0, fd);
5936 tcg_gen_andi_i32(t0, fpu_fcr31, get_fp_bit(cc+1));
5937 tcg_gen_brcondi_i32(cond, t0, 0, l2);
5938 gen_load_fpr32h(t0, fs);
5939 gen_store_fpr32h(t0, fd);
5940 tcg_temp_free_i32(t0);
5945 static void gen_farith (DisasContext *ctx, uint32_t op1,
5946 int ft, int fs, int fd, int cc)
5948 const char *opn = "farith";
5949 const char *condnames[] = {
5967 const char *condnames_abs[] = {
5985 enum { BINOP, CMPOP, OTHEROP } optype = OTHEROP;
5986 uint32_t func = ctx->opcode & 0x3f;
5988 switch (ctx->opcode & FOP(0x3f, 0x1f)) {
5991 TCGv_i32 fp0 = tcg_temp_new_i32();
5992 TCGv_i32 fp1 = tcg_temp_new_i32();
5994 gen_load_fpr32(fp0, fs);
5995 gen_load_fpr32(fp1, ft);
5996 gen_helper_float_add_s(fp0, fp0, fp1);
5997 tcg_temp_free_i32(fp1);
5998 gen_store_fpr32(fp0, fd);
5999 tcg_temp_free_i32(fp0);
6006 TCGv_i32 fp0 = tcg_temp_new_i32();
6007 TCGv_i32 fp1 = tcg_temp_new_i32();
6009 gen_load_fpr32(fp0, fs);
6010 gen_load_fpr32(fp1, ft);
6011 gen_helper_float_sub_s(fp0, fp0, fp1);
6012 tcg_temp_free_i32(fp1);
6013 gen_store_fpr32(fp0, fd);
6014 tcg_temp_free_i32(fp0);
6021 TCGv_i32 fp0 = tcg_temp_new_i32();
6022 TCGv_i32 fp1 = tcg_temp_new_i32();
6024 gen_load_fpr32(fp0, fs);
6025 gen_load_fpr32(fp1, ft);
6026 gen_helper_float_mul_s(fp0, fp0, fp1);
6027 tcg_temp_free_i32(fp1);
6028 gen_store_fpr32(fp0, fd);
6029 tcg_temp_free_i32(fp0);
6036 TCGv_i32 fp0 = tcg_temp_new_i32();
6037 TCGv_i32 fp1 = tcg_temp_new_i32();
6039 gen_load_fpr32(fp0, fs);
6040 gen_load_fpr32(fp1, ft);
6041 gen_helper_float_div_s(fp0, fp0, fp1);
6042 tcg_temp_free_i32(fp1);
6043 gen_store_fpr32(fp0, fd);
6044 tcg_temp_free_i32(fp0);
6051 TCGv_i32 fp0 = tcg_temp_new_i32();
6053 gen_load_fpr32(fp0, fs);
6054 gen_helper_float_sqrt_s(fp0, fp0);
6055 gen_store_fpr32(fp0, fd);
6056 tcg_temp_free_i32(fp0);
6062 TCGv_i32 fp0 = tcg_temp_new_i32();
6064 gen_load_fpr32(fp0, fs);
6065 gen_helper_float_abs_s(fp0, fp0);
6066 gen_store_fpr32(fp0, fd);
6067 tcg_temp_free_i32(fp0);
6073 TCGv_i32 fp0 = tcg_temp_new_i32();
6075 gen_load_fpr32(fp0, fs);
6076 gen_store_fpr32(fp0, fd);
6077 tcg_temp_free_i32(fp0);
6083 TCGv_i32 fp0 = tcg_temp_new_i32();
6085 gen_load_fpr32(fp0, fs);
6086 gen_helper_float_chs_s(fp0, fp0);
6087 gen_store_fpr32(fp0, fd);
6088 tcg_temp_free_i32(fp0);
6093 check_cp1_64bitmode(ctx);
6095 TCGv_i32 fp32 = tcg_temp_new_i32();
6096 TCGv_i64 fp64 = tcg_temp_new_i64();
6098 gen_load_fpr32(fp32, fs);
6099 gen_helper_float_roundl_s(fp64, fp32);
6100 tcg_temp_free_i32(fp32);
6101 gen_store_fpr64(ctx, fp64, fd);
6102 tcg_temp_free_i64(fp64);
6107 check_cp1_64bitmode(ctx);
6109 TCGv_i32 fp32 = tcg_temp_new_i32();
6110 TCGv_i64 fp64 = tcg_temp_new_i64();
6112 gen_load_fpr32(fp32, fs);
6113 gen_helper_float_truncl_s(fp64, fp32);
6114 tcg_temp_free_i32(fp32);
6115 gen_store_fpr64(ctx, fp64, fd);
6116 tcg_temp_free_i64(fp64);
6121 check_cp1_64bitmode(ctx);
6123 TCGv_i32 fp32 = tcg_temp_new_i32();
6124 TCGv_i64 fp64 = tcg_temp_new_i64();
6126 gen_load_fpr32(fp32, fs);
6127 gen_helper_float_ceill_s(fp64, fp32);
6128 tcg_temp_free_i32(fp32);
6129 gen_store_fpr64(ctx, fp64, fd);
6130 tcg_temp_free_i64(fp64);
6135 check_cp1_64bitmode(ctx);
6137 TCGv_i32 fp32 = tcg_temp_new_i32();
6138 TCGv_i64 fp64 = tcg_temp_new_i64();
6140 gen_load_fpr32(fp32, fs);
6141 gen_helper_float_floorl_s(fp64, fp32);
6142 tcg_temp_free_i32(fp32);
6143 gen_store_fpr64(ctx, fp64, fd);
6144 tcg_temp_free_i64(fp64);
6150 TCGv_i32 fp0 = tcg_temp_new_i32();
6152 gen_load_fpr32(fp0, fs);
6153 gen_helper_float_roundw_s(fp0, fp0);
6154 gen_store_fpr32(fp0, fd);
6155 tcg_temp_free_i32(fp0);
6161 TCGv_i32 fp0 = tcg_temp_new_i32();
6163 gen_load_fpr32(fp0, fs);
6164 gen_helper_float_truncw_s(fp0, fp0);
6165 gen_store_fpr32(fp0, fd);
6166 tcg_temp_free_i32(fp0);
6172 TCGv_i32 fp0 = tcg_temp_new_i32();
6174 gen_load_fpr32(fp0, fs);
6175 gen_helper_float_ceilw_s(fp0, fp0);
6176 gen_store_fpr32(fp0, fd);
6177 tcg_temp_free_i32(fp0);
6183 TCGv_i32 fp0 = tcg_temp_new_i32();
6185 gen_load_fpr32(fp0, fs);
6186 gen_helper_float_floorw_s(fp0, fp0);
6187 gen_store_fpr32(fp0, fd);
6188 tcg_temp_free_i32(fp0);
6193 gen_movcf_s(fs, fd, (ft >> 2) & 0x7, ft & 0x1);
6198 int l1 = gen_new_label();
6202 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1);
6204 fp0 = tcg_temp_new_i32();
6205 gen_load_fpr32(fp0, fs);
6206 gen_store_fpr32(fp0, fd);
6207 tcg_temp_free_i32(fp0);
6214 int l1 = gen_new_label();
6218 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[ft], 0, l1);
6219 fp0 = tcg_temp_new_i32();
6220 gen_load_fpr32(fp0, fs);
6221 gen_store_fpr32(fp0, fd);
6222 tcg_temp_free_i32(fp0);
6231 TCGv_i32 fp0 = tcg_temp_new_i32();
6233 gen_load_fpr32(fp0, fs);
6234 gen_helper_float_recip_s(fp0, fp0);
6235 gen_store_fpr32(fp0, fd);
6236 tcg_temp_free_i32(fp0);
6243 TCGv_i32 fp0 = tcg_temp_new_i32();
6245 gen_load_fpr32(fp0, fs);
6246 gen_helper_float_rsqrt_s(fp0, fp0);
6247 gen_store_fpr32(fp0, fd);
6248 tcg_temp_free_i32(fp0);
6253 check_cp1_64bitmode(ctx);
6255 TCGv_i32 fp0 = tcg_temp_new_i32();
6256 TCGv_i32 fp1 = tcg_temp_new_i32();
6258 gen_load_fpr32(fp0, fs);
6259 gen_load_fpr32(fp1, fd);
6260 gen_helper_float_recip2_s(fp0, fp0, fp1);
6261 tcg_temp_free_i32(fp1);
6262 gen_store_fpr32(fp0, fd);
6263 tcg_temp_free_i32(fp0);
6268 check_cp1_64bitmode(ctx);
6270 TCGv_i32 fp0 = tcg_temp_new_i32();
6272 gen_load_fpr32(fp0, fs);
6273 gen_helper_float_recip1_s(fp0, fp0);
6274 gen_store_fpr32(fp0, fd);
6275 tcg_temp_free_i32(fp0);
6280 check_cp1_64bitmode(ctx);
6282 TCGv_i32 fp0 = tcg_temp_new_i32();
6284 gen_load_fpr32(fp0, fs);
6285 gen_helper_float_rsqrt1_s(fp0, fp0);
6286 gen_store_fpr32(fp0, fd);
6287 tcg_temp_free_i32(fp0);
6292 check_cp1_64bitmode(ctx);
6294 TCGv_i32 fp0 = tcg_temp_new_i32();
6295 TCGv_i32 fp1 = tcg_temp_new_i32();
6297 gen_load_fpr32(fp0, fs);
6298 gen_load_fpr32(fp1, ft);
6299 gen_helper_float_rsqrt2_s(fp0, fp0, fp1);
6300 tcg_temp_free_i32(fp1);
6301 gen_store_fpr32(fp0, fd);
6302 tcg_temp_free_i32(fp0);
6307 check_cp1_registers(ctx, fd);
6309 TCGv_i32 fp32 = tcg_temp_new_i32();
6310 TCGv_i64 fp64 = tcg_temp_new_i64();
6312 gen_load_fpr32(fp32, fs);
6313 gen_helper_float_cvtd_s(fp64, fp32);
6314 tcg_temp_free_i32(fp32);
6315 gen_store_fpr64(ctx, fp64, fd);
6316 tcg_temp_free_i64(fp64);
6322 TCGv_i32 fp0 = tcg_temp_new_i32();
6324 gen_load_fpr32(fp0, fs);
6325 gen_helper_float_cvtw_s(fp0, fp0);
6326 gen_store_fpr32(fp0, fd);
6327 tcg_temp_free_i32(fp0);
6332 check_cp1_64bitmode(ctx);
6334 TCGv_i32 fp32 = tcg_temp_new_i32();
6335 TCGv_i64 fp64 = tcg_temp_new_i64();
6337 gen_load_fpr32(fp32, fs);
6338 gen_helper_float_cvtl_s(fp64, fp32);
6339 tcg_temp_free_i32(fp32);
6340 gen_store_fpr64(ctx, fp64, fd);
6341 tcg_temp_free_i64(fp64);
6346 check_cp1_64bitmode(ctx);
6348 TCGv_i64 fp64 = tcg_temp_new_i64();
6349 TCGv_i32 fp32_0 = tcg_temp_new_i32();
6350 TCGv_i32 fp32_1 = tcg_temp_new_i32();
6352 gen_load_fpr32(fp32_0, fs);
6353 gen_load_fpr32(fp32_1, ft);
6354 tcg_gen_concat_i32_i64(fp64, fp32_0, fp32_1);
6355 tcg_temp_free_i32(fp32_1);
6356 tcg_temp_free_i32(fp32_0);
6357 gen_store_fpr64(ctx, fp64, fd);
6358 tcg_temp_free_i64(fp64);
6379 TCGv_i32 fp0 = tcg_temp_new_i32();
6380 TCGv_i32 fp1 = tcg_temp_new_i32();
6382 gen_load_fpr32(fp0, fs);
6383 gen_load_fpr32(fp1, ft);
6384 if (ctx->opcode & (1 << 6)) {
6386 gen_cmpabs_s(func-48, fp0, fp1, cc);
6387 opn = condnames_abs[func-48];
6389 gen_cmp_s(func-48, fp0, fp1, cc);
6390 opn = condnames[func-48];
6392 tcg_temp_free_i32(fp0);
6393 tcg_temp_free_i32(fp1);
6397 check_cp1_registers(ctx, fs | ft | fd);
6399 TCGv_i64 fp0 = tcg_temp_new_i64();
6400 TCGv_i64 fp1 = tcg_temp_new_i64();
6402 gen_load_fpr64(ctx, fp0, fs);
6403 gen_load_fpr64(ctx, fp1, ft);
6404 gen_helper_float_add_d(fp0, fp0, fp1);
6405 tcg_temp_free_i64(fp1);
6406 gen_store_fpr64(ctx, fp0, fd);
6407 tcg_temp_free_i64(fp0);
6413 check_cp1_registers(ctx, fs | ft | fd);
6415 TCGv_i64 fp0 = tcg_temp_new_i64();
6416 TCGv_i64 fp1 = tcg_temp_new_i64();
6418 gen_load_fpr64(ctx, fp0, fs);
6419 gen_load_fpr64(ctx, fp1, ft);
6420 gen_helper_float_sub_d(fp0, fp0, fp1);
6421 tcg_temp_free_i64(fp1);
6422 gen_store_fpr64(ctx, fp0, fd);
6423 tcg_temp_free_i64(fp0);
6429 check_cp1_registers(ctx, fs | ft | fd);
6431 TCGv_i64 fp0 = tcg_temp_new_i64();
6432 TCGv_i64 fp1 = tcg_temp_new_i64();
6434 gen_load_fpr64(ctx, fp0, fs);
6435 gen_load_fpr64(ctx, fp1, ft);
6436 gen_helper_float_mul_d(fp0, fp0, fp1);
6437 tcg_temp_free_i64(fp1);
6438 gen_store_fpr64(ctx, fp0, fd);
6439 tcg_temp_free_i64(fp0);
6445 check_cp1_registers(ctx, fs | ft | fd);
6447 TCGv_i64 fp0 = tcg_temp_new_i64();
6448 TCGv_i64 fp1 = tcg_temp_new_i64();
6450 gen_load_fpr64(ctx, fp0, fs);
6451 gen_load_fpr64(ctx, fp1, ft);
6452 gen_helper_float_div_d(fp0, fp0, fp1);
6453 tcg_temp_free_i64(fp1);
6454 gen_store_fpr64(ctx, fp0, fd);
6455 tcg_temp_free_i64(fp0);
6461 check_cp1_registers(ctx, fs | fd);
6463 TCGv_i64 fp0 = tcg_temp_new_i64();
6465 gen_load_fpr64(ctx, fp0, fs);
6466 gen_helper_float_sqrt_d(fp0, fp0);
6467 gen_store_fpr64(ctx, fp0, fd);
6468 tcg_temp_free_i64(fp0);
6473 check_cp1_registers(ctx, fs | fd);
6475 TCGv_i64 fp0 = tcg_temp_new_i64();
6477 gen_load_fpr64(ctx, fp0, fs);
6478 gen_helper_float_abs_d(fp0, fp0);
6479 gen_store_fpr64(ctx, fp0, fd);
6480 tcg_temp_free_i64(fp0);
6485 check_cp1_registers(ctx, fs | fd);
6487 TCGv_i64 fp0 = tcg_temp_new_i64();
6489 gen_load_fpr64(ctx, fp0, fs);
6490 gen_store_fpr64(ctx, fp0, fd);
6491 tcg_temp_free_i64(fp0);
6496 check_cp1_registers(ctx, fs | fd);
6498 TCGv_i64 fp0 = tcg_temp_new_i64();
6500 gen_load_fpr64(ctx, fp0, fs);
6501 gen_helper_float_chs_d(fp0, fp0);
6502 gen_store_fpr64(ctx, fp0, fd);
6503 tcg_temp_free_i64(fp0);
6508 check_cp1_64bitmode(ctx);
6510 TCGv_i64 fp0 = tcg_temp_new_i64();
6512 gen_load_fpr64(ctx, fp0, fs);
6513 gen_helper_float_roundl_d(fp0, fp0);
6514 gen_store_fpr64(ctx, fp0, fd);
6515 tcg_temp_free_i64(fp0);
6520 check_cp1_64bitmode(ctx);
6522 TCGv_i64 fp0 = tcg_temp_new_i64();
6524 gen_load_fpr64(ctx, fp0, fs);
6525 gen_helper_float_truncl_d(fp0, fp0);
6526 gen_store_fpr64(ctx, fp0, fd);
6527 tcg_temp_free_i64(fp0);
6532 check_cp1_64bitmode(ctx);
6534 TCGv_i64 fp0 = tcg_temp_new_i64();
6536 gen_load_fpr64(ctx, fp0, fs);
6537 gen_helper_float_ceill_d(fp0, fp0);
6538 gen_store_fpr64(ctx, fp0, fd);
6539 tcg_temp_free_i64(fp0);
6544 check_cp1_64bitmode(ctx);
6546 TCGv_i64 fp0 = tcg_temp_new_i64();
6548 gen_load_fpr64(ctx, fp0, fs);
6549 gen_helper_float_floorl_d(fp0, fp0);
6550 gen_store_fpr64(ctx, fp0, fd);
6551 tcg_temp_free_i64(fp0);
6556 check_cp1_registers(ctx, fs);
6558 TCGv_i32 fp32 = tcg_temp_new_i32();
6559 TCGv_i64 fp64 = tcg_temp_new_i64();
6561 gen_load_fpr64(ctx, fp64, fs);
6562 gen_helper_float_roundw_d(fp32, fp64);
6563 tcg_temp_free_i64(fp64);
6564 gen_store_fpr32(fp32, fd);
6565 tcg_temp_free_i32(fp32);
6570 check_cp1_registers(ctx, fs);
6572 TCGv_i32 fp32 = tcg_temp_new_i32();
6573 TCGv_i64 fp64 = tcg_temp_new_i64();
6575 gen_load_fpr64(ctx, fp64, fs);
6576 gen_helper_float_truncw_d(fp32, fp64);
6577 tcg_temp_free_i64(fp64);
6578 gen_store_fpr32(fp32, fd);
6579 tcg_temp_free_i32(fp32);
6584 check_cp1_registers(ctx, fs);
6586 TCGv_i32 fp32 = tcg_temp_new_i32();
6587 TCGv_i64 fp64 = tcg_temp_new_i64();
6589 gen_load_fpr64(ctx, fp64, fs);
6590 gen_helper_float_ceilw_d(fp32, fp64);
6591 tcg_temp_free_i64(fp64);
6592 gen_store_fpr32(fp32, fd);
6593 tcg_temp_free_i32(fp32);
6598 check_cp1_registers(ctx, fs);
6600 TCGv_i32 fp32 = tcg_temp_new_i32();
6601 TCGv_i64 fp64 = tcg_temp_new_i64();
6603 gen_load_fpr64(ctx, fp64, fs);
6604 gen_helper_float_floorw_d(fp32, fp64);
6605 tcg_temp_free_i64(fp64);
6606 gen_store_fpr32(fp32, fd);
6607 tcg_temp_free_i32(fp32);
6612 gen_movcf_d(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1);
6617 int l1 = gen_new_label();
6621 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1);
6623 fp0 = tcg_temp_new_i64();
6624 gen_load_fpr64(ctx, fp0, fs);
6625 gen_store_fpr64(ctx, fp0, fd);
6626 tcg_temp_free_i64(fp0);
6633 int l1 = gen_new_label();
6637 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[ft], 0, l1);
6638 fp0 = tcg_temp_new_i64();
6639 gen_load_fpr64(ctx, fp0, fs);
6640 gen_store_fpr64(ctx, fp0, fd);
6641 tcg_temp_free_i64(fp0);
6648 check_cp1_64bitmode(ctx);
6650 TCGv_i64 fp0 = tcg_temp_new_i64();
6652 gen_load_fpr64(ctx, fp0, fs);
6653 gen_helper_float_recip_d(fp0, fp0);
6654 gen_store_fpr64(ctx, fp0, fd);
6655 tcg_temp_free_i64(fp0);
6660 check_cp1_64bitmode(ctx);
6662 TCGv_i64 fp0 = tcg_temp_new_i64();
6664 gen_load_fpr64(ctx, fp0, fs);
6665 gen_helper_float_rsqrt_d(fp0, fp0);
6666 gen_store_fpr64(ctx, fp0, fd);
6667 tcg_temp_free_i64(fp0);
6672 check_cp1_64bitmode(ctx);
6674 TCGv_i64 fp0 = tcg_temp_new_i64();
6675 TCGv_i64 fp1 = tcg_temp_new_i64();
6677 gen_load_fpr64(ctx, fp0, fs);
6678 gen_load_fpr64(ctx, fp1, ft);
6679 gen_helper_float_recip2_d(fp0, fp0, fp1);
6680 tcg_temp_free_i64(fp1);
6681 gen_store_fpr64(ctx, fp0, fd);
6682 tcg_temp_free_i64(fp0);
6687 check_cp1_64bitmode(ctx);
6689 TCGv_i64 fp0 = tcg_temp_new_i64();
6691 gen_load_fpr64(ctx, fp0, fs);
6692 gen_helper_float_recip1_d(fp0, fp0);
6693 gen_store_fpr64(ctx, fp0, fd);
6694 tcg_temp_free_i64(fp0);
6699 check_cp1_64bitmode(ctx);
6701 TCGv_i64 fp0 = tcg_temp_new_i64();
6703 gen_load_fpr64(ctx, fp0, fs);
6704 gen_helper_float_rsqrt1_d(fp0, fp0);
6705 gen_store_fpr64(ctx, fp0, fd);
6706 tcg_temp_free_i64(fp0);
6711 check_cp1_64bitmode(ctx);
6713 TCGv_i64 fp0 = tcg_temp_new_i64();
6714 TCGv_i64 fp1 = tcg_temp_new_i64();
6716 gen_load_fpr64(ctx, fp0, fs);
6717 gen_load_fpr64(ctx, fp1, ft);
6718 gen_helper_float_rsqrt2_d(fp0, fp0, fp1);
6719 tcg_temp_free_i64(fp1);
6720 gen_store_fpr64(ctx, fp0, fd);
6721 tcg_temp_free_i64(fp0);
6742 TCGv_i64 fp0 = tcg_temp_new_i64();
6743 TCGv_i64 fp1 = tcg_temp_new_i64();
6745 gen_load_fpr64(ctx, fp0, fs);
6746 gen_load_fpr64(ctx, fp1, ft);
6747 if (ctx->opcode & (1 << 6)) {
6749 check_cp1_registers(ctx, fs | ft);
6750 gen_cmpabs_d(func-48, fp0, fp1, cc);
6751 opn = condnames_abs[func-48];
6753 check_cp1_registers(ctx, fs | ft);
6754 gen_cmp_d(func-48, fp0, fp1, cc);
6755 opn = condnames[func-48];
6757 tcg_temp_free_i64(fp0);
6758 tcg_temp_free_i64(fp1);
6762 check_cp1_registers(ctx, fs);
6764 TCGv_i32 fp32 = tcg_temp_new_i32();
6765 TCGv_i64 fp64 = tcg_temp_new_i64();
6767 gen_load_fpr64(ctx, fp64, fs);
6768 gen_helper_float_cvts_d(fp32, fp64);
6769 tcg_temp_free_i64(fp64);
6770 gen_store_fpr32(fp32, fd);
6771 tcg_temp_free_i32(fp32);
6776 check_cp1_registers(ctx, fs);
6778 TCGv_i32 fp32 = tcg_temp_new_i32();
6779 TCGv_i64 fp64 = tcg_temp_new_i64();
6781 gen_load_fpr64(ctx, fp64, fs);
6782 gen_helper_float_cvtw_d(fp32, fp64);
6783 tcg_temp_free_i64(fp64);
6784 gen_store_fpr32(fp32, fd);
6785 tcg_temp_free_i32(fp32);
6790 check_cp1_64bitmode(ctx);
6792 TCGv_i64 fp0 = tcg_temp_new_i64();
6794 gen_load_fpr64(ctx, fp0, fs);
6795 gen_helper_float_cvtl_d(fp0, fp0);
6796 gen_store_fpr64(ctx, fp0, fd);
6797 tcg_temp_free_i64(fp0);
6803 TCGv_i32 fp0 = tcg_temp_new_i32();
6805 gen_load_fpr32(fp0, fs);
6806 gen_helper_float_cvts_w(fp0, fp0);
6807 gen_store_fpr32(fp0, fd);
6808 tcg_temp_free_i32(fp0);
6813 check_cp1_registers(ctx, fd);
6815 TCGv_i32 fp32 = tcg_temp_new_i32();
6816 TCGv_i64 fp64 = tcg_temp_new_i64();
6818 gen_load_fpr32(fp32, fs);
6819 gen_helper_float_cvtd_w(fp64, fp32);
6820 tcg_temp_free_i32(fp32);
6821 gen_store_fpr64(ctx, fp64, fd);
6822 tcg_temp_free_i64(fp64);
6827 check_cp1_64bitmode(ctx);
6829 TCGv_i32 fp32 = tcg_temp_new_i32();
6830 TCGv_i64 fp64 = tcg_temp_new_i64();
6832 gen_load_fpr64(ctx, fp64, fs);
6833 gen_helper_float_cvts_l(fp32, fp64);
6834 tcg_temp_free_i64(fp64);
6835 gen_store_fpr32(fp32, fd);
6836 tcg_temp_free_i32(fp32);
6841 check_cp1_64bitmode(ctx);
6843 TCGv_i64 fp0 = tcg_temp_new_i64();
6845 gen_load_fpr64(ctx, fp0, fs);
6846 gen_helper_float_cvtd_l(fp0, fp0);
6847 gen_store_fpr64(ctx, fp0, fd);
6848 tcg_temp_free_i64(fp0);
6853 check_cp1_64bitmode(ctx);
6855 TCGv_i64 fp0 = tcg_temp_new_i64();
6857 gen_load_fpr64(ctx, fp0, fs);
6858 gen_helper_float_cvtps_pw(fp0, fp0);
6859 gen_store_fpr64(ctx, fp0, fd);
6860 tcg_temp_free_i64(fp0);
6865 check_cp1_64bitmode(ctx);
6867 TCGv_i64 fp0 = tcg_temp_new_i64();
6868 TCGv_i64 fp1 = tcg_temp_new_i64();
6870 gen_load_fpr64(ctx, fp0, fs);
6871 gen_load_fpr64(ctx, fp1, ft);
6872 gen_helper_float_add_ps(fp0, fp0, fp1);
6873 tcg_temp_free_i64(fp1);
6874 gen_store_fpr64(ctx, fp0, fd);
6875 tcg_temp_free_i64(fp0);
6880 check_cp1_64bitmode(ctx);
6882 TCGv_i64 fp0 = tcg_temp_new_i64();
6883 TCGv_i64 fp1 = tcg_temp_new_i64();
6885 gen_load_fpr64(ctx, fp0, fs);
6886 gen_load_fpr64(ctx, fp1, ft);
6887 gen_helper_float_sub_ps(fp0, fp0, fp1);
6888 tcg_temp_free_i64(fp1);
6889 gen_store_fpr64(ctx, fp0, fd);
6890 tcg_temp_free_i64(fp0);
6895 check_cp1_64bitmode(ctx);
6897 TCGv_i64 fp0 = tcg_temp_new_i64();
6898 TCGv_i64 fp1 = tcg_temp_new_i64();
6900 gen_load_fpr64(ctx, fp0, fs);
6901 gen_load_fpr64(ctx, fp1, ft);
6902 gen_helper_float_mul_ps(fp0, fp0, fp1);
6903 tcg_temp_free_i64(fp1);
6904 gen_store_fpr64(ctx, fp0, fd);
6905 tcg_temp_free_i64(fp0);
6910 check_cp1_64bitmode(ctx);
6912 TCGv_i64 fp0 = tcg_temp_new_i64();
6914 gen_load_fpr64(ctx, fp0, fs);
6915 gen_helper_float_abs_ps(fp0, fp0);
6916 gen_store_fpr64(ctx, fp0, fd);
6917 tcg_temp_free_i64(fp0);
6922 check_cp1_64bitmode(ctx);
6924 TCGv_i64 fp0 = tcg_temp_new_i64();
6926 gen_load_fpr64(ctx, fp0, fs);
6927 gen_store_fpr64(ctx, fp0, fd);
6928 tcg_temp_free_i64(fp0);
6933 check_cp1_64bitmode(ctx);
6935 TCGv_i64 fp0 = tcg_temp_new_i64();
6937 gen_load_fpr64(ctx, fp0, fs);
6938 gen_helper_float_chs_ps(fp0, fp0);
6939 gen_store_fpr64(ctx, fp0, fd);
6940 tcg_temp_free_i64(fp0);
6945 check_cp1_64bitmode(ctx);
6946 gen_movcf_ps(fs, fd, (ft >> 2) & 0x7, ft & 0x1);
6950 check_cp1_64bitmode(ctx);
6952 int l1 = gen_new_label();
6956 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1);
6957 fp0 = tcg_temp_new_i64();
6958 gen_load_fpr64(ctx, fp0, fs);
6959 gen_store_fpr64(ctx, fp0, fd);
6960 tcg_temp_free_i64(fp0);
6966 check_cp1_64bitmode(ctx);
6968 int l1 = gen_new_label();
6972 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[ft], 0, l1);
6973 fp0 = tcg_temp_new_i64();
6974 gen_load_fpr64(ctx, fp0, fs);
6975 gen_store_fpr64(ctx, fp0, fd);
6976 tcg_temp_free_i64(fp0);
6983 check_cp1_64bitmode(ctx);
6985 TCGv_i64 fp0 = tcg_temp_new_i64();
6986 TCGv_i64 fp1 = tcg_temp_new_i64();
6988 gen_load_fpr64(ctx, fp0, ft);
6989 gen_load_fpr64(ctx, fp1, fs);
6990 gen_helper_float_addr_ps(fp0, fp0, fp1);
6991 tcg_temp_free_i64(fp1);
6992 gen_store_fpr64(ctx, fp0, fd);
6993 tcg_temp_free_i64(fp0);
6998 check_cp1_64bitmode(ctx);
7000 TCGv_i64 fp0 = tcg_temp_new_i64();
7001 TCGv_i64 fp1 = tcg_temp_new_i64();
7003 gen_load_fpr64(ctx, fp0, ft);
7004 gen_load_fpr64(ctx, fp1, fs);
7005 gen_helper_float_mulr_ps(fp0, fp0, fp1);
7006 tcg_temp_free_i64(fp1);
7007 gen_store_fpr64(ctx, fp0, fd);
7008 tcg_temp_free_i64(fp0);
7013 check_cp1_64bitmode(ctx);
7015 TCGv_i64 fp0 = tcg_temp_new_i64();
7016 TCGv_i64 fp1 = tcg_temp_new_i64();
7018 gen_load_fpr64(ctx, fp0, fs);
7019 gen_load_fpr64(ctx, fp1, fd);
7020 gen_helper_float_recip2_ps(fp0, fp0, fp1);
7021 tcg_temp_free_i64(fp1);
7022 gen_store_fpr64(ctx, fp0, fd);
7023 tcg_temp_free_i64(fp0);
7028 check_cp1_64bitmode(ctx);
7030 TCGv_i64 fp0 = tcg_temp_new_i64();
7032 gen_load_fpr64(ctx, fp0, fs);
7033 gen_helper_float_recip1_ps(fp0, fp0);
7034 gen_store_fpr64(ctx, fp0, fd);
7035 tcg_temp_free_i64(fp0);
7040 check_cp1_64bitmode(ctx);
7042 TCGv_i64 fp0 = tcg_temp_new_i64();
7044 gen_load_fpr64(ctx, fp0, fs);
7045 gen_helper_float_rsqrt1_ps(fp0, fp0);
7046 gen_store_fpr64(ctx, fp0, fd);
7047 tcg_temp_free_i64(fp0);
7052 check_cp1_64bitmode(ctx);
7054 TCGv_i64 fp0 = tcg_temp_new_i64();
7055 TCGv_i64 fp1 = tcg_temp_new_i64();
7057 gen_load_fpr64(ctx, fp0, fs);
7058 gen_load_fpr64(ctx, fp1, ft);
7059 gen_helper_float_rsqrt2_ps(fp0, fp0, fp1);
7060 tcg_temp_free_i64(fp1);
7061 gen_store_fpr64(ctx, fp0, fd);
7062 tcg_temp_free_i64(fp0);
7067 check_cp1_64bitmode(ctx);
7069 TCGv_i32 fp0 = tcg_temp_new_i32();
7071 gen_load_fpr32h(fp0, fs);
7072 gen_helper_float_cvts_pu(fp0, fp0);
7073 gen_store_fpr32(fp0, fd);
7074 tcg_temp_free_i32(fp0);
7079 check_cp1_64bitmode(ctx);
7081 TCGv_i64 fp0 = tcg_temp_new_i64();
7083 gen_load_fpr64(ctx, fp0, fs);
7084 gen_helper_float_cvtpw_ps(fp0, fp0);
7085 gen_store_fpr64(ctx, fp0, fd);
7086 tcg_temp_free_i64(fp0);
7091 check_cp1_64bitmode(ctx);
7093 TCGv_i32 fp0 = tcg_temp_new_i32();
7095 gen_load_fpr32(fp0, fs);
7096 gen_helper_float_cvts_pl(fp0, fp0);
7097 gen_store_fpr32(fp0, fd);
7098 tcg_temp_free_i32(fp0);
7103 check_cp1_64bitmode(ctx);
7105 TCGv_i32 fp0 = tcg_temp_new_i32();
7106 TCGv_i32 fp1 = tcg_temp_new_i32();
7108 gen_load_fpr32(fp0, fs);
7109 gen_load_fpr32(fp1, ft);
7110 gen_store_fpr32h(fp0, fd);
7111 gen_store_fpr32(fp1, fd);
7112 tcg_temp_free_i32(fp0);
7113 tcg_temp_free_i32(fp1);
7118 check_cp1_64bitmode(ctx);
7120 TCGv_i32 fp0 = tcg_temp_new_i32();
7121 TCGv_i32 fp1 = tcg_temp_new_i32();
7123 gen_load_fpr32(fp0, fs);
7124 gen_load_fpr32h(fp1, ft);
7125 gen_store_fpr32(fp1, fd);
7126 gen_store_fpr32h(fp0, fd);
7127 tcg_temp_free_i32(fp0);
7128 tcg_temp_free_i32(fp1);
7133 check_cp1_64bitmode(ctx);
7135 TCGv_i32 fp0 = tcg_temp_new_i32();
7136 TCGv_i32 fp1 = tcg_temp_new_i32();
7138 gen_load_fpr32h(fp0, fs);
7139 gen_load_fpr32(fp1, ft);
7140 gen_store_fpr32(fp1, fd);
7141 gen_store_fpr32h(fp0, fd);
7142 tcg_temp_free_i32(fp0);
7143 tcg_temp_free_i32(fp1);
7148 check_cp1_64bitmode(ctx);
7150 TCGv_i32 fp0 = tcg_temp_new_i32();
7151 TCGv_i32 fp1 = tcg_temp_new_i32();
7153 gen_load_fpr32h(fp0, fs);
7154 gen_load_fpr32h(fp1, ft);
7155 gen_store_fpr32(fp1, fd);
7156 gen_store_fpr32h(fp0, fd);
7157 tcg_temp_free_i32(fp0);
7158 tcg_temp_free_i32(fp1);
7178 check_cp1_64bitmode(ctx);
7180 TCGv_i64 fp0 = tcg_temp_new_i64();
7181 TCGv_i64 fp1 = tcg_temp_new_i64();
7183 gen_load_fpr64(ctx, fp0, fs);
7184 gen_load_fpr64(ctx, fp1, ft);
7185 if (ctx->opcode & (1 << 6)) {
7186 gen_cmpabs_ps(func-48, fp0, fp1, cc);
7187 opn = condnames_abs[func-48];
7189 gen_cmp_ps(func-48, fp0, fp1, cc);
7190 opn = condnames[func-48];
7192 tcg_temp_free_i64(fp0);
7193 tcg_temp_free_i64(fp1);
7198 generate_exception (ctx, EXCP_RI);
7203 MIPS_DEBUG("%s %s, %s, %s", opn, fregnames[fd], fregnames[fs], fregnames[ft]);
7206 MIPS_DEBUG("%s %s,%s", opn, fregnames[fs], fregnames[ft]);
7209 MIPS_DEBUG("%s %s,%s", opn, fregnames[fd], fregnames[fs]);
7214 /* Coprocessor 3 (FPU) */
7215 static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
7216 int fd, int fs, int base, int index)
7218 const char *opn = "extended float load/store";
7220 TCGv t0 = tcg_temp_new();
7223 gen_load_gpr(t0, index);
7224 } else if (index == 0) {
7225 gen_load_gpr(t0, base);
7227 gen_load_gpr(t0, index);
7228 gen_op_addr_add(ctx, t0, cpu_gpr[base]);
7230 /* Don't do NOP if destination is zero: we must perform the actual
7232 save_cpu_state(ctx, 0);
7237 TCGv_i32 fp0 = tcg_temp_new_i32();
7239 tcg_gen_qemu_ld32s(t0, t0, ctx->mem_idx);
7240 tcg_gen_trunc_tl_i32(fp0, t0);
7241 gen_store_fpr32(fp0, fd);
7242 tcg_temp_free_i32(fp0);
7248 check_cp1_registers(ctx, fd);
7250 TCGv_i64 fp0 = tcg_temp_new_i64();
7252 tcg_gen_qemu_ld64(fp0, t0, ctx->mem_idx);
7253 gen_store_fpr64(ctx, fp0, fd);
7254 tcg_temp_free_i64(fp0);
7259 check_cp1_64bitmode(ctx);
7260 tcg_gen_andi_tl(t0, t0, ~0x7);
7262 TCGv_i64 fp0 = tcg_temp_new_i64();
7264 tcg_gen_qemu_ld64(fp0, t0, ctx->mem_idx);
7265 gen_store_fpr64(ctx, fp0, fd);
7266 tcg_temp_free_i64(fp0);
7273 TCGv_i32 fp0 = tcg_temp_new_i32();
7274 TCGv t1 = tcg_temp_new();
7276 gen_load_fpr32(fp0, fs);
7277 tcg_gen_extu_i32_tl(t1, fp0);
7278 tcg_gen_qemu_st32(t1, t0, ctx->mem_idx);
7279 tcg_temp_free_i32(fp0);
7287 check_cp1_registers(ctx, fs);
7289 TCGv_i64 fp0 = tcg_temp_new_i64();
7291 gen_load_fpr64(ctx, fp0, fs);
7292 tcg_gen_qemu_st64(fp0, t0, ctx->mem_idx);
7293 tcg_temp_free_i64(fp0);
7299 check_cp1_64bitmode(ctx);
7300 tcg_gen_andi_tl(t0, t0, ~0x7);
7302 TCGv_i64 fp0 = tcg_temp_new_i64();
7304 gen_load_fpr64(ctx, fp0, fs);
7305 tcg_gen_qemu_st64(fp0, t0, ctx->mem_idx);
7306 tcg_temp_free_i64(fp0);
7313 MIPS_DEBUG("%s %s, %s(%s)", opn, fregnames[store ? fs : fd],
7314 regnames[index], regnames[base]);
7317 static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
7318 int fd, int fr, int fs, int ft)
7320 const char *opn = "flt3_arith";
7324 check_cp1_64bitmode(ctx);
7326 TCGv t0 = tcg_temp_local_new();
7327 TCGv_i32 fp = tcg_temp_new_i32();
7328 TCGv_i32 fph = tcg_temp_new_i32();
7329 int l1 = gen_new_label();
7330 int l2 = gen_new_label();
7332 gen_load_gpr(t0, fr);
7333 tcg_gen_andi_tl(t0, t0, 0x7);
7335 tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
7336 gen_load_fpr32(fp, fs);
7337 gen_load_fpr32h(fph, fs);
7338 gen_store_fpr32(fp, fd);
7339 gen_store_fpr32h(fph, fd);
7342 tcg_gen_brcondi_tl(TCG_COND_NE, t0, 4, l2);
7344 #ifdef TARGET_WORDS_BIGENDIAN
7345 gen_load_fpr32(fp, fs);
7346 gen_load_fpr32h(fph, ft);
7347 gen_store_fpr32h(fp, fd);
7348 gen_store_fpr32(fph, fd);
7350 gen_load_fpr32h(fph, fs);
7351 gen_load_fpr32(fp, ft);
7352 gen_store_fpr32(fph, fd);
7353 gen_store_fpr32h(fp, fd);
7356 tcg_temp_free_i32(fp);
7357 tcg_temp_free_i32(fph);
7364 TCGv_i32 fp0 = tcg_temp_new_i32();
7365 TCGv_i32 fp1 = tcg_temp_new_i32();
7366 TCGv_i32 fp2 = tcg_temp_new_i32();
7368 gen_load_fpr32(fp0, fs);
7369 gen_load_fpr32(fp1, ft);
7370 gen_load_fpr32(fp2, fr);
7371 gen_helper_float_muladd_s(fp2, fp0, fp1, fp2);
7372 tcg_temp_free_i32(fp0);
7373 tcg_temp_free_i32(fp1);
7374 gen_store_fpr32(fp2, fd);
7375 tcg_temp_free_i32(fp2);
7381 check_cp1_registers(ctx, fd | fs | ft | fr);
7383 TCGv_i64 fp0 = tcg_temp_new_i64();
7384 TCGv_i64 fp1 = tcg_temp_new_i64();
7385 TCGv_i64 fp2 = tcg_temp_new_i64();
7387 gen_load_fpr64(ctx, fp0, fs);
7388 gen_load_fpr64(ctx, fp1, ft);
7389 gen_load_fpr64(ctx, fp2, fr);
7390 gen_helper_float_muladd_d(fp2, fp0, fp1, fp2);
7391 tcg_temp_free_i64(fp0);
7392 tcg_temp_free_i64(fp1);
7393 gen_store_fpr64(ctx, fp2, fd);
7394 tcg_temp_free_i64(fp2);
7399 check_cp1_64bitmode(ctx);
7401 TCGv_i64 fp0 = tcg_temp_new_i64();
7402 TCGv_i64 fp1 = tcg_temp_new_i64();
7403 TCGv_i64 fp2 = tcg_temp_new_i64();
7405 gen_load_fpr64(ctx, fp0, fs);
7406 gen_load_fpr64(ctx, fp1, ft);
7407 gen_load_fpr64(ctx, fp2, fr);
7408 gen_helper_float_muladd_ps(fp2, fp0, fp1, fp2);
7409 tcg_temp_free_i64(fp0);
7410 tcg_temp_free_i64(fp1);
7411 gen_store_fpr64(ctx, fp2, fd);
7412 tcg_temp_free_i64(fp2);
7419 TCGv_i32 fp0 = tcg_temp_new_i32();
7420 TCGv_i32 fp1 = tcg_temp_new_i32();
7421 TCGv_i32 fp2 = tcg_temp_new_i32();
7423 gen_load_fpr32(fp0, fs);
7424 gen_load_fpr32(fp1, ft);
7425 gen_load_fpr32(fp2, fr);
7426 gen_helper_float_mulsub_s(fp2, fp0, fp1, fp2);
7427 tcg_temp_free_i32(fp0);
7428 tcg_temp_free_i32(fp1);
7429 gen_store_fpr32(fp2, fd);
7430 tcg_temp_free_i32(fp2);
7436 check_cp1_registers(ctx, fd | fs | ft | fr);
7438 TCGv_i64 fp0 = tcg_temp_new_i64();
7439 TCGv_i64 fp1 = tcg_temp_new_i64();
7440 TCGv_i64 fp2 = tcg_temp_new_i64();
7442 gen_load_fpr64(ctx, fp0, fs);
7443 gen_load_fpr64(ctx, fp1, ft);
7444 gen_load_fpr64(ctx, fp2, fr);
7445 gen_helper_float_mulsub_d(fp2, fp0, fp1, fp2);
7446 tcg_temp_free_i64(fp0);
7447 tcg_temp_free_i64(fp1);
7448 gen_store_fpr64(ctx, fp2, fd);
7449 tcg_temp_free_i64(fp2);
7454 check_cp1_64bitmode(ctx);
7456 TCGv_i64 fp0 = tcg_temp_new_i64();
7457 TCGv_i64 fp1 = tcg_temp_new_i64();
7458 TCGv_i64 fp2 = tcg_temp_new_i64();
7460 gen_load_fpr64(ctx, fp0, fs);
7461 gen_load_fpr64(ctx, fp1, ft);
7462 gen_load_fpr64(ctx, fp2, fr);
7463 gen_helper_float_mulsub_ps(fp2, fp0, fp1, fp2);
7464 tcg_temp_free_i64(fp0);
7465 tcg_temp_free_i64(fp1);
7466 gen_store_fpr64(ctx, fp2, fd);
7467 tcg_temp_free_i64(fp2);
7474 TCGv_i32 fp0 = tcg_temp_new_i32();
7475 TCGv_i32 fp1 = tcg_temp_new_i32();
7476 TCGv_i32 fp2 = tcg_temp_new_i32();
7478 gen_load_fpr32(fp0, fs);
7479 gen_load_fpr32(fp1, ft);
7480 gen_load_fpr32(fp2, fr);
7481 gen_helper_float_nmuladd_s(fp2, fp0, fp1, fp2);
7482 tcg_temp_free_i32(fp0);
7483 tcg_temp_free_i32(fp1);
7484 gen_store_fpr32(fp2, fd);
7485 tcg_temp_free_i32(fp2);
7491 check_cp1_registers(ctx, fd | fs | ft | fr);
7493 TCGv_i64 fp0 = tcg_temp_new_i64();
7494 TCGv_i64 fp1 = tcg_temp_new_i64();
7495 TCGv_i64 fp2 = tcg_temp_new_i64();
7497 gen_load_fpr64(ctx, fp0, fs);
7498 gen_load_fpr64(ctx, fp1, ft);
7499 gen_load_fpr64(ctx, fp2, fr);
7500 gen_helper_float_nmuladd_d(fp2, fp0, fp1, fp2);
7501 tcg_temp_free_i64(fp0);
7502 tcg_temp_free_i64(fp1);
7503 gen_store_fpr64(ctx, fp2, fd);
7504 tcg_temp_free_i64(fp2);
7509 check_cp1_64bitmode(ctx);
7511 TCGv_i64 fp0 = tcg_temp_new_i64();
7512 TCGv_i64 fp1 = tcg_temp_new_i64();
7513 TCGv_i64 fp2 = tcg_temp_new_i64();
7515 gen_load_fpr64(ctx, fp0, fs);
7516 gen_load_fpr64(ctx, fp1, ft);
7517 gen_load_fpr64(ctx, fp2, fr);
7518 gen_helper_float_nmuladd_ps(fp2, fp0, fp1, fp2);
7519 tcg_temp_free_i64(fp0);
7520 tcg_temp_free_i64(fp1);
7521 gen_store_fpr64(ctx, fp2, fd);
7522 tcg_temp_free_i64(fp2);
7529 TCGv_i32 fp0 = tcg_temp_new_i32();
7530 TCGv_i32 fp1 = tcg_temp_new_i32();
7531 TCGv_i32 fp2 = tcg_temp_new_i32();
7533 gen_load_fpr32(fp0, fs);
7534 gen_load_fpr32(fp1, ft);
7535 gen_load_fpr32(fp2, fr);
7536 gen_helper_float_nmulsub_s(fp2, fp0, fp1, fp2);
7537 tcg_temp_free_i32(fp0);
7538 tcg_temp_free_i32(fp1);
7539 gen_store_fpr32(fp2, fd);
7540 tcg_temp_free_i32(fp2);
7546 check_cp1_registers(ctx, fd | fs | ft | fr);
7548 TCGv_i64 fp0 = tcg_temp_new_i64();
7549 TCGv_i64 fp1 = tcg_temp_new_i64();
7550 TCGv_i64 fp2 = tcg_temp_new_i64();
7552 gen_load_fpr64(ctx, fp0, fs);
7553 gen_load_fpr64(ctx, fp1, ft);
7554 gen_load_fpr64(ctx, fp2, fr);
7555 gen_helper_float_nmulsub_d(fp2, fp0, fp1, fp2);
7556 tcg_temp_free_i64(fp0);
7557 tcg_temp_free_i64(fp1);
7558 gen_store_fpr64(ctx, fp2, fd);
7559 tcg_temp_free_i64(fp2);
7564 check_cp1_64bitmode(ctx);
7566 TCGv_i64 fp0 = tcg_temp_new_i64();
7567 TCGv_i64 fp1 = tcg_temp_new_i64();
7568 TCGv_i64 fp2 = tcg_temp_new_i64();
7570 gen_load_fpr64(ctx, fp0, fs);
7571 gen_load_fpr64(ctx, fp1, ft);
7572 gen_load_fpr64(ctx, fp2, fr);
7573 gen_helper_float_nmulsub_ps(fp2, fp0, fp1, fp2);
7574 tcg_temp_free_i64(fp0);
7575 tcg_temp_free_i64(fp1);
7576 gen_store_fpr64(ctx, fp2, fd);
7577 tcg_temp_free_i64(fp2);
7583 generate_exception (ctx, EXCP_RI);
7586 MIPS_DEBUG("%s %s, %s, %s, %s", opn, fregnames[fd], fregnames[fr],
7587 fregnames[fs], fregnames[ft]);
7590 /* ISA extensions (ASEs) */
7591 /* MIPS16 extension to MIPS32 */
7592 /* SmartMIPS extension to MIPS32 */
7594 #if defined(TARGET_MIPS64)
7596 /* MDMX extension to MIPS64 */
7600 static void decode_opc (CPUState *env, DisasContext *ctx)
7604 uint32_t op, op1, op2;
7607 /* make sure instructions are on a word boundary */
7608 if (ctx->pc & 0x3) {
7609 env->CP0_BadVAddr = ctx->pc;
7610 generate_exception(ctx, EXCP_AdEL);
7614 /* Handle blikely not taken case */
7615 if ((ctx->hflags & MIPS_HFLAG_BMASK) == MIPS_HFLAG_BL) {
7616 int l1 = gen_new_label();
7618 MIPS_DEBUG("blikely condition (" TARGET_FMT_lx ")", ctx->pc + 4);
7619 tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1);
7620 tcg_gen_movi_i32(hflags, ctx->hflags & ~MIPS_HFLAG_BMASK);
7621 gen_goto_tb(ctx, 1, ctx->pc + 4);
7624 op = MASK_OP_MAJOR(ctx->opcode);
7625 rs = (ctx->opcode >> 21) & 0x1f;
7626 rt = (ctx->opcode >> 16) & 0x1f;
7627 rd = (ctx->opcode >> 11) & 0x1f;
7628 sa = (ctx->opcode >> 6) & 0x1f;
7629 imm = (int16_t)ctx->opcode;
7632 op1 = MASK_SPECIAL(ctx->opcode);
7634 case OPC_SLL: /* Shift with immediate */
7637 gen_shift_imm(env, ctx, op1, rd, rt, sa);
7639 case OPC_MOVN: /* Conditional move */
7641 check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32);
7642 gen_cond_move(env, op1, rd, rs, rt);
7644 case OPC_ADD ... OPC_SUBU:
7645 gen_arith(env, ctx, op1, rd, rs, rt);
7647 case OPC_SLLV: /* Shifts */
7650 gen_shift(env, ctx, op1, rd, rs, rt);
7652 case OPC_SLT: /* Set on less than */
7654 gen_slt(env, op1, rd, rs, rt);
7656 case OPC_AND: /* Logic*/
7660 gen_logic(env, op1, rd, rs, rt);
7662 case OPC_MULT ... OPC_DIVU:
7664 check_insn(env, ctx, INSN_VR54XX);
7665 op1 = MASK_MUL_VR54XX(ctx->opcode);
7666 gen_mul_vr54xx(ctx, op1, rd, rs, rt);
7668 gen_muldiv(ctx, op1, rs, rt);
7670 case OPC_JR ... OPC_JALR:
7671 gen_compute_branch(ctx, op1, rs, rd, sa);
7673 case OPC_TGE ... OPC_TEQ: /* Traps */
7675 gen_trap(ctx, op1, rs, rt, -1);
7677 case OPC_MFHI: /* Move from HI/LO */
7679 gen_HILO(ctx, op1, rd);
7682 case OPC_MTLO: /* Move to HI/LO */
7683 gen_HILO(ctx, op1, rs);
7685 case OPC_PMON: /* Pmon entry point, also R4010 selsl */
7686 #ifdef MIPS_STRICT_STANDARD
7687 MIPS_INVAL("PMON / selsl");
7688 generate_exception(ctx, EXCP_RI);
7690 gen_helper_0i(pmon, sa);
7694 generate_exception(ctx, EXCP_SYSCALL);
7695 ctx->bstate = BS_STOP;
7698 generate_exception(ctx, EXCP_BREAK);
7701 #ifdef MIPS_STRICT_STANDARD
7703 generate_exception(ctx, EXCP_RI);
7705 /* Implemented as RI exception for now. */
7706 MIPS_INVAL("spim (unofficial)");
7707 generate_exception(ctx, EXCP_RI);
7715 check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32);
7716 if (env->CP0_Config1 & (1 << CP0C1_FP)) {
7717 check_cp1_enabled(ctx);
7718 gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7,
7719 (ctx->opcode >> 16) & 1);
7721 generate_exception_err(ctx, EXCP_CpU, 1);
7725 #if defined(TARGET_MIPS64)
7726 /* MIPS64 specific opcodes */
7733 check_insn(env, ctx, ISA_MIPS3);
7735 gen_shift_imm(env, ctx, op1, rd, rt, sa);
7737 case OPC_DADD ... OPC_DSUBU:
7738 check_insn(env, ctx, ISA_MIPS3);
7740 gen_arith(env, ctx, op1, rd, rs, rt);
7745 check_insn(env, ctx, ISA_MIPS3);
7747 gen_shift(env, ctx, op1, rd, rs, rt);
7749 case OPC_DMULT ... OPC_DDIVU:
7750 check_insn(env, ctx, ISA_MIPS3);
7752 gen_muldiv(ctx, op1, rs, rt);
7755 default: /* Invalid */
7756 MIPS_INVAL("special");
7757 generate_exception(ctx, EXCP_RI);
7762 op1 = MASK_SPECIAL2(ctx->opcode);
7764 case OPC_MADD ... OPC_MADDU: /* Multiply and add/sub */
7765 case OPC_MSUB ... OPC_MSUBU:
7766 check_insn(env, ctx, ISA_MIPS32);
7767 gen_muldiv(ctx, op1, rs, rt);
7770 gen_arith(env, ctx, op1, rd, rs, rt);
7774 check_insn(env, ctx, ISA_MIPS32);
7775 gen_cl(ctx, op1, rd, rs);
7778 /* XXX: not clear which exception should be raised
7779 * when in debug mode...
7781 check_insn(env, ctx, ISA_MIPS32);
7782 if (!(ctx->hflags & MIPS_HFLAG_DM)) {
7783 generate_exception(ctx, EXCP_DBp);
7785 generate_exception(ctx, EXCP_DBp);
7789 #if defined(TARGET_MIPS64)
7792 check_insn(env, ctx, ISA_MIPS64);
7794 gen_cl(ctx, op1, rd, rs);
7797 default: /* Invalid */
7798 MIPS_INVAL("special2");
7799 generate_exception(ctx, EXCP_RI);
7804 op1 = MASK_SPECIAL3(ctx->opcode);
7808 check_insn(env, ctx, ISA_MIPS32R2);
7809 gen_bitops(ctx, op1, rt, rs, sa, rd);
7812 check_insn(env, ctx, ISA_MIPS32R2);
7813 op2 = MASK_BSHFL(ctx->opcode);
7814 gen_bshfl(ctx, op2, rt, rd);
7817 check_insn(env, ctx, ISA_MIPS32R2);
7819 TCGv t0 = tcg_temp_new();
7823 save_cpu_state(ctx, 1);
7824 gen_helper_rdhwr_cpunum(t0);
7825 gen_store_gpr(t0, rt);
7828 save_cpu_state(ctx, 1);
7829 gen_helper_rdhwr_synci_step(t0);
7830 gen_store_gpr(t0, rt);
7833 save_cpu_state(ctx, 1);
7834 gen_helper_rdhwr_cc(t0);
7835 gen_store_gpr(t0, rt);
7838 save_cpu_state(ctx, 1);
7839 gen_helper_rdhwr_ccres(t0);
7840 gen_store_gpr(t0, rt);
7843 #if defined(CONFIG_USER_ONLY)
7844 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, tls_value));
7845 gen_store_gpr(t0, rt);
7848 /* XXX: Some CPUs implement this in hardware.
7849 Not supported yet. */
7851 default: /* Invalid */
7852 MIPS_INVAL("rdhwr");
7853 generate_exception(ctx, EXCP_RI);
7860 check_insn(env, ctx, ASE_MT);
7862 TCGv t0 = tcg_temp_new();
7863 TCGv t1 = tcg_temp_new();
7865 gen_load_gpr(t0, rt);
7866 gen_load_gpr(t1, rs);
7867 gen_helper_fork(t0, t1);
7873 check_insn(env, ctx, ASE_MT);
7875 TCGv t0 = tcg_temp_new();
7877 save_cpu_state(ctx, 1);
7878 gen_load_gpr(t0, rs);
7879 gen_helper_yield(t0, t0);
7880 gen_store_gpr(t0, rd);
7884 #if defined(TARGET_MIPS64)
7885 case OPC_DEXTM ... OPC_DEXT:
7886 case OPC_DINSM ... OPC_DINS:
7887 check_insn(env, ctx, ISA_MIPS64R2);
7889 gen_bitops(ctx, op1, rt, rs, sa, rd);
7892 check_insn(env, ctx, ISA_MIPS64R2);
7894 op2 = MASK_DBSHFL(ctx->opcode);
7895 gen_bshfl(ctx, op2, rt, rd);
7898 default: /* Invalid */
7899 MIPS_INVAL("special3");
7900 generate_exception(ctx, EXCP_RI);
7905 op1 = MASK_REGIMM(ctx->opcode);
7907 case OPC_BLTZ ... OPC_BGEZL: /* REGIMM branches */
7908 case OPC_BLTZAL ... OPC_BGEZALL:
7909 gen_compute_branch(ctx, op1, rs, -1, imm << 2);
7911 case OPC_TGEI ... OPC_TEQI: /* REGIMM traps */
7913 gen_trap(ctx, op1, rs, -1, imm);
7916 check_insn(env, ctx, ISA_MIPS32R2);
7919 default: /* Invalid */
7920 MIPS_INVAL("regimm");
7921 generate_exception(ctx, EXCP_RI);
7926 check_cp0_enabled(ctx);
7927 op1 = MASK_CP0(ctx->opcode);
7933 #if defined(TARGET_MIPS64)
7937 #ifndef CONFIG_USER_ONLY
7938 gen_cp0(env, ctx, op1, rt, rd);
7939 #endif /* !CONFIG_USER_ONLY */
7941 case OPC_C0_FIRST ... OPC_C0_LAST:
7942 #ifndef CONFIG_USER_ONLY
7943 gen_cp0(env, ctx, MASK_C0(ctx->opcode), rt, rd);
7944 #endif /* !CONFIG_USER_ONLY */
7947 #ifndef CONFIG_USER_ONLY
7949 TCGv t0 = tcg_temp_new();
7951 op2 = MASK_MFMC0(ctx->opcode);
7954 check_insn(env, ctx, ASE_MT);
7955 gen_helper_dmt(t0, t0);
7956 gen_store_gpr(t0, rt);
7959 check_insn(env, ctx, ASE_MT);
7960 gen_helper_emt(t0, t0);
7961 gen_store_gpr(t0, rt);
7964 check_insn(env, ctx, ASE_MT);
7965 gen_helper_dvpe(t0, t0);
7966 gen_store_gpr(t0, rt);
7969 check_insn(env, ctx, ASE_MT);
7970 gen_helper_evpe(t0, t0);
7971 gen_store_gpr(t0, rt);
7974 check_insn(env, ctx, ISA_MIPS32R2);
7975 save_cpu_state(ctx, 1);
7977 gen_store_gpr(t0, rt);
7978 /* Stop translation as we may have switched the execution mode */
7979 ctx->bstate = BS_STOP;
7982 check_insn(env, ctx, ISA_MIPS32R2);
7983 save_cpu_state(ctx, 1);
7985 gen_store_gpr(t0, rt);
7986 /* Stop translation as we may have switched the execution mode */
7987 ctx->bstate = BS_STOP;
7989 default: /* Invalid */
7990 MIPS_INVAL("mfmc0");
7991 generate_exception(ctx, EXCP_RI);
7996 #endif /* !CONFIG_USER_ONLY */
7999 check_insn(env, ctx, ISA_MIPS32R2);
8000 gen_load_srsgpr(rt, rd);
8003 check_insn(env, ctx, ISA_MIPS32R2);
8004 gen_store_srsgpr(rt, rd);
8008 generate_exception(ctx, EXCP_RI);
8012 case OPC_ADDI: /* Arithmetic with immediate opcode */
8014 gen_arith_imm(env, ctx, op, rt, rs, imm);
8016 case OPC_SLTI: /* Set on less than with immediate opcode */
8018 gen_slt_imm(env, op, rt, rs, imm);
8020 case OPC_ANDI: /* Arithmetic with immediate opcode */
8024 gen_logic_imm(env, op, rt, rs, imm);
8026 case OPC_J ... OPC_JAL: /* Jump */
8027 offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2;
8028 gen_compute_branch(ctx, op, rs, rt, offset);
8030 case OPC_BEQ ... OPC_BGTZ: /* Branch */
8031 case OPC_BEQL ... OPC_BGTZL:
8032 gen_compute_branch(ctx, op, rs, rt, imm << 2);
8034 case OPC_LB ... OPC_LWR: /* Load and stores */
8035 case OPC_SB ... OPC_SW:
8038 gen_ldst(ctx, op, rt, rs, imm);
8041 gen_st_cond(ctx, op, rt, rs, imm);
8044 check_insn(env, ctx, ISA_MIPS3 | ISA_MIPS32);
8048 check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32);
8052 /* Floating point (COP1). */
8057 if (env->CP0_Config1 & (1 << CP0C1_FP)) {
8058 check_cp1_enabled(ctx);
8059 gen_flt_ldst(ctx, op, rt, rs, imm);
8061 generate_exception_err(ctx, EXCP_CpU, 1);
8066 if (env->CP0_Config1 & (1 << CP0C1_FP)) {
8067 check_cp1_enabled(ctx);
8068 op1 = MASK_CP1(ctx->opcode);
8072 check_insn(env, ctx, ISA_MIPS32R2);
8077 gen_cp1(ctx, op1, rt, rd);
8079 #if defined(TARGET_MIPS64)
8082 check_insn(env, ctx, ISA_MIPS3);
8083 gen_cp1(ctx, op1, rt, rd);
8089 check_insn(env, ctx, ASE_MIPS3D);
8092 gen_compute_branch1(env, ctx, MASK_BC1(ctx->opcode),
8093 (rt >> 2) & 0x7, imm << 2);
8100 gen_farith(ctx, MASK_CP1_FUNC(ctx->opcode), rt, rd, sa,
8105 generate_exception (ctx, EXCP_RI);
8109 generate_exception_err(ctx, EXCP_CpU, 1);
8119 /* COP2: Not implemented. */
8120 generate_exception_err(ctx, EXCP_CpU, 2);
8124 if (env->CP0_Config1 & (1 << CP0C1_FP)) {
8125 check_cp1_enabled(ctx);
8126 op1 = MASK_CP3(ctx->opcode);
8134 gen_flt3_ldst(ctx, op1, sa, rd, rs, rt);
8152 gen_flt3_arith(ctx, op1, sa, rs, rd, rt);
8156 generate_exception (ctx, EXCP_RI);
8160 generate_exception_err(ctx, EXCP_CpU, 1);
8164 #if defined(TARGET_MIPS64)
8165 /* MIPS64 opcodes */
8167 case OPC_LDL ... OPC_LDR:
8168 case OPC_SDL ... OPC_SDR:
8172 check_insn(env, ctx, ISA_MIPS3);
8174 gen_ldst(ctx, op, rt, rs, imm);
8177 check_insn(env, ctx, ISA_MIPS3);
8179 gen_st_cond(ctx, op, rt, rs, imm);
8183 check_insn(env, ctx, ISA_MIPS3);
8185 gen_arith_imm(env, ctx, op, rt, rs, imm);
8189 check_insn(env, ctx, ASE_MIPS16);
8190 /* MIPS16: Not implemented. */
8192 check_insn(env, ctx, ASE_MDMX);
8193 /* MDMX: Not implemented. */
8194 default: /* Invalid */
8195 MIPS_INVAL("major opcode");
8196 generate_exception(ctx, EXCP_RI);
8199 if (ctx->hflags & MIPS_HFLAG_BMASK) {
8200 int hflags = ctx->hflags & MIPS_HFLAG_BMASK;
8201 /* Branches completion */
8202 ctx->hflags &= ~MIPS_HFLAG_BMASK;
8203 ctx->bstate = BS_BRANCH;
8204 save_cpu_state(ctx, 0);
8205 /* FIXME: Need to clear can_do_io. */
8208 /* unconditional branch */
8209 MIPS_DEBUG("unconditional branch");
8210 gen_goto_tb(ctx, 0, ctx->btarget);
8213 /* blikely taken case */
8214 MIPS_DEBUG("blikely branch taken");
8215 gen_goto_tb(ctx, 0, ctx->btarget);
8218 /* Conditional branch */
8219 MIPS_DEBUG("conditional branch");
8221 int l1 = gen_new_label();
8223 tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1);
8224 gen_goto_tb(ctx, 1, ctx->pc + 4);
8226 gen_goto_tb(ctx, 0, ctx->btarget);
8230 /* unconditional branch to register */
8231 MIPS_DEBUG("branch to register");
8232 tcg_gen_mov_tl(cpu_PC, btarget);
8236 MIPS_DEBUG("unknown branch");
8243 gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
8247 target_ulong pc_start;
8248 uint16_t *gen_opc_end;
8255 qemu_log("search pc %d\n", search_pc);
8258 /* Leave some spare opc slots for branch handling. */
8259 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE - 16;
8263 ctx.bstate = BS_NONE;
8264 /* Restore delay slot state from the tb context. */
8265 ctx.hflags = (uint32_t)tb->flags; /* FIXME: maybe use 64 bits here? */
8266 restore_cpu_state(env, &ctx);
8267 #ifdef CONFIG_USER_ONLY
8268 ctx.mem_idx = MIPS_HFLAG_UM;
8270 ctx.mem_idx = ctx.hflags & MIPS_HFLAG_KSU;
8273 max_insns = tb->cflags & CF_COUNT_MASK;
8275 max_insns = CF_COUNT_MASK;
8277 qemu_log_mask(CPU_LOG_TB_CPU, "------------------------------------------------\n");
8278 /* FIXME: This may print out stale hflags from env... */
8279 log_cpu_state_mask(CPU_LOG_TB_CPU, env, 0);
8281 LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb, ctx.mem_idx, ctx.hflags);
8283 while (ctx.bstate == BS_NONE) {
8284 if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
8285 TAILQ_FOREACH(bp, &env->breakpoints, entry) {
8286 if (bp->pc == ctx.pc) {
8287 save_cpu_state(&ctx, 1);
8288 ctx.bstate = BS_BRANCH;
8289 gen_helper_0i(raise_exception, EXCP_DEBUG);
8290 /* Include the breakpoint location or the tb won't
8291 * be flushed when it must be. */
8293 goto done_generating;
8299 j = gen_opc_ptr - gen_opc_buf;
8303 gen_opc_instr_start[lj++] = 0;
8305 gen_opc_pc[lj] = ctx.pc;
8306 gen_opc_hflags[lj] = ctx.hflags & MIPS_HFLAG_BMASK;
8307 gen_opc_instr_start[lj] = 1;
8308 gen_opc_icount[lj] = num_insns;
8310 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
8312 ctx.opcode = ldl_code(ctx.pc);
8313 decode_opc(env, &ctx);
8317 if (env->singlestep_enabled)
8320 if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0)
8323 if (gen_opc_ptr >= gen_opc_end)
8326 if (num_insns >= max_insns)
8332 if (tb->cflags & CF_LAST_IO)
8334 if (env->singlestep_enabled) {
8335 save_cpu_state(&ctx, ctx.bstate == BS_NONE);
8336 gen_helper_0i(raise_exception, EXCP_DEBUG);
8338 switch (ctx.bstate) {
8340 gen_helper_interrupt_restart();
8341 gen_goto_tb(&ctx, 0, ctx.pc);
8344 save_cpu_state(&ctx, 0);
8345 gen_goto_tb(&ctx, 0, ctx.pc);
8348 gen_helper_interrupt_restart();
8357 gen_icount_end(tb, num_insns);
8358 *gen_opc_ptr = INDEX_op_end;
8360 j = gen_opc_ptr - gen_opc_buf;
8363 gen_opc_instr_start[lj++] = 0;
8365 tb->size = ctx.pc - pc_start;
8366 tb->icount = num_insns;
8370 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
8371 qemu_log("IN: %s\n", lookup_symbol(pc_start));
8372 log_target_disas(pc_start, ctx.pc - pc_start, 0);
8375 qemu_log_mask(CPU_LOG_TB_CPU, "---------------- %d %08x\n", ctx.bstate, ctx.hflags);
8379 void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
8381 gen_intermediate_code_internal(env, tb, 0);
8384 void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
8386 gen_intermediate_code_internal(env, tb, 1);
8389 static void fpu_dump_state(CPUState *env, FILE *f,
8390 int (*fpu_fprintf)(FILE *f, const char *fmt, ...),
8394 int is_fpu64 = !!(env->hflags & MIPS_HFLAG_F64);
8396 #define printfpr(fp) \
8399 fpu_fprintf(f, "w:%08x d:%016lx fd:%13g fs:%13g psu: %13g\n", \
8400 (fp)->w[FP_ENDIAN_IDX], (fp)->d, (fp)->fd, \
8401 (fp)->fs[FP_ENDIAN_IDX], (fp)->fs[!FP_ENDIAN_IDX]); \
8404 tmp.w[FP_ENDIAN_IDX] = (fp)->w[FP_ENDIAN_IDX]; \
8405 tmp.w[!FP_ENDIAN_IDX] = ((fp) + 1)->w[FP_ENDIAN_IDX]; \
8406 fpu_fprintf(f, "w:%08x d:%016lx fd:%13g fs:%13g psu:%13g\n", \
8407 tmp.w[FP_ENDIAN_IDX], tmp.d, tmp.fd, \
8408 tmp.fs[FP_ENDIAN_IDX], tmp.fs[!FP_ENDIAN_IDX]); \
8413 fpu_fprintf(f, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%08x(0x%02x)\n",
8414 env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64, env->active_fpu.fp_status,
8415 get_float_exception_flags(&env->active_fpu.fp_status));
8416 for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) {
8417 fpu_fprintf(f, "%3s: ", fregnames[i]);
8418 printfpr(&env->active_fpu.fpr[i]);
8424 #if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
8425 /* Debug help: The architecture requires 32bit code to maintain proper
8426 sign-extended values on 64bit machines. */
8428 #define SIGN_EXT_P(val) ((((val) & ~0x7fffffff) == 0) || (((val) & ~0x7fffffff) == ~0x7fffffff))
8431 cpu_mips_check_sign_extensions (CPUState *env, FILE *f,
8432 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
8437 if (!SIGN_EXT_P(env->active_tc.PC))
8438 cpu_fprintf(f, "BROKEN: pc=0x" TARGET_FMT_lx "\n", env->active_tc.PC);
8439 if (!SIGN_EXT_P(env->active_tc.HI[0]))
8440 cpu_fprintf(f, "BROKEN: HI=0x" TARGET_FMT_lx "\n", env->active_tc.HI[0]);
8441 if (!SIGN_EXT_P(env->active_tc.LO[0]))
8442 cpu_fprintf(f, "BROKEN: LO=0x" TARGET_FMT_lx "\n", env->active_tc.LO[0]);
8443 if (!SIGN_EXT_P(env->btarget))
8444 cpu_fprintf(f, "BROKEN: btarget=0x" TARGET_FMT_lx "\n", env->btarget);
8446 for (i = 0; i < 32; i++) {
8447 if (!SIGN_EXT_P(env->active_tc.gpr[i]))
8448 cpu_fprintf(f, "BROKEN: %s=0x" TARGET_FMT_lx "\n", regnames[i], env->active_tc.gpr[i]);
8451 if (!SIGN_EXT_P(env->CP0_EPC))
8452 cpu_fprintf(f, "BROKEN: EPC=0x" TARGET_FMT_lx "\n", env->CP0_EPC);
8453 if (!SIGN_EXT_P(env->CP0_LLAddr))
8454 cpu_fprintf(f, "BROKEN: LLAddr=0x" TARGET_FMT_lx "\n", env->CP0_LLAddr);
8458 void cpu_dump_state (CPUState *env, FILE *f,
8459 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
8464 cpu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx " LO=0x" TARGET_FMT_lx " ds %04x " TARGET_FMT_lx " %d\n",
8465 env->active_tc.PC, env->active_tc.HI[0], env->active_tc.LO[0],
8466 env->hflags, env->btarget, env->bcond);
8467 for (i = 0; i < 32; i++) {
8469 cpu_fprintf(f, "GPR%02d:", i);
8470 cpu_fprintf(f, " %s " TARGET_FMT_lx, regnames[i], env->active_tc.gpr[i]);
8472 cpu_fprintf(f, "\n");
8475 cpu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" TARGET_FMT_lx "\n",
8476 env->CP0_Status, env->CP0_Cause, env->CP0_EPC);
8477 cpu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x" TARGET_FMT_lx "\n",
8478 env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr);
8479 if (env->hflags & MIPS_HFLAG_FPU)
8480 fpu_dump_state(env, f, cpu_fprintf, flags);
8481 #if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
8482 cpu_mips_check_sign_extensions(env, f, cpu_fprintf, flags);
8486 static void mips_tcg_init(void)
8491 /* Initialize various static tables. */
8495 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
8496 TCGV_UNUSED(cpu_gpr[0]);
8497 for (i = 1; i < 32; i++)
8498 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
8499 offsetof(CPUState, active_tc.gpr[i]),
8501 cpu_PC = tcg_global_mem_new(TCG_AREG0,
8502 offsetof(CPUState, active_tc.PC), "PC");
8503 for (i = 0; i < MIPS_DSP_ACC; i++) {
8504 cpu_HI[i] = tcg_global_mem_new(TCG_AREG0,
8505 offsetof(CPUState, active_tc.HI[i]),
8507 cpu_LO[i] = tcg_global_mem_new(TCG_AREG0,
8508 offsetof(CPUState, active_tc.LO[i]),
8510 cpu_ACX[i] = tcg_global_mem_new(TCG_AREG0,
8511 offsetof(CPUState, active_tc.ACX[i]),
8514 cpu_dspctrl = tcg_global_mem_new(TCG_AREG0,
8515 offsetof(CPUState, active_tc.DSPControl),
8517 bcond = tcg_global_mem_new(TCG_AREG0,
8518 offsetof(CPUState, bcond), "bcond");
8519 btarget = tcg_global_mem_new(TCG_AREG0,
8520 offsetof(CPUState, btarget), "btarget");
8521 hflags = tcg_global_mem_new_i32(TCG_AREG0,
8522 offsetof(CPUState, hflags), "hflags");
8524 fpu_fcr0 = tcg_global_mem_new_i32(TCG_AREG0,
8525 offsetof(CPUState, active_fpu.fcr0),
8527 fpu_fcr31 = tcg_global_mem_new_i32(TCG_AREG0,
8528 offsetof(CPUState, active_fpu.fcr31),
8531 /* register helpers */
8532 #define GEN_HELPER 2
8538 #include "translate_init.c"
8540 CPUMIPSState *cpu_mips_init (const char *cpu_model)
8543 const mips_def_t *def;
8545 def = cpu_mips_find_by_name(cpu_model);
8548 env = qemu_mallocz(sizeof(CPUMIPSState));
8549 env->cpu_model = def;
8552 env->cpu_model_str = cpu_model;
8555 qemu_init_vcpu(env);
8559 void cpu_reset (CPUMIPSState *env)
8561 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
8562 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
8563 log_cpu_state(env, 0);
8566 memset(env, 0, offsetof(CPUMIPSState, breakpoints));
8571 #if defined(CONFIG_USER_ONLY)
8572 env->hflags = MIPS_HFLAG_UM;
8573 /* Enable access to the SYNCI_Step register. */
8574 env->CP0_HWREna |= (1 << 1);
8576 if (env->hflags & MIPS_HFLAG_BMASK) {
8577 /* If the exception was raised from a delay slot,
8578 come back to the jump. */
8579 env->CP0_ErrorEPC = env->active_tc.PC - 4;
8581 env->CP0_ErrorEPC = env->active_tc.PC;
8583 env->active_tc.PC = (int32_t)0xBFC00000;
8585 /* SMP not implemented */
8586 env->CP0_EBase = 0x80000000;
8587 env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
8588 /* vectored interrupts not implemented, timer on int 7,
8589 no performance counters. */
8590 env->CP0_IntCtl = 0xe0000000;
8594 for (i = 0; i < 7; i++) {
8595 env->CP0_WatchLo[i] = 0;
8596 env->CP0_WatchHi[i] = 0x80000000;
8598 env->CP0_WatchLo[7] = 0;
8599 env->CP0_WatchHi[7] = 0;
8601 /* Count register increments in debug mode, EJTAG version 1 */
8602 env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
8603 env->hflags = MIPS_HFLAG_CP0;
8605 env->exception_index = EXCP_NONE;
8606 cpu_mips_register(env, env->cpu_model);
8609 void gen_pc_load(CPUState *env, TranslationBlock *tb,
8610 unsigned long searched_pc, int pc_pos, void *puc)
8612 env->active_tc.PC = gen_opc_pc[pc_pos];
8613 env->hflags &= ~MIPS_HFLAG_BMASK;
8614 env->hflags |= gen_opc_hflags[pc_pos];