2 * MIPS32 emulation for qemu: main translation routines.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2006 Marius Groeger (FPU operations)
6 * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
34 #include "qemu-common.h"
36 //#define MIPS_DEBUG_DISAS
37 //#define MIPS_DEBUG_SIGN_EXTENSIONS
38 //#define MIPS_SINGLE_STEP
40 /* MIPS major opcodes */
41 #define MASK_OP_MAJOR(op) (op & (0x3F << 26))
44 /* indirect opcode tables */
45 OPC_SPECIAL = (0x00 << 26),
46 OPC_REGIMM = (0x01 << 26),
47 OPC_CP0 = (0x10 << 26),
48 OPC_CP1 = (0x11 << 26),
49 OPC_CP2 = (0x12 << 26),
50 OPC_CP3 = (0x13 << 26),
51 OPC_SPECIAL2 = (0x1C << 26),
52 OPC_SPECIAL3 = (0x1F << 26),
53 /* arithmetic with immediate */
54 OPC_ADDI = (0x08 << 26),
55 OPC_ADDIU = (0x09 << 26),
56 OPC_SLTI = (0x0A << 26),
57 OPC_SLTIU = (0x0B << 26),
58 OPC_ANDI = (0x0C << 26),
59 OPC_ORI = (0x0D << 26),
60 OPC_XORI = (0x0E << 26),
61 OPC_LUI = (0x0F << 26),
62 OPC_DADDI = (0x18 << 26),
63 OPC_DADDIU = (0x19 << 26),
64 /* Jump and branches */
66 OPC_JAL = (0x03 << 26),
67 OPC_BEQ = (0x04 << 26), /* Unconditional if rs = rt = 0 (B) */
68 OPC_BEQL = (0x14 << 26),
69 OPC_BNE = (0x05 << 26),
70 OPC_BNEL = (0x15 << 26),
71 OPC_BLEZ = (0x06 << 26),
72 OPC_BLEZL = (0x16 << 26),
73 OPC_BGTZ = (0x07 << 26),
74 OPC_BGTZL = (0x17 << 26),
75 OPC_JALX = (0x1D << 26), /* MIPS 16 only */
77 OPC_LDL = (0x1A << 26),
78 OPC_LDR = (0x1B << 26),
79 OPC_LB = (0x20 << 26),
80 OPC_LH = (0x21 << 26),
81 OPC_LWL = (0x22 << 26),
82 OPC_LW = (0x23 << 26),
83 OPC_LBU = (0x24 << 26),
84 OPC_LHU = (0x25 << 26),
85 OPC_LWR = (0x26 << 26),
86 OPC_LWU = (0x27 << 26),
87 OPC_SB = (0x28 << 26),
88 OPC_SH = (0x29 << 26),
89 OPC_SWL = (0x2A << 26),
90 OPC_SW = (0x2B << 26),
91 OPC_SDL = (0x2C << 26),
92 OPC_SDR = (0x2D << 26),
93 OPC_SWR = (0x2E << 26),
94 OPC_LL = (0x30 << 26),
95 OPC_LLD = (0x34 << 26),
96 OPC_LD = (0x37 << 26),
97 OPC_SC = (0x38 << 26),
98 OPC_SCD = (0x3C << 26),
99 OPC_SD = (0x3F << 26),
100 /* Floating point load/store */
101 OPC_LWC1 = (0x31 << 26),
102 OPC_LWC2 = (0x32 << 26),
103 OPC_LDC1 = (0x35 << 26),
104 OPC_LDC2 = (0x36 << 26),
105 OPC_SWC1 = (0x39 << 26),
106 OPC_SWC2 = (0x3A << 26),
107 OPC_SDC1 = (0x3D << 26),
108 OPC_SDC2 = (0x3E << 26),
109 /* MDMX ASE specific */
110 OPC_MDMX = (0x1E << 26),
111 /* Cache and prefetch */
112 OPC_CACHE = (0x2F << 26),
113 OPC_PREF = (0x33 << 26),
114 /* Reserved major opcode */
115 OPC_MAJOR3B_RESERVED = (0x3B << 26),
118 /* MIPS special opcodes */
119 #define MASK_SPECIAL(op) MASK_OP_MAJOR(op) | (op & 0x3F)
123 OPC_SLL = 0x00 | OPC_SPECIAL,
124 /* NOP is SLL r0, r0, 0 */
125 /* SSNOP is SLL r0, r0, 1 */
126 /* EHB is SLL r0, r0, 3 */
127 OPC_SRL = 0x02 | OPC_SPECIAL, /* also ROTR */
128 OPC_SRA = 0x03 | OPC_SPECIAL,
129 OPC_SLLV = 0x04 | OPC_SPECIAL,
130 OPC_SRLV = 0x06 | OPC_SPECIAL, /* also ROTRV */
131 OPC_SRAV = 0x07 | OPC_SPECIAL,
132 OPC_DSLLV = 0x14 | OPC_SPECIAL,
133 OPC_DSRLV = 0x16 | OPC_SPECIAL, /* also DROTRV */
134 OPC_DSRAV = 0x17 | OPC_SPECIAL,
135 OPC_DSLL = 0x38 | OPC_SPECIAL,
136 OPC_DSRL = 0x3A | OPC_SPECIAL, /* also DROTR */
137 OPC_DSRA = 0x3B | OPC_SPECIAL,
138 OPC_DSLL32 = 0x3C | OPC_SPECIAL,
139 OPC_DSRL32 = 0x3E | OPC_SPECIAL, /* also DROTR32 */
140 OPC_DSRA32 = 0x3F | OPC_SPECIAL,
141 /* Multiplication / division */
142 OPC_MULT = 0x18 | OPC_SPECIAL,
143 OPC_MULTU = 0x19 | OPC_SPECIAL,
144 OPC_DIV = 0x1A | OPC_SPECIAL,
145 OPC_DIVU = 0x1B | OPC_SPECIAL,
146 OPC_DMULT = 0x1C | OPC_SPECIAL,
147 OPC_DMULTU = 0x1D | OPC_SPECIAL,
148 OPC_DDIV = 0x1E | OPC_SPECIAL,
149 OPC_DDIVU = 0x1F | OPC_SPECIAL,
150 /* 2 registers arithmetic / logic */
151 OPC_ADD = 0x20 | OPC_SPECIAL,
152 OPC_ADDU = 0x21 | OPC_SPECIAL,
153 OPC_SUB = 0x22 | OPC_SPECIAL,
154 OPC_SUBU = 0x23 | OPC_SPECIAL,
155 OPC_AND = 0x24 | OPC_SPECIAL,
156 OPC_OR = 0x25 | OPC_SPECIAL,
157 OPC_XOR = 0x26 | OPC_SPECIAL,
158 OPC_NOR = 0x27 | OPC_SPECIAL,
159 OPC_SLT = 0x2A | OPC_SPECIAL,
160 OPC_SLTU = 0x2B | OPC_SPECIAL,
161 OPC_DADD = 0x2C | OPC_SPECIAL,
162 OPC_DADDU = 0x2D | OPC_SPECIAL,
163 OPC_DSUB = 0x2E | OPC_SPECIAL,
164 OPC_DSUBU = 0x2F | OPC_SPECIAL,
166 OPC_JR = 0x08 | OPC_SPECIAL, /* Also JR.HB */
167 OPC_JALR = 0x09 | OPC_SPECIAL, /* Also JALR.HB */
169 OPC_TGE = 0x30 | OPC_SPECIAL,
170 OPC_TGEU = 0x31 | OPC_SPECIAL,
171 OPC_TLT = 0x32 | OPC_SPECIAL,
172 OPC_TLTU = 0x33 | OPC_SPECIAL,
173 OPC_TEQ = 0x34 | OPC_SPECIAL,
174 OPC_TNE = 0x36 | OPC_SPECIAL,
175 /* HI / LO registers load & stores */
176 OPC_MFHI = 0x10 | OPC_SPECIAL,
177 OPC_MTHI = 0x11 | OPC_SPECIAL,
178 OPC_MFLO = 0x12 | OPC_SPECIAL,
179 OPC_MTLO = 0x13 | OPC_SPECIAL,
180 /* Conditional moves */
181 OPC_MOVZ = 0x0A | OPC_SPECIAL,
182 OPC_MOVN = 0x0B | OPC_SPECIAL,
184 OPC_MOVCI = 0x01 | OPC_SPECIAL,
187 OPC_PMON = 0x05 | OPC_SPECIAL, /* inofficial */
188 OPC_SYSCALL = 0x0C | OPC_SPECIAL,
189 OPC_BREAK = 0x0D | OPC_SPECIAL,
190 OPC_SPIM = 0x0E | OPC_SPECIAL, /* inofficial */
191 OPC_SYNC = 0x0F | OPC_SPECIAL,
193 OPC_SPECIAL15_RESERVED = 0x15 | OPC_SPECIAL,
194 OPC_SPECIAL28_RESERVED = 0x28 | OPC_SPECIAL,
195 OPC_SPECIAL29_RESERVED = 0x29 | OPC_SPECIAL,
196 OPC_SPECIAL35_RESERVED = 0x35 | OPC_SPECIAL,
197 OPC_SPECIAL37_RESERVED = 0x37 | OPC_SPECIAL,
198 OPC_SPECIAL39_RESERVED = 0x39 | OPC_SPECIAL,
199 OPC_SPECIAL3D_RESERVED = 0x3D | OPC_SPECIAL,
202 /* Multiplication variants of the vr54xx. */
203 #define MASK_MUL_VR54XX(op) MASK_SPECIAL(op) | (op & (0x1F << 6))
206 OPC_VR54XX_MULS = (0x03 << 6) | OPC_MULT,
207 OPC_VR54XX_MULSU = (0x03 << 6) | OPC_MULTU,
208 OPC_VR54XX_MACC = (0x05 << 6) | OPC_MULT,
209 OPC_VR54XX_MACCU = (0x05 << 6) | OPC_MULTU,
210 OPC_VR54XX_MSAC = (0x07 << 6) | OPC_MULT,
211 OPC_VR54XX_MSACU = (0x07 << 6) | OPC_MULTU,
212 OPC_VR54XX_MULHI = (0x09 << 6) | OPC_MULT,
213 OPC_VR54XX_MULHIU = (0x09 << 6) | OPC_MULTU,
214 OPC_VR54XX_MULSHI = (0x0B << 6) | OPC_MULT,
215 OPC_VR54XX_MULSHIU = (0x0B << 6) | OPC_MULTU,
216 OPC_VR54XX_MACCHI = (0x0D << 6) | OPC_MULT,
217 OPC_VR54XX_MACCHIU = (0x0D << 6) | OPC_MULTU,
218 OPC_VR54XX_MSACHI = (0x0F << 6) | OPC_MULT,
219 OPC_VR54XX_MSACHIU = (0x0F << 6) | OPC_MULTU,
222 /* REGIMM (rt field) opcodes */
223 #define MASK_REGIMM(op) MASK_OP_MAJOR(op) | (op & (0x1F << 16))
226 OPC_BLTZ = (0x00 << 16) | OPC_REGIMM,
227 OPC_BLTZL = (0x02 << 16) | OPC_REGIMM,
228 OPC_BGEZ = (0x01 << 16) | OPC_REGIMM,
229 OPC_BGEZL = (0x03 << 16) | OPC_REGIMM,
230 OPC_BLTZAL = (0x10 << 16) | OPC_REGIMM,
231 OPC_BLTZALL = (0x12 << 16) | OPC_REGIMM,
232 OPC_BGEZAL = (0x11 << 16) | OPC_REGIMM,
233 OPC_BGEZALL = (0x13 << 16) | OPC_REGIMM,
234 OPC_TGEI = (0x08 << 16) | OPC_REGIMM,
235 OPC_TGEIU = (0x09 << 16) | OPC_REGIMM,
236 OPC_TLTI = (0x0A << 16) | OPC_REGIMM,
237 OPC_TLTIU = (0x0B << 16) | OPC_REGIMM,
238 OPC_TEQI = (0x0C << 16) | OPC_REGIMM,
239 OPC_TNEI = (0x0E << 16) | OPC_REGIMM,
240 OPC_SYNCI = (0x1F << 16) | OPC_REGIMM,
243 /* Special2 opcodes */
244 #define MASK_SPECIAL2(op) MASK_OP_MAJOR(op) | (op & 0x3F)
247 /* Multiply & xxx operations */
248 OPC_MADD = 0x00 | OPC_SPECIAL2,
249 OPC_MADDU = 0x01 | OPC_SPECIAL2,
250 OPC_MUL = 0x02 | OPC_SPECIAL2,
251 OPC_MSUB = 0x04 | OPC_SPECIAL2,
252 OPC_MSUBU = 0x05 | OPC_SPECIAL2,
254 OPC_CLZ = 0x20 | OPC_SPECIAL2,
255 OPC_CLO = 0x21 | OPC_SPECIAL2,
256 OPC_DCLZ = 0x24 | OPC_SPECIAL2,
257 OPC_DCLO = 0x25 | OPC_SPECIAL2,
259 OPC_SDBBP = 0x3F | OPC_SPECIAL2,
262 /* Special3 opcodes */
263 #define MASK_SPECIAL3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
266 OPC_EXT = 0x00 | OPC_SPECIAL3,
267 OPC_DEXTM = 0x01 | OPC_SPECIAL3,
268 OPC_DEXTU = 0x02 | OPC_SPECIAL3,
269 OPC_DEXT = 0x03 | OPC_SPECIAL3,
270 OPC_INS = 0x04 | OPC_SPECIAL3,
271 OPC_DINSM = 0x05 | OPC_SPECIAL3,
272 OPC_DINSU = 0x06 | OPC_SPECIAL3,
273 OPC_DINS = 0x07 | OPC_SPECIAL3,
274 OPC_FORK = 0x08 | OPC_SPECIAL3,
275 OPC_YIELD = 0x09 | OPC_SPECIAL3,
276 OPC_BSHFL = 0x20 | OPC_SPECIAL3,
277 OPC_DBSHFL = 0x24 | OPC_SPECIAL3,
278 OPC_RDHWR = 0x3B | OPC_SPECIAL3,
282 #define MASK_BSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
285 OPC_WSBH = (0x02 << 6) | OPC_BSHFL,
286 OPC_SEB = (0x10 << 6) | OPC_BSHFL,
287 OPC_SEH = (0x18 << 6) | OPC_BSHFL,
291 #define MASK_DBSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
294 OPC_DSBH = (0x02 << 6) | OPC_DBSHFL,
295 OPC_DSHD = (0x05 << 6) | OPC_DBSHFL,
298 /* Coprocessor 0 (rs field) */
299 #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
302 OPC_MFC0 = (0x00 << 21) | OPC_CP0,
303 OPC_DMFC0 = (0x01 << 21) | OPC_CP0,
304 OPC_MTC0 = (0x04 << 21) | OPC_CP0,
305 OPC_DMTC0 = (0x05 << 21) | OPC_CP0,
306 OPC_MFTR = (0x08 << 21) | OPC_CP0,
307 OPC_RDPGPR = (0x0A << 21) | OPC_CP0,
308 OPC_MFMC0 = (0x0B << 21) | OPC_CP0,
309 OPC_MTTR = (0x0C << 21) | OPC_CP0,
310 OPC_WRPGPR = (0x0E << 21) | OPC_CP0,
311 OPC_C0 = (0x10 << 21) | OPC_CP0,
312 OPC_C0_FIRST = (0x10 << 21) | OPC_CP0,
313 OPC_C0_LAST = (0x1F << 21) | OPC_CP0,
317 #define MASK_MFMC0(op) MASK_CP0(op) | (op & 0xFFFF)
320 OPC_DMT = 0x01 | (0 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0,
321 OPC_EMT = 0x01 | (1 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0,
322 OPC_DVPE = 0x01 | (0 << 5) | OPC_MFMC0,
323 OPC_EVPE = 0x01 | (1 << 5) | OPC_MFMC0,
324 OPC_DI = (0 << 5) | (0x0C << 11) | OPC_MFMC0,
325 OPC_EI = (1 << 5) | (0x0C << 11) | OPC_MFMC0,
328 /* Coprocessor 0 (with rs == C0) */
329 #define MASK_C0(op) MASK_CP0(op) | (op & 0x3F)
332 OPC_TLBR = 0x01 | OPC_C0,
333 OPC_TLBWI = 0x02 | OPC_C0,
334 OPC_TLBWR = 0x06 | OPC_C0,
335 OPC_TLBP = 0x08 | OPC_C0,
336 OPC_RFE = 0x10 | OPC_C0,
337 OPC_ERET = 0x18 | OPC_C0,
338 OPC_DERET = 0x1F | OPC_C0,
339 OPC_WAIT = 0x20 | OPC_C0,
342 /* Coprocessor 1 (rs field) */
343 #define MASK_CP1(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
346 OPC_MFC1 = (0x00 << 21) | OPC_CP1,
347 OPC_DMFC1 = (0x01 << 21) | OPC_CP1,
348 OPC_CFC1 = (0x02 << 21) | OPC_CP1,
349 OPC_MFHC1 = (0x03 << 21) | OPC_CP1,
350 OPC_MTC1 = (0x04 << 21) | OPC_CP1,
351 OPC_DMTC1 = (0x05 << 21) | OPC_CP1,
352 OPC_CTC1 = (0x06 << 21) | OPC_CP1,
353 OPC_MTHC1 = (0x07 << 21) | OPC_CP1,
354 OPC_BC1 = (0x08 << 21) | OPC_CP1, /* bc */
355 OPC_BC1ANY2 = (0x09 << 21) | OPC_CP1,
356 OPC_BC1ANY4 = (0x0A << 21) | OPC_CP1,
357 OPC_S_FMT = (0x10 << 21) | OPC_CP1, /* 16: fmt=single fp */
358 OPC_D_FMT = (0x11 << 21) | OPC_CP1, /* 17: fmt=double fp */
359 OPC_E_FMT = (0x12 << 21) | OPC_CP1, /* 18: fmt=extended fp */
360 OPC_Q_FMT = (0x13 << 21) | OPC_CP1, /* 19: fmt=quad fp */
361 OPC_W_FMT = (0x14 << 21) | OPC_CP1, /* 20: fmt=32bit fixed */
362 OPC_L_FMT = (0x15 << 21) | OPC_CP1, /* 21: fmt=64bit fixed */
363 OPC_PS_FMT = (0x16 << 21) | OPC_CP1, /* 22: fmt=paired single fp */
366 #define MASK_CP1_FUNC(op) MASK_CP1(op) | (op & 0x3F)
367 #define MASK_BC1(op) MASK_CP1(op) | (op & (0x3 << 16))
370 OPC_BC1F = (0x00 << 16) | OPC_BC1,
371 OPC_BC1T = (0x01 << 16) | OPC_BC1,
372 OPC_BC1FL = (0x02 << 16) | OPC_BC1,
373 OPC_BC1TL = (0x03 << 16) | OPC_BC1,
377 OPC_BC1FANY2 = (0x00 << 16) | OPC_BC1ANY2,
378 OPC_BC1TANY2 = (0x01 << 16) | OPC_BC1ANY2,
382 OPC_BC1FANY4 = (0x00 << 16) | OPC_BC1ANY4,
383 OPC_BC1TANY4 = (0x01 << 16) | OPC_BC1ANY4,
386 #define MASK_CP2(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
389 OPC_MFC2 = (0x00 << 21) | OPC_CP2,
390 OPC_DMFC2 = (0x01 << 21) | OPC_CP2,
391 OPC_CFC2 = (0x02 << 21) | OPC_CP2,
392 OPC_MFHC2 = (0x03 << 21) | OPC_CP2,
393 OPC_MTC2 = (0x04 << 21) | OPC_CP2,
394 OPC_DMTC2 = (0x05 << 21) | OPC_CP2,
395 OPC_CTC2 = (0x06 << 21) | OPC_CP2,
396 OPC_MTHC2 = (0x07 << 21) | OPC_CP2,
397 OPC_BC2 = (0x08 << 21) | OPC_CP2,
400 #define MASK_CP3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
403 OPC_LWXC1 = 0x00 | OPC_CP3,
404 OPC_LDXC1 = 0x01 | OPC_CP3,
405 OPC_LUXC1 = 0x05 | OPC_CP3,
406 OPC_SWXC1 = 0x08 | OPC_CP3,
407 OPC_SDXC1 = 0x09 | OPC_CP3,
408 OPC_SUXC1 = 0x0D | OPC_CP3,
409 OPC_PREFX = 0x0F | OPC_CP3,
410 OPC_ALNV_PS = 0x1E | OPC_CP3,
411 OPC_MADD_S = 0x20 | OPC_CP3,
412 OPC_MADD_D = 0x21 | OPC_CP3,
413 OPC_MADD_PS = 0x26 | OPC_CP3,
414 OPC_MSUB_S = 0x28 | OPC_CP3,
415 OPC_MSUB_D = 0x29 | OPC_CP3,
416 OPC_MSUB_PS = 0x2E | OPC_CP3,
417 OPC_NMADD_S = 0x30 | OPC_CP3,
418 OPC_NMADD_D = 0x31 | OPC_CP3,
419 OPC_NMADD_PS= 0x36 | OPC_CP3,
420 OPC_NMSUB_S = 0x38 | OPC_CP3,
421 OPC_NMSUB_D = 0x39 | OPC_CP3,
422 OPC_NMSUB_PS= 0x3E | OPC_CP3,
425 /* global register indices */
426 static TCGv cpu_env, bcond, btarget, current_fpu;
428 #include "gen-icount.h"
430 static inline void tcg_gen_helper_0_i(void *func, TCGv arg)
432 TCGv tmp = tcg_const_i32(arg);
434 tcg_gen_helper_0_1(func, tmp);
438 static inline void tcg_gen_helper_0_ii(void *func, TCGv arg1, TCGv arg2)
440 TCGv tmp1 = tcg_const_i32(arg1);
441 TCGv tmp2 = tcg_const_i32(arg2);
443 tcg_gen_helper_0_2(func, tmp1, tmp2);
448 static inline void tcg_gen_helper_0_1i(void *func, TCGv arg1, TCGv arg2)
450 TCGv tmp = tcg_const_i32(arg2);
452 tcg_gen_helper_0_2(func, arg1, tmp);
456 static inline void tcg_gen_helper_0_2i(void *func, TCGv arg1, TCGv arg2, TCGv arg3)
458 TCGv tmp = tcg_const_i32(arg3);
460 tcg_gen_helper_0_3(func, arg1, arg2, tmp);
464 static inline void tcg_gen_helper_0_1ii(void *func, TCGv arg1, TCGv arg2, TCGv arg3)
466 TCGv tmp1 = tcg_const_i32(arg2);
467 TCGv tmp2 = tcg_const_i32(arg3);
469 tcg_gen_helper_0_3(func, arg1, tmp1, tmp2);
474 static inline void tcg_gen_helper_1_i(void *func, TCGv ret, TCGv arg)
476 TCGv tmp = tcg_const_i32(arg);
478 tcg_gen_helper_1_1(func, ret, tmp);
482 static inline void tcg_gen_helper_1_1i(void *func, TCGv ret, TCGv arg1, TCGv arg2)
484 TCGv tmp = tcg_const_i32(arg2);
486 tcg_gen_helper_1_2(func, ret, arg1, tmp);
490 static inline void tcg_gen_helper_1_1ii(void *func, TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3)
492 TCGv tmp1 = tcg_const_i32(arg2);
493 TCGv tmp2 = tcg_const_i32(arg3);
495 tcg_gen_helper_1_3(func, ret, arg1, tmp1, tmp2);
500 static inline void tcg_gen_helper_1_2i(void *func, TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3)
502 TCGv tmp = tcg_const_i32(arg3);
504 tcg_gen_helper_1_3(func, ret, arg1, arg2, tmp);
508 static inline void tcg_gen_helper_1_2ii(void *func, TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, TCGv arg4)
510 TCGv tmp1 = tcg_const_i32(arg3);
511 TCGv tmp2 = tcg_const_i32(arg4);
513 tcg_gen_helper_1_4(func, ret, arg1, arg2, tmp1, tmp2);
518 typedef struct DisasContext {
519 struct TranslationBlock *tb;
520 target_ulong pc, saved_pc;
523 /* Routine used to access memory */
525 uint32_t hflags, saved_hflags;
527 target_ulong btarget;
531 BS_NONE = 0, /* We go out of the TB without reaching a branch or an
532 * exception condition */
533 BS_STOP = 1, /* We want to stop translation for any reason */
534 BS_BRANCH = 2, /* We reached a branch condition */
535 BS_EXCP = 3, /* We reached an exception condition */
538 static const char *regnames[] =
539 { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
540 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
541 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
542 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", };
544 static const char *fregnames[] =
545 { "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
546 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
547 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
548 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", };
550 #ifdef MIPS_DEBUG_DISAS
551 #define MIPS_DEBUG(fmt, args...) \
553 if (loglevel & CPU_LOG_TB_IN_ASM) { \
554 fprintf(logfile, TARGET_FMT_lx ": %08x " fmt "\n", \
555 ctx->pc, ctx->opcode , ##args); \
559 #define MIPS_DEBUG(fmt, args...) do { } while(0)
562 #define MIPS_INVAL(op) \
564 MIPS_DEBUG("Invalid %s %03x %03x %03x", op, ctx->opcode >> 26, \
565 ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \
568 /* General purpose registers moves. */
569 static inline void gen_load_gpr (TCGv t, int reg)
572 tcg_gen_movi_tl(t, 0);
574 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, active_tc.gpr) +
575 sizeof(target_ulong) * reg);
578 static inline void gen_store_gpr (TCGv t, int reg)
581 tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, active_tc.gpr) +
582 sizeof(target_ulong) * reg);
585 /* Moves to/from HI and LO registers. */
586 static inline void gen_load_LO (TCGv t, int reg)
588 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, active_tc.LO) +
589 sizeof(target_ulong) * reg);
592 static inline void gen_store_LO (TCGv t, int reg)
594 tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, active_tc.LO) +
595 sizeof(target_ulong) * reg);
598 static inline void gen_load_HI (TCGv t, int reg)
600 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, active_tc.HI) +
601 sizeof(target_ulong) * reg);
604 static inline void gen_store_HI (TCGv t, int reg)
606 tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, active_tc.HI) +
607 sizeof(target_ulong) * reg);
610 /* Moves to/from shadow registers. */
611 static inline void gen_load_srsgpr (int from, int to)
613 TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);
616 tcg_gen_movi_tl(r_tmp1, 0);
618 TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32);
620 tcg_gen_ld_i32(r_tmp2, cpu_env, offsetof(CPUState, CP0_SRSCtl));
621 tcg_gen_shri_i32(r_tmp2, r_tmp2, CP0SRSCtl_PSS);
622 tcg_gen_andi_i32(r_tmp2, r_tmp2, 0xf);
623 tcg_gen_muli_i32(r_tmp2, r_tmp2, sizeof(target_ulong) * 32);
624 tcg_gen_add_i32(r_tmp2, cpu_env, r_tmp2);
626 tcg_gen_ld_tl(r_tmp1, r_tmp2, sizeof(target_ulong) * from);
627 tcg_temp_free(r_tmp2);
629 gen_store_gpr(r_tmp1, to);
630 tcg_temp_free(r_tmp1);
633 static inline void gen_store_srsgpr (int from, int to)
636 TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);
637 TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32);
639 gen_load_gpr(r_tmp1, from);
640 tcg_gen_ld_i32(r_tmp2, cpu_env, offsetof(CPUState, CP0_SRSCtl));
641 tcg_gen_shri_i32(r_tmp2, r_tmp2, CP0SRSCtl_PSS);
642 tcg_gen_andi_i32(r_tmp2, r_tmp2, 0xf);
643 tcg_gen_muli_i32(r_tmp2, r_tmp2, sizeof(target_ulong) * 32);
644 tcg_gen_add_i32(r_tmp2, cpu_env, r_tmp2);
646 tcg_gen_st_tl(r_tmp1, r_tmp2, sizeof(target_ulong) * to);
647 tcg_temp_free(r_tmp1);
648 tcg_temp_free(r_tmp2);
652 /* Floating point register moves. */
653 static inline void gen_load_fpr32 (TCGv t, int reg)
655 tcg_gen_ld_i32(t, current_fpu, 8 * reg + 4 * FP_ENDIAN_IDX);
658 static inline void gen_store_fpr32 (TCGv t, int reg)
660 tcg_gen_st_i32(t, current_fpu, 8 * reg + 4 * FP_ENDIAN_IDX);
663 static inline void gen_load_fpr64 (DisasContext *ctx, TCGv t, int reg)
665 if (ctx->hflags & MIPS_HFLAG_F64) {
666 tcg_gen_ld_i64(t, current_fpu, 8 * reg);
668 TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
669 TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64);
671 tcg_gen_ld_i32(r_tmp1, current_fpu, 8 * (reg | 1) + 4 * FP_ENDIAN_IDX);
672 tcg_gen_extu_i32_i64(t, r_tmp1);
673 tcg_gen_shli_i64(t, t, 32);
674 tcg_gen_ld_i32(r_tmp1, current_fpu, 8 * (reg & ~1) + 4 * FP_ENDIAN_IDX);
675 tcg_gen_extu_i32_i64(r_tmp2, r_tmp1);
676 tcg_gen_or_i64(t, t, r_tmp2);
677 tcg_temp_free(r_tmp1);
678 tcg_temp_free(r_tmp2);
682 static inline void gen_store_fpr64 (DisasContext *ctx, TCGv t, int reg)
684 if (ctx->hflags & MIPS_HFLAG_F64) {
685 tcg_gen_st_i64(t, current_fpu, 8 * reg);
687 TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
689 tcg_gen_trunc_i64_i32(r_tmp, t);
690 tcg_gen_st_i32(r_tmp, current_fpu, 8 * (reg & ~1) + 4 * FP_ENDIAN_IDX);
691 tcg_gen_shri_i64(t, t, 32);
692 tcg_gen_trunc_i64_i32(r_tmp, t);
693 tcg_gen_st_i32(r_tmp, current_fpu, 8 * (reg | 1) + 4 * FP_ENDIAN_IDX);
694 tcg_temp_free(r_tmp);
698 static inline void gen_load_fpr32h (TCGv t, int reg)
700 tcg_gen_ld_i32(t, current_fpu, 8 * reg + 4 * !FP_ENDIAN_IDX);
703 static inline void gen_store_fpr32h (TCGv t, int reg)
705 tcg_gen_st_i32(t, current_fpu, 8 * reg + 4 * !FP_ENDIAN_IDX);
708 static inline void get_fp_cond (TCGv t)
710 TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
711 TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32);
713 tcg_gen_ld_i32(r_tmp1, current_fpu, offsetof(CPUMIPSFPUContext, fcr31));
714 tcg_gen_shri_i32(r_tmp2, r_tmp1, 24);
715 tcg_gen_andi_i32(r_tmp2, r_tmp2, 0xfe);
716 tcg_gen_shri_i32(r_tmp1, r_tmp1, 23);
717 tcg_gen_andi_i32(r_tmp1, r_tmp1, 0x1);
718 tcg_gen_or_i32(t, r_tmp1, r_tmp2);
719 tcg_temp_free(r_tmp1);
720 tcg_temp_free(r_tmp2);
723 typedef void (fcmp_fun32)(uint32_t, uint32_t, int);
724 typedef void (fcmp_fun64)(uint64_t, uint64_t, int);
726 #define FOP_CONDS(fcmp_fun, type, arg0, arg1, fmt) \
727 static fcmp_fun * fcmp ## type ## _ ## fmt ## _table[16] = { \
728 do_cmp ## type ## _ ## fmt ## _f, \
729 do_cmp ## type ## _ ## fmt ## _un, \
730 do_cmp ## type ## _ ## fmt ## _eq, \
731 do_cmp ## type ## _ ## fmt ## _ueq, \
732 do_cmp ## type ## _ ## fmt ## _olt, \
733 do_cmp ## type ## _ ## fmt ## _ult, \
734 do_cmp ## type ## _ ## fmt ## _ole, \
735 do_cmp ## type ## _ ## fmt ## _ule, \
736 do_cmp ## type ## _ ## fmt ## _sf, \
737 do_cmp ## type ## _ ## fmt ## _ngle, \
738 do_cmp ## type ## _ ## fmt ## _seq, \
739 do_cmp ## type ## _ ## fmt ## _ngl, \
740 do_cmp ## type ## _ ## fmt ## _lt, \
741 do_cmp ## type ## _ ## fmt ## _nge, \
742 do_cmp ## type ## _ ## fmt ## _le, \
743 do_cmp ## type ## _ ## fmt ## _ngt, \
745 static inline void gen_cmp ## type ## _ ## fmt(int n, arg0 a, arg1 b, int cc) \
747 tcg_gen_helper_0_2i(fcmp ## type ## _ ## fmt ## _table[n], a, b, cc); \
750 FOP_CONDS(fcmp_fun64, , uint64_t, uint64_t, d)
751 FOP_CONDS(fcmp_fun64, abs, uint64_t, uint64_t, d)
752 FOP_CONDS(fcmp_fun32, , uint32_t, uint32_t, s)
753 FOP_CONDS(fcmp_fun32, abs, uint32_t, uint32_t, s)
754 FOP_CONDS(fcmp_fun64, , uint64_t, uint64_t, ps)
755 FOP_CONDS(fcmp_fun64, abs, uint64_t, uint64_t, ps)
759 #define OP_COND(name, cond) \
760 static inline void glue(gen_op_, name) (TCGv t0, TCGv t1) \
762 int l1 = gen_new_label(); \
763 int l2 = gen_new_label(); \
765 tcg_gen_brcond_tl(cond, t0, t1, l1); \
766 tcg_gen_movi_tl(t0, 0); \
769 tcg_gen_movi_tl(t0, 1); \
772 OP_COND(eq, TCG_COND_EQ);
773 OP_COND(ne, TCG_COND_NE);
774 OP_COND(ge, TCG_COND_GE);
775 OP_COND(geu, TCG_COND_GEU);
776 OP_COND(lt, TCG_COND_LT);
777 OP_COND(ltu, TCG_COND_LTU);
780 #define OP_CONDI(name, cond) \
781 static inline void glue(gen_op_, name) (TCGv t, target_ulong val) \
783 int l1 = gen_new_label(); \
784 int l2 = gen_new_label(); \
786 tcg_gen_brcondi_tl(cond, t, val, l1); \
787 tcg_gen_movi_tl(t, 0); \
790 tcg_gen_movi_tl(t, 1); \
793 OP_CONDI(lti, TCG_COND_LT);
794 OP_CONDI(ltiu, TCG_COND_LTU);
797 #define OP_CONDZ(name, cond) \
798 static inline void glue(gen_op_, name) (TCGv t) \
800 int l1 = gen_new_label(); \
801 int l2 = gen_new_label(); \
803 tcg_gen_brcondi_tl(cond, t, 0, l1); \
804 tcg_gen_movi_tl(t, 0); \
807 tcg_gen_movi_tl(t, 1); \
810 OP_CONDZ(gez, TCG_COND_GE);
811 OP_CONDZ(gtz, TCG_COND_GT);
812 OP_CONDZ(lez, TCG_COND_LE);
813 OP_CONDZ(ltz, TCG_COND_LT);
816 static inline void gen_save_pc(target_ulong pc)
818 TCGv r_tmp = tcg_temp_new(TCG_TYPE_TL);
820 tcg_gen_movi_tl(r_tmp, pc);
821 tcg_gen_st_tl(r_tmp, cpu_env, offsetof(CPUState, active_tc.PC));
822 tcg_temp_free(r_tmp);
825 static inline void save_cpu_state (DisasContext *ctx, int do_save_pc)
827 #if defined MIPS_DEBUG_DISAS
828 if (loglevel & CPU_LOG_TB_IN_ASM) {
829 fprintf(logfile, "hflags %08x saved %08x\n",
830 ctx->hflags, ctx->saved_hflags);
833 if (do_save_pc && ctx->pc != ctx->saved_pc) {
834 gen_save_pc(ctx->pc);
835 ctx->saved_pc = ctx->pc;
837 if (ctx->hflags != ctx->saved_hflags) {
838 TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
840 tcg_gen_movi_i32(r_tmp, ctx->hflags);
841 tcg_gen_st_i32(r_tmp, cpu_env, offsetof(CPUState, hflags));
842 tcg_temp_free(r_tmp);
843 ctx->saved_hflags = ctx->hflags;
844 switch (ctx->hflags & MIPS_HFLAG_BMASK) {
850 tcg_gen_movi_tl(btarget, ctx->btarget);
856 static inline void restore_cpu_state (CPUState *env, DisasContext *ctx)
858 ctx->saved_hflags = ctx->hflags;
859 switch (ctx->hflags & MIPS_HFLAG_BMASK) {
865 ctx->btarget = env->btarget;
871 generate_exception_err (DisasContext *ctx, int excp, int err)
873 save_cpu_state(ctx, 1);
874 tcg_gen_helper_0_ii(do_raise_exception_err, excp, err);
875 tcg_gen_helper_0_0(do_interrupt_restart);
880 generate_exception (DisasContext *ctx, int excp)
882 save_cpu_state(ctx, 1);
883 tcg_gen_helper_0_i(do_raise_exception, excp);
884 tcg_gen_helper_0_0(do_interrupt_restart);
888 /* Addresses computation */
889 static inline void gen_op_addr_add (TCGv t0, TCGv t1)
891 tcg_gen_add_tl(t0, t0, t1);
893 #if defined(TARGET_MIPS64)
894 /* For compatibility with 32-bit code, data reference in user mode
895 with Status_UX = 0 should be casted to 32-bit and sign extended.
896 See the MIPS64 PRA manual, section 4.10. */
898 int l1 = gen_new_label();
899 TCGv r_tmp = tcg_temp_local_new(TCG_TYPE_I32);
901 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, hflags));
902 tcg_gen_andi_i32(r_tmp, r_tmp, MIPS_HFLAG_KSU);
903 tcg_gen_brcondi_i32(TCG_COND_NE, r_tmp, MIPS_HFLAG_UM, l1);
904 tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Status));
905 tcg_gen_andi_i32(r_tmp, r_tmp, (1 << CP0St_UX));
906 tcg_gen_brcondi_i32(TCG_COND_NE, r_tmp, 0, l1);
907 tcg_temp_free(r_tmp);
908 tcg_gen_ext32s_i64(t0, t0);
914 static inline void check_cp0_enabled(DisasContext *ctx)
916 if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0)))
917 generate_exception_err(ctx, EXCP_CpU, 1);
920 static inline void check_cp1_enabled(DisasContext *ctx)
922 if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU)))
923 generate_exception_err(ctx, EXCP_CpU, 1);
926 /* Verify that the processor is running with COP1X instructions enabled.
927 This is associated with the nabla symbol in the MIPS32 and MIPS64
930 static inline void check_cop1x(DisasContext *ctx)
932 if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X)))
933 generate_exception(ctx, EXCP_RI);
936 /* Verify that the processor is running with 64-bit floating-point
937 operations enabled. */
939 static inline void check_cp1_64bitmode(DisasContext *ctx)
941 if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X)))
942 generate_exception(ctx, EXCP_RI);
946 * Verify if floating point register is valid; an operation is not defined
947 * if bit 0 of any register specification is set and the FR bit in the
948 * Status register equals zero, since the register numbers specify an
949 * even-odd pair of adjacent coprocessor general registers. When the FR bit
950 * in the Status register equals one, both even and odd register numbers
951 * are valid. This limitation exists only for 64 bit wide (d,l,ps) registers.
953 * Multiple 64 bit wide registers can be checked by calling
954 * gen_op_cp1_registers(freg1 | freg2 | ... | fregN);
956 static inline void check_cp1_registers(DisasContext *ctx, int regs)
958 if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1)))
959 generate_exception(ctx, EXCP_RI);
962 /* This code generates a "reserved instruction" exception if the
963 CPU does not support the instruction set corresponding to flags. */
964 static inline void check_insn(CPUState *env, DisasContext *ctx, int flags)
966 if (unlikely(!(env->insn_flags & flags)))
967 generate_exception(ctx, EXCP_RI);
970 /* This code generates a "reserved instruction" exception if 64-bit
971 instructions are not enabled. */
972 static inline void check_mips_64(DisasContext *ctx)
974 if (unlikely(!(ctx->hflags & MIPS_HFLAG_64)))
975 generate_exception(ctx, EXCP_RI);
978 /* load/store instructions. */
979 #define OP_LD(insn,fname) \
980 static inline void op_ldst_##insn(TCGv t0, DisasContext *ctx) \
982 tcg_gen_qemu_##fname(t0, t0, ctx->mem_idx); \
989 #if defined(TARGET_MIPS64)
995 #define OP_ST(insn,fname) \
996 static inline void op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \
998 tcg_gen_qemu_##fname(t1, t0, ctx->mem_idx); \
1003 #if defined(TARGET_MIPS64)
1008 #define OP_LD_ATOMIC(insn,fname) \
1009 static inline void op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \
1011 tcg_gen_mov_tl(t1, t0); \
1012 tcg_gen_qemu_##fname(t0, t0, ctx->mem_idx); \
1013 tcg_gen_st_tl(t1, cpu_env, offsetof(CPUState, CP0_LLAddr)); \
1015 OP_LD_ATOMIC(ll,ld32s);
1016 #if defined(TARGET_MIPS64)
1017 OP_LD_ATOMIC(lld,ld64);
1021 #define OP_ST_ATOMIC(insn,fname,almask) \
1022 static inline void op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \
1024 TCGv r_tmp = tcg_temp_local_new(TCG_TYPE_TL); \
1025 int l1 = gen_new_label(); \
1026 int l2 = gen_new_label(); \
1027 int l3 = gen_new_label(); \
1029 tcg_gen_andi_tl(r_tmp, t0, almask); \
1030 tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp, 0, l1); \
1031 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_BadVAddr)); \
1032 generate_exception(ctx, EXCP_AdES); \
1033 gen_set_label(l1); \
1034 tcg_gen_ld_tl(r_tmp, cpu_env, offsetof(CPUState, CP0_LLAddr)); \
1035 tcg_gen_brcond_tl(TCG_COND_NE, t0, r_tmp, l2); \
1036 tcg_temp_free(r_tmp); \
1037 tcg_gen_qemu_##fname(t1, t0, ctx->mem_idx); \
1038 tcg_gen_movi_tl(t0, 1); \
1040 gen_set_label(l2); \
1041 tcg_gen_movi_tl(t0, 0); \
1042 gen_set_label(l3); \
1044 OP_ST_ATOMIC(sc,st32,0x3);
1045 #if defined(TARGET_MIPS64)
1046 OP_ST_ATOMIC(scd,st64,0x7);
1050 /* Load and store */
1051 static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
1052 int base, int16_t offset)
1054 const char *opn = "ldst";
1055 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
1056 TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);
1059 tcg_gen_movi_tl(t0, offset);
1060 } else if (offset == 0) {
1061 gen_load_gpr(t0, base);
1063 gen_load_gpr(t0, base);
1064 tcg_gen_movi_tl(t1, offset);
1065 gen_op_addr_add(t0, t1);
1067 /* Don't do NOP if destination is zero: we must perform the actual
1070 #if defined(TARGET_MIPS64)
1072 op_ldst_lwu(t0, ctx);
1073 gen_store_gpr(t0, rt);
1077 op_ldst_ld(t0, ctx);
1078 gen_store_gpr(t0, rt);
1082 op_ldst_lld(t0, t1, ctx);
1083 gen_store_gpr(t0, rt);
1087 gen_load_gpr(t1, rt);
1088 op_ldst_sd(t0, t1, ctx);
1092 save_cpu_state(ctx, 1);
1093 gen_load_gpr(t1, rt);
1094 op_ldst_scd(t0, t1, ctx);
1095 gen_store_gpr(t0, rt);
1099 save_cpu_state(ctx, 1);
1100 gen_load_gpr(t1, rt);
1101 tcg_gen_helper_1_2i(do_ldl, t1, t0, t1, ctx->mem_idx);
1102 gen_store_gpr(t1, rt);
1106 save_cpu_state(ctx, 1);
1107 gen_load_gpr(t1, rt);
1108 tcg_gen_helper_0_2i(do_sdl, t0, t1, ctx->mem_idx);
1112 save_cpu_state(ctx, 1);
1113 gen_load_gpr(t1, rt);
1114 tcg_gen_helper_1_2i(do_ldr, t1, t0, t1, ctx->mem_idx);
1115 gen_store_gpr(t1, rt);
1119 save_cpu_state(ctx, 1);
1120 gen_load_gpr(t1, rt);
1121 tcg_gen_helper_0_2i(do_sdr, t0, t1, ctx->mem_idx);
1126 op_ldst_lw(t0, ctx);
1127 gen_store_gpr(t0, rt);
1131 gen_load_gpr(t1, rt);
1132 op_ldst_sw(t0, t1, ctx);
1136 op_ldst_lh(t0, ctx);
1137 gen_store_gpr(t0, rt);
1141 gen_load_gpr(t1, rt);
1142 op_ldst_sh(t0, t1, ctx);
1146 op_ldst_lhu(t0, ctx);
1147 gen_store_gpr(t0, rt);
1151 op_ldst_lb(t0, ctx);
1152 gen_store_gpr(t0, rt);
1156 gen_load_gpr(t1, rt);
1157 op_ldst_sb(t0, t1, ctx);
1161 op_ldst_lbu(t0, ctx);
1162 gen_store_gpr(t0, rt);
1166 save_cpu_state(ctx, 1);
1167 gen_load_gpr(t1, rt);
1168 tcg_gen_helper_1_2i(do_lwl, t1, t0, t1, ctx->mem_idx);
1169 gen_store_gpr(t1, rt);
1173 save_cpu_state(ctx, 1);
1174 gen_load_gpr(t1, rt);
1175 tcg_gen_helper_0_2i(do_swl, t0, t1, ctx->mem_idx);
1179 save_cpu_state(ctx, 1);
1180 gen_load_gpr(t1, rt);
1181 tcg_gen_helper_1_2i(do_lwr, t1, t0, t1, ctx->mem_idx);
1182 gen_store_gpr(t1, rt);
1186 save_cpu_state(ctx, 1);
1187 gen_load_gpr(t1, rt);
1188 tcg_gen_helper_0_2i(do_swr, t0, t1, ctx->mem_idx);
1192 op_ldst_ll(t0, t1, ctx);
1193 gen_store_gpr(t0, rt);
1197 save_cpu_state(ctx, 1);
1198 gen_load_gpr(t1, rt);
1199 op_ldst_sc(t0, t1, ctx);
1200 gen_store_gpr(t0, rt);
1205 generate_exception(ctx, EXCP_RI);
1208 MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]);
1214 /* Load and store */
1215 static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
1216 int base, int16_t offset)
1218 const char *opn = "flt_ldst";
1219 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
1222 tcg_gen_movi_tl(t0, offset);
1223 } else if (offset == 0) {
1224 gen_load_gpr(t0, base);
1226 TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);
1228 gen_load_gpr(t0, base);
1229 tcg_gen_movi_tl(t1, offset);
1230 gen_op_addr_add(t0, t1);
1233 /* Don't do NOP if destination is zero: we must perform the actual
1238 TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
1240 tcg_gen_qemu_ld32s(fp0, t0, ctx->mem_idx);
1241 gen_store_fpr32(fp0, ft);
1248 TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
1250 gen_load_fpr32(fp0, ft);
1251 tcg_gen_qemu_st32(fp0, t0, ctx->mem_idx);
1258 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
1260 tcg_gen_qemu_ld64(fp0, t0, ctx->mem_idx);
1261 gen_store_fpr64(ctx, fp0, ft);
1268 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
1270 gen_load_fpr64(ctx, fp0, ft);
1271 tcg_gen_qemu_st64(fp0, t0, ctx->mem_idx);
1278 generate_exception(ctx, EXCP_RI);
1281 MIPS_DEBUG("%s %s, %d(%s)", opn, fregnames[ft], offset, regnames[base]);
1286 /* Arithmetic with immediate operand */
1287 static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
1288 int rt, int rs, int16_t imm)
1291 const char *opn = "imm arith";
1292 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
1294 if (rt == 0 && opc != OPC_ADDI && opc != OPC_DADDI) {
1295 /* If no destination, treat it as a NOP.
1296 For addi, we must generate the overflow exception when needed. */
1300 uimm = (uint16_t)imm;
1304 #if defined(TARGET_MIPS64)
1310 uimm = (target_long)imm; /* Sign extend to 32/64 bits */
1315 gen_load_gpr(t0, rs);
1318 tcg_gen_movi_tl(t0, imm << 16);
1323 #if defined(TARGET_MIPS64)
1332 gen_load_gpr(t0, rs);
1338 TCGv r_tmp1 = tcg_temp_local_new(TCG_TYPE_TL);
1339 TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);
1340 int l1 = gen_new_label();
1342 save_cpu_state(ctx, 1);
1343 tcg_gen_ext32s_tl(r_tmp1, t0);
1344 tcg_gen_addi_tl(t0, r_tmp1, uimm);
1346 tcg_gen_xori_tl(r_tmp1, r_tmp1, uimm);
1347 tcg_gen_xori_tl(r_tmp1, r_tmp1, -1);
1348 tcg_gen_xori_tl(r_tmp2, t0, uimm);
1349 tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2);
1350 tcg_temp_free(r_tmp2);
1351 tcg_gen_shri_tl(r_tmp1, r_tmp1, 31);
1352 tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp1, 0, l1);
1353 tcg_temp_free(r_tmp1);
1354 /* operands of same sign, result different sign */
1355 generate_exception(ctx, EXCP_OVERFLOW);
1358 tcg_gen_ext32s_tl(t0, t0);
1363 tcg_gen_ext32s_tl(t0, t0);
1364 tcg_gen_addi_tl(t0, t0, uimm);
1365 tcg_gen_ext32s_tl(t0, t0);
1368 #if defined(TARGET_MIPS64)
1371 TCGv r_tmp1 = tcg_temp_local_new(TCG_TYPE_TL);
1372 TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);
1373 int l1 = gen_new_label();
1375 save_cpu_state(ctx, 1);
1376 tcg_gen_mov_tl(r_tmp1, t0);
1377 tcg_gen_addi_tl(t0, t0, uimm);
1379 tcg_gen_xori_tl(r_tmp1, r_tmp1, uimm);
1380 tcg_gen_xori_tl(r_tmp1, r_tmp1, -1);
1381 tcg_gen_xori_tl(r_tmp2, t0, uimm);
1382 tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2);
1383 tcg_temp_free(r_tmp2);
1384 tcg_gen_shri_tl(r_tmp1, r_tmp1, 63);
1385 tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp1, 0, l1);
1386 tcg_temp_free(r_tmp1);
1387 /* operands of same sign, result different sign */
1388 generate_exception(ctx, EXCP_OVERFLOW);
1394 tcg_gen_addi_tl(t0, t0, uimm);
1399 gen_op_lti(t0, uimm);
1403 gen_op_ltiu(t0, uimm);
1407 tcg_gen_andi_tl(t0, t0, uimm);
1411 tcg_gen_ori_tl(t0, t0, uimm);
1415 tcg_gen_xori_tl(t0, t0, uimm);
1422 tcg_gen_ext32u_tl(t0, t0);
1423 tcg_gen_shli_tl(t0, t0, uimm);
1424 tcg_gen_ext32s_tl(t0, t0);
1428 tcg_gen_ext32s_tl(t0, t0);
1429 tcg_gen_sari_tl(t0, t0, uimm);
1430 tcg_gen_ext32s_tl(t0, t0);
1434 switch ((ctx->opcode >> 21) & 0x1f) {
1436 tcg_gen_ext32u_tl(t0, t0);
1437 tcg_gen_shri_tl(t0, t0, uimm);
1438 tcg_gen_ext32s_tl(t0, t0);
1442 /* rotr is decoded as srl on non-R2 CPUs */
1443 if (env->insn_flags & ISA_MIPS32R2) {
1445 TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
1446 TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32);
1448 tcg_gen_trunc_tl_i32(r_tmp1, t0);
1449 tcg_gen_movi_i32(r_tmp2, 0x20);
1450 tcg_gen_subi_i32(r_tmp2, r_tmp2, uimm);
1451 tcg_gen_shl_i32(r_tmp2, r_tmp1, r_tmp2);
1452 tcg_gen_shri_i32(r_tmp1, r_tmp1, uimm);
1453 tcg_gen_or_i32(r_tmp1, r_tmp1, r_tmp2);
1454 tcg_gen_ext_i32_tl(t0, r_tmp1);
1455 tcg_temp_free(r_tmp1);
1456 tcg_temp_free(r_tmp2);
1460 tcg_gen_ext32u_tl(t0, t0);
1461 tcg_gen_shri_tl(t0, t0, uimm);
1462 tcg_gen_ext32s_tl(t0, t0);
1467 MIPS_INVAL("invalid srl flag");
1468 generate_exception(ctx, EXCP_RI);
1472 #if defined(TARGET_MIPS64)
1474 tcg_gen_shli_tl(t0, t0, uimm);
1478 tcg_gen_sari_tl(t0, t0, uimm);
1482 switch ((ctx->opcode >> 21) & 0x1f) {
1484 tcg_gen_shri_tl(t0, t0, uimm);
1488 /* drotr is decoded as dsrl on non-R2 CPUs */
1489 if (env->insn_flags & ISA_MIPS32R2) {
1491 TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);
1493 tcg_gen_movi_tl(r_tmp1, 0x40);
1494 tcg_gen_subi_tl(r_tmp1, r_tmp1, uimm);
1495 tcg_gen_shl_tl(r_tmp1, t0, r_tmp1);
1496 tcg_gen_shri_tl(t0, t0, uimm);
1497 tcg_gen_or_tl(t0, t0, r_tmp1);
1498 tcg_temp_free(r_tmp1);
1502 tcg_gen_shri_tl(t0, t0, uimm);
1507 MIPS_INVAL("invalid dsrl flag");
1508 generate_exception(ctx, EXCP_RI);
1513 tcg_gen_shli_tl(t0, t0, uimm + 32);
1517 tcg_gen_sari_tl(t0, t0, uimm + 32);
1521 switch ((ctx->opcode >> 21) & 0x1f) {
1523 tcg_gen_shri_tl(t0, t0, uimm + 32);
1527 /* drotr32 is decoded as dsrl32 on non-R2 CPUs */
1528 if (env->insn_flags & ISA_MIPS32R2) {
1529 TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);
1530 TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);
1532 tcg_gen_movi_tl(r_tmp1, 0x40);
1533 tcg_gen_movi_tl(r_tmp2, 32);
1534 tcg_gen_addi_tl(r_tmp2, r_tmp2, uimm);
1535 tcg_gen_sub_tl(r_tmp1, r_tmp1, r_tmp2);
1536 tcg_gen_shl_tl(r_tmp1, t0, r_tmp1);
1537 tcg_gen_shr_tl(t0, t0, r_tmp2);
1538 tcg_gen_or_tl(t0, t0, r_tmp1);
1539 tcg_temp_free(r_tmp1);
1540 tcg_temp_free(r_tmp2);
1543 tcg_gen_shri_tl(t0, t0, uimm + 32);
1548 MIPS_INVAL("invalid dsrl32 flag");
1549 generate_exception(ctx, EXCP_RI);
1556 generate_exception(ctx, EXCP_RI);
1559 gen_store_gpr(t0, rt);
1560 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt], regnames[rs], uimm);
1566 static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
1567 int rd, int rs, int rt)
1569 const char *opn = "arith";
1570 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
1571 TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);
1573 if (rd == 0 && opc != OPC_ADD && opc != OPC_SUB
1574 && opc != OPC_DADD && opc != OPC_DSUB) {
1575 /* If no destination, treat it as a NOP.
1576 For add & sub, we must generate the overflow exception when needed. */
1580 gen_load_gpr(t0, rs);
1581 /* Specialcase the conventional move operation. */
1582 if (rt == 0 && (opc == OPC_ADDU || opc == OPC_DADDU
1583 || opc == OPC_SUBU || opc == OPC_DSUBU)) {
1584 gen_store_gpr(t0, rd);
1587 gen_load_gpr(t1, rt);
1591 TCGv r_tmp1 = tcg_temp_local_new(TCG_TYPE_TL);
1592 TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);
1593 int l1 = gen_new_label();
1595 save_cpu_state(ctx, 1);
1596 tcg_gen_ext32s_tl(r_tmp1, t0);
1597 tcg_gen_ext32s_tl(r_tmp2, t1);
1598 tcg_gen_add_tl(t0, r_tmp1, r_tmp2);
1600 tcg_gen_xor_tl(r_tmp1, r_tmp1, t1);
1601 tcg_gen_xori_tl(r_tmp1, r_tmp1, -1);
1602 tcg_gen_xor_tl(r_tmp2, t0, t1);
1603 tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2);
1604 tcg_temp_free(r_tmp2);
1605 tcg_gen_shri_tl(r_tmp1, r_tmp1, 31);
1606 tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp1, 0, l1);
1607 tcg_temp_free(r_tmp1);
1608 /* operands of same sign, result different sign */
1609 generate_exception(ctx, EXCP_OVERFLOW);
1612 tcg_gen_ext32s_tl(t0, t0);
1617 tcg_gen_ext32s_tl(t0, t0);
1618 tcg_gen_ext32s_tl(t1, t1);
1619 tcg_gen_add_tl(t0, t0, t1);
1620 tcg_gen_ext32s_tl(t0, t0);
1625 TCGv r_tmp1 = tcg_temp_local_new(TCG_TYPE_TL);
1626 TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);
1627 int l1 = gen_new_label();
1629 save_cpu_state(ctx, 1);
1630 tcg_gen_ext32s_tl(r_tmp1, t0);
1631 tcg_gen_ext32s_tl(r_tmp2, t1);
1632 tcg_gen_sub_tl(t0, r_tmp1, r_tmp2);
1634 tcg_gen_xor_tl(r_tmp2, r_tmp1, t1);
1635 tcg_gen_xor_tl(r_tmp1, r_tmp1, t0);
1636 tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2);
1637 tcg_temp_free(r_tmp2);
1638 tcg_gen_shri_tl(r_tmp1, r_tmp1, 31);
1639 tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp1, 0, l1);
1640 tcg_temp_free(r_tmp1);
1641 /* operands of different sign, first operand and result different sign */
1642 generate_exception(ctx, EXCP_OVERFLOW);
1645 tcg_gen_ext32s_tl(t0, t0);
1650 tcg_gen_ext32s_tl(t0, t0);
1651 tcg_gen_ext32s_tl(t1, t1);
1652 tcg_gen_sub_tl(t0, t0, t1);
1653 tcg_gen_ext32s_tl(t0, t0);
1656 #if defined(TARGET_MIPS64)
1659 TCGv r_tmp1 = tcg_temp_local_new(TCG_TYPE_TL);
1660 TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);
1661 int l1 = gen_new_label();
1663 save_cpu_state(ctx, 1);
1664 tcg_gen_mov_tl(r_tmp1, t0);
1665 tcg_gen_add_tl(t0, t0, t1);
1667 tcg_gen_xor_tl(r_tmp1, r_tmp1, t1);
1668 tcg_gen_xori_tl(r_tmp1, r_tmp1, -1);
1669 tcg_gen_xor_tl(r_tmp2, t0, t1);
1670 tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2);
1671 tcg_temp_free(r_tmp2);
1672 tcg_gen_shri_tl(r_tmp1, r_tmp1, 63);
1673 tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp1, 0, l1);
1674 tcg_temp_free(r_tmp1);
1675 /* operands of same sign, result different sign */
1676 generate_exception(ctx, EXCP_OVERFLOW);
1682 tcg_gen_add_tl(t0, t0, t1);
1687 TCGv r_tmp1 = tcg_temp_local_new(TCG_TYPE_TL);
1688 TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_TL);
1689 int l1 = gen_new_label();
1691 save_cpu_state(ctx, 1);
1692 tcg_gen_mov_tl(r_tmp1, t0);
1693 tcg_gen_sub_tl(t0, t0, t1);
1695 tcg_gen_xor_tl(r_tmp2, r_tmp1, t1);
1696 tcg_gen_xor_tl(r_tmp1, r_tmp1, t0);
1697 tcg_gen_and_tl(r_tmp1, r_tmp1, r_tmp2);
1698 tcg_temp_free(r_tmp2);
1699 tcg_gen_shri_tl(r_tmp1, r_tmp1, 63);
1700 tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp1, 0, l1);
1701 tcg_temp_free(r_tmp1);
1702 /* operands of different sign, first operand and result different sign */
1703 generate_exception(ctx, EXCP_OVERFLOW);
1709 tcg_gen_sub_tl(t0, t0, t1);
1722 tcg_gen_and_tl(t0, t0, t1);
1726 tcg_gen_or_tl(t0, t0, t1);
1727 tcg_gen_not_tl(t0, t0);
1731 tcg_gen_or_tl(t0, t0, t1);
1735 tcg_gen_xor_tl(t0, t0, t1);
1739 tcg_gen_ext32s_tl(t0, t0);
1740 tcg_gen_ext32s_tl(t1, t1);
1741 tcg_gen_mul_tl(t0, t0, t1);
1742 tcg_gen_ext32s_tl(t0, t0);
1747 int l1 = gen_new_label();
1749 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
1750 gen_store_gpr(t0, rd);
1757 int l1 = gen_new_label();
1759 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
1760 gen_store_gpr(t0, rd);
1766 tcg_gen_ext32u_tl(t0, t0);
1767 tcg_gen_ext32u_tl(t1, t1);
1768 tcg_gen_andi_tl(t0, t0, 0x1f);
1769 tcg_gen_shl_tl(t0, t1, t0);
1770 tcg_gen_ext32s_tl(t0, t0);
1774 tcg_gen_ext32s_tl(t1, t1);
1775 tcg_gen_andi_tl(t0, t0, 0x1f);
1776 tcg_gen_sar_tl(t0, t1, t0);
1777 tcg_gen_ext32s_tl(t0, t0);
1781 switch ((ctx->opcode >> 6) & 0x1f) {
1783 tcg_gen_ext32u_tl(t1, t1);
1784 tcg_gen_andi_tl(t0, t0, 0x1f);
1785 tcg_gen_shr_tl(t0, t1, t0);
1786 tcg_gen_ext32s_tl(t0, t0);
1790 /* rotrv is decoded as srlv on non-R2 CPUs */
1791 if (env->insn_flags & ISA_MIPS32R2) {
1792 int l1 = gen_new_label();
1793 int l2 = gen_new_label();
1795 tcg_gen_andi_tl(t0, t0, 0x1f);
1796 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1798 TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
1799 TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32);
1800 TCGv r_tmp3 = tcg_temp_new(TCG_TYPE_I32);
1802 tcg_gen_trunc_tl_i32(r_tmp1, t0);
1803 tcg_gen_trunc_tl_i32(r_tmp2, t1);
1804 tcg_gen_movi_i32(r_tmp3, 0x20);
1805 tcg_gen_sub_i32(r_tmp3, r_tmp3, r_tmp1);
1806 tcg_gen_shl_i32(r_tmp3, r_tmp2, r_tmp3);
1807 tcg_gen_shr_i32(r_tmp1, r_tmp2, r_tmp1);
1808 tcg_gen_or_i32(r_tmp1, r_tmp1, r_tmp3);
1809 tcg_gen_ext_i32_tl(t0, r_tmp1);
1810 tcg_temp_free(r_tmp1);
1811 tcg_temp_free(r_tmp2);
1812 tcg_temp_free(r_tmp3);
1816 tcg_gen_mov_tl(t0, t1);
1820 tcg_gen_ext32u_tl(t1, t1);
1821 tcg_gen_andi_tl(t0, t0, 0x1f);
1822 tcg_gen_shr_tl(t0, t1, t0);
1823 tcg_gen_ext32s_tl(t0, t0);
1828 MIPS_INVAL("invalid srlv flag");
1829 generate_exception(ctx, EXCP_RI);
1833 #if defined(TARGET_MIPS64)
1835 tcg_gen_andi_tl(t0, t0, 0x3f);
1836 tcg_gen_shl_tl(t0, t1, t0);
1840 tcg_gen_andi_tl(t0, t0, 0x3f);
1841 tcg_gen_sar_tl(t0, t1, t0);
1845 switch ((ctx->opcode >> 6) & 0x1f) {
1847 tcg_gen_andi_tl(t0, t0, 0x3f);
1848 tcg_gen_shr_tl(t0, t1, t0);
1852 /* drotrv is decoded as dsrlv on non-R2 CPUs */
1853 if (env->insn_flags & ISA_MIPS32R2) {
1854 int l1 = gen_new_label();
1855 int l2 = gen_new_label();
1857 tcg_gen_andi_tl(t0, t0, 0x3f);
1858 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1860 TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);
1862 tcg_gen_movi_tl(r_tmp1, 0x40);
1863 tcg_gen_sub_tl(r_tmp1, r_tmp1, t0);
1864 tcg_gen_shl_tl(r_tmp1, t1, r_tmp1);
1865 tcg_gen_shr_tl(t0, t1, t0);
1866 tcg_gen_or_tl(t0, t0, r_tmp1);
1867 tcg_temp_free(r_tmp1);
1871 tcg_gen_mov_tl(t0, t1);
1875 tcg_gen_andi_tl(t0, t0, 0x3f);
1876 tcg_gen_shr_tl(t0, t1, t0);
1881 MIPS_INVAL("invalid dsrlv flag");
1882 generate_exception(ctx, EXCP_RI);
1889 generate_exception(ctx, EXCP_RI);
1892 gen_store_gpr(t0, rd);
1894 MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]);
1900 /* Arithmetic on HI/LO registers */
1901 static void gen_HILO (DisasContext *ctx, uint32_t opc, int reg)
1903 const char *opn = "hilo";
1904 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
1906 if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) {
1914 gen_store_gpr(t0, reg);
1919 gen_store_gpr(t0, reg);
1923 gen_load_gpr(t0, reg);
1924 gen_store_HI(t0, 0);
1928 gen_load_gpr(t0, reg);
1929 gen_store_LO(t0, 0);
1934 generate_exception(ctx, EXCP_RI);
1937 MIPS_DEBUG("%s %s", opn, regnames[reg]);
1942 static void gen_muldiv (DisasContext *ctx, uint32_t opc,
1945 const char *opn = "mul/div";
1946 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
1947 TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);
1949 gen_load_gpr(t0, rs);
1950 gen_load_gpr(t1, rt);
1954 int l1 = gen_new_label();
1956 tcg_gen_ext32s_tl(t0, t0);
1957 tcg_gen_ext32s_tl(t1, t1);
1958 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
1960 TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64);
1961 TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64);
1962 TCGv r_tmp3 = tcg_temp_new(TCG_TYPE_I64);
1964 tcg_gen_ext_tl_i64(r_tmp1, t0);
1965 tcg_gen_ext_tl_i64(r_tmp2, t1);
1966 tcg_gen_div_i64(r_tmp3, r_tmp1, r_tmp2);
1967 tcg_gen_rem_i64(r_tmp2, r_tmp1, r_tmp2);
1968 tcg_gen_trunc_i64_tl(t0, r_tmp3);
1969 tcg_gen_trunc_i64_tl(t1, r_tmp2);
1970 tcg_temp_free(r_tmp1);
1971 tcg_temp_free(r_tmp2);
1972 tcg_temp_free(r_tmp3);
1973 tcg_gen_ext32s_tl(t0, t0);
1974 tcg_gen_ext32s_tl(t1, t1);
1975 gen_store_LO(t0, 0);
1976 gen_store_HI(t1, 0);
1984 int l1 = gen_new_label();
1986 tcg_gen_ext32s_tl(t1, t1);
1987 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
1989 TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
1990 TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32);
1991 TCGv r_tmp3 = tcg_temp_new(TCG_TYPE_I32);
1993 tcg_gen_trunc_tl_i32(r_tmp1, t0);
1994 tcg_gen_trunc_tl_i32(r_tmp2, t1);
1995 tcg_gen_divu_i32(r_tmp3, r_tmp1, r_tmp2);
1996 tcg_gen_remu_i32(r_tmp1, r_tmp1, r_tmp2);
1997 tcg_gen_ext_i32_tl(t0, r_tmp3);
1998 tcg_gen_ext_i32_tl(t1, r_tmp1);
1999 tcg_temp_free(r_tmp1);
2000 tcg_temp_free(r_tmp2);
2001 tcg_temp_free(r_tmp3);
2002 gen_store_LO(t0, 0);
2003 gen_store_HI(t1, 0);
2011 TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64);
2012 TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64);
2014 tcg_gen_ext32s_tl(t0, t0);
2015 tcg_gen_ext32s_tl(t1, t1);
2016 tcg_gen_ext_tl_i64(r_tmp1, t0);
2017 tcg_gen_ext_tl_i64(r_tmp2, t1);
2018 tcg_gen_mul_i64(r_tmp1, r_tmp1, r_tmp2);
2019 tcg_temp_free(r_tmp2);
2020 tcg_gen_trunc_i64_tl(t0, r_tmp1);
2021 tcg_gen_shri_i64(r_tmp1, r_tmp1, 32);
2022 tcg_gen_trunc_i64_tl(t1, r_tmp1);
2023 tcg_temp_free(r_tmp1);
2024 tcg_gen_ext32s_tl(t0, t0);
2025 tcg_gen_ext32s_tl(t1, t1);
2026 gen_store_LO(t0, 0);
2027 gen_store_HI(t1, 0);
2033 TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64);
2034 TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64);
2036 tcg_gen_ext32u_tl(t0, t0);
2037 tcg_gen_ext32u_tl(t1, t1);
2038 tcg_gen_extu_tl_i64(r_tmp1, t0);
2039 tcg_gen_extu_tl_i64(r_tmp2, t1);
2040 tcg_gen_mul_i64(r_tmp1, r_tmp1, r_tmp2);
2041 tcg_temp_free(r_tmp2);
2042 tcg_gen_trunc_i64_tl(t0, r_tmp1);
2043 tcg_gen_shri_i64(r_tmp1, r_tmp1, 32);
2044 tcg_gen_trunc_i64_tl(t1, r_tmp1);
2045 tcg_temp_free(r_tmp1);
2046 tcg_gen_ext32s_tl(t0, t0);
2047 tcg_gen_ext32s_tl(t1, t1);
2048 gen_store_LO(t0, 0);
2049 gen_store_HI(t1, 0);
2053 #if defined(TARGET_MIPS64)
2056 int l1 = gen_new_label();
2058 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
2060 int l2 = gen_new_label();
2062 tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2);
2063 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2);
2065 tcg_gen_movi_tl(t1, 0);
2066 gen_store_LO(t0, 0);
2067 gen_store_HI(t1, 0);
2072 TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64);
2073 TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64);
2075 tcg_gen_div_i64(r_tmp1, t0, t1);
2076 tcg_gen_rem_i64(r_tmp2, t0, t1);
2077 gen_store_LO(r_tmp1, 0);
2078 gen_store_HI(r_tmp2, 0);
2079 tcg_temp_free(r_tmp1);
2080 tcg_temp_free(r_tmp2);
2089 int l1 = gen_new_label();
2091 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
2093 TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64);
2094 TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64);
2096 tcg_gen_divu_i64(r_tmp1, t0, t1);
2097 tcg_gen_remu_i64(r_tmp2, t0, t1);
2098 tcg_temp_free(r_tmp1);
2099 tcg_temp_free(r_tmp2);
2100 gen_store_LO(r_tmp1, 0);
2101 gen_store_HI(r_tmp2, 0);
2108 tcg_gen_helper_0_2(do_dmult, t0, t1);
2112 tcg_gen_helper_0_2(do_dmultu, t0, t1);
2118 TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64);
2119 TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64);
2120 TCGv r_tmp3 = tcg_temp_new(TCG_TYPE_I64);
2122 tcg_gen_ext32s_tl(t0, t0);
2123 tcg_gen_ext32s_tl(t1, t1);
2124 tcg_gen_ext_tl_i64(r_tmp1, t0);
2125 tcg_gen_ext_tl_i64(r_tmp2, t1);
2126 tcg_gen_mul_i64(r_tmp1, r_tmp1, r_tmp2);
2129 tcg_gen_extu_tl_i64(r_tmp2, t0);
2130 tcg_gen_extu_tl_i64(r_tmp3, t1);
2131 tcg_gen_shli_i64(r_tmp3, r_tmp3, 32);
2132 tcg_gen_or_i64(r_tmp2, r_tmp2, r_tmp3);
2133 tcg_temp_free(r_tmp3);
2134 tcg_gen_add_i64(r_tmp1, r_tmp1, r_tmp2);
2135 tcg_temp_free(r_tmp2);
2136 tcg_gen_trunc_i64_tl(t0, r_tmp1);
2137 tcg_gen_shri_i64(r_tmp1, r_tmp1, 32);
2138 tcg_gen_trunc_i64_tl(t1, r_tmp1);
2139 tcg_temp_free(r_tmp1);
2140 tcg_gen_ext32s_tl(t0, t0);
2141 tcg_gen_ext32s_tl(t1, t1);
2142 gen_store_LO(t0, 0);
2143 gen_store_HI(t1, 0);
2149 TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64);
2150 TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64);
2151 TCGv r_tmp3 = tcg_temp_new(TCG_TYPE_I64);
2153 tcg_gen_ext32u_tl(t0, t0);
2154 tcg_gen_ext32u_tl(t1, t1);
2155 tcg_gen_extu_tl_i64(r_tmp1, t0);
2156 tcg_gen_extu_tl_i64(r_tmp2, t1);
2157 tcg_gen_mul_i64(r_tmp1, r_tmp1, r_tmp2);
2160 tcg_gen_extu_tl_i64(r_tmp2, t0);
2161 tcg_gen_extu_tl_i64(r_tmp3, t1);
2162 tcg_gen_shli_i64(r_tmp3, r_tmp3, 32);
2163 tcg_gen_or_i64(r_tmp2, r_tmp2, r_tmp3);
2164 tcg_temp_free(r_tmp3);
2165 tcg_gen_add_i64(r_tmp1, r_tmp1, r_tmp2);
2166 tcg_temp_free(r_tmp2);
2167 tcg_gen_trunc_i64_tl(t0, r_tmp1);
2168 tcg_gen_shri_i64(r_tmp1, r_tmp1, 32);
2169 tcg_gen_trunc_i64_tl(t1, r_tmp1);
2170 tcg_temp_free(r_tmp1);
2171 tcg_gen_ext32s_tl(t0, t0);
2172 tcg_gen_ext32s_tl(t1, t1);
2173 gen_store_LO(t0, 0);
2174 gen_store_HI(t1, 0);
2180 TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64);
2181 TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64);
2182 TCGv r_tmp3 = tcg_temp_new(TCG_TYPE_I64);
2184 tcg_gen_ext32s_tl(t0, t0);
2185 tcg_gen_ext32s_tl(t1, t1);
2186 tcg_gen_ext_tl_i64(r_tmp1, t0);
2187 tcg_gen_ext_tl_i64(r_tmp2, t1);
2188 tcg_gen_mul_i64(r_tmp1, r_tmp1, r_tmp2);
2191 tcg_gen_extu_tl_i64(r_tmp2, t0);
2192 tcg_gen_extu_tl_i64(r_tmp3, t1);
2193 tcg_gen_shli_i64(r_tmp3, r_tmp3, 32);
2194 tcg_gen_or_i64(r_tmp2, r_tmp2, r_tmp3);
2195 tcg_temp_free(r_tmp3);
2196 tcg_gen_sub_i64(r_tmp1, r_tmp1, r_tmp2);
2197 tcg_temp_free(r_tmp2);
2198 tcg_gen_trunc_i64_tl(t0, r_tmp1);
2199 tcg_gen_shri_i64(r_tmp1, r_tmp1, 32);
2200 tcg_gen_trunc_i64_tl(t1, r_tmp1);
2201 tcg_temp_free(r_tmp1);
2202 tcg_gen_ext32s_tl(t0, t0);
2203 tcg_gen_ext32s_tl(t1, t1);
2204 gen_store_LO(t0, 0);
2205 gen_store_HI(t1, 0);
2211 TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64);
2212 TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64);
2213 TCGv r_tmp3 = tcg_temp_new(TCG_TYPE_I64);
2215 tcg_gen_ext32u_tl(t0, t0);
2216 tcg_gen_ext32u_tl(t1, t1);
2217 tcg_gen_extu_tl_i64(r_tmp1, t0);
2218 tcg_gen_extu_tl_i64(r_tmp2, t1);
2219 tcg_gen_mul_i64(r_tmp1, r_tmp1, r_tmp2);
2222 tcg_gen_extu_tl_i64(r_tmp2, t0);
2223 tcg_gen_extu_tl_i64(r_tmp3, t1);
2224 tcg_gen_shli_i64(r_tmp3, r_tmp3, 32);
2225 tcg_gen_or_i64(r_tmp2, r_tmp2, r_tmp3);
2226 tcg_temp_free(r_tmp3);
2227 tcg_gen_sub_i64(r_tmp1, r_tmp1, r_tmp2);
2228 tcg_temp_free(r_tmp2);
2229 tcg_gen_trunc_i64_tl(t0, r_tmp1);
2230 tcg_gen_shri_i64(r_tmp1, r_tmp1, 32);
2231 tcg_gen_trunc_i64_tl(t1, r_tmp1);
2232 tcg_temp_free(r_tmp1);
2233 tcg_gen_ext32s_tl(t0, t0);
2234 tcg_gen_ext32s_tl(t1, t1);
2235 gen_store_LO(t0, 0);
2236 gen_store_HI(t1, 0);
2242 generate_exception(ctx, EXCP_RI);
2245 MIPS_DEBUG("%s %s %s", opn, regnames[rs], regnames[rt]);
2251 static void gen_mul_vr54xx (DisasContext *ctx, uint32_t opc,
2252 int rd, int rs, int rt)
2254 const char *opn = "mul vr54xx";
2255 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
2256 TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);
2258 gen_load_gpr(t0, rs);
2259 gen_load_gpr(t1, rt);
2262 case OPC_VR54XX_MULS:
2263 tcg_gen_helper_1_2(do_muls, t0, t0, t1);
2266 case OPC_VR54XX_MULSU:
2267 tcg_gen_helper_1_2(do_mulsu, t0, t0, t1);
2270 case OPC_VR54XX_MACC:
2271 tcg_gen_helper_1_2(do_macc, t0, t0, t1);
2274 case OPC_VR54XX_MACCU:
2275 tcg_gen_helper_1_2(do_maccu, t0, t0, t1);
2278 case OPC_VR54XX_MSAC:
2279 tcg_gen_helper_1_2(do_msac, t0, t0, t1);
2282 case OPC_VR54XX_MSACU:
2283 tcg_gen_helper_1_2(do_msacu, t0, t0, t1);
2286 case OPC_VR54XX_MULHI:
2287 tcg_gen_helper_1_2(do_mulhi, t0, t0, t1);
2290 case OPC_VR54XX_MULHIU:
2291 tcg_gen_helper_1_2(do_mulhiu, t0, t0, t1);
2294 case OPC_VR54XX_MULSHI:
2295 tcg_gen_helper_1_2(do_mulshi, t0, t0, t1);
2298 case OPC_VR54XX_MULSHIU:
2299 tcg_gen_helper_1_2(do_mulshiu, t0, t0, t1);
2302 case OPC_VR54XX_MACCHI:
2303 tcg_gen_helper_1_2(do_macchi, t0, t0, t1);
2306 case OPC_VR54XX_MACCHIU:
2307 tcg_gen_helper_1_2(do_macchiu, t0, t0, t1);
2310 case OPC_VR54XX_MSACHI:
2311 tcg_gen_helper_1_2(do_msachi, t0, t0, t1);
2314 case OPC_VR54XX_MSACHIU:
2315 tcg_gen_helper_1_2(do_msachiu, t0, t0, t1);
2319 MIPS_INVAL("mul vr54xx");
2320 generate_exception(ctx, EXCP_RI);
2323 gen_store_gpr(t0, rd);
2324 MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]);
2331 static void gen_cl (DisasContext *ctx, uint32_t opc,
2334 const char *opn = "CLx";
2335 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
2342 gen_load_gpr(t0, rs);
2345 tcg_gen_helper_1_1(do_clo, t0, t0);
2349 tcg_gen_helper_1_1(do_clz, t0, t0);
2352 #if defined(TARGET_MIPS64)
2354 tcg_gen_helper_1_1(do_dclo, t0, t0);
2358 tcg_gen_helper_1_1(do_dclz, t0, t0);
2364 generate_exception(ctx, EXCP_RI);
2367 gen_store_gpr(t0, rd);
2368 MIPS_DEBUG("%s %s, %s", opn, regnames[rd], regnames[rs]);
2375 static void gen_trap (DisasContext *ctx, uint32_t opc,
2376 int rs, int rt, int16_t imm)
2379 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
2380 TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);
2383 /* Load needed operands */
2391 /* Compare two registers */
2393 gen_load_gpr(t0, rs);
2394 gen_load_gpr(t1, rt);
2404 /* Compare register to immediate */
2405 if (rs != 0 || imm != 0) {
2406 gen_load_gpr(t0, rs);
2407 tcg_gen_movi_tl(t1, (int32_t)imm);
2414 case OPC_TEQ: /* rs == rs */
2415 case OPC_TEQI: /* r0 == 0 */
2416 case OPC_TGE: /* rs >= rs */
2417 case OPC_TGEI: /* r0 >= 0 */
2418 case OPC_TGEU: /* rs >= rs unsigned */
2419 case OPC_TGEIU: /* r0 >= 0 unsigned */
2421 tcg_gen_movi_tl(t0, 1);
2423 case OPC_TLT: /* rs < rs */
2424 case OPC_TLTI: /* r0 < 0 */
2425 case OPC_TLTU: /* rs < rs unsigned */
2426 case OPC_TLTIU: /* r0 < 0 unsigned */
2427 case OPC_TNE: /* rs != rs */
2428 case OPC_TNEI: /* r0 != 0 */
2429 /* Never trap: treat as NOP. */
2433 generate_exception(ctx, EXCP_RI);
2464 generate_exception(ctx, EXCP_RI);
2468 save_cpu_state(ctx, 1);
2470 int l1 = gen_new_label();
2472 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2473 tcg_gen_helper_0_i(do_raise_exception, EXCP_TRAP);
2476 ctx->bstate = BS_STOP;
2482 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
2484 TranslationBlock *tb;
2486 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
2489 tcg_gen_exit_tb((long)tb + n);
2496 /* Branches (before delay slot) */
2497 static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
2498 int rs, int rt, int32_t offset)
2500 target_ulong btgt = -1;
2503 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
2504 TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);
2506 if (ctx->hflags & MIPS_HFLAG_BMASK) {
2507 #ifdef MIPS_DEBUG_DISAS
2508 if (loglevel & CPU_LOG_TB_IN_ASM) {
2510 "Branch in delay slot at PC 0x" TARGET_FMT_lx "\n",
2514 generate_exception(ctx, EXCP_RI);
2518 /* Load needed operands */
2524 /* Compare two registers */
2526 gen_load_gpr(t0, rs);
2527 gen_load_gpr(t1, rt);
2530 btgt = ctx->pc + 4 + offset;
2544 /* Compare to zero */
2546 gen_load_gpr(t0, rs);
2549 btgt = ctx->pc + 4 + offset;
2553 /* Jump to immediate */
2554 btgt = ((ctx->pc + 4) & (int32_t)0xF0000000) | (uint32_t)offset;
2558 /* Jump to register */
2559 if (offset != 0 && offset != 16) {
2560 /* Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the
2561 others are reserved. */
2562 MIPS_INVAL("jump hint");
2563 generate_exception(ctx, EXCP_RI);
2566 gen_load_gpr(btarget, rs);
2569 MIPS_INVAL("branch/jump");
2570 generate_exception(ctx, EXCP_RI);
2574 /* No condition to be computed */
2576 case OPC_BEQ: /* rx == rx */
2577 case OPC_BEQL: /* rx == rx likely */
2578 case OPC_BGEZ: /* 0 >= 0 */
2579 case OPC_BGEZL: /* 0 >= 0 likely */
2580 case OPC_BLEZ: /* 0 <= 0 */
2581 case OPC_BLEZL: /* 0 <= 0 likely */
2583 ctx->hflags |= MIPS_HFLAG_B;
2584 MIPS_DEBUG("balways");
2586 case OPC_BGEZAL: /* 0 >= 0 */
2587 case OPC_BGEZALL: /* 0 >= 0 likely */
2588 /* Always take and link */
2590 ctx->hflags |= MIPS_HFLAG_B;
2591 MIPS_DEBUG("balways and link");
2593 case OPC_BNE: /* rx != rx */
2594 case OPC_BGTZ: /* 0 > 0 */
2595 case OPC_BLTZ: /* 0 < 0 */
2597 MIPS_DEBUG("bnever (NOP)");
2599 case OPC_BLTZAL: /* 0 < 0 */
2600 tcg_gen_movi_tl(t0, ctx->pc + 8);
2601 gen_store_gpr(t0, 31);
2602 MIPS_DEBUG("bnever and link");
2604 case OPC_BLTZALL: /* 0 < 0 likely */
2605 tcg_gen_movi_tl(t0, ctx->pc + 8);
2606 gen_store_gpr(t0, 31);
2607 /* Skip the instruction in the delay slot */
2608 MIPS_DEBUG("bnever, link and skip");
2611 case OPC_BNEL: /* rx != rx likely */
2612 case OPC_BGTZL: /* 0 > 0 likely */
2613 case OPC_BLTZL: /* 0 < 0 likely */
2614 /* Skip the instruction in the delay slot */
2615 MIPS_DEBUG("bnever and skip");
2619 ctx->hflags |= MIPS_HFLAG_B;
2620 MIPS_DEBUG("j " TARGET_FMT_lx, btgt);
2624 ctx->hflags |= MIPS_HFLAG_B;
2625 MIPS_DEBUG("jal " TARGET_FMT_lx, btgt);
2628 ctx->hflags |= MIPS_HFLAG_BR;
2629 MIPS_DEBUG("jr %s", regnames[rs]);
2633 ctx->hflags |= MIPS_HFLAG_BR;
2634 MIPS_DEBUG("jalr %s, %s", regnames[rt], regnames[rs]);
2637 MIPS_INVAL("branch/jump");
2638 generate_exception(ctx, EXCP_RI);
2645 MIPS_DEBUG("beq %s, %s, " TARGET_FMT_lx,
2646 regnames[rs], regnames[rt], btgt);
2650 MIPS_DEBUG("beql %s, %s, " TARGET_FMT_lx,
2651 regnames[rs], regnames[rt], btgt);
2655 MIPS_DEBUG("bne %s, %s, " TARGET_FMT_lx,
2656 regnames[rs], regnames[rt], btgt);
2660 MIPS_DEBUG("bnel %s, %s, " TARGET_FMT_lx,
2661 regnames[rs], regnames[rt], btgt);
2665 MIPS_DEBUG("bgez %s, " TARGET_FMT_lx, regnames[rs], btgt);
2669 MIPS_DEBUG("bgezl %s, " TARGET_FMT_lx, regnames[rs], btgt);
2673 MIPS_DEBUG("bgezal %s, " TARGET_FMT_lx, regnames[rs], btgt);
2679 MIPS_DEBUG("bgezall %s, " TARGET_FMT_lx, regnames[rs], btgt);
2683 MIPS_DEBUG("bgtz %s, " TARGET_FMT_lx, regnames[rs], btgt);
2687 MIPS_DEBUG("bgtzl %s, " TARGET_FMT_lx, regnames[rs], btgt);
2691 MIPS_DEBUG("blez %s, " TARGET_FMT_lx, regnames[rs], btgt);
2695 MIPS_DEBUG("blezl %s, " TARGET_FMT_lx, regnames[rs], btgt);
2699 MIPS_DEBUG("bltz %s, " TARGET_FMT_lx, regnames[rs], btgt);
2703 MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx, regnames[rs], btgt);
2708 MIPS_DEBUG("bltzal %s, " TARGET_FMT_lx, regnames[rs], btgt);
2710 ctx->hflags |= MIPS_HFLAG_BC;
2711 tcg_gen_trunc_tl_i32(bcond, t0);
2716 MIPS_DEBUG("bltzall %s, " TARGET_FMT_lx, regnames[rs], btgt);
2718 ctx->hflags |= MIPS_HFLAG_BL;
2719 tcg_gen_trunc_tl_i32(bcond, t0);
2722 MIPS_INVAL("conditional branch/jump");
2723 generate_exception(ctx, EXCP_RI);
2727 MIPS_DEBUG("enter ds: link %d cond %02x target " TARGET_FMT_lx,
2728 blink, ctx->hflags, btgt);
2730 ctx->btarget = btgt;
2732 tcg_gen_movi_tl(t0, ctx->pc + 8);
2733 gen_store_gpr(t0, blink);
2741 /* special3 bitfield operations */
2742 static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt,
2743 int rs, int lsb, int msb)
2745 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
2746 TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);
2748 gen_load_gpr(t1, rs);
2753 tcg_gen_helper_1_1ii(do_ext, t0, t1, lsb, msb + 1);
2755 #if defined(TARGET_MIPS64)
2759 tcg_gen_helper_1_1ii(do_dext, t0, t1, lsb, msb + 1 + 32);
2764 tcg_gen_helper_1_1ii(do_dext, t0, t1, lsb + 32, msb + 1);
2769 tcg_gen_helper_1_1ii(do_dext, t0, t1, lsb, msb + 1);
2775 gen_load_gpr(t0, rt);
2776 tcg_gen_helper_1_2ii(do_ins, t0, t0, t1, lsb, msb - lsb + 1);
2778 #if defined(TARGET_MIPS64)
2782 gen_load_gpr(t0, rt);
2783 tcg_gen_helper_1_2ii(do_dins, t0, t0, t1, lsb, msb - lsb + 1 + 32);
2788 gen_load_gpr(t0, rt);
2789 tcg_gen_helper_1_2ii(do_dins, t0, t0, t1, lsb + 32, msb - lsb + 1);
2794 gen_load_gpr(t0, rt);
2795 tcg_gen_helper_1_2ii(do_dins, t0, t0, t1, lsb, msb - lsb + 1);
2800 MIPS_INVAL("bitops");
2801 generate_exception(ctx, EXCP_RI);
2806 gen_store_gpr(t0, rt);
2811 /* CP0 (MMU and control) */
2812 #ifndef CONFIG_USER_ONLY
2813 static inline void gen_mfc0_load32 (TCGv t, target_ulong off)
2815 TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
2817 tcg_gen_ld_i32(r_tmp, cpu_env, off);
2818 tcg_gen_ext_i32_tl(t, r_tmp);
2819 tcg_temp_free(r_tmp);
2822 static inline void gen_mfc0_load64 (TCGv t, target_ulong off)
2824 tcg_gen_ld_tl(t, cpu_env, off);
2825 tcg_gen_ext32s_tl(t, t);
2828 static inline void gen_mtc0_store32 (TCGv t, target_ulong off)
2830 TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
2832 tcg_gen_trunc_tl_i32(r_tmp, t);
2833 tcg_gen_st_i32(r_tmp, cpu_env, off);
2834 tcg_temp_free(r_tmp);
2837 static inline void gen_mtc0_store64 (TCGv t, target_ulong off)
2839 tcg_gen_ext32s_tl(t, t);
2840 tcg_gen_st_tl(t, cpu_env, off);
2843 static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int sel)
2845 const char *rn = "invalid";
2848 check_insn(env, ctx, ISA_MIPS32);
2854 gen_mfc0_load32(t0, offsetof(CPUState, CP0_Index));
2858 check_insn(env, ctx, ASE_MT);
2859 tcg_gen_helper_1_0(do_mfc0_mvpcontrol, t0);
2863 check_insn(env, ctx, ASE_MT);
2864 tcg_gen_helper_1_0(do_mfc0_mvpconf0, t0);
2868 check_insn(env, ctx, ASE_MT);
2869 tcg_gen_helper_1_0(do_mfc0_mvpconf1, t0);
2879 tcg_gen_helper_1_0(do_mfc0_random, t0);
2883 check_insn(env, ctx, ASE_MT);
2884 gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEControl));
2888 check_insn(env, ctx, ASE_MT);
2889 gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEConf0));
2893 check_insn(env, ctx, ASE_MT);
2894 gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEConf1));
2898 check_insn(env, ctx, ASE_MT);
2899 gen_mfc0_load64(t0, offsetof(CPUState, CP0_YQMask));
2903 check_insn(env, ctx, ASE_MT);
2904 gen_mfc0_load64(t0, offsetof(CPUState, CP0_VPESchedule));
2908 check_insn(env, ctx, ASE_MT);
2909 gen_mfc0_load64(t0, offsetof(CPUState, CP0_VPEScheFBack));
2910 rn = "VPEScheFBack";
2913 check_insn(env, ctx, ASE_MT);
2914 gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEOpt));
2924 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EntryLo0));
2925 tcg_gen_ext32s_tl(t0, t0);
2929 check_insn(env, ctx, ASE_MT);
2930 tcg_gen_helper_1_0(do_mfc0_tcstatus, t0);
2934 check_insn(env, ctx, ASE_MT);
2935 tcg_gen_helper_1_0(do_mfc0_tcbind, t0);
2939 check_insn(env, ctx, ASE_MT);
2940 tcg_gen_helper_1_0(do_mfc0_tcrestart, t0);
2944 check_insn(env, ctx, ASE_MT);
2945 tcg_gen_helper_1_0(do_mfc0_tchalt, t0);
2949 check_insn(env, ctx, ASE_MT);
2950 tcg_gen_helper_1_0(do_mfc0_tccontext, t0);
2954 check_insn(env, ctx, ASE_MT);
2955 tcg_gen_helper_1_0(do_mfc0_tcschedule, t0);
2959 check_insn(env, ctx, ASE_MT);
2960 tcg_gen_helper_1_0(do_mfc0_tcschefback, t0);
2970 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EntryLo1));
2971 tcg_gen_ext32s_tl(t0, t0);
2981 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_Context));
2982 tcg_gen_ext32s_tl(t0, t0);
2986 // tcg_gen_helper_1_0(do_mfc0_contextconfig, t0); /* SmartMIPS ASE */
2987 rn = "ContextConfig";
2996 gen_mfc0_load32(t0, offsetof(CPUState, CP0_PageMask));
3000 check_insn(env, ctx, ISA_MIPS32R2);
3001 gen_mfc0_load32(t0, offsetof(CPUState, CP0_PageGrain));
3011 gen_mfc0_load32(t0, offsetof(CPUState, CP0_Wired));
3015 check_insn(env, ctx, ISA_MIPS32R2);
3016 gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf0));
3020 check_insn(env, ctx, ISA_MIPS32R2);
3021 gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf1));
3025 check_insn(env, ctx, ISA_MIPS32R2);
3026 gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf2));
3030 check_insn(env, ctx, ISA_MIPS32R2);
3031 gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf3));
3035 check_insn(env, ctx, ISA_MIPS32R2);
3036 gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf4));
3046 check_insn(env, ctx, ISA_MIPS32R2);
3047 gen_mfc0_load32(t0, offsetof(CPUState, CP0_HWREna));
3057 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_BadVAddr));
3058 tcg_gen_ext32s_tl(t0, t0);
3068 /* Mark as an IO operation because we read the time. */
3071 tcg_gen_helper_1_0(do_mfc0_count, t0);
3074 ctx->bstate = BS_STOP;
3078 /* 6,7 are implementation dependent */
3086 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EntryHi));
3087 tcg_gen_ext32s_tl(t0, t0);
3097 gen_mfc0_load32(t0, offsetof(CPUState, CP0_Compare));
3100 /* 6,7 are implementation dependent */
3108 gen_mfc0_load32(t0, offsetof(CPUState, CP0_Status));
3112 check_insn(env, ctx, ISA_MIPS32R2);
3113 gen_mfc0_load32(t0, offsetof(CPUState, CP0_IntCtl));
3117 check_insn(env, ctx, ISA_MIPS32R2);
3118 gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSCtl));
3122 check_insn(env, ctx, ISA_MIPS32R2);
3123 gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSMap));
3133 gen_mfc0_load32(t0, offsetof(CPUState, CP0_Cause));
3143 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EPC));
3144 tcg_gen_ext32s_tl(t0, t0);
3154 gen_mfc0_load32(t0, offsetof(CPUState, CP0_PRid));
3158 check_insn(env, ctx, ISA_MIPS32R2);
3159 gen_mfc0_load32(t0, offsetof(CPUState, CP0_EBase));
3169 gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config0));
3173 gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config1));
3177 gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config2));
3181 gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config3));
3184 /* 4,5 are reserved */
3185 /* 6,7 are implementation dependent */
3187 gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config6));
3191 gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config7));
3201 tcg_gen_helper_1_0(do_mfc0_lladdr, t0);
3211 tcg_gen_helper_1_i(do_mfc0_watchlo, t0, sel);
3221 tcg_gen_helper_1_i(do_mfc0_watchhi, t0, sel);
3231 #if defined(TARGET_MIPS64)
3232 check_insn(env, ctx, ISA_MIPS3);
3233 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_XContext));
3234 tcg_gen_ext32s_tl(t0, t0);
3243 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3246 gen_mfc0_load32(t0, offsetof(CPUState, CP0_Framemask));
3255 rn = "'Diagnostic"; /* implementation dependent */
3260 tcg_gen_helper_1_0(do_mfc0_debug, t0); /* EJTAG support */
3264 // tcg_gen_helper_1_0(do_mfc0_tracecontrol, t0); /* PDtrace support */
3265 rn = "TraceControl";
3268 // tcg_gen_helper_1_0(do_mfc0_tracecontrol2, t0); /* PDtrace support */
3269 rn = "TraceControl2";
3272 // tcg_gen_helper_1_0(do_mfc0_usertracedata, t0); /* PDtrace support */
3273 rn = "UserTraceData";
3276 // tcg_gen_helper_1_0(do_mfc0_tracebpc, t0); /* PDtrace support */
3287 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_DEPC));
3288 tcg_gen_ext32s_tl(t0, t0);
3298 gen_mfc0_load32(t0, offsetof(CPUState, CP0_Performance0));
3299 rn = "Performance0";
3302 // tcg_gen_helper_1_0(do_mfc0_performance1, t0);
3303 rn = "Performance1";
3306 // tcg_gen_helper_1_0(do_mfc0_performance2, t0);
3307 rn = "Performance2";
3310 // tcg_gen_helper_1_0(do_mfc0_performance3, t0);
3311 rn = "Performance3";
3314 // tcg_gen_helper_1_0(do_mfc0_performance4, t0);
3315 rn = "Performance4";
3318 // tcg_gen_helper_1_0(do_mfc0_performance5, t0);
3319 rn = "Performance5";
3322 // tcg_gen_helper_1_0(do_mfc0_performance6, t0);
3323 rn = "Performance6";
3326 // tcg_gen_helper_1_0(do_mfc0_performance7, t0);
3327 rn = "Performance7";
3352 gen_mfc0_load32(t0, offsetof(CPUState, CP0_TagLo));
3359 gen_mfc0_load32(t0, offsetof(CPUState, CP0_DataLo));
3372 gen_mfc0_load32(t0, offsetof(CPUState, CP0_TagHi));
3379 gen_mfc0_load32(t0, offsetof(CPUState, CP0_DataHi));
3389 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
3390 tcg_gen_ext32s_tl(t0, t0);
3401 gen_mfc0_load32(t0, offsetof(CPUState, CP0_DESAVE));
3411 #if defined MIPS_DEBUG_DISAS
3412 if (loglevel & CPU_LOG_TB_IN_ASM) {
3413 fprintf(logfile, "mfc0 %s (reg %d sel %d)\n",
3420 #if defined MIPS_DEBUG_DISAS
3421 if (loglevel & CPU_LOG_TB_IN_ASM) {
3422 fprintf(logfile, "mfc0 %s (reg %d sel %d)\n",
3426 generate_exception(ctx, EXCP_RI);
3429 static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int sel)
3431 const char *rn = "invalid";
3434 check_insn(env, ctx, ISA_MIPS32);
3443 tcg_gen_helper_0_1(do_mtc0_index, t0);
3447 check_insn(env, ctx, ASE_MT);
3448 tcg_gen_helper_0_1(do_mtc0_mvpcontrol, t0);
3452 check_insn(env, ctx, ASE_MT);
3457 check_insn(env, ctx, ASE_MT);
3472 check_insn(env, ctx, ASE_MT);
3473 tcg_gen_helper_0_1(do_mtc0_vpecontrol, t0);
3477 check_insn(env, ctx, ASE_MT);
3478 tcg_gen_helper_0_1(do_mtc0_vpeconf0, t0);
3482 check_insn(env, ctx, ASE_MT);
3483 tcg_gen_helper_0_1(do_mtc0_vpeconf1, t0);
3487 check_insn(env, ctx, ASE_MT);
3488 tcg_gen_helper_0_1(do_mtc0_yqmask, t0);
3492 check_insn(env, ctx, ASE_MT);
3493 gen_mtc0_store64(t0, offsetof(CPUState, CP0_VPESchedule));
3497 check_insn(env, ctx, ASE_MT);
3498 gen_mtc0_store64(t0, offsetof(CPUState, CP0_VPEScheFBack));
3499 rn = "VPEScheFBack";
3502 check_insn(env, ctx, ASE_MT);
3503 tcg_gen_helper_0_1(do_mtc0_vpeopt, t0);
3513 tcg_gen_helper_0_1(do_mtc0_entrylo0, t0);
3517 check_insn(env, ctx, ASE_MT);
3518 tcg_gen_helper_0_1(do_mtc0_tcstatus, t0);
3522 check_insn(env, ctx, ASE_MT);
3523 tcg_gen_helper_0_1(do_mtc0_tcbind, t0);
3527 check_insn(env, ctx, ASE_MT);
3528 tcg_gen_helper_0_1(do_mtc0_tcrestart, t0);
3532 check_insn(env, ctx, ASE_MT);
3533 tcg_gen_helper_0_1(do_mtc0_tchalt, t0);
3537 check_insn(env, ctx, ASE_MT);
3538 tcg_gen_helper_0_1(do_mtc0_tccontext, t0);
3542 check_insn(env, ctx, ASE_MT);
3543 tcg_gen_helper_0_1(do_mtc0_tcschedule, t0);
3547 check_insn(env, ctx, ASE_MT);
3548 tcg_gen_helper_0_1(do_mtc0_tcschefback, t0);
3558 tcg_gen_helper_0_1(do_mtc0_entrylo1, t0);
3568 tcg_gen_helper_0_1(do_mtc0_context, t0);
3572 // tcg_gen_helper_0_1(do_mtc0_contextconfig, t0); /* SmartMIPS ASE */
3573 rn = "ContextConfig";
3582 tcg_gen_helper_0_1(do_mtc0_pagemask, t0);
3586 check_insn(env, ctx, ISA_MIPS32R2);
3587 tcg_gen_helper_0_1(do_mtc0_pagegrain, t0);
3597 tcg_gen_helper_0_1(do_mtc0_wired, t0);
3601 check_insn(env, ctx, ISA_MIPS32R2);
3602 tcg_gen_helper_0_1(do_mtc0_srsconf0, t0);
3606 check_insn(env, ctx, ISA_MIPS32R2);
3607 tcg_gen_helper_0_1(do_mtc0_srsconf1, t0);
3611 check_insn(env, ctx, ISA_MIPS32R2);
3612 tcg_gen_helper_0_1(do_mtc0_srsconf2, t0);
3616 check_insn(env, ctx, ISA_MIPS32R2);
3617 tcg_gen_helper_0_1(do_mtc0_srsconf3, t0);
3621 check_insn(env, ctx, ISA_MIPS32R2);
3622 tcg_gen_helper_0_1(do_mtc0_srsconf4, t0);
3632 check_insn(env, ctx, ISA_MIPS32R2);
3633 tcg_gen_helper_0_1(do_mtc0_hwrena, t0);
3647 tcg_gen_helper_0_1(do_mtc0_count, t0);
3650 /* 6,7 are implementation dependent */
3654 /* Stop translation as we may have switched the execution mode */
3655 ctx->bstate = BS_STOP;
3660 tcg_gen_helper_0_1(do_mtc0_entryhi, t0);
3670 tcg_gen_helper_0_1(do_mtc0_compare, t0);
3673 /* 6,7 are implementation dependent */
3677 /* Stop translation as we may have switched the execution mode */
3678 ctx->bstate = BS_STOP;
3683 tcg_gen_helper_0_1(do_mtc0_status, t0);
3684 /* BS_STOP isn't good enough here, hflags may have changed. */
3685 gen_save_pc(ctx->pc + 4);
3686 ctx->bstate = BS_EXCP;
3690 check_insn(env, ctx, ISA_MIPS32R2);
3691 tcg_gen_helper_0_1(do_mtc0_intctl, t0);
3692 /* Stop translation as we may have switched the execution mode */
3693 ctx->bstate = BS_STOP;
3697 check_insn(env, ctx, ISA_MIPS32R2);
3698 tcg_gen_helper_0_1(do_mtc0_srsctl, t0);
3699 /* Stop translation as we may have switched the execution mode */
3700 ctx->bstate = BS_STOP;
3704 check_insn(env, ctx, ISA_MIPS32R2);
3705 gen_mtc0_store32(t0, offsetof(CPUState, CP0_SRSMap));
3706 /* Stop translation as we may have switched the execution mode */
3707 ctx->bstate = BS_STOP;
3717 tcg_gen_helper_0_1(do_mtc0_cause, t0);
3723 /* Stop translation as we may have switched the execution mode */
3724 ctx->bstate = BS_STOP;
3729 gen_mtc0_store64(t0, offsetof(CPUState, CP0_EPC));
3743 check_insn(env, ctx, ISA_MIPS32R2);
3744 tcg_gen_helper_0_1(do_mtc0_ebase, t0);
3754 tcg_gen_helper_0_1(do_mtc0_config0, t0);
3756 /* Stop translation as we may have switched the execution mode */
3757 ctx->bstate = BS_STOP;
3760 /* ignored, read only */
3764 tcg_gen_helper_0_1(do_mtc0_config2, t0);
3766 /* Stop translation as we may have switched the execution mode */
3767 ctx->bstate = BS_STOP;
3770 /* ignored, read only */
3773 /* 4,5 are reserved */
3774 /* 6,7 are implementation dependent */
3784 rn = "Invalid config selector";
3801 tcg_gen_helper_0_1i(do_mtc0_watchlo, t0, sel);
3811 tcg_gen_helper_0_1i(do_mtc0_watchhi, t0, sel);
3821 #if defined(TARGET_MIPS64)
3822 check_insn(env, ctx, ISA_MIPS3);
3823 tcg_gen_helper_0_1(do_mtc0_xcontext, t0);
3832 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3835 tcg_gen_helper_0_1(do_mtc0_framemask, t0);
3844 rn = "Diagnostic"; /* implementation dependent */
3849 tcg_gen_helper_0_1(do_mtc0_debug, t0); /* EJTAG support */
3850 /* BS_STOP isn't good enough here, hflags may have changed. */
3851 gen_save_pc(ctx->pc + 4);
3852 ctx->bstate = BS_EXCP;
3856 // tcg_gen_helper_0_1(do_mtc0_tracecontrol, t0); /* PDtrace support */
3857 rn = "TraceControl";
3858 /* Stop translation as we may have switched the execution mode */
3859 ctx->bstate = BS_STOP;
3862 // tcg_gen_helper_0_1(do_mtc0_tracecontrol2, t0); /* PDtrace support */
3863 rn = "TraceControl2";
3864 /* Stop translation as we may have switched the execution mode */
3865 ctx->bstate = BS_STOP;
3868 /* Stop translation as we may have switched the execution mode */
3869 ctx->bstate = BS_STOP;
3870 // tcg_gen_helper_0_1(do_mtc0_usertracedata, t0); /* PDtrace support */
3871 rn = "UserTraceData";
3872 /* Stop translation as we may have switched the execution mode */
3873 ctx->bstate = BS_STOP;
3876 // tcg_gen_helper_0_1(do_mtc0_tracebpc, t0); /* PDtrace support */
3877 /* Stop translation as we may have switched the execution mode */
3878 ctx->bstate = BS_STOP;
3889 gen_mtc0_store64(t0, offsetof(CPUState, CP0_DEPC));
3899 tcg_gen_helper_0_1(do_mtc0_performance0, t0);
3900 rn = "Performance0";
3903 // tcg_gen_helper_0_1(do_mtc0_performance1, t0);
3904 rn = "Performance1";
3907 // tcg_gen_helper_0_1(do_mtc0_performance2, t0);
3908 rn = "Performance2";
3911 // tcg_gen_helper_0_1(do_mtc0_performance3, t0);
3912 rn = "Performance3";
3915 // tcg_gen_helper_0_1(do_mtc0_performance4, t0);
3916 rn = "Performance4";
3919 // tcg_gen_helper_0_1(do_mtc0_performance5, t0);
3920 rn = "Performance5";
3923 // tcg_gen_helper_0_1(do_mtc0_performance6, t0);
3924 rn = "Performance6";
3927 // tcg_gen_helper_0_1(do_mtc0_performance7, t0);
3928 rn = "Performance7";
3954 tcg_gen_helper_0_1(do_mtc0_taglo, t0);
3961 tcg_gen_helper_0_1(do_mtc0_datalo, t0);
3974 tcg_gen_helper_0_1(do_mtc0_taghi, t0);
3981 tcg_gen_helper_0_1(do_mtc0_datahi, t0);
3992 gen_mtc0_store64(t0, offsetof(CPUState, CP0_ErrorEPC));
4003 gen_mtc0_store32(t0, offsetof(CPUState, CP0_DESAVE));
4009 /* Stop translation as we may have switched the execution mode */
4010 ctx->bstate = BS_STOP;
4015 #if defined MIPS_DEBUG_DISAS
4016 if (loglevel & CPU_LOG_TB_IN_ASM) {
4017 fprintf(logfile, "mtc0 %s (reg %d sel %d)\n",
4021 /* For simplicity assume that all writes can cause interrupts. */
4024 ctx->bstate = BS_STOP;
4029 #if defined MIPS_DEBUG_DISAS
4030 if (loglevel & CPU_LOG_TB_IN_ASM) {
4031 fprintf(logfile, "mtc0 %s (reg %d sel %d)\n",
4035 generate_exception(ctx, EXCP_RI);
4038 #if defined(TARGET_MIPS64)
4039 static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int sel)
4041 const char *rn = "invalid";
4044 check_insn(env, ctx, ISA_MIPS64);
4050 gen_mfc0_load32(t0, offsetof(CPUState, CP0_Index));
4054 check_insn(env, ctx, ASE_MT);
4055 tcg_gen_helper_1_0(do_mfc0_mvpcontrol, t0);
4059 check_insn(env, ctx, ASE_MT);
4060 tcg_gen_helper_1_0(do_mfc0_mvpconf0, t0);
4064 check_insn(env, ctx, ASE_MT);
4065 tcg_gen_helper_1_0(do_mfc0_mvpconf1, t0);
4075 tcg_gen_helper_1_0(do_mfc0_random, t0);
4079 check_insn(env, ctx, ASE_MT);
4080 gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEControl));
4084 check_insn(env, ctx, ASE_MT);
4085 gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEConf0));
4089 check_insn(env, ctx, ASE_MT);
4090 gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEConf1));
4094 check_insn(env, ctx, ASE_MT);
4095 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_YQMask));
4099 check_insn(env, ctx, ASE_MT);
4100 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_VPESchedule));
4104 check_insn(env, ctx, ASE_MT);
4105 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_VPEScheFBack));
4106 rn = "VPEScheFBack";
4109 check_insn(env, ctx, ASE_MT);
4110 gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEOpt));
4120 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EntryLo0));
4124 check_insn(env, ctx, ASE_MT);
4125 tcg_gen_helper_1_0(do_mfc0_tcstatus, t0);
4129 check_insn(env, ctx, ASE_MT);
4130 tcg_gen_helper_1_0(do_mfc0_tcbind, t0);
4134 check_insn(env, ctx, ASE_MT);
4135 tcg_gen_helper_1_0(do_dmfc0_tcrestart, t0);
4139 check_insn(env, ctx, ASE_MT);
4140 tcg_gen_helper_1_0(do_dmfc0_tchalt, t0);
4144 check_insn(env, ctx, ASE_MT);
4145 tcg_gen_helper_1_0(do_dmfc0_tccontext, t0);
4149 check_insn(env, ctx, ASE_MT);
4150 tcg_gen_helper_1_0(do_dmfc0_tcschedule, t0);
4154 check_insn(env, ctx, ASE_MT);
4155 tcg_gen_helper_1_0(do_dmfc0_tcschefback, t0);
4165 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EntryLo1));
4175 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_Context));
4179 // tcg_gen_helper_1_0(do_dmfc0_contextconfig, t0); /* SmartMIPS ASE */
4180 rn = "ContextConfig";
4189 gen_mfc0_load32(t0, offsetof(CPUState, CP0_PageMask));
4193 check_insn(env, ctx, ISA_MIPS32R2);
4194 gen_mfc0_load32(t0, offsetof(CPUState, CP0_PageGrain));
4204 gen_mfc0_load32(t0, offsetof(CPUState, CP0_Wired));
4208 check_insn(env, ctx, ISA_MIPS32R2);
4209 gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf0));
4213 check_insn(env, ctx, ISA_MIPS32R2);
4214 gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf1));
4218 check_insn(env, ctx, ISA_MIPS32R2);
4219 gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf2));
4223 check_insn(env, ctx, ISA_MIPS32R2);
4224 gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf3));
4228 check_insn(env, ctx, ISA_MIPS32R2);
4229 gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf4));
4239 check_insn(env, ctx, ISA_MIPS32R2);
4240 gen_mfc0_load32(t0, offsetof(CPUState, CP0_HWREna));
4250 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_BadVAddr));
4260 /* Mark as an IO operation because we read the time. */
4263 tcg_gen_helper_1_0(do_mfc0_count, t0);
4266 ctx->bstate = BS_STOP;
4270 /* 6,7 are implementation dependent */
4278 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EntryHi));
4288 gen_mfc0_load32(t0, offsetof(CPUState, CP0_Compare));
4291 /* 6,7 are implementation dependent */
4299 gen_mfc0_load32(t0, offsetof(CPUState, CP0_Status));
4303 check_insn(env, ctx, ISA_MIPS32R2);
4304 gen_mfc0_load32(t0, offsetof(CPUState, CP0_IntCtl));
4308 check_insn(env, ctx, ISA_MIPS32R2);
4309 gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSCtl));
4313 check_insn(env, ctx, ISA_MIPS32R2);
4314 gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSMap));
4324 gen_mfc0_load32(t0, offsetof(CPUState, CP0_Cause));
4334 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EPC));
4344 gen_mfc0_load32(t0, offsetof(CPUState, CP0_PRid));
4348 check_insn(env, ctx, ISA_MIPS32R2);
4349 gen_mfc0_load32(t0, offsetof(CPUState, CP0_EBase));
4359 gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config0));
4363 gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config1));
4367 gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config2));
4371 gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config3));
4374 /* 6,7 are implementation dependent */
4376 gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config6));
4380 gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config7));
4390 tcg_gen_helper_1_0(do_dmfc0_lladdr, t0);
4400 tcg_gen_helper_1_i(do_dmfc0_watchlo, t0, sel);
4410 tcg_gen_helper_1_i(do_mfc0_watchhi, t0, sel);
4420 check_insn(env, ctx, ISA_MIPS3);
4421 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_XContext));
4429 /* Officially reserved, but sel 0 is used for R1x000 framemask */
4432 gen_mfc0_load32(t0, offsetof(CPUState, CP0_Framemask));
4441 rn = "'Diagnostic"; /* implementation dependent */
4446 tcg_gen_helper_1_0(do_mfc0_debug, t0); /* EJTAG support */
4450 // tcg_gen_helper_1_0(do_dmfc0_tracecontrol, t0); /* PDtrace support */
4451 rn = "TraceControl";
4454 // tcg_gen_helper_1_0(do_dmfc0_tracecontrol2, t0); /* PDtrace support */
4455 rn = "TraceControl2";
4458 // tcg_gen_helper_1_0(do_dmfc0_usertracedata, t0); /* PDtrace support */
4459 rn = "UserTraceData";
4462 // tcg_gen_helper_1_0(do_dmfc0_tracebpc, t0); /* PDtrace support */
4473 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_DEPC));
4483 gen_mfc0_load32(t0, offsetof(CPUState, CP0_Performance0));
4484 rn = "Performance0";
4487 // tcg_gen_helper_1_0(do_dmfc0_performance1, t0);
4488 rn = "Performance1";
4491 // tcg_gen_helper_1_0(do_dmfc0_performance2, t0);
4492 rn = "Performance2";
4495 // tcg_gen_helper_1_0(do_dmfc0_performance3, t0);
4496 rn = "Performance3";
4499 // tcg_gen_helper_1_0(do_dmfc0_performance4, t0);
4500 rn = "Performance4";
4503 // tcg_gen_helper_1_0(do_dmfc0_performance5, t0);
4504 rn = "Performance5";
4507 // tcg_gen_helper_1_0(do_dmfc0_performance6, t0);
4508 rn = "Performance6";
4511 // tcg_gen_helper_1_0(do_dmfc0_performance7, t0);
4512 rn = "Performance7";
4537 gen_mfc0_load32(t0, offsetof(CPUState, CP0_TagLo));
4544 gen_mfc0_load32(t0, offsetof(CPUState, CP0_DataLo));
4557 gen_mfc0_load32(t0, offsetof(CPUState, CP0_TagHi));
4564 gen_mfc0_load32(t0, offsetof(CPUState, CP0_DataHi));
4574 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
4585 gen_mfc0_load32(t0, offsetof(CPUState, CP0_DESAVE));
4595 #if defined MIPS_DEBUG_DISAS
4596 if (loglevel & CPU_LOG_TB_IN_ASM) {
4597 fprintf(logfile, "dmfc0 %s (reg %d sel %d)\n",
4604 #if defined MIPS_DEBUG_DISAS
4605 if (loglevel & CPU_LOG_TB_IN_ASM) {
4606 fprintf(logfile, "dmfc0 %s (reg %d sel %d)\n",
4610 generate_exception(ctx, EXCP_RI);
4613 static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int sel)
4615 const char *rn = "invalid";
4618 check_insn(env, ctx, ISA_MIPS64);
4627 tcg_gen_helper_0_1(do_mtc0_index, t0);
4631 check_insn(env, ctx, ASE_MT);
4632 tcg_gen_helper_0_1(do_mtc0_mvpcontrol, t0);
4636 check_insn(env, ctx, ASE_MT);
4641 check_insn(env, ctx, ASE_MT);
4656 check_insn(env, ctx, ASE_MT);
4657 tcg_gen_helper_0_1(do_mtc0_vpecontrol, t0);
4661 check_insn(env, ctx, ASE_MT);
4662 tcg_gen_helper_0_1(do_mtc0_vpeconf0, t0);
4666 check_insn(env, ctx, ASE_MT);
4667 tcg_gen_helper_0_1(do_mtc0_vpeconf1, t0);
4671 check_insn(env, ctx, ASE_MT);
4672 tcg_gen_helper_0_1(do_mtc0_yqmask, t0);
4676 check_insn(env, ctx, ASE_MT);
4677 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_VPESchedule));
4681 check_insn(env, ctx, ASE_MT);
4682 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_VPEScheFBack));
4683 rn = "VPEScheFBack";
4686 check_insn(env, ctx, ASE_MT);
4687 tcg_gen_helper_0_1(do_mtc0_vpeopt, t0);
4697 tcg_gen_helper_0_1(do_mtc0_entrylo0, t0);
4701 check_insn(env, ctx, ASE_MT);
4702 tcg_gen_helper_0_1(do_mtc0_tcstatus, t0);
4706 check_insn(env, ctx, ASE_MT);
4707 tcg_gen_helper_0_1(do_mtc0_tcbind, t0);
4711 check_insn(env, ctx, ASE_MT);
4712 tcg_gen_helper_0_1(do_mtc0_tcrestart, t0);
4716 check_insn(env, ctx, ASE_MT);
4717 tcg_gen_helper_0_1(do_mtc0_tchalt, t0);
4721 check_insn(env, ctx, ASE_MT);
4722 tcg_gen_helper_0_1(do_mtc0_tccontext, t0);
4726 check_insn(env, ctx, ASE_MT);
4727 tcg_gen_helper_0_1(do_mtc0_tcschedule, t0);
4731 check_insn(env, ctx, ASE_MT);
4732 tcg_gen_helper_0_1(do_mtc0_tcschefback, t0);
4742 tcg_gen_helper_0_1(do_mtc0_entrylo1, t0);
4752 tcg_gen_helper_0_1(do_mtc0_context, t0);
4756 // tcg_gen_helper_0_1(do_mtc0_contextconfig, t0); /* SmartMIPS ASE */
4757 rn = "ContextConfig";
4766 tcg_gen_helper_0_1(do_mtc0_pagemask, t0);
4770 check_insn(env, ctx, ISA_MIPS32R2);
4771 tcg_gen_helper_0_1(do_mtc0_pagegrain, t0);
4781 tcg_gen_helper_0_1(do_mtc0_wired, t0);
4785 check_insn(env, ctx, ISA_MIPS32R2);
4786 tcg_gen_helper_0_1(do_mtc0_srsconf0, t0);
4790 check_insn(env, ctx, ISA_MIPS32R2);
4791 tcg_gen_helper_0_1(do_mtc0_srsconf1, t0);
4795 check_insn(env, ctx, ISA_MIPS32R2);
4796 tcg_gen_helper_0_1(do_mtc0_srsconf2, t0);
4800 check_insn(env, ctx, ISA_MIPS32R2);
4801 tcg_gen_helper_0_1(do_mtc0_srsconf3, t0);
4805 check_insn(env, ctx, ISA_MIPS32R2);
4806 tcg_gen_helper_0_1(do_mtc0_srsconf4, t0);
4816 check_insn(env, ctx, ISA_MIPS32R2);
4817 tcg_gen_helper_0_1(do_mtc0_hwrena, t0);
4831 tcg_gen_helper_0_1(do_mtc0_count, t0);
4834 /* 6,7 are implementation dependent */
4838 /* Stop translation as we may have switched the execution mode */
4839 ctx->bstate = BS_STOP;
4844 tcg_gen_helper_0_1(do_mtc0_entryhi, t0);
4854 tcg_gen_helper_0_1(do_mtc0_compare, t0);
4857 /* 6,7 are implementation dependent */
4861 /* Stop translation as we may have switched the execution mode */
4862 ctx->bstate = BS_STOP;
4867 tcg_gen_helper_0_1(do_mtc0_status, t0);
4868 /* BS_STOP isn't good enough here, hflags may have changed. */
4869 gen_save_pc(ctx->pc + 4);
4870 ctx->bstate = BS_EXCP;
4874 check_insn(env, ctx, ISA_MIPS32R2);
4875 tcg_gen_helper_0_1(do_mtc0_intctl, t0);
4876 /* Stop translation as we may have switched the execution mode */
4877 ctx->bstate = BS_STOP;
4881 check_insn(env, ctx, ISA_MIPS32R2);
4882 tcg_gen_helper_0_1(do_mtc0_srsctl, t0);
4883 /* Stop translation as we may have switched the execution mode */
4884 ctx->bstate = BS_STOP;
4888 check_insn(env, ctx, ISA_MIPS32R2);
4889 gen_mtc0_store32(t0, offsetof(CPUState, CP0_SRSMap));
4890 /* Stop translation as we may have switched the execution mode */
4891 ctx->bstate = BS_STOP;
4901 tcg_gen_helper_0_1(do_mtc0_cause, t0);
4907 /* Stop translation as we may have switched the execution mode */
4908 ctx->bstate = BS_STOP;
4913 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_EPC));
4927 check_insn(env, ctx, ISA_MIPS32R2);
4928 tcg_gen_helper_0_1(do_mtc0_ebase, t0);
4938 tcg_gen_helper_0_1(do_mtc0_config0, t0);
4940 /* Stop translation as we may have switched the execution mode */
4941 ctx->bstate = BS_STOP;
4948 tcg_gen_helper_0_1(do_mtc0_config2, t0);
4950 /* Stop translation as we may have switched the execution mode */
4951 ctx->bstate = BS_STOP;
4957 /* 6,7 are implementation dependent */
4959 rn = "Invalid config selector";
4976 tcg_gen_helper_0_1i(do_mtc0_watchlo, t0, sel);
4986 tcg_gen_helper_0_1i(do_mtc0_watchhi, t0, sel);
4996 check_insn(env, ctx, ISA_MIPS3);
4997 tcg_gen_helper_0_1(do_mtc0_xcontext, t0);
5005 /* Officially reserved, but sel 0 is used for R1x000 framemask */
5008 tcg_gen_helper_0_1(do_mtc0_framemask, t0);
5017 rn = "Diagnostic"; /* implementation dependent */
5022 tcg_gen_helper_0_1(do_mtc0_debug, t0); /* EJTAG support */
5023 /* BS_STOP isn't good enough here, hflags may have changed. */
5024 gen_save_pc(ctx->pc + 4);
5025 ctx->bstate = BS_EXCP;
5029 // tcg_gen_helper_0_1(do_mtc0_tracecontrol, t0); /* PDtrace support */
5030 /* Stop translation as we may have switched the execution mode */
5031 ctx->bstate = BS_STOP;
5032 rn = "TraceControl";
5035 // tcg_gen_helper_0_1(do_mtc0_tracecontrol2, t0); /* PDtrace support */
5036 /* Stop translation as we may have switched the execution mode */
5037 ctx->bstate = BS_STOP;
5038 rn = "TraceControl2";
5041 // tcg_gen_helper_0_1(do_mtc0_usertracedata, t0); /* PDtrace support */
5042 /* Stop translation as we may have switched the execution mode */
5043 ctx->bstate = BS_STOP;
5044 rn = "UserTraceData";
5047 // tcg_gen_helper_0_1(do_mtc0_tracebpc, t0); /* PDtrace support */
5048 /* Stop translation as we may have switched the execution mode */
5049 ctx->bstate = BS_STOP;
5060 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_DEPC));
5070 tcg_gen_helper_0_1(do_mtc0_performance0, t0);
5071 rn = "Performance0";
5074 // tcg_gen_helper_0_1(do_mtc0_performance1, t0);
5075 rn = "Performance1";
5078 // tcg_gen_helper_0_1(do_mtc0_performance2, t0);
5079 rn = "Performance2";
5082 // tcg_gen_helper_0_1(do_mtc0_performance3, t0);
5083 rn = "Performance3";
5086 // tcg_gen_helper_0_1(do_mtc0_performance4, t0);
5087 rn = "Performance4";
5090 // tcg_gen_helper_0_1(do_mtc0_performance5, t0);
5091 rn = "Performance5";
5094 // tcg_gen_helper_0_1(do_mtc0_performance6, t0);
5095 rn = "Performance6";
5098 // tcg_gen_helper_0_1(do_mtc0_performance7, t0);
5099 rn = "Performance7";
5125 tcg_gen_helper_0_1(do_mtc0_taglo, t0);
5132 tcg_gen_helper_0_1(do_mtc0_datalo, t0);
5145 tcg_gen_helper_0_1(do_mtc0_taghi, t0);
5152 tcg_gen_helper_0_1(do_mtc0_datahi, t0);
5163 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
5174 gen_mtc0_store32(t0, offsetof(CPUState, CP0_DESAVE));
5180 /* Stop translation as we may have switched the execution mode */
5181 ctx->bstate = BS_STOP;
5186 #if defined MIPS_DEBUG_DISAS
5187 if (loglevel & CPU_LOG_TB_IN_ASM) {
5188 fprintf(logfile, "dmtc0 %s (reg %d sel %d)\n",
5193 /* For simplicity assume that all writes can cause interrupts. */
5196 ctx->bstate = BS_STOP;
5202 #if defined MIPS_DEBUG_DISAS
5203 if (loglevel & CPU_LOG_TB_IN_ASM) {
5204 fprintf(logfile, "dmtc0 %s (reg %d sel %d)\n",
5208 generate_exception(ctx, EXCP_RI);
5210 #endif /* TARGET_MIPS64 */
5212 static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, int rd,
5213 int u, int sel, int h)
5215 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
5216 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
5218 if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 &&
5219 ((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) !=
5220 (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE))))
5221 tcg_gen_movi_tl(t0, -1);
5222 else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
5223 (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC)))
5224 tcg_gen_movi_tl(t0, -1);
5230 tcg_gen_helper_1_1(do_mftc0_tcstatus, t0, t0);
5233 tcg_gen_helper_1_1(do_mftc0_tcbind, t0, t0);
5236 tcg_gen_helper_1_1(do_mftc0_tcrestart, t0, t0);
5239 tcg_gen_helper_1_1(do_mftc0_tchalt, t0, t0);
5242 tcg_gen_helper_1_1(do_mftc0_tccontext, t0, t0);
5245 tcg_gen_helper_1_1(do_mftc0_tcschedule, t0, t0);
5248 tcg_gen_helper_1_1(do_mftc0_tcschefback, t0, t0);
5251 gen_mfc0(env, ctx, t0, rt, sel);
5258 tcg_gen_helper_1_1(do_mftc0_entryhi, t0, t0);
5261 gen_mfc0(env, ctx, t0, rt, sel);
5267 tcg_gen_helper_1_1(do_mftc0_status, t0, t0);
5270 gen_mfc0(env, ctx, t0, rt, sel);
5276 tcg_gen_helper_1_1(do_mftc0_debug, t0, t0);
5279 gen_mfc0(env, ctx, t0, rt, sel);
5284 gen_mfc0(env, ctx, t0, rt, sel);
5286 } else switch (sel) {
5287 /* GPR registers. */
5289 tcg_gen_helper_1_1i(do_mftgpr, t0, t0, rt);
5291 /* Auxiliary CPU registers */
5295 tcg_gen_helper_1_1i(do_mftlo, t0, t0, 0);
5298 tcg_gen_helper_1_1i(do_mfthi, t0, t0, 0);
5301 tcg_gen_helper_1_1i(do_mftacx, t0, t0, 0);
5304 tcg_gen_helper_1_1i(do_mftlo, t0, t0, 1);
5307 tcg_gen_helper_1_1i(do_mfthi, t0, t0, 1);
5310 tcg_gen_helper_1_1i(do_mftacx, t0, t0, 1);
5313 tcg_gen_helper_1_1i(do_mftlo, t0, t0, 2);
5316 tcg_gen_helper_1_1i(do_mfthi, t0, t0, 2);
5319 tcg_gen_helper_1_1i(do_mftacx, t0, t0, 2);
5322 tcg_gen_helper_1_1i(do_mftlo, t0, t0, 3);
5325 tcg_gen_helper_1_1i(do_mfthi, t0, t0, 3);
5328 tcg_gen_helper_1_1i(do_mftacx, t0, t0, 3);
5331 tcg_gen_helper_1_1(do_mftdsp, t0, t0);
5337 /* Floating point (COP1). */
5339 /* XXX: For now we support only a single FPU context. */
5341 TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
5343 gen_load_fpr32(fp0, rt);
5344 tcg_gen_ext_i32_tl(t0, fp0);
5347 TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
5349 gen_load_fpr32h(fp0, rt);
5350 tcg_gen_ext_i32_tl(t0, fp0);
5355 /* XXX: For now we support only a single FPU context. */
5356 tcg_gen_helper_1_1i(do_cfc1, t0, t0, rt);
5358 /* COP2: Not implemented. */
5365 #if defined MIPS_DEBUG_DISAS
5366 if (loglevel & CPU_LOG_TB_IN_ASM) {
5367 fprintf(logfile, "mftr (reg %d u %d sel %d h %d)\n",
5371 gen_store_gpr(t0, rd);
5377 #if defined MIPS_DEBUG_DISAS
5378 if (loglevel & CPU_LOG_TB_IN_ASM) {
5379 fprintf(logfile, "mftr (reg %d u %d sel %d h %d)\n",
5383 generate_exception(ctx, EXCP_RI);
5386 static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, int rt,
5387 int u, int sel, int h)
5389 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
5390 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
5392 gen_load_gpr(t0, rt);
5393 if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 &&
5394 ((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) !=
5395 (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE))))
5397 else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
5398 (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC)))
5405 tcg_gen_helper_0_1(do_mttc0_tcstatus, t0);
5408 tcg_gen_helper_0_1(do_mttc0_tcbind, t0);
5411 tcg_gen_helper_0_1(do_mttc0_tcrestart, t0);
5414 tcg_gen_helper_0_1(do_mttc0_tchalt, t0);
5417 tcg_gen_helper_0_1(do_mttc0_tccontext, t0);
5420 tcg_gen_helper_0_1(do_mttc0_tcschedule, t0);
5423 tcg_gen_helper_0_1(do_mttc0_tcschefback, t0);
5426 gen_mtc0(env, ctx, t0, rd, sel);
5433 tcg_gen_helper_0_1(do_mttc0_entryhi, t0);
5436 gen_mtc0(env, ctx, t0, rd, sel);
5442 tcg_gen_helper_0_1(do_mttc0_status, t0);
5445 gen_mtc0(env, ctx, t0, rd, sel);
5451 tcg_gen_helper_0_1(do_mttc0_debug, t0);
5454 gen_mtc0(env, ctx, t0, rd, sel);
5459 gen_mtc0(env, ctx, t0, rd, sel);
5461 } else switch (sel) {
5462 /* GPR registers. */
5464 tcg_gen_helper_0_1i(do_mttgpr, t0, rd);
5466 /* Auxiliary CPU registers */
5470 tcg_gen_helper_0_1i(do_mttlo, t0, 0);
5473 tcg_gen_helper_0_1i(do_mtthi, t0, 0);
5476 tcg_gen_helper_0_1i(do_mttacx, t0, 0);
5479 tcg_gen_helper_0_1i(do_mttlo, t0, 1);
5482 tcg_gen_helper_0_1i(do_mtthi, t0, 1);
5485 tcg_gen_helper_0_1i(do_mttacx, t0, 1);
5488 tcg_gen_helper_0_1i(do_mttlo, t0, 2);
5491 tcg_gen_helper_0_1i(do_mtthi, t0, 2);
5494 tcg_gen_helper_0_1i(do_mttacx, t0, 2);
5497 tcg_gen_helper_0_1i(do_mttlo, t0, 3);
5500 tcg_gen_helper_0_1i(do_mtthi, t0, 3);
5503 tcg_gen_helper_0_1i(do_mttacx, t0, 3);
5506 tcg_gen_helper_0_1(do_mttdsp, t0);
5512 /* Floating point (COP1). */
5514 /* XXX: For now we support only a single FPU context. */
5516 TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
5518 tcg_gen_trunc_tl_i32(fp0, t0);
5519 gen_store_fpr32(fp0, rd);
5522 TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
5524 tcg_gen_trunc_tl_i32(fp0, t0);
5525 gen_store_fpr32h(fp0, rd);
5530 /* XXX: For now we support only a single FPU context. */
5531 tcg_gen_helper_0_1i(do_ctc1, t0, rd);
5533 /* COP2: Not implemented. */
5540 #if defined MIPS_DEBUG_DISAS
5541 if (loglevel & CPU_LOG_TB_IN_ASM) {
5542 fprintf(logfile, "mttr (reg %d u %d sel %d h %d)\n",
5551 #if defined MIPS_DEBUG_DISAS
5552 if (loglevel & CPU_LOG_TB_IN_ASM) {
5553 fprintf(logfile, "mttr (reg %d u %d sel %d h %d)\n",
5557 generate_exception(ctx, EXCP_RI);
5560 static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int rd)
5562 const char *opn = "ldst";
5571 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
5573 gen_mfc0(env, ctx, t0, rd, ctx->opcode & 0x7);
5574 gen_store_gpr(t0, rt);
5581 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
5583 gen_load_gpr(t0, rt);
5584 save_cpu_state(ctx, 1);
5585 gen_mtc0(env, ctx, t0, rd, ctx->opcode & 0x7);
5590 #if defined(TARGET_MIPS64)
5592 check_insn(env, ctx, ISA_MIPS3);
5598 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
5600 gen_dmfc0(env, ctx, t0, rd, ctx->opcode & 0x7);
5601 gen_store_gpr(t0, rt);
5607 check_insn(env, ctx, ISA_MIPS3);
5609 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
5611 gen_load_gpr(t0, rt);
5612 save_cpu_state(ctx, 1);
5613 gen_dmtc0(env, ctx, t0, rd, ctx->opcode & 0x7);
5620 check_insn(env, ctx, ASE_MT);
5625 gen_mftr(env, ctx, rt, rd, (ctx->opcode >> 5) & 1,
5626 ctx->opcode & 0x7, (ctx->opcode >> 4) & 1);
5630 check_insn(env, ctx, ASE_MT);
5631 gen_mttr(env, ctx, rd, rt, (ctx->opcode >> 5) & 1,
5632 ctx->opcode & 0x7, (ctx->opcode >> 4) & 1);
5637 if (!env->tlb->do_tlbwi)
5639 tcg_gen_helper_0_0(env->tlb->do_tlbwi);
5643 if (!env->tlb->do_tlbwr)
5645 tcg_gen_helper_0_0(env->tlb->do_tlbwr);
5649 if (!env->tlb->do_tlbp)
5651 tcg_gen_helper_0_0(env->tlb->do_tlbp);
5655 if (!env->tlb->do_tlbr)
5657 tcg_gen_helper_0_0(env->tlb->do_tlbr);
5661 check_insn(env, ctx, ISA_MIPS2);
5662 save_cpu_state(ctx, 1);
5663 tcg_gen_helper_0_0(do_eret);
5664 ctx->bstate = BS_EXCP;
5668 check_insn(env, ctx, ISA_MIPS32);
5669 if (!(ctx->hflags & MIPS_HFLAG_DM)) {
5671 generate_exception(ctx, EXCP_RI);
5673 save_cpu_state(ctx, 1);
5674 tcg_gen_helper_0_0(do_deret);
5675 ctx->bstate = BS_EXCP;
5680 check_insn(env, ctx, ISA_MIPS3 | ISA_MIPS32);
5681 /* If we get an exception, we want to restart at next instruction */
5683 save_cpu_state(ctx, 1);
5685 tcg_gen_helper_0_0(do_wait);
5686 ctx->bstate = BS_EXCP;
5691 generate_exception(ctx, EXCP_RI);
5694 MIPS_DEBUG("%s %s %d", opn, regnames[rt], rd);
5696 #endif /* !CONFIG_USER_ONLY */
5698 /* CP1 Branches (before delay slot) */
5699 static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,
5700 int32_t cc, int32_t offset)
5702 target_ulong btarget;
5703 const char *opn = "cp1 cond branch";
5704 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
5705 TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);
5708 check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32);
5710 btarget = ctx->pc + 4 + offset;
5715 int l1 = gen_new_label();
5716 int l2 = gen_new_label();
5717 TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
5719 get_fp_cond(r_tmp1);
5720 tcg_gen_ext_i32_tl(t0, r_tmp1);
5721 tcg_temp_free(r_tmp1);
5722 tcg_gen_not_tl(t0, t0);
5723 tcg_gen_movi_tl(t1, 0x1 << cc);
5724 tcg_gen_and_tl(t0, t0, t1);
5725 tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
5726 tcg_gen_movi_tl(t0, 0);
5729 tcg_gen_movi_tl(t0, 1);
5736 int l1 = gen_new_label();
5737 int l2 = gen_new_label();
5738 TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
5740 get_fp_cond(r_tmp1);
5741 tcg_gen_ext_i32_tl(t0, r_tmp1);
5742 tcg_temp_free(r_tmp1);
5743 tcg_gen_not_tl(t0, t0);
5744 tcg_gen_movi_tl(t1, 0x1 << cc);
5745 tcg_gen_and_tl(t0, t0, t1);
5746 tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
5747 tcg_gen_movi_tl(t0, 0);
5750 tcg_gen_movi_tl(t0, 1);
5757 int l1 = gen_new_label();
5758 int l2 = gen_new_label();
5759 TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
5761 get_fp_cond(r_tmp1);
5762 tcg_gen_ext_i32_tl(t0, r_tmp1);
5763 tcg_temp_free(r_tmp1);
5764 tcg_gen_movi_tl(t1, 0x1 << cc);
5765 tcg_gen_and_tl(t0, t0, t1);
5766 tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
5767 tcg_gen_movi_tl(t0, 0);
5770 tcg_gen_movi_tl(t0, 1);
5777 int l1 = gen_new_label();
5778 int l2 = gen_new_label();
5779 TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
5781 get_fp_cond(r_tmp1);
5782 tcg_gen_ext_i32_tl(t0, r_tmp1);
5783 tcg_temp_free(r_tmp1);
5784 tcg_gen_movi_tl(t1, 0x1 << cc);
5785 tcg_gen_and_tl(t0, t0, t1);
5786 tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
5787 tcg_gen_movi_tl(t0, 0);
5790 tcg_gen_movi_tl(t0, 1);
5795 ctx->hflags |= MIPS_HFLAG_BL;
5796 tcg_gen_trunc_tl_i32(bcond, t0);
5800 int l1 = gen_new_label();
5801 int l2 = gen_new_label();
5802 TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
5804 get_fp_cond(r_tmp1);
5805 tcg_gen_ext_i32_tl(t0, r_tmp1);
5806 tcg_temp_free(r_tmp1);
5807 tcg_gen_not_tl(t0, t0);
5808 tcg_gen_movi_tl(t1, 0x3 << cc);
5809 tcg_gen_and_tl(t0, t0, t1);
5810 tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
5811 tcg_gen_movi_tl(t0, 0);
5814 tcg_gen_movi_tl(t0, 1);
5821 int l1 = gen_new_label();
5822 int l2 = gen_new_label();
5823 TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
5825 get_fp_cond(r_tmp1);
5826 tcg_gen_ext_i32_tl(t0, r_tmp1);
5827 tcg_temp_free(r_tmp1);
5828 tcg_gen_movi_tl(t1, 0x3 << cc);
5829 tcg_gen_and_tl(t0, t0, t1);
5830 tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
5831 tcg_gen_movi_tl(t0, 0);
5834 tcg_gen_movi_tl(t0, 1);
5841 int l1 = gen_new_label();
5842 int l2 = gen_new_label();
5843 TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
5845 get_fp_cond(r_tmp1);
5846 tcg_gen_ext_i32_tl(t0, r_tmp1);
5847 tcg_temp_free(r_tmp1);
5848 tcg_gen_not_tl(t0, t0);
5849 tcg_gen_movi_tl(t1, 0xf << cc);
5850 tcg_gen_and_tl(t0, t0, t1);
5851 tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
5852 tcg_gen_movi_tl(t0, 0);
5855 tcg_gen_movi_tl(t0, 1);
5862 int l1 = gen_new_label();
5863 int l2 = gen_new_label();
5864 TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I32);
5866 get_fp_cond(r_tmp1);
5867 tcg_gen_ext_i32_tl(t0, r_tmp1);
5868 tcg_temp_free(r_tmp1);
5869 tcg_gen_movi_tl(t1, 0xf << cc);
5870 tcg_gen_and_tl(t0, t0, t1);
5871 tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
5872 tcg_gen_movi_tl(t0, 0);
5875 tcg_gen_movi_tl(t0, 1);
5880 ctx->hflags |= MIPS_HFLAG_BC;
5881 tcg_gen_trunc_tl_i32(bcond, t0);
5885 generate_exception (ctx, EXCP_RI);
5888 MIPS_DEBUG("%s: cond %02x target " TARGET_FMT_lx, opn,
5889 ctx->hflags, btarget);
5890 ctx->btarget = btarget;
5897 /* Coprocessor 1 (FPU) */
5899 #define FOP(func, fmt) (((fmt) << 21) | (func))
5901 static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
5903 const char *opn = "cp1 move";
5904 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
5909 TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
5911 gen_load_fpr32(fp0, fs);
5912 tcg_gen_ext_i32_tl(t0, fp0);
5915 gen_store_gpr(t0, rt);
5919 gen_load_gpr(t0, rt);
5921 TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
5923 tcg_gen_trunc_tl_i32(fp0, t0);
5924 gen_store_fpr32(fp0, fs);
5930 tcg_gen_helper_1_i(do_cfc1, t0, fs);
5931 gen_store_gpr(t0, rt);
5935 gen_load_gpr(t0, rt);
5936 tcg_gen_helper_0_1i(do_ctc1, t0, fs);
5941 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
5943 gen_load_fpr64(ctx, fp0, fs);
5944 tcg_gen_mov_tl(t0, fp0);
5947 gen_store_gpr(t0, rt);
5951 gen_load_gpr(t0, rt);
5953 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
5955 tcg_gen_mov_tl(fp0, t0);
5956 gen_store_fpr64(ctx, fp0, fs);
5963 TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
5965 gen_load_fpr32h(fp0, fs);
5966 tcg_gen_ext_i32_tl(t0, fp0);
5969 gen_store_gpr(t0, rt);
5973 gen_load_gpr(t0, rt);
5975 TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
5977 tcg_gen_trunc_tl_i32(fp0, t0);
5978 gen_store_fpr32h(fp0, fs);
5985 generate_exception (ctx, EXCP_RI);
5988 MIPS_DEBUG("%s %s %s", opn, regnames[rt], fregnames[fs]);
5994 static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf)
5996 int l1 = gen_new_label();
5999 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
6000 TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);
6003 ccbit = 1 << (24 + cc);
6011 gen_load_gpr(t0, rd);
6012 gen_load_gpr(t1, rs);
6014 TCGv r_ptr = tcg_temp_new(TCG_TYPE_PTR);
6015 TCGv r_tmp = tcg_temp_local_new(TCG_TYPE_I32);
6017 tcg_gen_ld_ptr(r_ptr, cpu_env, offsetof(CPUState, fpu));
6018 tcg_gen_ld_i32(r_tmp, r_ptr, offsetof(CPUMIPSFPUContext, fcr31));
6019 tcg_temp_free(r_ptr);
6020 tcg_gen_andi_i32(r_tmp, r_tmp, ccbit);
6021 tcg_gen_brcondi_i32(cond, r_tmp, 0, l1);
6022 tcg_temp_free(r_tmp);
6024 tcg_gen_mov_tl(t0, t1);
6028 gen_store_gpr(t0, rd);
6032 static inline void gen_movcf_s (int fs, int fd, int cc, int tf)
6036 TCGv r_tmp1 = tcg_temp_local_new(TCG_TYPE_I32);
6037 TCGv fp0 = tcg_temp_local_new(TCG_TYPE_I32);
6038 TCGv fp1 = tcg_temp_local_new(TCG_TYPE_I32);
6039 int l1 = gen_new_label();
6042 ccbit = 1 << (24 + cc);
6051 gen_load_fpr32(fp0, fs);
6052 gen_load_fpr32(fp1, fd);
6053 tcg_gen_ld_i32(r_tmp1, current_fpu, offsetof(CPUMIPSFPUContext, fcr31));
6054 tcg_gen_andi_i32(r_tmp1, r_tmp1, ccbit);
6055 tcg_gen_brcondi_i32(cond, r_tmp1, 0, l1);
6056 tcg_gen_movi_i32(fp1, fp0);
6059 tcg_temp_free(r_tmp1);
6060 gen_store_fpr32(fp1, fd);
6064 static inline void gen_movcf_d (DisasContext *ctx, int fs, int fd, int cc, int tf)
6068 TCGv r_tmp1 = tcg_temp_local_new(TCG_TYPE_I32);
6069 TCGv fp0 = tcg_temp_local_new(TCG_TYPE_I64);
6070 TCGv fp1 = tcg_temp_local_new(TCG_TYPE_I64);
6071 int l1 = gen_new_label();
6074 ccbit = 1 << (24 + cc);
6083 gen_load_fpr64(ctx, fp0, fs);
6084 gen_load_fpr64(ctx, fp1, fd);
6085 tcg_gen_ld_i32(r_tmp1, current_fpu, offsetof(CPUMIPSFPUContext, fcr31));
6086 tcg_gen_andi_i32(r_tmp1, r_tmp1, ccbit);
6087 tcg_gen_brcondi_i32(cond, r_tmp1, 0, l1);
6088 tcg_gen_movi_i64(fp1, fp0);
6091 tcg_temp_free(r_tmp1);
6092 gen_store_fpr64(ctx, fp1, fd);
6096 static inline void gen_movcf_ps (int fs, int fd, int cc, int tf)
6099 TCGv r_tmp1 = tcg_temp_local_new(TCG_TYPE_I32);
6100 TCGv r_tmp2 = tcg_temp_local_new(TCG_TYPE_I32);
6101 TCGv fp0 = tcg_temp_local_new(TCG_TYPE_I32);
6102 TCGv fph0 = tcg_temp_local_new(TCG_TYPE_I32);
6103 TCGv fp1 = tcg_temp_local_new(TCG_TYPE_I32);
6104 TCGv fph1 = tcg_temp_local_new(TCG_TYPE_I32);
6105 int l1 = gen_new_label();
6106 int l2 = gen_new_label();
6113 gen_load_fpr32(fp0, fs);
6114 gen_load_fpr32h(fph0, fs);
6115 gen_load_fpr32(fp1, fd);
6116 gen_load_fpr32h(fph1, fd);
6117 get_fp_cond(r_tmp1);
6118 tcg_gen_shri_i32(r_tmp1, r_tmp1, cc);
6119 tcg_gen_andi_i32(r_tmp2, r_tmp1, 0x1);
6120 tcg_gen_brcondi_i32(cond, r_tmp2, 0, l1);
6121 tcg_gen_movi_i32(fp1, fp0);
6124 tcg_gen_andi_i32(r_tmp2, r_tmp1, 0x2);
6125 tcg_gen_brcondi_i32(cond, r_tmp2, 0, l2);
6126 tcg_gen_movi_i32(fph1, fph0);
6127 tcg_temp_free(fph0);
6129 tcg_temp_free(r_tmp1);
6130 tcg_temp_free(r_tmp2);
6131 gen_store_fpr32(fp1, fd);
6132 gen_store_fpr32h(fph1, fd);
6134 tcg_temp_free(fph1);
6138 static void gen_farith (DisasContext *ctx, uint32_t op1,
6139 int ft, int fs, int fd, int cc)
6141 const char *opn = "farith";
6142 const char *condnames[] = {
6160 const char *condnames_abs[] = {
6178 enum { BINOP, CMPOP, OTHEROP } optype = OTHEROP;
6179 uint32_t func = ctx->opcode & 0x3f;
6181 switch (ctx->opcode & FOP(0x3f, 0x1f)) {
6184 TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
6185 TCGv fp1 = tcg_temp_new(TCG_TYPE_I32);
6187 gen_load_fpr32(fp0, fs);
6188 gen_load_fpr32(fp1, ft);
6189 tcg_gen_helper_1_2(do_float_add_s, fp0, fp0, fp1);
6191 gen_store_fpr32(fp0, fd);
6199 TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
6200 TCGv fp1 = tcg_temp_new(TCG_TYPE_I32);
6202 gen_load_fpr32(fp0, fs);
6203 gen_load_fpr32(fp1, ft);
6204 tcg_gen_helper_1_2(do_float_sub_s, fp0, fp0, fp1);
6206 gen_store_fpr32(fp0, fd);
6214 TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
6215 TCGv fp1 = tcg_temp_new(TCG_TYPE_I32);
6217 gen_load_fpr32(fp0, fs);
6218 gen_load_fpr32(fp1, ft);
6219 tcg_gen_helper_1_2(do_float_mul_s, fp0, fp0, fp1);
6221 gen_store_fpr32(fp0, fd);
6229 TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
6230 TCGv fp1 = tcg_temp_new(TCG_TYPE_I32);
6232 gen_load_fpr32(fp0, fs);
6233 gen_load_fpr32(fp1, ft);
6234 tcg_gen_helper_1_2(do_float_div_s, fp0, fp0, fp1);
6236 gen_store_fpr32(fp0, fd);
6244 TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
6246 gen_load_fpr32(fp0, fs);
6247 tcg_gen_helper_1_1(do_float_sqrt_s, fp0, fp0);
6248 gen_store_fpr32(fp0, fd);
6255 TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
6257 gen_load_fpr32(fp0, fs);
6258 tcg_gen_helper_1_1(do_float_abs_s, fp0, fp0);
6259 gen_store_fpr32(fp0, fd);
6266 TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
6268 gen_load_fpr32(fp0, fs);
6269 gen_store_fpr32(fp0, fd);
6276 TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
6278 gen_load_fpr32(fp0, fs);
6279 tcg_gen_helper_1_1(do_float_chs_s, fp0, fp0);
6280 gen_store_fpr32(fp0, fd);
6286 check_cp1_64bitmode(ctx);
6288 TCGv fp32 = tcg_temp_new(TCG_TYPE_I32);
6289 TCGv fp64 = tcg_temp_new(TCG_TYPE_I64);
6291 gen_load_fpr32(fp32, fs);
6292 tcg_gen_helper_1_1(do_float_roundl_s, fp64, fp32);
6293 tcg_temp_free(fp32);
6294 gen_store_fpr64(ctx, fp64, fd);
6295 tcg_temp_free(fp64);
6300 check_cp1_64bitmode(ctx);
6302 TCGv fp32 = tcg_temp_new(TCG_TYPE_I32);
6303 TCGv fp64 = tcg_temp_new(TCG_TYPE_I64);
6305 gen_load_fpr32(fp32, fs);
6306 tcg_gen_helper_1_1(do_float_truncl_s, fp64, fp32);
6307 tcg_temp_free(fp32);
6308 gen_store_fpr64(ctx, fp64, fd);
6309 tcg_temp_free(fp64);
6314 check_cp1_64bitmode(ctx);
6316 TCGv fp32 = tcg_temp_new(TCG_TYPE_I32);
6317 TCGv fp64 = tcg_temp_new(TCG_TYPE_I64);
6319 gen_load_fpr32(fp32, fs);
6320 tcg_gen_helper_1_1(do_float_ceill_s, fp64, fp32);
6321 tcg_temp_free(fp32);
6322 gen_store_fpr64(ctx, fp64, fd);
6323 tcg_temp_free(fp64);
6328 check_cp1_64bitmode(ctx);
6330 TCGv fp32 = tcg_temp_new(TCG_TYPE_I32);
6331 TCGv fp64 = tcg_temp_new(TCG_TYPE_I64);
6333 gen_load_fpr32(fp32, fs);
6334 tcg_gen_helper_1_1(do_float_floorl_s, fp64, fp32);
6335 tcg_temp_free(fp32);
6336 gen_store_fpr64(ctx, fp64, fd);
6337 tcg_temp_free(fp64);
6343 TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
6345 gen_load_fpr32(fp0, fs);
6346 tcg_gen_helper_1_1(do_float_roundw_s, fp0, fp0);
6347 gen_store_fpr32(fp0, fd);
6354 TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
6356 gen_load_fpr32(fp0, fs);
6357 tcg_gen_helper_1_1(do_float_truncw_s, fp0, fp0);
6358 gen_store_fpr32(fp0, fd);
6365 TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
6367 gen_load_fpr32(fp0, fs);
6368 tcg_gen_helper_1_1(do_float_ceilw_s, fp0, fp0);
6369 gen_store_fpr32(fp0, fd);
6376 TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
6378 gen_load_fpr32(fp0, fs);
6379 tcg_gen_helper_1_1(do_float_floorw_s, fp0, fp0);
6380 gen_store_fpr32(fp0, fd);
6386 gen_movcf_s(fs, fd, (ft >> 2) & 0x7, ft & 0x1);
6391 int l1 = gen_new_label();
6392 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
6393 TCGv fp0 = tcg_temp_local_new(TCG_TYPE_I32);
6395 gen_load_gpr(t0, ft);
6396 tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
6398 gen_load_fpr32(fp0, fs);
6399 gen_store_fpr32(fp0, fd);
6407 int l1 = gen_new_label();
6408 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
6409 TCGv fp0 = tcg_temp_local_new(TCG_TYPE_I32);
6411 gen_load_gpr(t0, ft);
6412 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
6414 gen_load_fpr32(fp0, fs);
6415 gen_store_fpr32(fp0, fd);
6424 TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
6426 gen_load_fpr32(fp0, fs);
6427 tcg_gen_helper_1_1(do_float_recip_s, fp0, fp0);
6428 gen_store_fpr32(fp0, fd);
6436 TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
6438 gen_load_fpr32(fp0, fs);
6439 tcg_gen_helper_1_1(do_float_rsqrt_s, fp0, fp0);
6440 gen_store_fpr32(fp0, fd);
6446 check_cp1_64bitmode(ctx);
6448 TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
6449 TCGv fp1 = tcg_temp_new(TCG_TYPE_I32);
6451 gen_load_fpr32(fp0, fs);
6452 gen_load_fpr32(fp1, fd);
6453 tcg_gen_helper_1_2(do_float_recip2_s, fp0, fp0, fp1);
6455 gen_store_fpr32(fp0, fd);
6461 check_cp1_64bitmode(ctx);
6463 TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
6465 gen_load_fpr32(fp0, fs);
6466 tcg_gen_helper_1_1(do_float_recip1_s, fp0, fp0);
6467 gen_store_fpr32(fp0, fd);
6473 check_cp1_64bitmode(ctx);
6475 TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
6477 gen_load_fpr32(fp0, fs);
6478 tcg_gen_helper_1_1(do_float_rsqrt1_s, fp0, fp0);
6479 gen_store_fpr32(fp0, fd);
6485 check_cp1_64bitmode(ctx);
6487 TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
6488 TCGv fp1 = tcg_temp_new(TCG_TYPE_I32);
6490 gen_load_fpr32(fp0, fs);
6491 gen_load_fpr32(fp1, ft);
6492 tcg_gen_helper_1_2(do_float_rsqrt2_s, fp0, fp0, fp1);
6494 gen_store_fpr32(fp0, fd);
6500 check_cp1_registers(ctx, fd);
6502 TCGv fp32 = tcg_temp_new(TCG_TYPE_I32);
6503 TCGv fp64 = tcg_temp_new(TCG_TYPE_I64);
6505 gen_load_fpr32(fp32, fs);
6506 tcg_gen_helper_1_1(do_float_cvtd_s, fp64, fp32);
6507 tcg_temp_free(fp32);
6508 gen_store_fpr64(ctx, fp64, fd);
6509 tcg_temp_free(fp64);
6515 TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
6517 gen_load_fpr32(fp0, fs);
6518 tcg_gen_helper_1_1(do_float_cvtw_s, fp0, fp0);
6519 gen_store_fpr32(fp0, fd);
6525 check_cp1_64bitmode(ctx);
6527 TCGv fp32 = tcg_temp_new(TCG_TYPE_I32);
6528 TCGv fp64 = tcg_temp_new(TCG_TYPE_I64);
6530 gen_load_fpr32(fp32, fs);
6531 tcg_gen_helper_1_1(do_float_cvtl_s, fp64, fp32);
6532 tcg_temp_free(fp32);
6533 gen_store_fpr64(ctx, fp64, fd);
6534 tcg_temp_free(fp64);
6539 check_cp1_64bitmode(ctx);
6541 TCGv fp64_0 = tcg_temp_new(TCG_TYPE_I64);
6542 TCGv fp64_1 = tcg_temp_new(TCG_TYPE_I64);
6543 TCGv fp32_0 = tcg_temp_new(TCG_TYPE_I32);
6544 TCGv fp32_1 = tcg_temp_new(TCG_TYPE_I32);
6546 gen_load_fpr32(fp32_0, fs);
6547 gen_load_fpr32(fp32_1, ft);
6548 tcg_gen_extu_i32_i64(fp64_0, fp32_0);
6549 tcg_gen_extu_i32_i64(fp64_1, fp32_1);
6550 tcg_temp_free(fp32_0);
6551 tcg_temp_free(fp32_1);
6552 tcg_gen_shli_i64(fp64_1, fp64_1, 32);
6553 tcg_gen_or_i64(fp64_0, fp64_0, fp64_1);
6554 tcg_temp_free(fp64_1);
6555 gen_store_fpr64(ctx, fp64_0, fd);
6556 tcg_temp_free(fp64_0);
6577 TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
6578 TCGv fp1 = tcg_temp_new(TCG_TYPE_I32);
6580 gen_load_fpr32(fp0, fs);
6581 gen_load_fpr32(fp1, ft);
6582 if (ctx->opcode & (1 << 6)) {
6584 gen_cmpabs_s(func-48, fp0, fp1, cc);
6585 opn = condnames_abs[func-48];
6587 gen_cmp_s(func-48, fp0, fp1, cc);
6588 opn = condnames[func-48];
6595 check_cp1_registers(ctx, fs | ft | fd);
6597 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
6598 TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
6600 gen_load_fpr64(ctx, fp0, fs);
6601 gen_load_fpr64(ctx, fp1, ft);
6602 tcg_gen_helper_1_2(do_float_add_d, fp0, fp0, fp1);
6604 gen_store_fpr64(ctx, fp0, fd);
6611 check_cp1_registers(ctx, fs | ft | fd);
6613 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
6614 TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
6616 gen_load_fpr64(ctx, fp0, fs);
6617 gen_load_fpr64(ctx, fp1, ft);
6618 tcg_gen_helper_1_2(do_float_sub_d, fp0, fp0, fp1);
6620 gen_store_fpr64(ctx, fp0, fd);
6627 check_cp1_registers(ctx, fs | ft | fd);
6629 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
6630 TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
6632 gen_load_fpr64(ctx, fp0, fs);
6633 gen_load_fpr64(ctx, fp1, ft);
6634 tcg_gen_helper_1_2(do_float_mul_d, fp0, fp0, fp1);
6636 gen_store_fpr64(ctx, fp0, fd);
6643 check_cp1_registers(ctx, fs | ft | fd);
6645 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
6646 TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
6648 gen_load_fpr64(ctx, fp0, fs);
6649 gen_load_fpr64(ctx, fp1, ft);
6650 tcg_gen_helper_1_2(do_float_div_d, fp0, fp0, fp1);
6652 gen_store_fpr64(ctx, fp0, fd);
6659 check_cp1_registers(ctx, fs | fd);
6661 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
6663 gen_load_fpr64(ctx, fp0, fs);
6664 tcg_gen_helper_1_1(do_float_sqrt_d, fp0, fp0);
6665 gen_store_fpr64(ctx, fp0, fd);
6671 check_cp1_registers(ctx, fs | fd);
6673 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
6675 gen_load_fpr64(ctx, fp0, fs);
6676 tcg_gen_helper_1_1(do_float_abs_d, fp0, fp0);
6677 gen_store_fpr64(ctx, fp0, fd);
6683 check_cp1_registers(ctx, fs | fd);
6685 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
6687 gen_load_fpr64(ctx, fp0, fs);
6688 gen_store_fpr64(ctx, fp0, fd);
6694 check_cp1_registers(ctx, fs | fd);
6696 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
6698 gen_load_fpr64(ctx, fp0, fs);
6699 tcg_gen_helper_1_1(do_float_chs_d, fp0, fp0);
6700 gen_store_fpr64(ctx, fp0, fd);
6706 check_cp1_64bitmode(ctx);
6708 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
6710 gen_load_fpr64(ctx, fp0, fs);
6711 tcg_gen_helper_1_1(do_float_roundl_d, fp0, fp0);
6712 gen_store_fpr64(ctx, fp0, fd);
6718 check_cp1_64bitmode(ctx);
6720 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
6722 gen_load_fpr64(ctx, fp0, fs);
6723 tcg_gen_helper_1_1(do_float_truncl_d, fp0, fp0);
6724 gen_store_fpr64(ctx, fp0, fd);
6730 check_cp1_64bitmode(ctx);
6732 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
6734 gen_load_fpr64(ctx, fp0, fs);
6735 tcg_gen_helper_1_1(do_float_ceill_d, fp0, fp0);
6736 gen_store_fpr64(ctx, fp0, fd);
6742 check_cp1_64bitmode(ctx);
6744 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
6746 gen_load_fpr64(ctx, fp0, fs);
6747 tcg_gen_helper_1_1(do_float_floorl_d, fp0, fp0);
6748 gen_store_fpr64(ctx, fp0, fd);
6754 check_cp1_registers(ctx, fs);
6756 TCGv fp32 = tcg_temp_new(TCG_TYPE_I32);
6757 TCGv fp64 = tcg_temp_new(TCG_TYPE_I64);
6759 gen_load_fpr64(ctx, fp64, fs);
6760 tcg_gen_helper_1_1(do_float_roundw_d, fp32, fp64);
6761 tcg_temp_free(fp64);
6762 gen_store_fpr32(fp32, fd);
6763 tcg_temp_free(fp32);
6768 check_cp1_registers(ctx, fs);
6770 TCGv fp32 = tcg_temp_new(TCG_TYPE_I32);
6771 TCGv fp64 = tcg_temp_new(TCG_TYPE_I64);
6773 gen_load_fpr64(ctx, fp64, fs);
6774 tcg_gen_helper_1_1(do_float_truncw_d, fp32, fp64);
6775 tcg_temp_free(fp64);
6776 gen_store_fpr32(fp32, fd);
6777 tcg_temp_free(fp32);
6782 check_cp1_registers(ctx, fs);
6784 TCGv fp32 = tcg_temp_new(TCG_TYPE_I32);
6785 TCGv fp64 = tcg_temp_new(TCG_TYPE_I64);
6787 gen_load_fpr64(ctx, fp64, fs);
6788 tcg_gen_helper_1_1(do_float_ceilw_d, fp32, fp64);
6789 tcg_temp_free(fp64);
6790 gen_store_fpr32(fp32, fd);
6791 tcg_temp_free(fp32);
6796 check_cp1_registers(ctx, fs);
6798 TCGv fp32 = tcg_temp_new(TCG_TYPE_I32);
6799 TCGv fp64 = tcg_temp_new(TCG_TYPE_I64);
6801 gen_load_fpr64(ctx, fp64, fs);
6802 tcg_gen_helper_1_1(do_float_floorw_d, fp32, fp64);
6803 tcg_temp_free(fp64);
6804 gen_store_fpr32(fp32, fd);
6805 tcg_temp_free(fp32);
6810 gen_movcf_d(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1);
6815 int l1 = gen_new_label();
6816 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
6817 TCGv fp0 = tcg_temp_local_new(TCG_TYPE_I64);
6819 gen_load_gpr(t0, ft);
6820 tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
6822 gen_load_fpr64(ctx, fp0, fs);
6823 gen_store_fpr64(ctx, fp0, fd);
6831 int l1 = gen_new_label();
6832 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
6833 TCGv fp0 = tcg_temp_local_new(TCG_TYPE_I64);
6835 gen_load_gpr(t0, ft);
6836 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
6838 gen_load_fpr64(ctx, fp0, fs);
6839 gen_store_fpr64(ctx, fp0, fd);
6846 check_cp1_64bitmode(ctx);
6848 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
6850 gen_load_fpr64(ctx, fp0, fs);
6851 tcg_gen_helper_1_1(do_float_recip_d, fp0, fp0);
6852 gen_store_fpr64(ctx, fp0, fd);
6858 check_cp1_64bitmode(ctx);
6860 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
6862 gen_load_fpr64(ctx, fp0, fs);
6863 tcg_gen_helper_1_1(do_float_rsqrt_d, fp0, fp0);
6864 gen_store_fpr64(ctx, fp0, fd);
6870 check_cp1_64bitmode(ctx);
6872 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
6873 TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
6875 gen_load_fpr64(ctx, fp0, fs);
6876 gen_load_fpr64(ctx, fp1, ft);
6877 tcg_gen_helper_1_2(do_float_recip2_d, fp0, fp0, fp1);
6879 gen_store_fpr64(ctx, fp0, fd);
6885 check_cp1_64bitmode(ctx);
6887 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
6889 gen_load_fpr64(ctx, fp0, fs);
6890 tcg_gen_helper_1_1(do_float_recip1_d, fp0, fp0);
6891 gen_store_fpr64(ctx, fp0, fd);
6897 check_cp1_64bitmode(ctx);
6899 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
6901 gen_load_fpr64(ctx, fp0, fs);
6902 tcg_gen_helper_1_1(do_float_rsqrt1_d, fp0, fp0);
6903 gen_store_fpr64(ctx, fp0, fd);
6909 check_cp1_64bitmode(ctx);
6911 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
6912 TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
6914 gen_load_fpr64(ctx, fp0, fs);
6915 gen_load_fpr64(ctx, fp1, ft);
6916 tcg_gen_helper_1_2(do_float_rsqrt2_d, fp0, fp0, fp1);
6918 gen_store_fpr64(ctx, fp0, fd);
6940 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
6941 TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
6943 gen_load_fpr64(ctx, fp0, fs);
6944 gen_load_fpr64(ctx, fp1, ft);
6945 if (ctx->opcode & (1 << 6)) {
6947 check_cp1_registers(ctx, fs | ft);
6948 gen_cmpabs_d(func-48, fp0, fp1, cc);
6949 opn = condnames_abs[func-48];
6951 check_cp1_registers(ctx, fs | ft);
6952 gen_cmp_d(func-48, fp0, fp1, cc);
6953 opn = condnames[func-48];
6960 check_cp1_registers(ctx, fs);
6962 TCGv fp32 = tcg_temp_new(TCG_TYPE_I32);
6963 TCGv fp64 = tcg_temp_new(TCG_TYPE_I64);
6965 gen_load_fpr64(ctx, fp64, fs);
6966 tcg_gen_helper_1_1(do_float_cvts_d, fp32, fp64);
6967 tcg_temp_free(fp64);
6968 gen_store_fpr32(fp32, fd);
6969 tcg_temp_free(fp32);
6974 check_cp1_registers(ctx, fs);
6976 TCGv fp32 = tcg_temp_new(TCG_TYPE_I32);
6977 TCGv fp64 = tcg_temp_new(TCG_TYPE_I64);
6979 gen_load_fpr64(ctx, fp64, fs);
6980 tcg_gen_helper_1_1(do_float_cvtw_d, fp32, fp64);
6981 tcg_temp_free(fp64);
6982 gen_store_fpr32(fp32, fd);
6983 tcg_temp_free(fp32);
6988 check_cp1_64bitmode(ctx);
6990 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
6992 gen_load_fpr64(ctx, fp0, fs);
6993 tcg_gen_helper_1_1(do_float_cvtl_d, fp0, fp0);
6994 gen_store_fpr64(ctx, fp0, fd);
7001 TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
7003 gen_load_fpr32(fp0, fs);
7004 tcg_gen_helper_1_1(do_float_cvts_w, fp0, fp0);
7005 gen_store_fpr32(fp0, fd);
7011 check_cp1_registers(ctx, fd);
7013 TCGv fp32 = tcg_temp_new(TCG_TYPE_I32);
7014 TCGv fp64 = tcg_temp_new(TCG_TYPE_I64);
7016 gen_load_fpr32(fp32, fs);
7017 tcg_gen_helper_1_1(do_float_cvtd_w, fp64, fp32);
7018 tcg_temp_free(fp32);
7019 gen_store_fpr64(ctx, fp64, fd);
7020 tcg_temp_free(fp64);
7025 check_cp1_64bitmode(ctx);
7027 TCGv fp32 = tcg_temp_new(TCG_TYPE_I32);
7028 TCGv fp64 = tcg_temp_new(TCG_TYPE_I64);
7030 gen_load_fpr64(ctx, fp64, fs);
7031 tcg_gen_helper_1_1(do_float_cvts_l, fp32, fp64);
7032 tcg_temp_free(fp64);
7033 gen_store_fpr32(fp32, fd);
7034 tcg_temp_free(fp32);
7039 check_cp1_64bitmode(ctx);
7041 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
7043 gen_load_fpr64(ctx, fp0, fs);
7044 tcg_gen_helper_1_1(do_float_cvtd_l, fp0, fp0);
7045 gen_store_fpr64(ctx, fp0, fd);
7051 check_cp1_64bitmode(ctx);
7053 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
7055 gen_load_fpr64(ctx, fp0, fs);
7056 tcg_gen_helper_1_1(do_float_cvtps_pw, fp0, fp0);
7057 gen_store_fpr64(ctx, fp0, fd);
7063 check_cp1_64bitmode(ctx);
7065 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
7066 TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
7068 gen_load_fpr64(ctx, fp0, fs);
7069 gen_load_fpr64(ctx, fp1, ft);
7070 tcg_gen_helper_1_2(do_float_add_ps, fp0, fp0, fp1);
7072 gen_store_fpr64(ctx, fp0, fd);
7078 check_cp1_64bitmode(ctx);
7080 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
7081 TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
7083 gen_load_fpr64(ctx, fp0, fs);
7084 gen_load_fpr64(ctx, fp1, ft);
7085 tcg_gen_helper_1_2(do_float_sub_ps, fp0, fp0, fp1);
7087 gen_store_fpr64(ctx, fp0, fd);
7093 check_cp1_64bitmode(ctx);
7095 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
7096 TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
7098 gen_load_fpr64(ctx, fp0, fs);
7099 gen_load_fpr64(ctx, fp1, ft);
7100 tcg_gen_helper_1_2(do_float_mul_ps, fp0, fp0, fp1);
7102 gen_store_fpr64(ctx, fp0, fd);
7108 check_cp1_64bitmode(ctx);
7110 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
7112 gen_load_fpr64(ctx, fp0, fs);
7113 tcg_gen_helper_1_1(do_float_abs_ps, fp0, fp0);
7114 gen_store_fpr64(ctx, fp0, fd);
7120 check_cp1_64bitmode(ctx);
7122 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
7124 gen_load_fpr64(ctx, fp0, fs);
7125 gen_store_fpr64(ctx, fp0, fd);
7131 check_cp1_64bitmode(ctx);
7133 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
7135 gen_load_fpr64(ctx, fp0, fs);
7136 tcg_gen_helper_1_1(do_float_chs_ps, fp0, fp0);
7137 gen_store_fpr64(ctx, fp0, fd);
7143 check_cp1_64bitmode(ctx);
7144 gen_movcf_ps(fs, fd, (ft >> 2) & 0x7, ft & 0x1);
7148 check_cp1_64bitmode(ctx);
7150 int l1 = gen_new_label();
7151 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
7152 TCGv fp0 = tcg_temp_local_new(TCG_TYPE_I32);
7153 TCGv fph0 = tcg_temp_local_new(TCG_TYPE_I32);
7155 gen_load_gpr(t0, ft);
7156 tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
7158 gen_load_fpr32(fp0, fs);
7159 gen_load_fpr32h(fph0, fs);
7160 gen_store_fpr32(fp0, fd);
7161 gen_store_fpr32h(fph0, fd);
7163 tcg_temp_free(fph0);
7169 check_cp1_64bitmode(ctx);
7171 int l1 = gen_new_label();
7172 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
7173 TCGv fp0 = tcg_temp_local_new(TCG_TYPE_I32);
7174 TCGv fph0 = tcg_temp_local_new(TCG_TYPE_I32);
7176 gen_load_gpr(t0, ft);
7177 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
7179 gen_load_fpr32(fp0, fs);
7180 gen_load_fpr32h(fph0, fs);
7181 gen_store_fpr32(fp0, fd);
7182 gen_store_fpr32h(fph0, fd);
7184 tcg_temp_free(fph0);
7190 check_cp1_64bitmode(ctx);
7192 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
7193 TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
7195 gen_load_fpr64(ctx, fp0, ft);
7196 gen_load_fpr64(ctx, fp1, fs);
7197 tcg_gen_helper_1_2(do_float_addr_ps, fp0, fp0, fp1);
7199 gen_store_fpr64(ctx, fp0, fd);
7205 check_cp1_64bitmode(ctx);
7207 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
7208 TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
7210 gen_load_fpr64(ctx, fp0, ft);
7211 gen_load_fpr64(ctx, fp1, fs);
7212 tcg_gen_helper_1_2(do_float_mulr_ps, fp0, fp0, fp1);
7214 gen_store_fpr64(ctx, fp0, fd);
7220 check_cp1_64bitmode(ctx);
7222 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
7223 TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
7225 gen_load_fpr64(ctx, fp0, fs);
7226 gen_load_fpr64(ctx, fp1, fd);
7227 tcg_gen_helper_1_2(do_float_recip2_ps, fp0, fp0, fp1);
7229 gen_store_fpr64(ctx, fp0, fd);
7235 check_cp1_64bitmode(ctx);
7237 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
7239 gen_load_fpr64(ctx, fp0, fs);
7240 tcg_gen_helper_1_1(do_float_recip1_ps, fp0, fp0);
7241 gen_store_fpr64(ctx, fp0, fd);
7247 check_cp1_64bitmode(ctx);
7249 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
7251 gen_load_fpr64(ctx, fp0, fs);
7252 tcg_gen_helper_1_1(do_float_rsqrt1_ps, fp0, fp0);
7253 gen_store_fpr64(ctx, fp0, fd);
7259 check_cp1_64bitmode(ctx);
7261 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
7262 TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
7264 gen_load_fpr64(ctx, fp0, fs);
7265 gen_load_fpr64(ctx, fp1, ft);
7266 tcg_gen_helper_1_2(do_float_rsqrt2_ps, fp0, fp0, fp1);
7268 gen_store_fpr64(ctx, fp0, fd);
7274 check_cp1_64bitmode(ctx);
7276 TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
7278 gen_load_fpr32h(fp0, fs);
7279 tcg_gen_helper_1_1(do_float_cvts_pu, fp0, fp0);
7280 gen_store_fpr32(fp0, fd);
7286 check_cp1_64bitmode(ctx);
7288 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
7290 gen_load_fpr64(ctx, fp0, fs);
7291 tcg_gen_helper_1_1(do_float_cvtpw_ps, fp0, fp0);
7292 gen_store_fpr64(ctx, fp0, fd);
7298 check_cp1_64bitmode(ctx);
7300 TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
7302 gen_load_fpr32(fp0, fs);
7303 tcg_gen_helper_1_1(do_float_cvts_pl, fp0, fp0);
7304 gen_store_fpr32(fp0, fd);
7310 check_cp1_64bitmode(ctx);
7312 TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
7313 TCGv fp1 = tcg_temp_new(TCG_TYPE_I32);
7315 gen_load_fpr32(fp0, fs);
7316 gen_load_fpr32(fp1, ft);
7317 gen_store_fpr32h(fp0, fd);
7318 gen_store_fpr32(fp1, fd);
7325 check_cp1_64bitmode(ctx);
7327 TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
7328 TCGv fp1 = tcg_temp_new(TCG_TYPE_I32);
7330 gen_load_fpr32(fp0, fs);
7331 gen_load_fpr32h(fp1, ft);
7332 gen_store_fpr32(fp1, fd);
7333 gen_store_fpr32h(fp0, fd);
7340 check_cp1_64bitmode(ctx);
7342 TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
7343 TCGv fp1 = tcg_temp_new(TCG_TYPE_I32);
7345 gen_load_fpr32h(fp0, fs);
7346 gen_load_fpr32(fp1, ft);
7347 gen_store_fpr32(fp1, fd);
7348 gen_store_fpr32h(fp0, fd);
7355 check_cp1_64bitmode(ctx);
7357 TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
7358 TCGv fp1 = tcg_temp_new(TCG_TYPE_I32);
7360 gen_load_fpr32h(fp0, fs);
7361 gen_load_fpr32h(fp1, ft);
7362 gen_store_fpr32(fp1, fd);
7363 gen_store_fpr32h(fp0, fd);
7385 check_cp1_64bitmode(ctx);
7387 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
7388 TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
7390 gen_load_fpr64(ctx, fp0, fs);
7391 gen_load_fpr64(ctx, fp1, ft);
7392 if (ctx->opcode & (1 << 6)) {
7393 gen_cmpabs_ps(func-48, fp0, fp1, cc);
7394 opn = condnames_abs[func-48];
7396 gen_cmp_ps(func-48, fp0, fp1, cc);
7397 opn = condnames[func-48];
7405 generate_exception (ctx, EXCP_RI);
7410 MIPS_DEBUG("%s %s, %s, %s", opn, fregnames[fd], fregnames[fs], fregnames[ft]);
7413 MIPS_DEBUG("%s %s,%s", opn, fregnames[fs], fregnames[ft]);
7416 MIPS_DEBUG("%s %s,%s", opn, fregnames[fd], fregnames[fs]);
7421 /* Coprocessor 3 (FPU) */
7422 static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
7423 int fd, int fs, int base, int index)
7425 const char *opn = "extended float load/store";
7427 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
7428 TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);
7431 gen_load_gpr(t0, index);
7432 } else if (index == 0) {
7433 gen_load_gpr(t0, base);
7435 gen_load_gpr(t0, base);
7436 gen_load_gpr(t1, index);
7437 gen_op_addr_add(t0, t1);
7439 /* Don't do NOP if destination is zero: we must perform the actual
7445 TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
7447 tcg_gen_qemu_ld32s(fp0, t0, ctx->mem_idx);
7448 gen_store_fpr32(fp0, fd);
7455 check_cp1_registers(ctx, fd);
7457 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
7459 tcg_gen_qemu_ld64(fp0, t0, ctx->mem_idx);
7460 gen_store_fpr64(ctx, fp0, fd);
7466 check_cp1_64bitmode(ctx);
7467 tcg_gen_andi_tl(t0, t0, ~0x7);
7469 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
7471 tcg_gen_qemu_ld64(fp0, t0, ctx->mem_idx);
7472 gen_store_fpr64(ctx, fp0, fd);
7480 TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
7482 gen_load_fpr32(fp0, fs);
7483 tcg_gen_qemu_st32(fp0, t0, ctx->mem_idx);
7491 check_cp1_registers(ctx, fs);
7493 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
7495 gen_load_fpr64(ctx, fp0, fs);
7496 tcg_gen_qemu_st64(fp0, t0, ctx->mem_idx);
7503 check_cp1_64bitmode(ctx);
7504 tcg_gen_andi_tl(t0, t0, ~0x7);
7506 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
7508 gen_load_fpr64(ctx, fp0, fs);
7509 tcg_gen_qemu_st64(fp0, t0, ctx->mem_idx);
7517 generate_exception(ctx, EXCP_RI);
7524 MIPS_DEBUG("%s %s, %s(%s)", opn, fregnames[store ? fs : fd],
7525 regnames[index], regnames[base]);
7528 static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
7529 int fd, int fr, int fs, int ft)
7531 const char *opn = "flt3_arith";
7535 check_cp1_64bitmode(ctx);
7537 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
7538 TCGv fp0 = tcg_temp_local_new(TCG_TYPE_I32);
7539 TCGv fph0 = tcg_temp_local_new(TCG_TYPE_I32);
7540 TCGv fp1 = tcg_temp_local_new(TCG_TYPE_I32);
7541 TCGv fph1 = tcg_temp_local_new(TCG_TYPE_I32);
7542 int l1 = gen_new_label();
7543 int l2 = gen_new_label();
7545 gen_load_gpr(t0, fr);
7546 tcg_gen_andi_tl(t0, t0, 0x7);
7547 gen_load_fpr32(fp0, fs);
7548 gen_load_fpr32h(fph0, fs);
7549 gen_load_fpr32(fp1, ft);
7550 gen_load_fpr32h(fph1, ft);
7552 tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
7553 gen_store_fpr32(fp0, fd);
7554 gen_store_fpr32h(fph0, fd);
7557 tcg_gen_brcondi_tl(TCG_COND_NE, t0, 4, l2);
7559 #ifdef TARGET_WORDS_BIGENDIAN
7560 gen_store_fpr32(fph1, fd);
7561 gen_store_fpr32h(fp0, fd);
7563 gen_store_fpr32(fph0, fd);
7564 gen_store_fpr32h(fp1, fd);
7568 tcg_temp_free(fph0);
7570 tcg_temp_free(fph1);
7577 TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
7578 TCGv fp1 = tcg_temp_new(TCG_TYPE_I32);
7579 TCGv fp2 = tcg_temp_new(TCG_TYPE_I32);
7581 gen_load_fpr32(fp0, fs);
7582 gen_load_fpr32(fp1, ft);
7583 gen_load_fpr32(fp2, fr);
7584 tcg_gen_helper_1_3(do_float_muladd_s, fp2, fp0, fp1, fp2);
7587 gen_store_fpr32(fp2, fd);
7594 check_cp1_registers(ctx, fd | fs | ft | fr);
7596 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
7597 TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
7598 TCGv fp2 = tcg_temp_new(TCG_TYPE_I64);
7600 gen_load_fpr64(ctx, fp0, fs);
7601 gen_load_fpr64(ctx, fp1, ft);
7602 gen_load_fpr64(ctx, fp2, fr);
7603 tcg_gen_helper_1_3(do_float_muladd_d, fp2, fp0, fp1, fp2);
7606 gen_store_fpr64(ctx, fp2, fd);
7612 check_cp1_64bitmode(ctx);
7614 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
7615 TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
7616 TCGv fp2 = tcg_temp_new(TCG_TYPE_I64);
7618 gen_load_fpr64(ctx, fp0, fs);
7619 gen_load_fpr64(ctx, fp1, ft);
7620 gen_load_fpr64(ctx, fp2, fr);
7621 tcg_gen_helper_1_3(do_float_muladd_ps, fp2, fp0, fp1, fp2);
7624 gen_store_fpr64(ctx, fp2, fd);
7632 TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
7633 TCGv fp1 = tcg_temp_new(TCG_TYPE_I32);
7634 TCGv fp2 = tcg_temp_new(TCG_TYPE_I32);
7636 gen_load_fpr32(fp0, fs);
7637 gen_load_fpr32(fp1, ft);
7638 gen_load_fpr32(fp2, fr);
7639 tcg_gen_helper_1_3(do_float_mulsub_s, fp2, fp0, fp1, fp2);
7642 gen_store_fpr32(fp2, fd);
7649 check_cp1_registers(ctx, fd | fs | ft | fr);
7651 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
7652 TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
7653 TCGv fp2 = tcg_temp_new(TCG_TYPE_I64);
7655 gen_load_fpr64(ctx, fp0, fs);
7656 gen_load_fpr64(ctx, fp1, ft);
7657 gen_load_fpr64(ctx, fp2, fr);
7658 tcg_gen_helper_1_3(do_float_mulsub_d, fp2, fp0, fp1, fp2);
7661 gen_store_fpr64(ctx, fp2, fd);
7667 check_cp1_64bitmode(ctx);
7669 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
7670 TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
7671 TCGv fp2 = tcg_temp_new(TCG_TYPE_I64);
7673 gen_load_fpr64(ctx, fp0, fs);
7674 gen_load_fpr64(ctx, fp1, ft);
7675 gen_load_fpr64(ctx, fp2, fr);
7676 tcg_gen_helper_1_3(do_float_mulsub_ps, fp2, fp0, fp1, fp2);
7679 gen_store_fpr64(ctx, fp2, fd);
7687 TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
7688 TCGv fp1 = tcg_temp_new(TCG_TYPE_I32);
7689 TCGv fp2 = tcg_temp_new(TCG_TYPE_I32);
7691 gen_load_fpr32(fp0, fs);
7692 gen_load_fpr32(fp1, ft);
7693 gen_load_fpr32(fp2, fr);
7694 tcg_gen_helper_1_3(do_float_nmuladd_s, fp2, fp0, fp1, fp2);
7697 gen_store_fpr32(fp2, fd);
7704 check_cp1_registers(ctx, fd | fs | ft | fr);
7706 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
7707 TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
7708 TCGv fp2 = tcg_temp_new(TCG_TYPE_I64);
7710 gen_load_fpr64(ctx, fp0, fs);
7711 gen_load_fpr64(ctx, fp1, ft);
7712 gen_load_fpr64(ctx, fp2, fr);
7713 tcg_gen_helper_1_3(do_float_nmuladd_d, fp2, fp0, fp1, fp2);
7716 gen_store_fpr64(ctx, fp2, fd);
7722 check_cp1_64bitmode(ctx);
7724 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
7725 TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
7726 TCGv fp2 = tcg_temp_new(TCG_TYPE_I64);
7728 gen_load_fpr64(ctx, fp0, fs);
7729 gen_load_fpr64(ctx, fp1, ft);
7730 gen_load_fpr64(ctx, fp2, fr);
7731 tcg_gen_helper_1_3(do_float_nmuladd_ps, fp2, fp0, fp1, fp2);
7734 gen_store_fpr64(ctx, fp2, fd);
7742 TCGv fp0 = tcg_temp_new(TCG_TYPE_I32);
7743 TCGv fp1 = tcg_temp_new(TCG_TYPE_I32);
7744 TCGv fp2 = tcg_temp_new(TCG_TYPE_I32);
7746 gen_load_fpr32(fp0, fs);
7747 gen_load_fpr32(fp1, ft);
7748 gen_load_fpr32(fp2, fr);
7749 tcg_gen_helper_1_3(do_float_nmulsub_s, fp2, fp0, fp1, fp2);
7752 gen_store_fpr32(fp2, fd);
7759 check_cp1_registers(ctx, fd | fs | ft | fr);
7761 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
7762 TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
7763 TCGv fp2 = tcg_temp_new(TCG_TYPE_I64);
7765 gen_load_fpr64(ctx, fp0, fs);
7766 gen_load_fpr64(ctx, fp1, ft);
7767 gen_load_fpr64(ctx, fp2, fr);
7768 tcg_gen_helper_1_3(do_float_nmulsub_d, fp2, fp0, fp1, fp2);
7771 gen_store_fpr64(ctx, fp2, fd);
7777 check_cp1_64bitmode(ctx);
7779 TCGv fp0 = tcg_temp_new(TCG_TYPE_I64);
7780 TCGv fp1 = tcg_temp_new(TCG_TYPE_I64);
7781 TCGv fp2 = tcg_temp_new(TCG_TYPE_I64);
7783 gen_load_fpr64(ctx, fp0, fs);
7784 gen_load_fpr64(ctx, fp1, ft);
7785 gen_load_fpr64(ctx, fp2, fr);
7786 tcg_gen_helper_1_3(do_float_nmulsub_ps, fp2, fp0, fp1, fp2);
7789 gen_store_fpr64(ctx, fp2, fd);
7796 generate_exception (ctx, EXCP_RI);
7799 MIPS_DEBUG("%s %s, %s, %s, %s", opn, fregnames[fd], fregnames[fr],
7800 fregnames[fs], fregnames[ft]);
7803 /* ISA extensions (ASEs) */
7804 /* MIPS16 extension to MIPS32 */
7805 /* SmartMIPS extension to MIPS32 */
7807 #if defined(TARGET_MIPS64)
7809 /* MDMX extension to MIPS64 */
7813 static void decode_opc (CPUState *env, DisasContext *ctx)
7817 uint32_t op, op1, op2;
7820 /* make sure instructions are on a word boundary */
7821 if (ctx->pc & 0x3) {
7822 env->CP0_BadVAddr = ctx->pc;
7823 generate_exception(ctx, EXCP_AdEL);
7827 /* Handle blikely not taken case */
7828 if ((ctx->hflags & MIPS_HFLAG_BMASK) == MIPS_HFLAG_BL) {
7829 int l1 = gen_new_label();
7831 MIPS_DEBUG("blikely condition (" TARGET_FMT_lx ")", ctx->pc + 4);
7832 tcg_gen_brcondi_i32(TCG_COND_NE, bcond, 0, l1);
7834 TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
7836 tcg_gen_movi_i32(r_tmp, ctx->hflags & ~MIPS_HFLAG_BMASK);
7837 tcg_gen_st_i32(r_tmp, cpu_env, offsetof(CPUState, hflags));
7838 tcg_temp_free(r_tmp);
7840 gen_goto_tb(ctx, 1, ctx->pc + 4);
7843 op = MASK_OP_MAJOR(ctx->opcode);
7844 rs = (ctx->opcode >> 21) & 0x1f;
7845 rt = (ctx->opcode >> 16) & 0x1f;
7846 rd = (ctx->opcode >> 11) & 0x1f;
7847 sa = (ctx->opcode >> 6) & 0x1f;
7848 imm = (int16_t)ctx->opcode;
7851 op1 = MASK_SPECIAL(ctx->opcode);
7853 case OPC_SLL: /* Arithmetic with immediate */
7854 case OPC_SRL ... OPC_SRA:
7855 gen_arith_imm(env, ctx, op1, rd, rt, sa);
7857 case OPC_MOVZ ... OPC_MOVN:
7858 check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32);
7859 case OPC_SLLV: /* Arithmetic */
7860 case OPC_SRLV ... OPC_SRAV:
7861 case OPC_ADD ... OPC_NOR:
7862 case OPC_SLT ... OPC_SLTU:
7863 gen_arith(env, ctx, op1, rd, rs, rt);
7865 case OPC_MULT ... OPC_DIVU:
7867 check_insn(env, ctx, INSN_VR54XX);
7868 op1 = MASK_MUL_VR54XX(ctx->opcode);
7869 gen_mul_vr54xx(ctx, op1, rd, rs, rt);
7871 gen_muldiv(ctx, op1, rs, rt);
7873 case OPC_JR ... OPC_JALR:
7874 gen_compute_branch(ctx, op1, rs, rd, sa);
7876 case OPC_TGE ... OPC_TEQ: /* Traps */
7878 gen_trap(ctx, op1, rs, rt, -1);
7880 case OPC_MFHI: /* Move from HI/LO */
7882 gen_HILO(ctx, op1, rd);
7885 case OPC_MTLO: /* Move to HI/LO */
7886 gen_HILO(ctx, op1, rs);
7888 case OPC_PMON: /* Pmon entry point, also R4010 selsl */
7889 #ifdef MIPS_STRICT_STANDARD
7890 MIPS_INVAL("PMON / selsl");
7891 generate_exception(ctx, EXCP_RI);
7893 tcg_gen_helper_0_i(do_pmon, sa);
7897 generate_exception(ctx, EXCP_SYSCALL);
7900 generate_exception(ctx, EXCP_BREAK);
7903 #ifdef MIPS_STRICT_STANDARD
7905 generate_exception(ctx, EXCP_RI);
7907 /* Implemented as RI exception for now. */
7908 MIPS_INVAL("spim (unofficial)");
7909 generate_exception(ctx, EXCP_RI);
7917 check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32);
7918 if (env->CP0_Config1 & (1 << CP0C1_FP)) {
7919 save_cpu_state(ctx, 1);
7920 check_cp1_enabled(ctx);
7921 gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7,
7922 (ctx->opcode >> 16) & 1);
7924 generate_exception_err(ctx, EXCP_CpU, 1);
7928 #if defined(TARGET_MIPS64)
7929 /* MIPS64 specific opcodes */
7931 case OPC_DSRL ... OPC_DSRA:
7933 case OPC_DSRL32 ... OPC_DSRA32:
7934 check_insn(env, ctx, ISA_MIPS3);
7936 gen_arith_imm(env, ctx, op1, rd, rt, sa);
7939 case OPC_DSRLV ... OPC_DSRAV:
7940 case OPC_DADD ... OPC_DSUBU:
7941 check_insn(env, ctx, ISA_MIPS3);
7943 gen_arith(env, ctx, op1, rd, rs, rt);
7945 case OPC_DMULT ... OPC_DDIVU:
7946 check_insn(env, ctx, ISA_MIPS3);
7948 gen_muldiv(ctx, op1, rs, rt);
7951 default: /* Invalid */
7952 MIPS_INVAL("special");
7953 generate_exception(ctx, EXCP_RI);
7958 op1 = MASK_SPECIAL2(ctx->opcode);
7960 case OPC_MADD ... OPC_MADDU: /* Multiply and add/sub */
7961 case OPC_MSUB ... OPC_MSUBU:
7962 check_insn(env, ctx, ISA_MIPS32);
7963 gen_muldiv(ctx, op1, rs, rt);
7966 gen_arith(env, ctx, op1, rd, rs, rt);
7968 case OPC_CLZ ... OPC_CLO:
7969 check_insn(env, ctx, ISA_MIPS32);
7970 gen_cl(ctx, op1, rd, rs);
7973 /* XXX: not clear which exception should be raised
7974 * when in debug mode...
7976 check_insn(env, ctx, ISA_MIPS32);
7977 if (!(ctx->hflags & MIPS_HFLAG_DM)) {
7978 generate_exception(ctx, EXCP_DBp);
7980 generate_exception(ctx, EXCP_DBp);
7984 #if defined(TARGET_MIPS64)
7985 case OPC_DCLZ ... OPC_DCLO:
7986 check_insn(env, ctx, ISA_MIPS64);
7988 gen_cl(ctx, op1, rd, rs);
7991 default: /* Invalid */
7992 MIPS_INVAL("special2");
7993 generate_exception(ctx, EXCP_RI);
7998 op1 = MASK_SPECIAL3(ctx->opcode);
8002 check_insn(env, ctx, ISA_MIPS32R2);
8003 gen_bitops(ctx, op1, rt, rs, sa, rd);
8006 check_insn(env, ctx, ISA_MIPS32R2);
8007 op2 = MASK_BSHFL(ctx->opcode);
8009 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
8010 TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);
8014 gen_load_gpr(t1, rt);
8015 tcg_gen_helper_1_1(do_wsbh, t0, t1);
8016 gen_store_gpr(t0, rd);
8019 gen_load_gpr(t1, rt);
8020 tcg_gen_ext8s_tl(t0, t1);
8021 gen_store_gpr(t0, rd);
8024 gen_load_gpr(t1, rt);
8025 tcg_gen_ext16s_tl(t0, t1);
8026 gen_store_gpr(t0, rd);
8028 default: /* Invalid */
8029 MIPS_INVAL("bshfl");
8030 generate_exception(ctx, EXCP_RI);
8038 check_insn(env, ctx, ISA_MIPS32R2);
8040 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
8044 save_cpu_state(ctx, 1);
8045 tcg_gen_helper_1_0(do_rdhwr_cpunum, t0);
8048 save_cpu_state(ctx, 1);
8049 tcg_gen_helper_1_0(do_rdhwr_synci_step, t0);
8052 save_cpu_state(ctx, 1);
8053 tcg_gen_helper_1_0(do_rdhwr_cc, t0);
8056 save_cpu_state(ctx, 1);
8057 tcg_gen_helper_1_0(do_rdhwr_ccres, t0);
8060 #if defined (CONFIG_USER_ONLY)
8061 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, tls_value));
8064 /* XXX: Some CPUs implement this in hardware. Not supported yet. */
8066 default: /* Invalid */
8067 MIPS_INVAL("rdhwr");
8068 generate_exception(ctx, EXCP_RI);
8071 gen_store_gpr(t0, rt);
8076 check_insn(env, ctx, ASE_MT);
8078 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
8079 TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);
8081 gen_load_gpr(t0, rt);
8082 gen_load_gpr(t1, rs);
8083 tcg_gen_helper_0_2(do_fork, t0, t1);
8089 check_insn(env, ctx, ASE_MT);
8091 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
8093 gen_load_gpr(t0, rs);
8094 tcg_gen_helper_1_1(do_yield, t0, t0);
8095 gen_store_gpr(t0, rd);
8099 #if defined(TARGET_MIPS64)
8100 case OPC_DEXTM ... OPC_DEXT:
8101 case OPC_DINSM ... OPC_DINS:
8102 check_insn(env, ctx, ISA_MIPS64R2);
8104 gen_bitops(ctx, op1, rt, rs, sa, rd);
8107 check_insn(env, ctx, ISA_MIPS64R2);
8109 op2 = MASK_DBSHFL(ctx->opcode);
8111 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
8112 TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);
8116 gen_load_gpr(t1, rt);
8117 tcg_gen_helper_1_1(do_dsbh, t0, t1);
8120 gen_load_gpr(t1, rt);
8121 tcg_gen_helper_1_1(do_dshd, t0, t1);
8123 default: /* Invalid */
8124 MIPS_INVAL("dbshfl");
8125 generate_exception(ctx, EXCP_RI);
8128 gen_store_gpr(t0, rd);
8134 default: /* Invalid */
8135 MIPS_INVAL("special3");
8136 generate_exception(ctx, EXCP_RI);
8141 op1 = MASK_REGIMM(ctx->opcode);
8143 case OPC_BLTZ ... OPC_BGEZL: /* REGIMM branches */
8144 case OPC_BLTZAL ... OPC_BGEZALL:
8145 gen_compute_branch(ctx, op1, rs, -1, imm << 2);
8147 case OPC_TGEI ... OPC_TEQI: /* REGIMM traps */
8149 gen_trap(ctx, op1, rs, -1, imm);
8152 check_insn(env, ctx, ISA_MIPS32R2);
8155 default: /* Invalid */
8156 MIPS_INVAL("regimm");
8157 generate_exception(ctx, EXCP_RI);
8162 check_cp0_enabled(ctx);
8163 op1 = MASK_CP0(ctx->opcode);
8169 #if defined(TARGET_MIPS64)
8173 #ifndef CONFIG_USER_ONLY
8174 gen_cp0(env, ctx, op1, rt, rd);
8177 case OPC_C0_FIRST ... OPC_C0_LAST:
8178 #ifndef CONFIG_USER_ONLY
8179 gen_cp0(env, ctx, MASK_C0(ctx->opcode), rt, rd);
8183 op2 = MASK_MFMC0(ctx->opcode);
8185 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
8189 check_insn(env, ctx, ASE_MT);
8190 tcg_gen_helper_1_1(do_dmt, t0, t0);
8193 check_insn(env, ctx, ASE_MT);
8194 tcg_gen_helper_1_1(do_emt, t0, t0);
8197 check_insn(env, ctx, ASE_MT);
8198 tcg_gen_helper_1_1(do_dvpe, t0, t0);
8201 check_insn(env, ctx, ASE_MT);
8202 tcg_gen_helper_1_1(do_evpe, t0, t0);
8205 check_insn(env, ctx, ISA_MIPS32R2);
8206 save_cpu_state(ctx, 1);
8207 tcg_gen_helper_1_0(do_di, t0);
8208 /* Stop translation as we may have switched the execution mode */
8209 ctx->bstate = BS_STOP;
8212 check_insn(env, ctx, ISA_MIPS32R2);
8213 save_cpu_state(ctx, 1);
8214 tcg_gen_helper_1_0(do_ei, t0);
8215 /* Stop translation as we may have switched the execution mode */
8216 ctx->bstate = BS_STOP;
8218 default: /* Invalid */
8219 MIPS_INVAL("mfmc0");
8220 generate_exception(ctx, EXCP_RI);
8223 gen_store_gpr(t0, rt);
8228 check_insn(env, ctx, ISA_MIPS32R2);
8229 gen_load_srsgpr(rt, rd);
8232 check_insn(env, ctx, ISA_MIPS32R2);
8233 gen_store_srsgpr(rt, rd);
8237 generate_exception(ctx, EXCP_RI);
8241 case OPC_ADDI ... OPC_LUI: /* Arithmetic with immediate opcode */
8242 gen_arith_imm(env, ctx, op, rt, rs, imm);
8244 case OPC_J ... OPC_JAL: /* Jump */
8245 offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2;
8246 gen_compute_branch(ctx, op, rs, rt, offset);
8248 case OPC_BEQ ... OPC_BGTZ: /* Branch */
8249 case OPC_BEQL ... OPC_BGTZL:
8250 gen_compute_branch(ctx, op, rs, rt, imm << 2);
8252 case OPC_LB ... OPC_LWR: /* Load and stores */
8253 case OPC_SB ... OPC_SW:
8257 gen_ldst(ctx, op, rt, rs, imm);
8260 check_insn(env, ctx, ISA_MIPS3 | ISA_MIPS32);
8264 check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32);
8268 /* Floating point (COP1). */
8273 if (env->CP0_Config1 & (1 << CP0C1_FP)) {
8274 save_cpu_state(ctx, 1);
8275 check_cp1_enabled(ctx);
8276 gen_flt_ldst(ctx, op, rt, rs, imm);
8278 generate_exception_err(ctx, EXCP_CpU, 1);
8283 if (env->CP0_Config1 & (1 << CP0C1_FP)) {
8284 save_cpu_state(ctx, 1);
8285 check_cp1_enabled(ctx);
8286 op1 = MASK_CP1(ctx->opcode);
8290 check_insn(env, ctx, ISA_MIPS32R2);
8295 gen_cp1(ctx, op1, rt, rd);
8297 #if defined(TARGET_MIPS64)
8300 check_insn(env, ctx, ISA_MIPS3);
8301 gen_cp1(ctx, op1, rt, rd);
8307 check_insn(env, ctx, ASE_MIPS3D);
8310 gen_compute_branch1(env, ctx, MASK_BC1(ctx->opcode),
8311 (rt >> 2) & 0x7, imm << 2);
8318 gen_farith(ctx, MASK_CP1_FUNC(ctx->opcode), rt, rd, sa,
8323 generate_exception (ctx, EXCP_RI);
8327 generate_exception_err(ctx, EXCP_CpU, 1);
8337 /* COP2: Not implemented. */
8338 generate_exception_err(ctx, EXCP_CpU, 2);
8342 if (env->CP0_Config1 & (1 << CP0C1_FP)) {
8343 save_cpu_state(ctx, 1);
8344 check_cp1_enabled(ctx);
8345 op1 = MASK_CP3(ctx->opcode);
8353 gen_flt3_ldst(ctx, op1, sa, rd, rs, rt);
8371 gen_flt3_arith(ctx, op1, sa, rs, rd, rt);
8375 generate_exception (ctx, EXCP_RI);
8379 generate_exception_err(ctx, EXCP_CpU, 1);
8383 #if defined(TARGET_MIPS64)
8384 /* MIPS64 opcodes */
8386 case OPC_LDL ... OPC_LDR:
8387 case OPC_SDL ... OPC_SDR:
8392 check_insn(env, ctx, ISA_MIPS3);
8394 gen_ldst(ctx, op, rt, rs, imm);
8396 case OPC_DADDI ... OPC_DADDIU:
8397 check_insn(env, ctx, ISA_MIPS3);
8399 gen_arith_imm(env, ctx, op, rt, rs, imm);
8403 check_insn(env, ctx, ASE_MIPS16);
8404 /* MIPS16: Not implemented. */
8406 check_insn(env, ctx, ASE_MDMX);
8407 /* MDMX: Not implemented. */
8408 default: /* Invalid */
8409 MIPS_INVAL("major opcode");
8410 generate_exception(ctx, EXCP_RI);
8413 if (ctx->hflags & MIPS_HFLAG_BMASK) {
8414 int hflags = ctx->hflags & MIPS_HFLAG_BMASK;
8415 /* Branches completion */
8416 ctx->hflags &= ~MIPS_HFLAG_BMASK;
8417 ctx->bstate = BS_BRANCH;
8418 save_cpu_state(ctx, 0);
8419 /* FIXME: Need to clear can_do_io. */
8422 /* unconditional branch */
8423 MIPS_DEBUG("unconditional branch");
8424 gen_goto_tb(ctx, 0, ctx->btarget);
8427 /* blikely taken case */
8428 MIPS_DEBUG("blikely branch taken");
8429 gen_goto_tb(ctx, 0, ctx->btarget);
8432 /* Conditional branch */
8433 MIPS_DEBUG("conditional branch");
8435 int l1 = gen_new_label();
8437 tcg_gen_brcondi_i32(TCG_COND_NE, bcond, 0, l1);
8438 gen_goto_tb(ctx, 1, ctx->pc + 4);
8440 gen_goto_tb(ctx, 0, ctx->btarget);
8444 /* unconditional branch to register */
8445 MIPS_DEBUG("branch to register");
8446 tcg_gen_st_tl(btarget, cpu_env, offsetof(CPUState, active_tc.PC));
8450 MIPS_DEBUG("unknown branch");
8457 gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
8461 target_ulong pc_start;
8462 uint16_t *gen_opc_end;
8467 if (search_pc && loglevel)
8468 fprintf (logfile, "search pc %d\n", search_pc);
8471 /* Leave some spare opc slots for branch handling. */
8472 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE - 16;
8476 ctx.bstate = BS_NONE;
8477 /* Restore delay slot state from the tb context. */
8478 ctx.hflags = (uint32_t)tb->flags; /* FIXME: maybe use 64 bits here? */
8479 restore_cpu_state(env, &ctx);
8480 #if defined(CONFIG_USER_ONLY)
8481 ctx.mem_idx = MIPS_HFLAG_UM;
8483 ctx.mem_idx = ctx.hflags & MIPS_HFLAG_KSU;
8486 max_insns = tb->cflags & CF_COUNT_MASK;
8488 max_insns = CF_COUNT_MASK;
8490 if (loglevel & CPU_LOG_TB_CPU) {
8491 fprintf(logfile, "------------------------------------------------\n");
8492 /* FIXME: This may print out stale hflags from env... */
8493 cpu_dump_state(env, logfile, fprintf, 0);
8496 #ifdef MIPS_DEBUG_DISAS
8497 if (loglevel & CPU_LOG_TB_IN_ASM)
8498 fprintf(logfile, "\ntb %p idx %d hflags %04x\n",
8499 tb, ctx.mem_idx, ctx.hflags);
8502 while (ctx.bstate == BS_NONE) {
8503 if (env->nb_breakpoints > 0) {
8504 for(j = 0; j < env->nb_breakpoints; j++) {
8505 if (env->breakpoints[j] == ctx.pc) {
8506 save_cpu_state(&ctx, 1);
8507 ctx.bstate = BS_BRANCH;
8508 tcg_gen_helper_0_i(do_raise_exception, EXCP_DEBUG);
8509 /* Include the breakpoint location or the tb won't
8510 * be flushed when it must be. */
8512 goto done_generating;
8518 j = gen_opc_ptr - gen_opc_buf;
8522 gen_opc_instr_start[lj++] = 0;
8524 gen_opc_pc[lj] = ctx.pc;
8525 gen_opc_hflags[lj] = ctx.hflags & MIPS_HFLAG_BMASK;
8526 gen_opc_instr_start[lj] = 1;
8527 gen_opc_icount[lj] = num_insns;
8529 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
8531 ctx.opcode = ldl_code(ctx.pc);
8532 decode_opc(env, &ctx);
8536 if (env->singlestep_enabled)
8539 if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0)
8542 if (gen_opc_ptr >= gen_opc_end)
8545 if (num_insns >= max_insns)
8547 #if defined (MIPS_SINGLE_STEP)
8551 if (tb->cflags & CF_LAST_IO)
8553 if (env->singlestep_enabled) {
8554 save_cpu_state(&ctx, ctx.bstate == BS_NONE);
8555 tcg_gen_helper_0_i(do_raise_exception, EXCP_DEBUG);
8557 switch (ctx.bstate) {
8559 tcg_gen_helper_0_0(do_interrupt_restart);
8560 gen_goto_tb(&ctx, 0, ctx.pc);
8563 save_cpu_state(&ctx, 0);
8564 gen_goto_tb(&ctx, 0, ctx.pc);
8567 tcg_gen_helper_0_0(do_interrupt_restart);
8576 gen_icount_end(tb, num_insns);
8577 *gen_opc_ptr = INDEX_op_end;
8579 j = gen_opc_ptr - gen_opc_buf;
8582 gen_opc_instr_start[lj++] = 0;
8584 tb->size = ctx.pc - pc_start;
8585 tb->icount = num_insns;
8588 #if defined MIPS_DEBUG_DISAS
8589 if (loglevel & CPU_LOG_TB_IN_ASM)
8590 fprintf(logfile, "\n");
8592 if (loglevel & CPU_LOG_TB_IN_ASM) {
8593 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
8594 target_disas(logfile, pc_start, ctx.pc - pc_start, 0);
8595 fprintf(logfile, "\n");
8597 if (loglevel & CPU_LOG_TB_CPU) {
8598 fprintf(logfile, "---------------- %d %08x\n", ctx.bstate, ctx.hflags);
8605 int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
8607 return gen_intermediate_code_internal(env, tb, 0);
8610 int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
8612 return gen_intermediate_code_internal(env, tb, 1);
8615 void fpu_dump_state(CPUState *env, FILE *f,
8616 int (*fpu_fprintf)(FILE *f, const char *fmt, ...),
8620 int is_fpu64 = !!(env->hflags & MIPS_HFLAG_F64);
8622 #define printfpr(fp) \
8625 fpu_fprintf(f, "w:%08x d:%016lx fd:%13g fs:%13g psu: %13g\n", \
8626 (fp)->w[FP_ENDIAN_IDX], (fp)->d, (fp)->fd, \
8627 (fp)->fs[FP_ENDIAN_IDX], (fp)->fs[!FP_ENDIAN_IDX]); \
8630 tmp.w[FP_ENDIAN_IDX] = (fp)->w[FP_ENDIAN_IDX]; \
8631 tmp.w[!FP_ENDIAN_IDX] = ((fp) + 1)->w[FP_ENDIAN_IDX]; \
8632 fpu_fprintf(f, "w:%08x d:%016lx fd:%13g fs:%13g psu:%13g\n", \
8633 tmp.w[FP_ENDIAN_IDX], tmp.d, tmp.fd, \
8634 tmp.fs[FP_ENDIAN_IDX], tmp.fs[!FP_ENDIAN_IDX]); \
8639 fpu_fprintf(f, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%08x(0x%02x)\n",
8640 env->fpu->fcr0, env->fpu->fcr31, is_fpu64, env->fpu->fp_status,
8641 get_float_exception_flags(&env->fpu->fp_status));
8642 for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) {
8643 fpu_fprintf(f, "%3s: ", fregnames[i]);
8644 printfpr(&env->fpu->fpr[i]);
8650 void dump_fpu (CPUState *env)
8654 "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx
8655 " LO=0x" TARGET_FMT_lx " ds %04x " TARGET_FMT_lx
8657 env->active_tc.PC, env->active_tc.HI[0],
8658 env->active_tc.LO[0], env->hflags, env->btarget,
8660 fpu_dump_state(env, logfile, fprintf, 0);
8664 #if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
8665 /* Debug help: The architecture requires 32bit code to maintain proper
8666 sign-extended values on 64bit machines. */
8668 #define SIGN_EXT_P(val) ((((val) & ~0x7fffffff) == 0) || (((val) & ~0x7fffffff) == ~0x7fffffff))
8670 void cpu_mips_check_sign_extensions (CPUState *env, FILE *f,
8671 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
8676 if (!SIGN_EXT_P(env->active_tc.PC))
8677 cpu_fprintf(f, "BROKEN: pc=0x" TARGET_FMT_lx "\n", env->active_tc.PC);
8678 if (!SIGN_EXT_P(env->active_tc.HI[0]))
8679 cpu_fprintf(f, "BROKEN: HI=0x" TARGET_FMT_lx "\n", env->active_tc.HI[0]);
8680 if (!SIGN_EXT_P(env->active_tc.LO[0]))
8681 cpu_fprintf(f, "BROKEN: LO=0x" TARGET_FMT_lx "\n", env->active_tc.LO[0]);
8682 if (!SIGN_EXT_P(env->btarget))
8683 cpu_fprintf(f, "BROKEN: btarget=0x" TARGET_FMT_lx "\n", env->btarget);
8685 for (i = 0; i < 32; i++) {
8686 if (!SIGN_EXT_P(env->active_tc.gpr[i]))
8687 cpu_fprintf(f, "BROKEN: %s=0x" TARGET_FMT_lx "\n", regnames[i], env->active_tc.gpr[i]);
8690 if (!SIGN_EXT_P(env->CP0_EPC))
8691 cpu_fprintf(f, "BROKEN: EPC=0x" TARGET_FMT_lx "\n", env->CP0_EPC);
8692 if (!SIGN_EXT_P(env->CP0_LLAddr))
8693 cpu_fprintf(f, "BROKEN: LLAddr=0x" TARGET_FMT_lx "\n", env->CP0_LLAddr);
8697 void cpu_dump_state (CPUState *env, FILE *f,
8698 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
8703 cpu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx " LO=0x" TARGET_FMT_lx " ds %04x " TARGET_FMT_lx " %d\n",
8704 env->active_tc.PC, env->active_tc.HI, env->active_tc.LO, env->hflags, env->btarget, env->bcond);
8705 for (i = 0; i < 32; i++) {
8707 cpu_fprintf(f, "GPR%02d:", i);
8708 cpu_fprintf(f, " %s " TARGET_FMT_lx, regnames[i], env->active_tc.gpr[i]);
8710 cpu_fprintf(f, "\n");
8713 cpu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" TARGET_FMT_lx "\n",
8714 env->CP0_Status, env->CP0_Cause, env->CP0_EPC);
8715 cpu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x" TARGET_FMT_lx "\n",
8716 env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr);
8717 if (env->hflags & MIPS_HFLAG_FPU)
8718 fpu_dump_state(env, f, cpu_fprintf, flags);
8719 #if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
8720 cpu_mips_check_sign_extensions(env, f, cpu_fprintf, flags);
8724 static void mips_tcg_init(void)
8728 /* Initialize various static tables. */
8732 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
8733 bcond = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
8734 offsetof(CPUState, bcond), "bcond");
8735 btarget = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
8736 offsetof(CPUState, btarget), "btarget");
8737 current_fpu = tcg_global_mem_new(TCG_TYPE_PTR,
8739 offsetof(CPUState, fpu),
8742 /* register helpers */
8744 #define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
8750 #include "translate_init.c"
8752 CPUMIPSState *cpu_mips_init (const char *cpu_model)
8755 const mips_def_t *def;
8757 def = cpu_mips_find_by_name(cpu_model);
8760 env = qemu_mallocz(sizeof(CPUMIPSState));
8763 env->cpu_model = def;
8766 env->cpu_model_str = cpu_model;
8772 void cpu_reset (CPUMIPSState *env)
8774 memset(env, 0, offsetof(CPUMIPSState, breakpoints));
8779 #if !defined(CONFIG_USER_ONLY)
8780 if (env->hflags & MIPS_HFLAG_BMASK) {
8781 /* If the exception was raised from a delay slot,
8782 * come back to the jump. */
8783 env->CP0_ErrorEPC = env->active_tc.PC - 4;
8785 env->CP0_ErrorEPC = env->active_tc.PC;
8787 env->active_tc.PC = (int32_t)0xBFC00000;
8789 /* SMP not implemented */
8790 env->CP0_EBase = 0x80000000;
8791 env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
8792 /* vectored interrupts not implemented, timer on int 7,
8793 no performance counters. */
8794 env->CP0_IntCtl = 0xe0000000;
8798 for (i = 0; i < 7; i++) {
8799 env->CP0_WatchLo[i] = 0;
8800 env->CP0_WatchHi[i] = 0x80000000;
8802 env->CP0_WatchLo[7] = 0;
8803 env->CP0_WatchHi[7] = 0;
8805 /* Count register increments in debug mode, EJTAG version 1 */
8806 env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
8808 env->exception_index = EXCP_NONE;
8809 #if defined(CONFIG_USER_ONLY)
8810 env->hflags = MIPS_HFLAG_UM;
8811 env->user_mode_only = 1;
8813 env->hflags = MIPS_HFLAG_CP0;
8815 cpu_mips_register(env, env->cpu_model);
8818 void gen_pc_load(CPUState *env, TranslationBlock *tb,
8819 unsigned long searched_pc, int pc_pos, void *puc)
8821 env->active_tc.PC = gen_opc_pc[pc_pos];
8822 env->hflags &= ~MIPS_HFLAG_BMASK;
8823 env->hflags |= gen_opc_hflags[pc_pos];