2 * MIPS emulation for qemu: CPU initialisation routines.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2007 Herve Poussineau
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 /* CPU / CPU family specific config register values. */
24 /* Have config1, is MIPS32R1, uses TLB, no virtual icache,
26 #define MIPS_CONFIG0 \
27 ((1 << CP0C0_M) | (0x0 << CP0C0_K23) | (0x0 << CP0C0_KU) | \
28 (0x0 << CP0C0_AT) | (0x0 << CP0C0_AR) | (0x1 << CP0C0_MT) | \
31 /* Have config2, 16 TLB entries, 64 sets Icache, 16 bytes Icache line,
32 2-way Icache, 64 sets Dcache, 16 bytes Dcache line, 2-way Dcache,
33 no coprocessor2 attached, no MDMX support attached,
34 no performance counters, watch registers present,
35 no code compression, EJTAG present, no FPU */
36 #define MIPS_CONFIG1 \
37 ((1 << CP0C1_M) | ((MIPS_TLB_NB - 1) << CP0C1_MMU) | \
38 (0x0 << CP0C1_IS) | (0x3 << CP0C1_IL) | (0x1 << CP0C1_IA) | \
39 (0x0 << CP0C1_DS) | (0x3 << CP0C1_DL) | (0x1 << CP0C1_DA) | \
40 (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
41 (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
44 /* Have config3, no tertiary/secondary caches implemented */
45 #define MIPS_CONFIG2 \
48 /* No config4, no DSP ASE, no large physaddr,
49 no external interrupt controller, no vectored interupts,
50 no 1kb pages, no MT ASE, no SmartMIPS ASE, no trace logic */
51 #define MIPS_CONFIG3 \
52 ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
53 (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
54 (0 << CP0C3_MT) | (0 << CP0C3_SM) | (0 << CP0C3_TL))
56 /* Define a implementation number of 1.
57 Define a major version 1, minor version 0. */
58 #define MIPS_FCR0 ((0 << 16) | (1 << 8) | (1 << 4) | 0)
62 const unsigned char *name;
73 /*****************************************************************************/
74 /* MIPS CPU definitions */
75 static mips_def_t mips_defs[] =
80 .CP0_PRid = 0x00018000,
81 .CP0_Config0 = MIPS_CONFIG0,
82 .CP0_Config1 = MIPS_CONFIG1,
83 .CP0_Config2 = MIPS_CONFIG2,
84 .CP0_Config3 = MIPS_CONFIG3,
85 .CP1_fcr0 = MIPS_FCR0,
89 .CP0_PRid = 0x00018400,
90 .CP0_Config0 = MIPS_CONFIG0,
91 .CP0_Config1 = MIPS_CONFIG1,
92 .CP0_Config2 = MIPS_CONFIG2,
93 .CP0_Config3 = MIPS_CONFIG3,
94 .CP1_fcr0 = MIPS_FCR0,
98 .CP0_PRid = 0x00019000,
99 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
100 .CP0_Config1 = MIPS_CONFIG1,
101 .CP0_Config2 = MIPS_CONFIG2,
102 .CP0_Config3 = MIPS_CONFIG3,
103 .CP1_fcr0 = MIPS_FCR0,
107 .CP0_PRid = 0x00019300,
108 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
109 .CP0_Config1 = MIPS_CONFIG1,
110 .CP0_Config2 = MIPS_CONFIG2,
111 .CP0_Config3 = MIPS_CONFIG3,
112 .CP1_fcr0 = MIPS_FCR0,
116 .CP0_PRid = 0x00019300,
117 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
118 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP),
119 .CP0_Config2 = MIPS_CONFIG2,
120 .CP0_Config3 = MIPS_CONFIG3,
121 .CP1_fcr0 = MIPS_FCR0,
126 .CP0_PRid = 0x00000400,
127 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT),
128 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP),
129 .CP0_Config2 = MIPS_CONFIG2,
130 .CP0_Config3 = MIPS_CONFIG3,
131 .CP1_fcr0 = MIPS_FCR0,
136 int mips_find_by_name (const unsigned char *name, mips_def_t **def)
142 for (i = 0; i < sizeof(mips_defs) / sizeof(mips_defs[0]); i++) {
143 if (strcasecmp(name, mips_defs[i].name) == 0) {
144 *def = &mips_defs[i];
153 void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
157 for (i = 0; i < sizeof(mips_defs) / sizeof(mips_defs[0]); i++) {
158 (*cpu_fprintf)(f, "MIPS '%s'\n",
163 int cpu_mips_register (CPUMIPSState *env, mips_def_t *def)
166 cpu_abort(env, "Unable to find MIPS CPU definition\n");
167 env->CP0_PRid = def->CP0_PRid;
168 #ifdef TARGET_WORDS_BIGENDIAN
169 env->CP0_Config0 = def->CP0_Config0 | (1 << CP0C0_BE);
171 env->CP0_Config0 = def->CP0_Config0;
173 env->CP0_Config1 = def->CP0_Config1;
174 env->CP0_Config2 = def->CP0_Config2;
175 env->CP0_Config3 = def->CP0_Config3;
176 env->CP0_Config6 = def->CP0_Config6;
177 env->CP0_Config7 = def->CP0_Config7;
178 env->fcr0 = def->CP1_fcr0;