2 * MIPS emulation for qemu: CPU initialisation routines.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2007 Herve Poussineau
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 /* CPU / CPU family specific config register values. */
24 /* Have config1, is MIPS32R1, uses TLB, no virtual icache,
26 #define MIPS_CONFIG0 \
27 ((1 << CP0C0_M) | (0x0 << CP0C0_K23) | (0x0 << CP0C0_KU) | \
28 (0x0 << CP0C0_AT) | (0x0 << CP0C0_AR) | (0x1 << CP0C0_MT) | \
31 /* Have config2, 64 sets Icache, 16 bytes Icache line,
32 2-way Icache, 64 sets Dcache, 16 bytes Dcache line, 2-way Dcache,
33 no coprocessor2 attached, no MDMX support attached,
34 no performance counters, watch registers present,
35 no code compression, EJTAG present, no FPU */
36 #define MIPS_CONFIG1 \
38 (0x0 << CP0C1_IS) | (0x3 << CP0C1_IL) | (0x1 << CP0C1_IA) | \
39 (0x0 << CP0C1_DS) | (0x3 << CP0C1_DL) | (0x1 << CP0C1_DA) | \
40 (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
41 (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
44 /* Have config3, no tertiary/secondary caches implemented */
45 #define MIPS_CONFIG2 \
48 /* No config4, no DSP ASE, no large physaddr,
49 no external interrupt controller, no vectored interupts,
50 no 1kb pages, no MT ASE, no SmartMIPS ASE, no trace logic */
51 #define MIPS_CONFIG3 \
52 ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
53 (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
54 (0 << CP0C3_MT) | (0 << CP0C3_SM) | (0 << CP0C3_TL))
56 /* Define a implementation number of 1.
57 Define a major version 1, minor version 0. */
58 #define MIPS_FCR0 ((0 << FCR0_S) | (0x1 << FCR0_PRID) | (0x10 << FCR0_REV))
62 const unsigned char *name;
72 int32_t Status_rw_bitmask;
76 /*****************************************************************************/
77 /* MIPS CPU definitions */
78 static mips_def_t mips_defs[] =
83 .CP0_PRid = 0x00018000,
84 .CP0_Config0 = MIPS_CONFIG0,
85 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU),
86 .CP0_Config2 = MIPS_CONFIG2,
87 .CP0_Config3 = MIPS_CONFIG3,
90 .Status_rw_bitmask = 0x3278FF17,
94 .CP0_PRid = 0x00018400,
95 .CP0_Config0 = MIPS_CONFIG0,
96 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU),
97 .CP0_Config2 = MIPS_CONFIG2,
98 .CP0_Config3 = MIPS_CONFIG3,
101 .Status_rw_bitmask = 0x3278FF17,
105 .CP0_PRid = 0x00019000,
106 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
107 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU),
108 .CP0_Config2 = MIPS_CONFIG2,
109 .CP0_Config3 = MIPS_CONFIG3,
112 .Status_rw_bitmask = 0x3278FF17,
116 .CP0_PRid = 0x00019300,
117 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
118 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU),
119 .CP0_Config2 = MIPS_CONFIG2,
120 .CP0_Config3 = MIPS_CONFIG3,
123 .Status_rw_bitmask = 0x3278FF17,
127 .CP0_PRid = 0x00019300,
128 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
129 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU),
130 .CP0_Config2 = MIPS_CONFIG2,
131 .CP0_Config3 = MIPS_CONFIG3,
134 .Status_rw_bitmask = 0x3678FF17,
135 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
136 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
141 .CP0_PRid = 0x00000400,
142 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT),
143 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU),
144 .CP0_Config2 = MIPS_CONFIG2,
145 .CP0_Config3 = MIPS_CONFIG3,
148 .Status_rw_bitmask = 0x3678FFFF,
149 /* The R4000 has a full 64bit FPU doesn't use the fcr0 bits. */
150 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
154 .CP0_PRid = 0x00018100,
155 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT),
156 .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
157 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
158 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
159 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
160 .CP0_Config2 = MIPS_CONFIG2,
161 .CP0_Config3 = MIPS_CONFIG3,
164 .Status_rw_bitmask = 0x32F8FFFF,
168 .CP0_PRid = 0x00018100,
169 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT),
170 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
171 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
172 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
173 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
174 .CP0_Config2 = MIPS_CONFIG2,
175 .CP0_Config3 = MIPS_CONFIG3,
178 .Status_rw_bitmask = 0x36F8FFFF,
179 /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
180 .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
181 (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
185 /* We emulate a later version of the 20Kc, earlier ones had a broken
187 .CP0_PRid = 0x000182a0,
188 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | (1 << CP0C0_VI),
189 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) |
190 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
191 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
192 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
193 .CP0_Config2 = MIPS_CONFIG2,
194 .CP0_Config3 = MIPS_CONFIG3,
197 .Status_rw_bitmask = 0x36FBFFFF,
198 /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
199 .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
200 (1 << FCR0_D) | (1 << FCR0_S) |
201 (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
206 int mips_find_by_name (const unsigned char *name, mips_def_t **def)
212 for (i = 0; i < sizeof(mips_defs) / sizeof(mips_defs[0]); i++) {
213 if (strcasecmp(name, mips_defs[i].name) == 0) {
214 *def = &mips_defs[i];
223 void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
227 for (i = 0; i < sizeof(mips_defs) / sizeof(mips_defs[0]); i++) {
228 (*cpu_fprintf)(f, "MIPS '%s'\n",
233 #ifndef CONFIG_USER_ONLY
234 static void no_mmu_init (CPUMIPSState *env, mips_def_t *def)
237 env->map_address = &no_mmu_map_address;
240 static void fixed_mmu_init (CPUMIPSState *env, mips_def_t *def)
243 env->map_address = &fixed_mmu_map_address;
246 static void r4k_mmu_init (CPUMIPSState *env, mips_def_t *def)
248 env->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
249 env->map_address = &r4k_map_address;
250 env->do_tlbwi = r4k_do_tlbwi;
251 env->do_tlbwr = r4k_do_tlbwr;
252 env->do_tlbp = r4k_do_tlbp;
253 env->do_tlbr = r4k_do_tlbr;
255 #endif /* CONFIG_USER_ONLY */
257 int cpu_mips_register (CPUMIPSState *env, mips_def_t *def)
260 def = env->cpu_model;
262 cpu_abort(env, "Unable to find MIPS CPU definition\n");
263 env->cpu_model = def;
264 env->CP0_PRid = def->CP0_PRid;
265 env->CP0_Config0 = def->CP0_Config0;
266 #ifdef TARGET_WORDS_BIGENDIAN
267 env->CP0_Config0 |= (1 << CP0C0_BE);
269 env->CP0_Config1 = def->CP0_Config1;
270 env->CP0_Config2 = def->CP0_Config2;
271 env->CP0_Config3 = def->CP0_Config3;
272 env->CP0_Config6 = def->CP0_Config6;
273 env->CP0_Config7 = def->CP0_Config7;
274 env->SYNCI_Step = def->SYNCI_Step;
275 env->CCRes = def->CCRes;
276 env->Status_rw_bitmask = def->Status_rw_bitmask;
277 env->fcr0 = def->CP1_fcr0;
278 #ifdef CONFIG_USER_ONLY
279 if (env->CP0_Config1 & (1 << CP0C1_FP))
280 env->hflags |= MIPS_HFLAG_FPU;
281 if (env->fcr0 & (1 << FCR0_F64))
282 env->hflags |= MIPS_HFLAG_F64;
284 /* There are more full-featured MMU variants in older MIPS CPUs,
285 R3000, R6000 and R8000 come to mind. If we ever support them,
286 this check will need to look up a different place than those
287 newfangled config registers. */
288 switch ((env->CP0_Config0 >> CP0C0_MT) & 3) {
290 no_mmu_init(env, def);
293 r4k_mmu_init(env, def);
296 fixed_mmu_init(env, def);
299 cpu_abort(env, "MMU type not supported\n");
301 env->CP0_Random = env->nb_tlb - 1;
302 env->tlb_in_use = env->nb_tlb;
303 #endif /* CONFIG_USER_ONLY */