2 * PowerPC emulation cpu definitions for qemu.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #if !defined (__CPU_PPC_H__)
26 #if defined (TARGET_PPC64)
27 typedef uint64_t ppc_gpr_t;
28 #define TARGET_GPR_BITS 64
29 #define TARGET_LONG_BITS 64
30 #define REGX "%016" PRIx64
31 #define TARGET_PAGE_BITS 12
32 #elif defined(TARGET_PPCEMB)
33 /* BookE have 36 bits physical address space */
34 #define TARGET_PHYS_ADDR_BITS 64
35 /* GPR are 64 bits: used by vector extension */
36 typedef uint64_t ppc_gpr_t;
37 #define TARGET_GPR_BITS 64
38 #define TARGET_LONG_BITS 32
39 #define REGX "%016" PRIx64
40 #if defined(CONFIG_USER_ONLY)
41 /* It looks like a lot of Linux programs assume page size
42 * is 4kB long. This is evil, but we have to deal with it...
44 #define TARGET_PAGE_BITS 12
46 /* Pages can be 1 kB small */
47 #define TARGET_PAGE_BITS 10
50 #if (HOST_LONG_BITS >= 64)
51 /* When using 64 bits temporary registers,
52 * we can use 64 bits GPR with no extra cost
53 * It's even an optimization as it will prevent
54 * the compiler to do unuseful masking in the micro-ops.
56 typedef uint64_t ppc_gpr_t;
57 #define TARGET_GPR_BITS 64
58 #define REGX "%08" PRIx64
60 typedef uint32_t ppc_gpr_t;
61 #define TARGET_GPR_BITS 32
62 #define REGX "%08" PRIx32
64 #define TARGET_LONG_BITS 32
65 #define TARGET_PAGE_BITS 12
70 #define ADDRX TARGET_FMT_lx
71 #define PADDRX TARGET_FMT_plx
75 #include "softfloat.h"
77 #define TARGET_HAS_ICE 1
79 #if defined (TARGET_PPC64)
80 #define ELF_MACHINE EM_PPC64
82 #define ELF_MACHINE EM_PPC
85 /* XXX: this should be tunable: PowerPC 601 & 64 bits PowerPC
86 * have different cache line sizes
88 #define ICACHE_LINE_SIZE 32
89 #define DCACHE_LINE_SIZE 32
91 /*****************************************************************************/
94 POWERPC_MMU_UNKNOWN = 0,
95 /* Standard 32 bits PowerPC MMU */
97 /* Standard 64 bits PowerPC MMU */
101 /* PowerPC 6xx MMU with software TLB */
102 POWERPC_MMU_SOFT_6xx,
103 /* PowerPC 74xx MMU with software TLB */
104 POWERPC_MMU_SOFT_74xx,
105 /* PowerPC 4xx MMU with software TLB */
106 POWERPC_MMU_SOFT_4xx,
107 /* PowerPC 4xx MMU with software TLB and zones protections */
108 POWERPC_MMU_SOFT_4xx_Z,
109 /* PowerPC 4xx MMU in real mode only */
110 POWERPC_MMU_REAL_4xx,
111 /* BookE MMU model */
113 /* BookE FSL MMU model */
114 POWERPC_MMU_BOOKE_FSL,
115 /* 64 bits "bridge" PowerPC MMU */
116 POWERPC_MMU_64BRIDGE,
119 /*****************************************************************************/
120 /* Exception model */
122 POWERPC_EXCP_UNKNOWN = 0,
123 /* Standard PowerPC exception model */
125 /* PowerPC 40x exception model */
127 /* PowerPC 601 exception model */
129 /* PowerPC 602 exception model */
131 /* PowerPC 603 exception model */
133 /* PowerPC 603e exception model */
135 /* PowerPC G2 exception model */
137 /* PowerPC 604 exception model */
139 /* PowerPC 7x0 exception model */
141 /* PowerPC 7x5 exception model */
143 /* PowerPC 74xx exception model */
145 /* PowerPC 970 exception model */
147 /* BookE exception model */
151 /*****************************************************************************/
152 /* Input pins model */
154 PPC_FLAGS_INPUT_UNKNOWN = 0,
155 /* PowerPC 6xx bus */
158 PPC_FLAGS_INPUT_BookE,
159 /* PowerPC 405 bus */
161 /* PowerPC 970 bus */
163 /* PowerPC 401 bus */
167 #define PPC_INPUT(env) (env->bus_model)
169 typedef struct ppc_def_t ppc_def_t;
170 typedef struct opc_handler_t opc_handler_t;
172 /*****************************************************************************/
173 /* Types used to describe some PowerPC registers */
174 typedef struct CPUPPCState CPUPPCState;
175 typedef struct ppc_tb_t ppc_tb_t;
176 typedef struct ppc_spr_t ppc_spr_t;
177 typedef struct ppc_dcr_t ppc_dcr_t;
178 typedef struct ppc_avr_t ppc_avr_t;
179 typedef union ppc_tlb_t ppc_tlb_t;
181 /* SPR access micro-ops generations callbacks */
183 void (*uea_read)(void *opaque, int spr_num);
184 void (*uea_write)(void *opaque, int spr_num);
185 #if !defined(CONFIG_USER_ONLY)
186 void (*oea_read)(void *opaque, int spr_num);
187 void (*oea_write)(void *opaque, int spr_num);
189 const unsigned char *name;
192 /* Altivec registers (128 bits) */
197 /* Software TLB cache */
198 typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
199 struct ppc6xx_tlb_t {
205 typedef struct ppcemb_tlb_t ppcemb_tlb_t;
206 struct ppcemb_tlb_t {
207 target_phys_addr_t RPN;
212 uint32_t attr; /* Storage attributes */
220 /*****************************************************************************/
221 /* Machine state register bits definition */
222 #define MSR_SF 63 /* Sixty-four-bit mode hflags */
223 #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
224 #define MSR_HV 60 /* hypervisor state hflags */
225 #define MSR_CM 31 /* Computation mode for BookE hflags */
226 #define MSR_ICM 30 /* Interrupt computation mode for BookE */
227 #define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
228 #define MSR_VR 25 /* altivec available hflags */
229 #define MSR_SPE 25 /* SPE enable for BookE hflags */
230 #define MSR_AP 23 /* Access privilege state on 602 hflags */
231 #define MSR_SA 22 /* Supervisor access mode on 602 hflags */
232 #define MSR_KEY 19 /* key bit on 603e */
233 #define MSR_POW 18 /* Power management */
234 #define MSR_WE 18 /* Wait state enable on embedded PowerPC */
235 #define MSR_TGPR 17 /* TGPR usage on 602/603 */
236 #define MSR_TLB 17 /* TLB update on ? */
237 #define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC */
238 #define MSR_ILE 16 /* Interrupt little-endian mode */
239 #define MSR_EE 15 /* External interrupt enable */
240 #define MSR_PR 14 /* Problem state hflags */
241 #define MSR_FP 13 /* Floating point available hflags */
242 #define MSR_ME 12 /* Machine check interrupt enable */
243 #define MSR_FE0 11 /* Floating point exception mode 0 hflags */
244 #define MSR_SE 10 /* Single-step trace enable hflags */
245 #define MSR_DWE 10 /* Debug wait enable on 405 */
246 #define MSR_UBLE 10 /* User BTB lock enable on e500 */
247 #define MSR_BE 9 /* Branch trace enable hflags */
248 #define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC */
249 #define MSR_FE1 8 /* Floating point exception mode 1 hflags */
250 #define MSR_AL 7 /* AL bit on POWER */
251 #define MSR_IP 6 /* Interrupt prefix */
252 #define MSR_IR 5 /* Instruction relocate */
253 #define MSR_IS 5 /* Instruction address space on embedded PowerPC */
254 #define MSR_DR 4 /* Data relocate */
255 #define MSR_DS 4 /* Data address space on embedded PowerPC */
256 #define MSR_PE 3 /* Protection enable on 403 */
257 #define MSR_EP 3 /* Exception prefix on 601 */
258 #define MSR_PX 2 /* Protection exclusive on 403 */
259 #define MSR_PMM 2 /* Performance monitor mark on POWER */
260 #define MSR_RI 1 /* Recoverable interrupt */
261 #define MSR_LE 0 /* Little-endian mode hflags */
262 #define msr_sf env->msr[MSR_SF]
263 #define msr_isf env->msr[MSR_ISF]
264 #define msr_hv env->msr[MSR_HV]
265 #define msr_cm env->msr[MSR_CM]
266 #define msr_icm env->msr[MSR_ICM]
267 #define msr_ucle env->msr[MSR_UCLE]
268 #define msr_vr env->msr[MSR_VR]
269 #define msr_spe env->msr[MSR_SPE]
270 #define msr_ap env->msr[MSR_AP]
271 #define msr_sa env->msr[MSR_SA]
272 #define msr_key env->msr[MSR_KEY]
273 #define msr_pow env->msr[MSR_POW]
274 #define msr_we env->msr[MSR_WE]
275 #define msr_tgpr env->msr[MSR_TGPR]
276 #define msr_tlb env->msr[MSR_TLB]
277 #define msr_ce env->msr[MSR_CE]
278 #define msr_ile env->msr[MSR_ILE]
279 #define msr_ee env->msr[MSR_EE]
280 #define msr_pr env->msr[MSR_PR]
281 #define msr_fp env->msr[MSR_FP]
282 #define msr_me env->msr[MSR_ME]
283 #define msr_fe0 env->msr[MSR_FE0]
284 #define msr_se env->msr[MSR_SE]
285 #define msr_dwe env->msr[MSR_DWE]
286 #define msr_uble env->msr[MSR_UBLE]
287 #define msr_be env->msr[MSR_BE]
288 #define msr_de env->msr[MSR_DE]
289 #define msr_fe1 env->msr[MSR_FE1]
290 #define msr_al env->msr[MSR_AL]
291 #define msr_ip env->msr[MSR_IP]
292 #define msr_ir env->msr[MSR_IR]
293 #define msr_is env->msr[MSR_IS]
294 #define msr_dr env->msr[MSR_DR]
295 #define msr_ds env->msr[MSR_DS]
296 #define msr_pe env->msr[MSR_PE]
297 #define msr_ep env->msr[MSR_EP]
298 #define msr_px env->msr[MSR_PX]
299 #define msr_pmm env->msr[MSR_PMM]
300 #define msr_ri env->msr[MSR_RI]
301 #define msr_le env->msr[MSR_LE]
303 /*****************************************************************************/
304 /* The whole PowerPC CPU context */
306 /* First are the most commonly used resources
307 * during translated code execution
309 #if TARGET_GPR_BITS > HOST_LONG_BITS
310 /* temporary fixed-point registers
311 * used to emulate 64 bits target on 32 bits hosts
313 ppc_gpr_t t0, t1, t2;
315 ppc_avr_t t0_avr, t1_avr, t2_avr;
317 /* general purpose registers */
323 /* condition register */
326 /* XXX: We use only 5 fields, but we want to keep the structure aligned */
328 /* Reservation address */
329 target_ulong reserve;
331 /* Those ones are used in supervisor mode only */
332 /* machine state register */
334 /* temporary general purpose registers */
335 ppc_gpr_t tgpr[4]; /* Used to speed-up TLB assist handlers */
337 /* Floating point execution context */
338 /* temporary float registers */
342 float_status fp_status;
343 /* floating point registers */
345 /* floating point status and control register */
350 int halted; /* TRUE if the CPU is in suspend state */
352 int access_type; /* when a memory exception occurs, the access
353 type is stored here */
356 /* Address space register */
358 /* segment registers */
363 target_ulong DBAT[2][8];
364 target_ulong IBAT[2][8];
366 /* Other registers */
367 /* Special purpose registers */
368 target_ulong spr[1024];
369 /* Altivec registers */
374 float_status spe_status;
377 /* Internal devices resources */
378 /* Time base and decrementer */
380 /* Device control registers */
383 /* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */
384 int nb_tlb; /* Total number of TLB */
385 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
386 int nb_ways; /* Number of ways in the TLB set */
387 int last_way; /* Last used way used to allocate TLB in a LRU way */
388 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
389 int nb_pids; /* Number of available PID registers */
390 ppc_tlb_t *tlb; /* TLB is optional. Allocate them only if needed */
391 /* 403 dedicated access protection registers */
394 /* Those resources are used during exception processing */
395 /* CPU model definition */
396 target_ulong msr_mask;
405 int interrupt_request;
406 uint32_t pending_interrupts;
407 #if !defined(CONFIG_USER_ONLY)
408 /* This is the IRQ controller, which is implementation dependant
409 * and only relevant when emulating a complete machine.
411 uint32_t irq_input_state;
415 /* Those resources are used only during code translation */
416 /* Next instruction pointer */
418 /* SPR translation callbacks */
419 ppc_spr_t spr_cb[1024];
420 /* opcode handlers */
421 opc_handler_t *opcodes[0x40];
423 /* Those resources are used only in Qemu core */
425 int user_mode_only; /* user mode only simulation */
426 target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
428 /* Power management */
431 /* temporary hack to handle OSI calls (only used if non NULL) */
432 int (*osi_call)(struct CPUPPCState *env);
435 /* Context used internally during MMU translations */
436 typedef struct mmu_ctx_t mmu_ctx_t;
438 target_phys_addr_t raddr; /* Real address */
439 int prot; /* Protection bits */
440 target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */
441 target_ulong ptem; /* Virtual segment ID | API */
442 int key; /* Access key */
445 /*****************************************************************************/
446 CPUPPCState *cpu_ppc_init (void);
447 int cpu_ppc_exec (CPUPPCState *s);
448 void cpu_ppc_close (CPUPPCState *s);
449 /* you can call this signal handler from your SIGBUS and SIGSEGV
450 signal handlers to inform the virtual CPU of exceptions. non zero
451 is returned if the signal was handled by the virtual CPU. */
452 int cpu_ppc_signal_handler (int host_signum, void *pinfo,
455 void do_interrupt (CPUPPCState *env);
456 void ppc_hw_interrupt (CPUPPCState *env);
457 void cpu_loop_exit (void);
459 void dump_stack (CPUPPCState *env);
461 #if !defined(CONFIG_USER_ONLY)
462 target_ulong do_load_ibatu (CPUPPCState *env, int nr);
463 target_ulong do_load_ibatl (CPUPPCState *env, int nr);
464 void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value);
465 void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value);
466 target_ulong do_load_dbatu (CPUPPCState *env, int nr);
467 target_ulong do_load_dbatl (CPUPPCState *env, int nr);
468 void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value);
469 void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value);
470 target_ulong do_load_sdr1 (CPUPPCState *env);
471 void do_store_sdr1 (CPUPPCState *env, target_ulong value);
472 #if defined(TARGET_PPC64)
473 target_ulong ppc_load_asr (CPUPPCState *env);
474 void ppc_store_asr (CPUPPCState *env, target_ulong value);
476 target_ulong do_load_sr (CPUPPCState *env, int srnum);
477 void do_store_sr (CPUPPCState *env, int srnum, target_ulong value);
479 uint32_t ppc_load_xer (CPUPPCState *env);
480 void ppc_store_xer (CPUPPCState *env, uint32_t value);
481 target_ulong do_load_msr (CPUPPCState *env);
482 void do_store_msr (CPUPPCState *env, target_ulong value);
483 void ppc_store_msr_32 (CPUPPCState *env, uint32_t value);
485 void do_compute_hflags (CPUPPCState *env);
486 void cpu_ppc_reset (void *opaque);
487 CPUPPCState *cpu_ppc_init (void);
488 void cpu_ppc_close(CPUPPCState *env);
490 int ppc_find_by_name (const unsigned char *name, ppc_def_t **def);
491 int ppc_find_by_pvr (uint32_t apvr, ppc_def_t **def);
492 void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
493 int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def);
495 /* Time-base and decrementer management */
496 #ifndef NO_CPU_IO_DEFS
497 uint32_t cpu_ppc_load_tbl (CPUPPCState *env);
498 uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
499 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
500 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
501 uint32_t cpu_ppc_load_decr (CPUPPCState *env);
502 void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
503 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
504 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
505 #if !defined(CONFIG_USER_ONLY)
506 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
507 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
508 target_ulong load_40x_pit (CPUPPCState *env);
509 void store_40x_pit (CPUPPCState *env, target_ulong val);
510 void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
511 void store_40x_sler (CPUPPCState *env, uint32_t val);
512 void store_booke_tcr (CPUPPCState *env, target_ulong val);
513 void store_booke_tsr (CPUPPCState *env, target_ulong val);
514 void ppc_tlb_invalidate_all (CPUPPCState *env);
515 int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid);
519 /* Device control registers */
520 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp);
521 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
523 #define CPUState CPUPPCState
524 #define cpu_init cpu_ppc_init
525 #define cpu_exec cpu_ppc_exec
526 #define cpu_gen_code cpu_ppc_gen_code
527 #define cpu_signal_handler cpu_ppc_signal_handler
531 /*****************************************************************************/
532 /* Registers definitions */
538 #define xer_so env->xer[4]
539 #define xer_ov env->xer[6]
540 #define xer_ca env->xer[2]
541 #define xer_cmp env->xer[1]
542 #define xer_bc env->xer[0]
544 /* SPR definitions */
545 #define SPR_MQ (0x000)
546 #define SPR_XER (0x001)
547 #define SPR_601_VRTCU (0x004)
548 #define SPR_601_VRTCL (0x005)
549 #define SPR_601_UDECR (0x006)
550 #define SPR_LR (0x008)
551 #define SPR_CTR (0x009)
552 #define SPR_DSISR (0x012)
553 #define SPR_DAR (0x013) /* DAE for PowerPC 601 */
554 #define SPR_601_RTCU (0x014)
555 #define SPR_601_RTCL (0x015)
556 #define SPR_DECR (0x016)
557 #define SPR_SDR1 (0x019)
558 #define SPR_SRR0 (0x01A)
559 #define SPR_SRR1 (0x01B)
560 #define SPR_AMR (0x01D)
561 #define SPR_BOOKE_PID (0x030)
562 #define SPR_BOOKE_DECAR (0x036)
563 #define SPR_BOOKE_CSRR0 (0x03A)
564 #define SPR_BOOKE_CSRR1 (0x03B)
565 #define SPR_BOOKE_DEAR (0x03D)
566 #define SPR_BOOKE_ESR (0x03E)
567 #define SPR_BOOKE_IVPR (0x03F)
568 #define SPR_8xx_EIE (0x050)
569 #define SPR_8xx_EID (0x051)
570 #define SPR_8xx_NRE (0x052)
571 #define SPR_CTRL (0x088)
572 #define SPR_58x_CMPA (0x090)
573 #define SPR_58x_CMPB (0x091)
574 #define SPR_58x_CMPC (0x092)
575 #define SPR_58x_CMPD (0x093)
576 #define SPR_58x_ICR (0x094)
577 #define SPR_58x_DER (0x094)
578 #define SPR_58x_COUNTA (0x096)
579 #define SPR_58x_COUNTB (0x097)
580 #define SPR_UCTRL (0x098)
581 #define SPR_58x_CMPE (0x098)
582 #define SPR_58x_CMPF (0x099)
583 #define SPR_58x_CMPG (0x09A)
584 #define SPR_58x_CMPH (0x09B)
585 #define SPR_58x_LCTRL1 (0x09C)
586 #define SPR_58x_LCTRL2 (0x09D)
587 #define SPR_58x_ICTRL (0x09E)
588 #define SPR_58x_BAR (0x09F)
589 #define SPR_VRSAVE (0x100)
590 #define SPR_USPRG0 (0x100)
591 #define SPR_USPRG1 (0x101)
592 #define SPR_USPRG2 (0x102)
593 #define SPR_USPRG3 (0x103)
594 #define SPR_USPRG4 (0x104)
595 #define SPR_USPRG5 (0x105)
596 #define SPR_USPRG6 (0x106)
597 #define SPR_USPRG7 (0x107)
598 #define SPR_VTBL (0x10C)
599 #define SPR_VTBU (0x10D)
600 #define SPR_SPRG0 (0x110)
601 #define SPR_SPRG1 (0x111)
602 #define SPR_SPRG2 (0x112)
603 #define SPR_SPRG3 (0x113)
604 #define SPR_SPRG4 (0x114)
605 #define SPR_SCOMC (0x114)
606 #define SPR_SPRG5 (0x115)
607 #define SPR_SCOMD (0x115)
608 #define SPR_SPRG6 (0x116)
609 #define SPR_SPRG7 (0x117)
610 #define SPR_ASR (0x118)
611 #define SPR_EAR (0x11A)
612 #define SPR_TBL (0x11C)
613 #define SPR_TBU (0x11D)
614 #define SPR_TBU40 (0x11E)
615 #define SPR_SVR (0x11E)
616 #define SPR_BOOKE_PIR (0x11E)
617 #define SPR_PVR (0x11F)
618 #define SPR_HSPRG0 (0x130)
619 #define SPR_BOOKE_DBSR (0x130)
620 #define SPR_HSPRG1 (0x131)
621 #define SPR_HDSISR (0x132)
622 #define SPR_HDAR (0x133)
623 #define SPR_BOOKE_DBCR0 (0x134)
624 #define SPR_IBCR (0x135)
625 #define SPR_PURR (0x135)
626 #define SPR_BOOKE_DBCR1 (0x135)
627 #define SPR_DBCR (0x136)
628 #define SPR_HDEC (0x136)
629 #define SPR_BOOKE_DBCR2 (0x136)
630 #define SPR_HIOR (0x137)
631 #define SPR_MBAR (0x137)
632 #define SPR_RMOR (0x138)
633 #define SPR_BOOKE_IAC1 (0x138)
634 #define SPR_HRMOR (0x139)
635 #define SPR_BOOKE_IAC2 (0x139)
636 #define SPR_HSSR0 (0x13A)
637 #define SPR_BOOKE_IAC3 (0x13A)
638 #define SPR_HSSR1 (0x13B)
639 #define SPR_BOOKE_IAC4 (0x13B)
640 #define SPR_LPCR (0x13C)
641 #define SPR_BOOKE_DAC1 (0x13C)
642 #define SPR_LPIDR (0x13D)
643 #define SPR_DABR2 (0x13D)
644 #define SPR_BOOKE_DAC2 (0x13D)
645 #define SPR_BOOKE_DVC1 (0x13E)
646 #define SPR_BOOKE_DVC2 (0x13F)
647 #define SPR_BOOKE_TSR (0x150)
648 #define SPR_BOOKE_TCR (0x154)
649 #define SPR_BOOKE_IVOR0 (0x190)
650 #define SPR_BOOKE_IVOR1 (0x191)
651 #define SPR_BOOKE_IVOR2 (0x192)
652 #define SPR_BOOKE_IVOR3 (0x193)
653 #define SPR_BOOKE_IVOR4 (0x194)
654 #define SPR_BOOKE_IVOR5 (0x195)
655 #define SPR_BOOKE_IVOR6 (0x196)
656 #define SPR_BOOKE_IVOR7 (0x197)
657 #define SPR_BOOKE_IVOR8 (0x198)
658 #define SPR_BOOKE_IVOR9 (0x199)
659 #define SPR_BOOKE_IVOR10 (0x19A)
660 #define SPR_BOOKE_IVOR11 (0x19B)
661 #define SPR_BOOKE_IVOR12 (0x19C)
662 #define SPR_BOOKE_IVOR13 (0x19D)
663 #define SPR_BOOKE_IVOR14 (0x19E)
664 #define SPR_BOOKE_IVOR15 (0x19F)
665 #define SPR_BOOKE_SPEFSCR (0x200)
666 #define SPR_E500_BBEAR (0x201)
667 #define SPR_E500_BBTAR (0x202)
668 #define SPR_BOOKE_ATBL (0x20E)
669 #define SPR_BOOKE_ATBU (0x20F)
670 #define SPR_IBAT0U (0x210)
671 #define SPR_BOOKE_IVOR32 (0x210)
672 #define SPR_IBAT0L (0x211)
673 #define SPR_BOOKE_IVOR33 (0x211)
674 #define SPR_IBAT1U (0x212)
675 #define SPR_BOOKE_IVOR34 (0x212)
676 #define SPR_IBAT1L (0x213)
677 #define SPR_BOOKE_IVOR35 (0x213)
678 #define SPR_IBAT2U (0x214)
679 #define SPR_BOOKE_IVOR36 (0x214)
680 #define SPR_IBAT2L (0x215)
681 #define SPR_E500_L1CFG0 (0x215)
682 #define SPR_BOOKE_IVOR37 (0x215)
683 #define SPR_IBAT3U (0x216)
684 #define SPR_E500_L1CFG1 (0x216)
685 #define SPR_IBAT3L (0x217)
686 #define SPR_DBAT0U (0x218)
687 #define SPR_DBAT0L (0x219)
688 #define SPR_DBAT1U (0x21A)
689 #define SPR_DBAT1L (0x21B)
690 #define SPR_DBAT2U (0x21C)
691 #define SPR_DBAT2L (0x21D)
692 #define SPR_DBAT3U (0x21E)
693 #define SPR_DBAT3L (0x21F)
694 #define SPR_IBAT4U (0x230)
695 #define SPR_IBAT4L (0x231)
696 #define SPR_IBAT5U (0x232)
697 #define SPR_IBAT5L (0x233)
698 #define SPR_IBAT6U (0x234)
699 #define SPR_IBAT6L (0x235)
700 #define SPR_IBAT7U (0x236)
701 #define SPR_IBAT7L (0x237)
702 #define SPR_DBAT4U (0x238)
703 #define SPR_DBAT4L (0x239)
704 #define SPR_DBAT5U (0x23A)
705 #define SPR_BOOKE_MCSRR0 (0x23A)
706 #define SPR_DBAT5L (0x23B)
707 #define SPR_BOOKE_MCSRR1 (0x23B)
708 #define SPR_DBAT6U (0x23C)
709 #define SPR_BOOKE_MCSR (0x23C)
710 #define SPR_DBAT6L (0x23D)
711 #define SPR_E500_MCAR (0x23D)
712 #define SPR_DBAT7U (0x23E)
713 #define SPR_BOOKE_DSRR0 (0x23E)
714 #define SPR_DBAT7L (0x23F)
715 #define SPR_BOOKE_DSRR1 (0x23F)
716 #define SPR_BOOKE_SPRG8 (0x25C)
717 #define SPR_BOOKE_SPRG9 (0x25D)
718 #define SPR_BOOKE_MAS0 (0x270)
719 #define SPR_BOOKE_MAS1 (0x271)
720 #define SPR_BOOKE_MAS2 (0x272)
721 #define SPR_BOOKE_MAS3 (0x273)
722 #define SPR_BOOKE_MAS4 (0x274)
723 #define SPR_BOOKE_MAS6 (0x276)
724 #define SPR_BOOKE_PID1 (0x279)
725 #define SPR_BOOKE_PID2 (0x27A)
726 #define SPR_BOOKE_TLB0CFG (0x2B0)
727 #define SPR_BOOKE_TLB1CFG (0x2B1)
728 #define SPR_BOOKE_TLB2CFG (0x2B2)
729 #define SPR_BOOKE_TLB3CFG (0x2B3)
730 #define SPR_BOOKE_EPR (0x2BE)
731 #define SPR_PERF0 (0x300)
732 #define SPR_PERF1 (0x301)
733 #define SPR_PERF2 (0x302)
734 #define SPR_PERF3 (0x303)
735 #define SPR_PERF4 (0x304)
736 #define SPR_PERF5 (0x305)
737 #define SPR_PERF6 (0x306)
738 #define SPR_PERF7 (0x307)
739 #define SPR_PERF8 (0x308)
740 #define SPR_PERF9 (0x309)
741 #define SPR_PERFA (0x30A)
742 #define SPR_PERFB (0x30B)
743 #define SPR_PERFC (0x30C)
744 #define SPR_PERFD (0x30D)
745 #define SPR_PERFE (0x30E)
746 #define SPR_PERFF (0x30F)
747 #define SPR_UPERF0 (0x310)
748 #define SPR_UPERF1 (0x311)
749 #define SPR_UPERF2 (0x312)
750 #define SPR_UPERF3 (0x313)
751 #define SPR_UPERF4 (0x314)
752 #define SPR_UPERF5 (0x315)
753 #define SPR_UPERF6 (0x316)
754 #define SPR_UPERF7 (0x317)
755 #define SPR_UPERF8 (0x318)
756 #define SPR_UPERF9 (0x319)
757 #define SPR_UPERFA (0x31A)
758 #define SPR_UPERFB (0x31B)
759 #define SPR_UPERFC (0x31C)
760 #define SPR_UPERFD (0x31D)
761 #define SPR_UPERFE (0x31E)
762 #define SPR_UPERFF (0x31F)
763 #define SPR_440_INV0 (0x370)
764 #define SPR_440_INV1 (0x371)
765 #define SPR_440_INV2 (0x372)
766 #define SPR_440_INV3 (0x373)
767 #define SPR_440_ITV0 (0x374)
768 #define SPR_440_ITV1 (0x375)
769 #define SPR_440_ITV2 (0x376)
770 #define SPR_440_ITV3 (0x377)
771 #define SPR_440_CCR1 (0x378)
772 #define SPR_DCRIPR (0x37B)
773 #define SPR_PPR (0x380)
774 #define SPR_440_DNV0 (0x390)
775 #define SPR_440_DNV1 (0x391)
776 #define SPR_440_DNV2 (0x392)
777 #define SPR_440_DNV3 (0x393)
778 #define SPR_440_DTV0 (0x394)
779 #define SPR_440_DTV1 (0x395)
780 #define SPR_440_DTV2 (0x396)
781 #define SPR_440_DTV3 (0x397)
782 #define SPR_440_DVLIM (0x398)
783 #define SPR_440_IVLIM (0x399)
784 #define SPR_440_RSTCFG (0x39B)
785 #define SPR_BOOKE_DCDBTRL (0x39C)
786 #define SPR_BOOKE_DCDBTRH (0x39D)
787 #define SPR_BOOKE_ICDBTRL (0x39E)
788 #define SPR_BOOKE_ICDBTRH (0x39F)
789 #define SPR_UMMCR2 (0x3A0)
790 #define SPR_UPMC5 (0x3A1)
791 #define SPR_UPMC6 (0x3A2)
792 #define SPR_UBAMR (0x3A7)
793 #define SPR_UMMCR0 (0x3A8)
794 #define SPR_UPMC1 (0x3A9)
795 #define SPR_UPMC2 (0x3AA)
796 #define SPR_USIAR (0x3AB)
797 #define SPR_UMMCR1 (0x3AC)
798 #define SPR_UPMC3 (0x3AD)
799 #define SPR_UPMC4 (0x3AE)
800 #define SPR_USDA (0x3AF)
801 #define SPR_40x_ZPR (0x3B0)
802 #define SPR_BOOKE_MAS7 (0x3B0)
803 #define SPR_620_PMR0 (0x3B0)
804 #define SPR_MMCR2 (0x3B0)
805 #define SPR_PMC5 (0x3B1)
806 #define SPR_40x_PID (0x3B1)
807 #define SPR_620_PMR1 (0x3B1)
808 #define SPR_PMC6 (0x3B2)
809 #define SPR_440_MMUCR (0x3B2)
810 #define SPR_620_PMR2 (0x3B2)
811 #define SPR_4xx_CCR0 (0x3B3)
812 #define SPR_BOOKE_EPLC (0x3B3)
813 #define SPR_620_PMR3 (0x3B3)
814 #define SPR_405_IAC3 (0x3B4)
815 #define SPR_BOOKE_EPSC (0x3B4)
816 #define SPR_620_PMR4 (0x3B4)
817 #define SPR_405_IAC4 (0x3B5)
818 #define SPR_620_PMR5 (0x3B5)
819 #define SPR_405_DVC1 (0x3B6)
820 #define SPR_620_PMR6 (0x3B6)
821 #define SPR_405_DVC2 (0x3B7)
822 #define SPR_620_PMR7 (0x3B7)
823 #define SPR_BAMR (0x3B7)
824 #define SPR_MMCR0 (0x3B8)
825 #define SPR_620_PMR8 (0x3B8)
826 #define SPR_PMC1 (0x3B9)
827 #define SPR_40x_SGR (0x3B9)
828 #define SPR_620_PMR9 (0x3B9)
829 #define SPR_PMC2 (0x3BA)
830 #define SPR_40x_DCWR (0x3BA)
831 #define SPR_620_PMRA (0x3BA)
832 #define SPR_SIAR (0x3BB)
833 #define SPR_405_SLER (0x3BB)
834 #define SPR_620_PMRB (0x3BB)
835 #define SPR_MMCR1 (0x3BC)
836 #define SPR_405_SU0R (0x3BC)
837 #define SPR_620_PMRC (0x3BC)
838 #define SPR_401_SKR (0x3BC)
839 #define SPR_PMC3 (0x3BD)
840 #define SPR_405_DBCR1 (0x3BD)
841 #define SPR_620_PMRD (0x3BD)
842 #define SPR_PMC4 (0x3BE)
843 #define SPR_620_PMRE (0x3BE)
844 #define SPR_SDA (0x3BF)
845 #define SPR_620_PMRF (0x3BF)
846 #define SPR_403_VTBL (0x3CC)
847 #define SPR_403_VTBU (0x3CD)
848 #define SPR_DMISS (0x3D0)
849 #define SPR_DCMP (0x3D1)
850 #define SPR_HASH1 (0x3D2)
851 #define SPR_HASH2 (0x3D3)
852 #define SPR_BOOKE_ICDBDR (0x3D3)
853 #define SPR_TLBMISS (0x3D4)
854 #define SPR_IMISS (0x3D4)
855 #define SPR_40x_ESR (0x3D4)
856 #define SPR_PTEHI (0x3D5)
857 #define SPR_ICMP (0x3D5)
858 #define SPR_40x_DEAR (0x3D5)
859 #define SPR_PTELO (0x3D6)
860 #define SPR_RPA (0x3D6)
861 #define SPR_40x_EVPR (0x3D6)
862 #define SPR_L3PM (0x3D7)
863 #define SPR_403_CDBCR (0x3D7)
864 #define SPR_L3OHCR (0x3D8)
865 #define SPR_TCR (0x3D8)
866 #define SPR_40x_TSR (0x3D8)
867 #define SPR_IBR (0x3DA)
868 #define SPR_40x_TCR (0x3DA)
869 #define SPR_ESASRR (0x3DB)
870 #define SPR_40x_PIT (0x3DB)
871 #define SPR_403_TBL (0x3DC)
872 #define SPR_403_TBU (0x3DD)
873 #define SPR_SEBR (0x3DE)
874 #define SPR_40x_SRR2 (0x3DE)
875 #define SPR_SER (0x3DF)
876 #define SPR_40x_SRR3 (0x3DF)
877 #define SPR_L3ITCR0 (0x3E8)
878 #define SPR_L3ITCR1 (0x3E9)
879 #define SPR_L3ITCR2 (0x3EA)
880 #define SPR_L3ITCR3 (0x3EB)
881 #define SPR_HID0 (0x3F0)
882 #define SPR_40x_DBSR (0x3F0)
883 #define SPR_HID1 (0x3F1)
884 #define SPR_IABR (0x3F2)
885 #define SPR_40x_DBCR0 (0x3F2)
886 #define SPR_601_HID2 (0x3F2)
887 #define SPR_E500_L1CSR0 (0x3F2)
888 #define SPR_ICTRL (0x3F3)
889 #define SPR_HID2 (0x3F3)
890 #define SPR_E500_L1CSR1 (0x3F3)
891 #define SPR_440_DBDR (0x3F3)
892 #define SPR_LDSTDB (0x3F4)
893 #define SPR_40x_IAC1 (0x3F4)
894 #define SPR_BOOKE_MMUCSR0 (0x3F4)
895 #define SPR_DABR (0x3F5)
896 #define DABR_MASK (~(target_ulong)0x7)
897 #define SPR_E500_BUCSR (0x3F5)
898 #define SPR_40x_IAC2 (0x3F5)
899 #define SPR_601_HID5 (0x3F5)
900 #define SPR_40x_DAC1 (0x3F6)
901 #define SPR_MSSCR0 (0x3F6)
902 #define SPR_MSSSR0 (0x3F7)
903 #define SPR_DABRX (0x3F7)
904 #define SPR_40x_DAC2 (0x3F7)
905 #define SPR_BOOKE_MMUCFG (0x3F7)
906 #define SPR_LDSTCR (0x3F8)
907 #define SPR_L2PMCR (0x3F8)
908 #define SPR_750_HID2 (0x3F8)
909 #define SPR_620_HID8 (0x3F8)
910 #define SPR_L2CR (0x3F9)
911 #define SPR_620_HID9 (0x3F9)
912 #define SPR_L3CR (0x3FA)
913 #define SPR_IABR2 (0x3FA)
914 #define SPR_40x_DCCR (0x3FA)
915 #define SPR_ICTC (0x3FB)
916 #define SPR_40x_ICCR (0x3FB)
917 #define SPR_THRM1 (0x3FC)
918 #define SPR_403_PBL1 (0x3FC)
919 #define SPR_SP (0x3FD)
920 #define SPR_THRM2 (0x3FD)
921 #define SPR_403_PBU1 (0x3FD)
922 #define SPR_604_HID13 (0x3FD)
923 #define SPR_LT (0x3FE)
924 #define SPR_THRM3 (0x3FE)
925 #define SPR_FPECR (0x3FE)
926 #define SPR_403_PBL2 (0x3FE)
927 #define SPR_PIR (0x3FF)
928 #define SPR_403_PBU2 (0x3FF)
929 #define SPR_601_HID15 (0x3FF)
930 #define SPR_604_HID15 (0x3FF)
931 #define SPR_E500_SVR (0x3FF)
933 /*****************************************************************************/
934 /* Memory access type :
935 * may be needed for precise access rights control and precise exceptions.
938 /* 1 bit to define user level / supervisor access */
941 /* Type of instruction that generated the access */
942 ACCESS_CODE = 0x10, /* Code fetch access */
943 ACCESS_INT = 0x20, /* Integer load/store access */
944 ACCESS_FLOAT = 0x30, /* floating point load/store access */
945 ACCESS_RES = 0x40, /* load/store with reservation */
946 ACCESS_EXT = 0x50, /* external access */
947 ACCESS_CACHE = 0x60, /* Cache manipulation */
950 /*****************************************************************************/
953 /* PowerPC hardware exceptions : exception vectors defined in PowerPC book 3 */
954 #define EXCP_RESET 0x0100 /* System reset */
955 #define EXCP_MACHINE_CHECK 0x0200 /* Machine check exception */
956 #define EXCP_DSI 0x0300 /* Data storage exception */
957 #define EXCP_DSEG 0x0380 /* Data segment exception */
958 #define EXCP_ISI 0x0400 /* Instruction storage exception */
959 #define EXCP_ISEG 0x0480 /* Instruction segment exception */
960 #define EXCP_EXTERNAL 0x0500 /* External interruption */
961 #define EXCP_ALIGN 0x0600 /* Alignment exception */
962 #define EXCP_PROGRAM 0x0700 /* Program exception */
963 #define EXCP_NO_FP 0x0800 /* Floating point unavailable exception */
964 #define EXCP_DECR 0x0900 /* Decrementer exception */
965 #define EXCP_HDECR 0x0980 /* Hypervisor decrementer exception */
966 #define EXCP_SYSCALL 0x0C00 /* System call */
967 #define EXCP_TRACE 0x0D00 /* Trace exception */
968 #define EXCP_PERF 0x0F00 /* Performance monitor exception */
969 /* Exceptions defined in PowerPC 32 bits programming environment manual */
970 #define EXCP_FP_ASSIST 0x0E00 /* Floating-point assist */
971 /* Implementation specific exceptions */
973 #define EXCP_40x_PIT 0x1000 /* Programmable interval timer interrupt */
974 #define EXCP_40x_FIT 0x1010 /* Fixed interval timer interrupt */
975 #define EXCP_40x_WATCHDOG 0x1020 /* Watchdog timer exception */
976 #define EXCP_40x_DTLBMISS 0x1100 /* Data TLB miss exception */
977 #define EXCP_40x_ITLBMISS 0x1200 /* Instruction TLB miss exception */
978 #define EXCP_40x_DEBUG 0x2000 /* Debug exception */
979 /* 405 specific exceptions */
980 #define EXCP_405_APU 0x0F20 /* APU unavailable exception */
981 /* 440 specific exceptions */
982 #define EXCP_440_CRIT 0x0100 /* Critical interrupt */
983 #define EXCP_440_SPEU 0x1600 /* SPE unavailable exception */
984 #define EXCP_440_SPED 0x1700 /* SPE floating-point data exception */
985 #define EXCP_440_SPER 0x1800 /* SPE floating-point round exception */
986 /* TLB assist exceptions (602/603) */
987 #define EXCP_I_TLBMISS 0x1000 /* Instruction TLB miss */
988 #define EXCP_DL_TLBMISS 0x1100 /* Data load TLB miss */
989 #define EXCP_DS_TLBMISS 0x1200 /* Data store TLB miss */
990 /* Breakpoint exceptions (602/603/604/620/740/745/750/755...) */
991 #define EXCP_IABR 0x1300 /* Instruction address breakpoint */
992 #define EXCP_SMI 0x1400 /* System management interrupt */
993 /* Altivec related exceptions */
994 #define EXCP_VPU 0x0F20 /* VPU unavailable exception */
995 /* 601 specific exceptions */
996 #define EXCP_601_IO 0x0A00 /* IO error exception */
997 #define EXCP_601_RUNM 0x2000 /* Run mode exception */
998 /* 602 specific exceptions */
999 #define EXCP_602_WATCHDOG 0x1500 /* Watchdog exception */
1000 #define EXCP_602_EMUL 0x1600 /* Emulation trap exception */
1001 /* G2 specific exceptions */
1002 #define EXCP_G2_CRIT 0x0A00 /* Critical interrupt */
1003 /* MPC740/745/750 & IBM 750 specific exceptions */
1004 #define EXCP_THRM 0x1700 /* Thermal management interrupt */
1005 /* 74xx specific exceptions */
1006 #define EXCP_74xx_VPUA 0x1600 /* VPU assist exception */
1007 /* 970FX specific exceptions */
1008 #define EXCP_970_SOFTP 0x1500 /* Soft patch exception */
1009 #define EXCP_970_MAINT 0x1600 /* Maintenance exception */
1010 #define EXCP_970_THRM 0x1800 /* Thermal exception */
1011 #define EXCP_970_VPUA 0x1700 /* VPU assist exception */
1012 /* SPE related exceptions */
1013 #define EXCP_NO_SPE 0x0F20 /* SPE unavailable exception */
1014 /* End of exception vectors area */
1015 #define EXCP_PPC_MAX 0x4000
1016 /* Qemu exceptions: special cases we want to stop translation */
1017 #define EXCP_MTMSR 0x11000 /* mtmsr instruction: */
1018 /* may change privilege level */
1019 #define EXCP_BRANCH 0x11001 /* branch instruction */
1020 #define EXCP_SYSCALL_USER 0x12000 /* System call in user mode only */
1024 /* Exception subtypes for EXCP_ALIGN */
1025 EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
1026 EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
1027 EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
1028 EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
1029 EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
1030 EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
1031 /* Exception subtypes for EXCP_PROGRAM */
1034 EXCP_FP_OX = 0x01, /* FP overflow */
1035 EXCP_FP_UX = 0x02, /* FP underflow */
1036 EXCP_FP_ZX = 0x03, /* FP divide by zero */
1037 EXCP_FP_XX = 0x04, /* FP inexact */
1038 EXCP_FP_VXNAN = 0x05, /* FP invalid SNaN op */
1039 EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
1040 EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
1041 EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
1042 EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
1043 EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
1044 EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
1045 EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
1046 EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
1047 /* Invalid instruction */
1049 EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
1050 EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
1051 EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
1052 EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
1053 /* Privileged instruction */
1055 EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
1056 EXCP_PRIV_REG = 0x02, /* Privileged register exception */
1061 /* Hardware interruption sources:
1062 * all those exception can be raised simulteaneously
1064 /* Input pins definitions */
1066 /* 6xx bus input pins */
1067 PPC6xx_INPUT_HRESET = 0,
1068 PPC6xx_INPUT_SRESET = 1,
1069 PPC6xx_INPUT_CKSTP_IN = 2,
1070 PPC6xx_INPUT_MCP = 3,
1071 PPC6xx_INPUT_SMI = 4,
1072 PPC6xx_INPUT_INT = 5,
1076 /* Embedded PowerPC input pins */
1077 PPCBookE_INPUT_HRESET = 0,
1078 PPCBookE_INPUT_SRESET = 1,
1079 PPCBookE_INPUT_CKSTP_IN = 2,
1080 PPCBookE_INPUT_MCP = 3,
1081 PPCBookE_INPUT_SMI = 4,
1082 PPCBookE_INPUT_INT = 5,
1083 PPCBookE_INPUT_CINT = 6,
1087 /* PowerPC 401/403 input pins */
1088 PPC401_INPUT_RESET = 0,
1089 PPC401_INPUT_CINT = 1,
1090 PPC401_INPUT_INT = 2,
1091 PPC401_INPUT_BERR = 3,
1092 PPC401_INPUT_HALT = 4,
1096 /* PowerPC 405 input pins */
1097 PPC405_INPUT_RESET_CORE = 0,
1098 PPC405_INPUT_RESET_CHIP = 1,
1099 PPC405_INPUT_RESET_SYS = 2,
1100 PPC405_INPUT_CINT = 3,
1101 PPC405_INPUT_INT = 4,
1102 PPC405_INPUT_HALT = 5,
1103 PPC405_INPUT_DEBUG = 6,
1107 /* PowerPC 620 (and probably others) input pins */
1108 PPC620_INPUT_HRESET = 0,
1109 PPC620_INPUT_SRESET = 1,
1110 PPC620_INPUT_CKSTP = 2,
1111 PPC620_INPUT_TBEN = 3,
1112 PPC620_INPUT_WAKEUP = 4,
1113 PPC620_INPUT_MCP = 5,
1114 PPC620_INPUT_SMI = 6,
1115 PPC620_INPUT_INT = 7,
1119 /* PowerPC 970 input pins */
1120 PPC970_INPUT_HRESET = 0,
1121 PPC970_INPUT_SRESET = 1,
1122 PPC970_INPUT_CKSTP = 2,
1123 PPC970_INPUT_TBEN = 3,
1124 PPC970_INPUT_MCP = 4,
1125 PPC970_INPUT_INT = 5,
1126 PPC970_INPUT_THINT = 6,
1129 /* Hardware exceptions definitions */
1131 /* External hardware exception sources */
1132 PPC_INTERRUPT_RESET = 0, /* Reset exception */
1133 PPC_INTERRUPT_MCK = 1, /* Machine check exception */
1134 PPC_INTERRUPT_EXT = 2, /* External interrupt */
1135 PPC_INTERRUPT_SMI = 3, /* System management interrupt */
1136 PPC_INTERRUPT_CEXT = 4, /* Critical external interrupt */
1137 PPC_INTERRUPT_DEBUG = 5, /* External debug exception */
1138 PPC_INTERRUPT_THERM = 6, /* Thermal exception */
1139 /* Internal hardware exception sources */
1140 PPC_INTERRUPT_DECR = 7, /* Decrementer exception */
1141 PPC_INTERRUPT_HDECR = 8, /* Hypervisor decrementer exception */
1142 PPC_INTERRUPT_PIT = 9, /* Programmable inteval timer interrupt */
1143 PPC_INTERRUPT_FIT = 10, /* Fixed interval timer interrupt */
1144 PPC_INTERRUPT_WDT = 11, /* Watchdog timer interrupt */
1147 /*****************************************************************************/
1149 #endif /* !defined (__CPU_PPC_H__) */
projects / qemu / blob