2 * PowerPC emulation helpers for qemu.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
30 #include "helper_regs.h"
31 #include "qemu-common.h"
37 //#define DEBUG_SOFTWARE_TLB
38 //#define DUMP_PAGE_TABLES
39 //#define DEBUG_EXCEPTIONS
40 //#define FLUSH_ALL_TLBS
43 # define LOG_MMU(...) qemu_log(__VA_ARGS__)
44 # define LOG_MMU_STATE(env) log_cpu_state((env), 0)
46 # define LOG_MMU(...) do { } while (0)
47 # define LOG_MMU_STATE(...) do { } while (0)
51 #ifdef DEBUG_SOFTWARE_TLB
52 # define LOG_SWTLB(...) qemu_log(__VA_ARGS__)
54 # define LOG_SWTLB(...) do { } while (0)
58 # define LOG_BATS(...) qemu_log(__VA_ARGS__)
60 # define LOG_BATS(...) do { } while (0)
64 # define LOG_SLB(...) qemu_log(__VA_ARGS__)
66 # define LOG_SLB(...) do { } while (0)
69 #ifdef DEBUG_EXCEPTIONS
70 # define LOG_EXCP(...) qemu_log(__VA_ARGS__)
72 # define LOG_EXCP(...) do { } while (0)
76 /*****************************************************************************/
77 /* PowerPC MMU emulation */
79 #if defined(CONFIG_USER_ONLY)
80 int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
81 int mmu_idx, int is_softmmu)
83 int exception, error_code;
86 exception = POWERPC_EXCP_ISI;
87 error_code = 0x40000000;
89 exception = POWERPC_EXCP_DSI;
90 error_code = 0x40000000;
92 error_code |= 0x02000000;
93 env->spr[SPR_DAR] = address;
94 env->spr[SPR_DSISR] = error_code;
96 env->exception_index = exception;
97 env->error_code = error_code;
102 target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
108 /* Common routines used by software and hardware TLBs emulation */
109 static always_inline int pte_is_valid (target_ulong pte0)
111 return pte0 & 0x80000000 ? 1 : 0;
114 static always_inline void pte_invalidate (target_ulong *pte0)
116 *pte0 &= ~0x80000000;
119 #if defined(TARGET_PPC64)
120 static always_inline int pte64_is_valid (target_ulong pte0)
122 return pte0 & 0x0000000000000001ULL ? 1 : 0;
125 static always_inline void pte64_invalidate (target_ulong *pte0)
127 *pte0 &= ~0x0000000000000001ULL;
131 #define PTE_PTEM_MASK 0x7FFFFFBF
132 #define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B)
133 #if defined(TARGET_PPC64)
134 #define PTE64_PTEM_MASK 0xFFFFFFFFFFFFFF80ULL
135 #define PTE64_CHECK_MASK (TARGET_PAGE_MASK | 0x7F)
138 static always_inline int pp_check (int key, int pp, int nx)
142 /* Compute access rights */
143 /* When pp is 3/7, the result is undefined. Set it to noaccess */
150 access |= PAGE_WRITE;
168 access = PAGE_READ | PAGE_WRITE;
178 static always_inline int check_prot (int prot, int rw, int access_type)
182 if (access_type == ACCESS_CODE) {
183 if (prot & PAGE_EXEC)
188 if (prot & PAGE_WRITE)
193 if (prot & PAGE_READ)
202 static always_inline int _pte_check (mmu_ctx_t *ctx, int is_64b,
203 target_ulong pte0, target_ulong pte1,
204 int h, int rw, int type)
206 target_ulong ptem, mmask;
207 int access, ret, pteh, ptev, pp;
211 /* Check validity and table match */
212 #if defined(TARGET_PPC64)
214 ptev = pte64_is_valid(pte0);
215 pteh = (pte0 >> 1) & 1;
219 ptev = pte_is_valid(pte0);
220 pteh = (pte0 >> 6) & 1;
222 if (ptev && h == pteh) {
223 /* Check vsid & api */
224 #if defined(TARGET_PPC64)
226 ptem = pte0 & PTE64_PTEM_MASK;
227 mmask = PTE64_CHECK_MASK;
228 pp = (pte1 & 0x00000003) | ((pte1 >> 61) & 0x00000004);
229 ctx->nx = (pte1 >> 2) & 1; /* No execute bit */
230 ctx->nx |= (pte1 >> 3) & 1; /* Guarded bit */
234 ptem = pte0 & PTE_PTEM_MASK;
235 mmask = PTE_CHECK_MASK;
236 pp = pte1 & 0x00000003;
238 if (ptem == ctx->ptem) {
239 if (ctx->raddr != (target_phys_addr_t)-1ULL) {
240 /* all matches should have equal RPN, WIMG & PP */
241 if ((ctx->raddr & mmask) != (pte1 & mmask)) {
242 qemu_log("Bad RPN/WIMG/PP\n");
246 /* Compute access rights */
247 access = pp_check(ctx->key, pp, ctx->nx);
248 /* Keep the matching PTE informations */
251 ret = check_prot(ctx->prot, rw, type);
254 LOG_MMU("PTE access granted !\n");
256 /* Access right violation */
257 LOG_MMU("PTE access rejected\n");
265 static always_inline int pte32_check (mmu_ctx_t *ctx,
266 target_ulong pte0, target_ulong pte1,
267 int h, int rw, int type)
269 return _pte_check(ctx, 0, pte0, pte1, h, rw, type);
272 #if defined(TARGET_PPC64)
273 static always_inline int pte64_check (mmu_ctx_t *ctx,
274 target_ulong pte0, target_ulong pte1,
275 int h, int rw, int type)
277 return _pte_check(ctx, 1, pte0, pte1, h, rw, type);
281 static always_inline int pte_update_flags (mmu_ctx_t *ctx, target_ulong *pte1p,
286 /* Update page flags */
287 if (!(*pte1p & 0x00000100)) {
288 /* Update accessed flag */
289 *pte1p |= 0x00000100;
292 if (!(*pte1p & 0x00000080)) {
293 if (rw == 1 && ret == 0) {
294 /* Update changed flag */
295 *pte1p |= 0x00000080;
298 /* Force page fault for first write access */
299 ctx->prot &= ~PAGE_WRITE;
306 /* Software driven TLB helpers */
307 static always_inline int ppc6xx_tlb_getnum (CPUState *env, target_ulong eaddr,
308 int way, int is_code)
312 /* Select TLB num in a way from address */
313 nr = (eaddr >> TARGET_PAGE_BITS) & (env->tlb_per_way - 1);
315 nr += env->tlb_per_way * way;
316 /* 6xx have separate TLBs for instructions and data */
317 if (is_code && env->id_tlbs == 1)
323 static always_inline void ppc6xx_tlb_invalidate_all (CPUState *env)
328 //LOG_SWTLB("Invalidate all TLBs\n");
329 /* Invalidate all defined software TLB */
331 if (env->id_tlbs == 1)
333 for (nr = 0; nr < max; nr++) {
334 tlb = &env->tlb[nr].tlb6;
335 pte_invalidate(&tlb->pte0);
340 static always_inline void __ppc6xx_tlb_invalidate_virt (CPUState *env,
345 #if !defined(FLUSH_ALL_TLBS)
349 /* Invalidate ITLB + DTLB, all ways */
350 for (way = 0; way < env->nb_ways; way++) {
351 nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code);
352 tlb = &env->tlb[nr].tlb6;
353 if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) {
354 LOG_SWTLB("TLB invalidate %d/%d " ADDRX "\n",
355 nr, env->nb_tlb, eaddr);
356 pte_invalidate(&tlb->pte0);
357 tlb_flush_page(env, tlb->EPN);
361 /* XXX: PowerPC specification say this is valid as well */
362 ppc6xx_tlb_invalidate_all(env);
366 static always_inline void ppc6xx_tlb_invalidate_virt (CPUState *env,
370 __ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0);
373 void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,
374 target_ulong pte0, target_ulong pte1)
379 nr = ppc6xx_tlb_getnum(env, EPN, way, is_code);
380 tlb = &env->tlb[nr].tlb6;
381 LOG_SWTLB("Set TLB %d/%d EPN " ADDRX " PTE0 " ADDRX
382 " PTE1 " ADDRX "\n", nr, env->nb_tlb, EPN, pte0, pte1);
383 /* Invalidate any pending reference in Qemu for this virtual address */
384 __ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1);
388 /* Store last way for LRU mechanism */
392 static always_inline int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx,
393 target_ulong eaddr, int rw,
401 ret = -1; /* No TLB found */
402 for (way = 0; way < env->nb_ways; way++) {
403 nr = ppc6xx_tlb_getnum(env, eaddr, way,
404 access_type == ACCESS_CODE ? 1 : 0);
405 tlb = &env->tlb[nr].tlb6;
406 /* This test "emulates" the PTE index match for hardware TLBs */
407 if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) {
408 LOG_SWTLB("TLB %d/%d %s [" ADDRX " " ADDRX
411 pte_is_valid(tlb->pte0) ? "valid" : "inval",
412 tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr);
415 LOG_SWTLB("TLB %d/%d %s " ADDRX " <> " ADDRX " " ADDRX
418 pte_is_valid(tlb->pte0) ? "valid" : "inval",
419 tlb->EPN, eaddr, tlb->pte1,
420 rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D');
421 switch (pte32_check(ctx, tlb->pte0, tlb->pte1, 0, rw, access_type)) {
423 /* TLB inconsistency */
426 /* Access violation */
436 /* XXX: we should go on looping to check all TLBs consistency
437 * but we can speed-up the whole thing as the
438 * result would be undefined if TLBs are not consistent.
447 LOG_SWTLB("found TLB at addr " PADDRX " prot=%01x ret=%d\n",
448 ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);
449 /* Update page flags */
450 pte_update_flags(ctx, &env->tlb[best].tlb6.pte1, ret, rw);
456 /* Perform BAT hit & translation */
457 static always_inline void bat_size_prot (CPUState *env, target_ulong *blp,
458 int *validp, int *protp,
459 target_ulong *BATu, target_ulong *BATl)
464 bl = (*BATu & 0x00001FFC) << 15;
467 if (((msr_pr == 0) && (*BATu & 0x00000002)) ||
468 ((msr_pr != 0) && (*BATu & 0x00000001))) {
470 pp = *BATl & 0x00000003;
472 prot = PAGE_READ | PAGE_EXEC;
482 static always_inline void bat_601_size_prot (CPUState *env,target_ulong *blp,
483 int *validp, int *protp,
488 int key, pp, valid, prot;
490 bl = (*BATl & 0x0000003F) << 17;
491 LOG_BATS("b %02x ==> bl " ADDRX " msk " ADDRX "\n",
492 (uint8_t)(*BATl & 0x0000003F), bl, ~bl);
494 valid = (*BATl >> 6) & 1;
496 pp = *BATu & 0x00000003;
498 key = (*BATu >> 3) & 1;
500 key = (*BATu >> 2) & 1;
501 prot = pp_check(key, pp, 0);
508 static always_inline int get_bat (CPUState *env, mmu_ctx_t *ctx,
509 target_ulong virtual, int rw, int type)
511 target_ulong *BATlt, *BATut, *BATu, *BATl;
512 target_ulong base, BEPIl, BEPIu, bl;
516 LOG_BATS("%s: %cBAT v " ADDRX "\n", __func__,
517 type == ACCESS_CODE ? 'I' : 'D', virtual);
520 BATlt = env->IBAT[1];
521 BATut = env->IBAT[0];
524 BATlt = env->DBAT[1];
525 BATut = env->DBAT[0];
528 base = virtual & 0xFFFC0000;
529 for (i = 0; i < env->nb_BATs; i++) {
532 BEPIu = *BATu & 0xF0000000;
533 BEPIl = *BATu & 0x0FFE0000;
534 if (unlikely(env->mmu_model == POWERPC_MMU_601)) {
535 bat_601_size_prot(env, &bl, &valid, &prot, BATu, BATl);
537 bat_size_prot(env, &bl, &valid, &prot, BATu, BATl);
539 LOG_BATS("%s: %cBAT%d v " ADDRX " BATu " ADDRX
540 " BATl " ADDRX "\n", __func__,
541 type == ACCESS_CODE ? 'I' : 'D', i, virtual, *BATu, *BATl);
542 if ((virtual & 0xF0000000) == BEPIu &&
543 ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
546 /* Get physical address */
547 ctx->raddr = (*BATl & 0xF0000000) |
548 ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) |
549 (virtual & 0x0001F000);
550 /* Compute access rights */
552 ret = check_prot(ctx->prot, rw, type);
554 LOG_BATS("BAT %d match: r " PADDRX " prot=%c%c\n",
555 i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-',
556 ctx->prot & PAGE_WRITE ? 'W' : '-');
562 #if defined(DEBUG_BATS)
564 QEMU_LOG0("no BAT match for " ADDRX ":\n", virtual);
565 for (i = 0; i < 4; i++) {
568 BEPIu = *BATu & 0xF0000000;
569 BEPIl = *BATu & 0x0FFE0000;
570 bl = (*BATu & 0x00001FFC) << 15;
571 QEMU_LOG0("%s: %cBAT%d v " ADDRX " BATu " ADDRX
572 " BATl " ADDRX " \n\t" ADDRX " " ADDRX " " ADDRX "\n",
573 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
574 *BATu, *BATl, BEPIu, BEPIl, bl);
583 /* PTE table lookup */
584 static always_inline int _find_pte (mmu_ctx_t *ctx, int is_64b, int h,
586 int target_page_bits)
588 target_ulong base, pte0, pte1;
592 ret = -1; /* No entry found */
593 base = ctx->pg_addr[h];
594 for (i = 0; i < 8; i++) {
595 #if defined(TARGET_PPC64)
597 pte0 = ldq_phys(base + (i * 16));
598 pte1 = ldq_phys(base + (i * 16) + 8);
600 /* We have a TLB that saves 4K pages, so let's
601 * split a huge page to 4k chunks */
602 if (target_page_bits != TARGET_PAGE_BITS)
603 pte1 |= (ctx->eaddr & (( 1 << target_page_bits ) - 1))
606 r = pte64_check(ctx, pte0, pte1, h, rw, type);
607 LOG_MMU("Load pte from " ADDRX " => " ADDRX " " ADDRX
608 " %d %d %d " ADDRX "\n",
609 base + (i * 16), pte0, pte1,
610 (int)(pte0 & 1), h, (int)((pte0 >> 1) & 1),
615 pte0 = ldl_phys(base + (i * 8));
616 pte1 = ldl_phys(base + (i * 8) + 4);
617 r = pte32_check(ctx, pte0, pte1, h, rw, type);
618 LOG_MMU("Load pte from " ADDRX " => " ADDRX " " ADDRX
619 " %d %d %d " ADDRX "\n",
620 base + (i * 8), pte0, pte1,
621 (int)(pte0 >> 31), h, (int)((pte0 >> 6) & 1),
626 /* PTE inconsistency */
629 /* Access violation */
639 /* XXX: we should go on looping to check all PTEs consistency
640 * but if we can speed-up the whole thing as the
641 * result would be undefined if PTEs are not consistent.
650 LOG_MMU("found PTE at addr " PADDRX " prot=%01x ret=%d\n",
651 ctx->raddr, ctx->prot, ret);
652 /* Update page flags */
654 if (pte_update_flags(ctx, &pte1, ret, rw) == 1) {
655 #if defined(TARGET_PPC64)
657 stq_phys_notdirty(base + (good * 16) + 8, pte1);
661 stl_phys_notdirty(base + (good * 8) + 4, pte1);
669 static always_inline int find_pte32 (mmu_ctx_t *ctx, int h, int rw,
670 int type, int target_page_bits)
672 return _find_pte(ctx, 0, h, rw, type, target_page_bits);
675 #if defined(TARGET_PPC64)
676 static always_inline int find_pte64 (mmu_ctx_t *ctx, int h, int rw,
677 int type, int target_page_bits)
679 return _find_pte(ctx, 1, h, rw, type, target_page_bits);
683 static always_inline int find_pte (CPUState *env, mmu_ctx_t *ctx,
684 int h, int rw, int type,
685 int target_page_bits)
687 #if defined(TARGET_PPC64)
688 if (env->mmu_model & POWERPC_MMU_64)
689 return find_pte64(ctx, h, rw, type, target_page_bits);
692 return find_pte32(ctx, h, rw, type, target_page_bits);
695 #if defined(TARGET_PPC64)
696 static ppc_slb_t *slb_get_entry(CPUPPCState *env, int nr)
698 ppc_slb_t *retval = &env->slb[nr];
700 #if 0 // XXX implement bridge mode?
701 if (env->spr[SPR_ASR] & 1) {
702 target_phys_addr_t sr_base;
704 sr_base = env->spr[SPR_ASR] & 0xfffffffffffff000;
705 sr_base += (12 * nr);
707 retval->tmp64 = ldq_phys(sr_base);
708 retval->tmp = ldl_phys(sr_base + 8);
715 static void slb_set_entry(CPUPPCState *env, int nr, ppc_slb_t *slb)
717 ppc_slb_t *entry = &env->slb[nr];
722 entry->tmp64 = slb->tmp64;
723 entry->tmp = slb->tmp;
726 static always_inline int slb_is_valid (ppc_slb_t *slb)
728 return (int)(slb->tmp64 & 0x0000000008000000ULL);
731 static always_inline void slb_invalidate (ppc_slb_t *slb)
733 slb->tmp64 &= ~0x0000000008000000ULL;
736 static always_inline int slb_lookup (CPUPPCState *env, target_ulong eaddr,
738 target_ulong *page_mask, int *attr,
739 int *target_page_bits)
745 LOG_SLB("%s: eaddr " ADDRX "\n", __func__, eaddr);
746 mask = 0x0000000000000000ULL; /* Avoid gcc warning */
747 for (n = 0; n < env->slb_nr; n++) {
748 ppc_slb_t *slb = slb_get_entry(env, n);
750 LOG_SLB("%s: seg %d %016" PRIx64 " %08"
751 PRIx32 "\n", __func__, n, slb->tmp64, slb->tmp);
752 if (slb_is_valid(slb)) {
753 /* SLB entry is valid */
754 if (slb->tmp & 0x8) {
756 mask = 0xFFFF000000000000ULL;
757 if (target_page_bits)
758 *target_page_bits = 24; // XXX 16M pages?
761 mask = 0xFFFFFFFFF0000000ULL;
762 if (target_page_bits)
763 *target_page_bits = TARGET_PAGE_BITS;
765 if ((eaddr & mask) == (slb->tmp64 & mask)) {
767 *vsid = ((slb->tmp64 << 24) | (slb->tmp >> 8)) & 0x0003FFFFFFFFFFFFULL;
769 *attr = slb->tmp & 0xFF;
779 void ppc_slb_invalidate_all (CPUPPCState *env)
781 int n, do_invalidate;
784 /* XXX: Warning: slbia never invalidates the first segment */
785 for (n = 1; n < env->slb_nr; n++) {
786 ppc_slb_t *slb = slb_get_entry(env, n);
788 if (slb_is_valid(slb)) {
790 slb_set_entry(env, n, slb);
791 /* XXX: given the fact that segment size is 256 MB or 1TB,
792 * and we still don't have a tlb_flush_mask(env, n, mask)
793 * in Qemu, we just invalidate all TLBs
802 void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0)
804 target_ulong vsid, page_mask;
808 n = slb_lookup(env, T0, &vsid, &page_mask, &attr, NULL);
810 ppc_slb_t *slb = slb_get_entry(env, n);
812 if (slb_is_valid(slb)) {
814 slb_set_entry(env, n, slb);
815 /* XXX: given the fact that segment size is 256 MB or 1TB,
816 * and we still don't have a tlb_flush_mask(env, n, mask)
817 * in Qemu, we just invalidate all TLBs
824 target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr)
827 ppc_slb_t *slb = slb_get_entry(env, slb_nr);
829 if (slb_is_valid(slb)) {
830 /* SLB entry is valid */
831 /* Copy SLB bits 62:88 to Rt 37:63 (VSID 23:49) */
832 rt = slb->tmp >> 8; /* 65:88 => 40:63 */
833 rt |= (slb->tmp64 & 0x7) << 24; /* 62:64 => 37:39 */
834 /* Copy SLB bits 89:92 to Rt 33:36 (KsKpNL) */
835 rt |= ((slb->tmp >> 4) & 0xF) << 27;
839 LOG_SLB("%s: %016" PRIx64 " %08" PRIx32 " => %d "
840 ADDRX "\n", __func__, slb->tmp64, slb->tmp, slb_nr, rt);
845 void ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs)
851 int flags, valid, slb_nr;
854 flags = ((rs >> 8) & 0xf);
857 valid = (rb & (1 << 27));
860 slb = slb_get_entry(env, slb_nr);
861 slb->tmp64 = (esid << 28) | valid | (vsid >> 24);
862 slb->tmp = (vsid << 8) | (flags << 3);
864 LOG_SLB("%s: %d " ADDRX " - " ADDRX " => %016" PRIx64
865 " %08" PRIx32 "\n", __func__,
866 slb_nr, rb, rs, tmp64, tmp);
868 slb_set_entry(env, slb_nr, slb);
870 #endif /* defined(TARGET_PPC64) */
872 /* Perform segment based translation */
873 static always_inline target_phys_addr_t get_pgaddr (target_phys_addr_t sdr1,
875 target_phys_addr_t hash,
876 target_phys_addr_t mask)
878 return (sdr1 & ((target_phys_addr_t)(-1ULL) << sdr_sh)) | (hash & mask);
881 static always_inline int get_segment (CPUState *env, mmu_ctx_t *ctx,
882 target_ulong eaddr, int rw, int type)
884 target_phys_addr_t sdr, hash, mask, sdr_mask, htab_mask;
885 target_ulong sr, vsid, vsid_mask, pgidx, page_mask;
886 #if defined(TARGET_PPC64)
889 int ds, vsid_sh, sdr_sh, pr, target_page_bits;
893 #if defined(TARGET_PPC64)
894 if (env->mmu_model & POWERPC_MMU_64) {
895 LOG_MMU("Check SLBs\n");
896 ret = slb_lookup(env, eaddr, &vsid, &page_mask, &attr,
900 ctx->key = ((attr & 0x40) && (pr != 0)) ||
901 ((attr & 0x80) && (pr == 0)) ? 1 : 0;
903 ctx->nx = attr & 0x10 ? 1 : 0;
905 vsid_mask = 0x00003FFFFFFFFF80ULL;
910 #endif /* defined(TARGET_PPC64) */
912 sr = env->sr[eaddr >> 28];
913 page_mask = 0x0FFFFFFF;
914 ctx->key = (((sr & 0x20000000) && (pr != 0)) ||
915 ((sr & 0x40000000) && (pr == 0))) ? 1 : 0;
916 ds = sr & 0x80000000 ? 1 : 0;
917 ctx->nx = sr & 0x10000000 ? 1 : 0;
918 vsid = sr & 0x00FFFFFF;
919 vsid_mask = 0x01FFFFC0;
923 target_page_bits = TARGET_PAGE_BITS;
924 LOG_MMU("Check segment v=" ADDRX " %d " ADDRX
925 " nip=" ADDRX " lr=" ADDRX " ir=%d dr=%d pr=%d %d t=%d\n",
926 eaddr, (int)(eaddr >> 28), sr, env->nip,
927 env->lr, (int)msr_ir, (int)msr_dr, pr != 0 ? 1 : 0,
930 LOG_MMU("pte segment: key=%d ds %d nx %d vsid " ADDRX "\n",
931 ctx->key, ds, ctx->nx, vsid);
934 /* Check if instruction fetch is allowed, if needed */
935 if (type != ACCESS_CODE || ctx->nx == 0) {
936 /* Page address translation */
937 /* Primary table address */
939 pgidx = (eaddr & page_mask) >> target_page_bits;
940 #if defined(TARGET_PPC64)
941 if (env->mmu_model & POWERPC_MMU_64) {
942 htab_mask = 0x0FFFFFFF >> (28 - (sdr & 0x1F));
943 /* XXX: this is false for 1 TB segments */
944 hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask;
948 htab_mask = sdr & 0x000001FF;
949 hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask;
951 mask = (htab_mask << sdr_sh) | sdr_mask;
952 LOG_MMU("sdr " PADDRX " sh %d hash " PADDRX
953 " mask " PADDRX " " ADDRX "\n",
954 sdr, sdr_sh, hash, mask, page_mask);
955 ctx->pg_addr[0] = get_pgaddr(sdr, sdr_sh, hash, mask);
956 /* Secondary table address */
957 hash = (~hash) & vsid_mask;
958 LOG_MMU("sdr " PADDRX " sh %d hash " PADDRX
959 " mask " PADDRX "\n",
960 sdr, sdr_sh, hash, mask);
961 ctx->pg_addr[1] = get_pgaddr(sdr, sdr_sh, hash, mask);
962 #if defined(TARGET_PPC64)
963 if (env->mmu_model & POWERPC_MMU_64) {
964 /* Only 5 bits of the page index are used in the AVPN */
965 if (target_page_bits > 23) {
966 ctx->ptem = (vsid << 12) |
967 ((pgidx << (target_page_bits - 16)) & 0xF80);
969 ctx->ptem = (vsid << 12) | ((pgidx >> 4) & 0x0F80);
974 ctx->ptem = (vsid << 7) | (pgidx >> 10);
976 /* Initialize real address with an invalid value */
977 ctx->raddr = (target_phys_addr_t)-1ULL;
978 if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx ||
979 env->mmu_model == POWERPC_MMU_SOFT_74xx)) {
980 /* Software TLB search */
981 ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type);
983 LOG_MMU("0 sdr1=" PADDRX " vsid=" ADDRX " "
984 "api=" ADDRX " hash=" PADDRX
985 " pg_addr=" PADDRX "\n",
986 sdr, vsid, pgidx, hash, ctx->pg_addr[0]);
987 /* Primary table lookup */
988 ret = find_pte(env, ctx, 0, rw, type, target_page_bits);
990 /* Secondary table lookup */
991 if (eaddr != 0xEFFFFFFF)
992 LOG_MMU("1 sdr1=" PADDRX " vsid=" ADDRX " "
993 "api=" ADDRX " hash=" PADDRX
994 " pg_addr=" PADDRX "\n",
995 sdr, vsid, pgidx, hash, ctx->pg_addr[1]);
996 ret2 = find_pte(env, ctx, 1, rw, type,
1002 #if defined (DUMP_PAGE_TABLES)
1003 if (qemu_log_enabled()) {
1004 target_phys_addr_t curaddr;
1005 uint32_t a0, a1, a2, a3;
1006 qemu_log("Page table: " PADDRX " len " PADDRX "\n",
1008 for (curaddr = sdr; curaddr < (sdr + mask + 0x80);
1010 a0 = ldl_phys(curaddr);
1011 a1 = ldl_phys(curaddr + 4);
1012 a2 = ldl_phys(curaddr + 8);
1013 a3 = ldl_phys(curaddr + 12);
1014 if (a0 != 0 || a1 != 0 || a2 != 0 || a3 != 0) {
1015 qemu_log(PADDRX ": %08x %08x %08x %08x\n",
1016 curaddr, a0, a1, a2, a3);
1022 LOG_MMU("No access allowed\n");
1026 LOG_MMU("direct store...\n");
1027 /* Direct-store segment : absolutely *BUGGY* for now */
1030 /* Integer load/store : only access allowed */
1033 /* No code fetch is allowed in direct-store areas */
1036 /* Floating point load/store */
1039 /* lwarx, ldarx or srwcx. */
1042 /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
1043 /* Should make the instruction do no-op.
1044 * As it already do no-op, it's quite easy :-)
1049 /* eciwx or ecowx */
1052 qemu_log("ERROR: instruction should not need "
1053 "address translation\n");
1056 if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) {
1067 /* Generic TLB check function for embedded PowerPC implementations */
1068 static always_inline int ppcemb_tlb_check (CPUState *env, ppcemb_tlb_t *tlb,
1069 target_phys_addr_t *raddrp,
1070 target_ulong address,
1071 uint32_t pid, int ext, int i)
1075 /* Check valid flag */
1076 if (!(tlb->prot & PAGE_VALID)) {
1077 qemu_log("%s: TLB %d not valid\n", __func__, i);
1080 mask = ~(tlb->size - 1);
1081 LOG_SWTLB("%s: TLB %d address " ADDRX " PID %u <=> " ADDRX
1083 __func__, i, address, pid, tlb->EPN, mask, (uint32_t)tlb->PID);
1085 if (tlb->PID != 0 && tlb->PID != pid)
1087 /* Check effective address */
1088 if ((address & mask) != tlb->EPN)
1090 *raddrp = (tlb->RPN & mask) | (address & ~mask);
1091 #if (TARGET_PHYS_ADDR_BITS >= 36)
1093 /* Extend the physical address to 36 bits */
1094 *raddrp |= (target_phys_addr_t)(tlb->RPN & 0xF) << 32;
1101 /* Generic TLB search function for PowerPC embedded implementations */
1102 int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid)
1105 target_phys_addr_t raddr;
1108 /* Default return value is no match */
1110 for (i = 0; i < env->nb_tlb; i++) {
1111 tlb = &env->tlb[i].tlbe;
1112 if (ppcemb_tlb_check(env, tlb, &raddr, address, pid, 0, i) == 0) {
1121 /* Helpers specific to PowerPC 40x implementations */
1122 static always_inline void ppc4xx_tlb_invalidate_all (CPUState *env)
1127 for (i = 0; i < env->nb_tlb; i++) {
1128 tlb = &env->tlb[i].tlbe;
1129 tlb->prot &= ~PAGE_VALID;
1134 static always_inline void ppc4xx_tlb_invalidate_virt (CPUState *env,
1138 #if !defined(FLUSH_ALL_TLBS)
1140 target_phys_addr_t raddr;
1141 target_ulong page, end;
1144 for (i = 0; i < env->nb_tlb; i++) {
1145 tlb = &env->tlb[i].tlbe;
1146 if (ppcemb_tlb_check(env, tlb, &raddr, eaddr, pid, 0, i) == 0) {
1147 end = tlb->EPN + tlb->size;
1148 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
1149 tlb_flush_page(env, page);
1150 tlb->prot &= ~PAGE_VALID;
1155 ppc4xx_tlb_invalidate_all(env);
1159 static int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
1160 target_ulong address, int rw, int access_type)
1163 target_phys_addr_t raddr;
1164 int i, ret, zsel, zpr, pr;
1167 raddr = (target_phys_addr_t)-1ULL;
1169 for (i = 0; i < env->nb_tlb; i++) {
1170 tlb = &env->tlb[i].tlbe;
1171 if (ppcemb_tlb_check(env, tlb, &raddr, address,
1172 env->spr[SPR_40x_PID], 0, i) < 0)
1174 zsel = (tlb->attr >> 4) & 0xF;
1175 zpr = (env->spr[SPR_40x_ZPR] >> (28 - (2 * zsel))) & 0x3;
1176 LOG_SWTLB("%s: TLB %d zsel %d zpr %d rw %d attr %08x\n",
1177 __func__, i, zsel, zpr, rw, tlb->attr);
1178 /* Check execute enable bit */
1185 /* All accesses granted */
1186 ctx->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
1198 /* Check from TLB entry */
1199 /* XXX: there is a problem here or in the TLB fill code... */
1200 ctx->prot = tlb->prot;
1201 ctx->prot |= PAGE_EXEC;
1202 ret = check_prot(ctx->prot, rw, access_type);
1207 LOG_SWTLB("%s: access granted " ADDRX " => " PADDRX
1208 " %d %d\n", __func__, address, ctx->raddr, ctx->prot,
1213 LOG_SWTLB("%s: access refused " ADDRX " => " PADDRX
1214 " %d %d\n", __func__, address, raddr, ctx->prot,
1220 void store_40x_sler (CPUPPCState *env, uint32_t val)
1222 /* XXX: TO BE FIXED */
1223 if (val != 0x00000000) {
1224 cpu_abort(env, "Little-endian regions are not supported by now\n");
1226 env->spr[SPR_405_SLER] = val;
1229 static int mmubooke_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
1230 target_ulong address, int rw,
1234 target_phys_addr_t raddr;
1238 raddr = (target_phys_addr_t)-1ULL;
1239 for (i = 0; i < env->nb_tlb; i++) {
1240 tlb = &env->tlb[i].tlbe;
1241 if (ppcemb_tlb_check(env, tlb, &raddr, address,
1242 env->spr[SPR_BOOKE_PID], 1, i) < 0)
1245 prot = tlb->prot & 0xF;
1247 prot = (tlb->prot >> 4) & 0xF;
1248 /* Check the address space */
1249 if (access_type == ACCESS_CODE) {
1250 if (msr_ir != (tlb->attr & 1))
1253 if (prot & PAGE_EXEC) {
1259 if (msr_dr != (tlb->attr & 1))
1262 if ((!rw && prot & PAGE_READ) || (rw && (prot & PAGE_WRITE))) {
1275 static always_inline int check_physical (CPUState *env, mmu_ctx_t *ctx,
1276 target_ulong eaddr, int rw)
1281 ctx->prot = PAGE_READ | PAGE_EXEC;
1283 switch (env->mmu_model) {
1284 case POWERPC_MMU_32B:
1285 case POWERPC_MMU_601:
1286 case POWERPC_MMU_SOFT_6xx:
1287 case POWERPC_MMU_SOFT_74xx:
1288 case POWERPC_MMU_SOFT_4xx:
1289 case POWERPC_MMU_REAL:
1290 case POWERPC_MMU_BOOKE:
1291 ctx->prot |= PAGE_WRITE;
1293 #if defined(TARGET_PPC64)
1294 case POWERPC_MMU_620:
1295 case POWERPC_MMU_64B:
1296 /* Real address are 60 bits long */
1297 ctx->raddr &= 0x0FFFFFFFFFFFFFFFULL;
1298 ctx->prot |= PAGE_WRITE;
1301 case POWERPC_MMU_SOFT_4xx_Z:
1302 if (unlikely(msr_pe != 0)) {
1303 /* 403 family add some particular protections,
1304 * using PBL/PBU registers for accesses with no translation.
1307 /* Check PLB validity */
1308 (env->pb[0] < env->pb[1] &&
1309 /* and address in plb area */
1310 eaddr >= env->pb[0] && eaddr < env->pb[1]) ||
1311 (env->pb[2] < env->pb[3] &&
1312 eaddr >= env->pb[2] && eaddr < env->pb[3]) ? 1 : 0;
1313 if (in_plb ^ msr_px) {
1314 /* Access in protected area */
1316 /* Access is not allowed */
1320 /* Read-write access is allowed */
1321 ctx->prot |= PAGE_WRITE;
1325 case POWERPC_MMU_MPC8xx:
1327 cpu_abort(env, "MPC8xx MMU model is not implemented\n");
1329 case POWERPC_MMU_BOOKE_FSL:
1331 cpu_abort(env, "BookE FSL MMU model not implemented\n");
1334 cpu_abort(env, "Unknown or invalid MMU model\n");
1341 int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
1342 int rw, int access_type)
1347 qemu_log("%s\n", __func__);
1349 if ((access_type == ACCESS_CODE && msr_ir == 0) ||
1350 (access_type != ACCESS_CODE && msr_dr == 0)) {
1351 /* No address translation */
1352 ret = check_physical(env, ctx, eaddr, rw);
1355 switch (env->mmu_model) {
1356 case POWERPC_MMU_32B:
1357 case POWERPC_MMU_601:
1358 case POWERPC_MMU_SOFT_6xx:
1359 case POWERPC_MMU_SOFT_74xx:
1360 /* Try to find a BAT */
1361 if (env->nb_BATs != 0)
1362 ret = get_bat(env, ctx, eaddr, rw, access_type);
1363 #if defined(TARGET_PPC64)
1364 case POWERPC_MMU_620:
1365 case POWERPC_MMU_64B:
1368 /* We didn't match any BAT entry or don't have BATs */
1369 ret = get_segment(env, ctx, eaddr, rw, access_type);
1372 case POWERPC_MMU_SOFT_4xx:
1373 case POWERPC_MMU_SOFT_4xx_Z:
1374 ret = mmu40x_get_physical_address(env, ctx, eaddr,
1377 case POWERPC_MMU_BOOKE:
1378 ret = mmubooke_get_physical_address(env, ctx, eaddr,
1381 case POWERPC_MMU_MPC8xx:
1383 cpu_abort(env, "MPC8xx MMU model is not implemented\n");
1385 case POWERPC_MMU_BOOKE_FSL:
1387 cpu_abort(env, "BookE FSL MMU model not implemented\n");
1389 case POWERPC_MMU_REAL:
1390 cpu_abort(env, "PowerPC in real mode do not do any translation\n");
1393 cpu_abort(env, "Unknown or invalid MMU model\n");
1398 qemu_log("%s address " ADDRX " => %d " PADDRX "\n",
1399 __func__, eaddr, ret, ctx->raddr);
1405 target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
1409 if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT) != 0))
1412 return ctx.raddr & TARGET_PAGE_MASK;
1415 /* Perform address translation */
1416 int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
1417 int mmu_idx, int is_softmmu)
1426 access_type = ACCESS_CODE;
1429 access_type = env->access_type;
1431 ret = get_physical_address(env, &ctx, address, rw, access_type);
1433 ret = tlb_set_page_exec(env, address & TARGET_PAGE_MASK,
1434 ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
1435 mmu_idx, is_softmmu);
1436 } else if (ret < 0) {
1438 if (access_type == ACCESS_CODE) {
1441 /* No matches in page tables or TLB */
1442 switch (env->mmu_model) {
1443 case POWERPC_MMU_SOFT_6xx:
1444 env->exception_index = POWERPC_EXCP_IFTLB;
1445 env->error_code = 1 << 18;
1446 env->spr[SPR_IMISS] = address;
1447 env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
1449 case POWERPC_MMU_SOFT_74xx:
1450 env->exception_index = POWERPC_EXCP_IFTLB;
1452 case POWERPC_MMU_SOFT_4xx:
1453 case POWERPC_MMU_SOFT_4xx_Z:
1454 env->exception_index = POWERPC_EXCP_ITLB;
1455 env->error_code = 0;
1456 env->spr[SPR_40x_DEAR] = address;
1457 env->spr[SPR_40x_ESR] = 0x00000000;
1459 case POWERPC_MMU_32B:
1460 case POWERPC_MMU_601:
1461 #if defined(TARGET_PPC64)
1462 case POWERPC_MMU_620:
1463 case POWERPC_MMU_64B:
1465 env->exception_index = POWERPC_EXCP_ISI;
1466 env->error_code = 0x40000000;
1468 case POWERPC_MMU_BOOKE:
1470 cpu_abort(env, "BookE MMU model is not implemented\n");
1472 case POWERPC_MMU_BOOKE_FSL:
1474 cpu_abort(env, "BookE FSL MMU model is not implemented\n");
1476 case POWERPC_MMU_MPC8xx:
1478 cpu_abort(env, "MPC8xx MMU model is not implemented\n");
1480 case POWERPC_MMU_REAL:
1481 cpu_abort(env, "PowerPC in real mode should never raise "
1482 "any MMU exceptions\n");
1485 cpu_abort(env, "Unknown or invalid MMU model\n");
1490 /* Access rights violation */
1491 env->exception_index = POWERPC_EXCP_ISI;
1492 env->error_code = 0x08000000;
1495 /* No execute protection violation */
1496 env->exception_index = POWERPC_EXCP_ISI;
1497 env->error_code = 0x10000000;
1500 /* Direct store exception */
1501 /* No code fetch is allowed in direct-store areas */
1502 env->exception_index = POWERPC_EXCP_ISI;
1503 env->error_code = 0x10000000;
1505 #if defined(TARGET_PPC64)
1507 /* No match in segment table */
1508 if (env->mmu_model == POWERPC_MMU_620) {
1509 env->exception_index = POWERPC_EXCP_ISI;
1510 /* XXX: this might be incorrect */
1511 env->error_code = 0x40000000;
1513 env->exception_index = POWERPC_EXCP_ISEG;
1514 env->error_code = 0;
1522 /* No matches in page tables or TLB */
1523 switch (env->mmu_model) {
1524 case POWERPC_MMU_SOFT_6xx:
1526 env->exception_index = POWERPC_EXCP_DSTLB;
1527 env->error_code = 1 << 16;
1529 env->exception_index = POWERPC_EXCP_DLTLB;
1530 env->error_code = 0;
1532 env->spr[SPR_DMISS] = address;
1533 env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;
1535 env->error_code |= ctx.key << 19;
1536 env->spr[SPR_HASH1] = ctx.pg_addr[0];
1537 env->spr[SPR_HASH2] = ctx.pg_addr[1];
1539 case POWERPC_MMU_SOFT_74xx:
1541 env->exception_index = POWERPC_EXCP_DSTLB;
1543 env->exception_index = POWERPC_EXCP_DLTLB;
1546 /* Implement LRU algorithm */
1547 env->error_code = ctx.key << 19;
1548 env->spr[SPR_TLBMISS] = (address & ~((target_ulong)0x3)) |
1549 ((env->last_way + 1) & (env->nb_ways - 1));
1550 env->spr[SPR_PTEHI] = 0x80000000 | ctx.ptem;
1552 case POWERPC_MMU_SOFT_4xx:
1553 case POWERPC_MMU_SOFT_4xx_Z:
1554 env->exception_index = POWERPC_EXCP_DTLB;
1555 env->error_code = 0;
1556 env->spr[SPR_40x_DEAR] = address;
1558 env->spr[SPR_40x_ESR] = 0x00800000;
1560 env->spr[SPR_40x_ESR] = 0x00000000;
1562 case POWERPC_MMU_32B:
1563 case POWERPC_MMU_601:
1564 #if defined(TARGET_PPC64)
1565 case POWERPC_MMU_620:
1566 case POWERPC_MMU_64B:
1568 env->exception_index = POWERPC_EXCP_DSI;
1569 env->error_code = 0;
1570 env->spr[SPR_DAR] = address;
1572 env->spr[SPR_DSISR] = 0x42000000;
1574 env->spr[SPR_DSISR] = 0x40000000;
1576 case POWERPC_MMU_MPC8xx:
1578 cpu_abort(env, "MPC8xx MMU model is not implemented\n");
1580 case POWERPC_MMU_BOOKE:
1582 cpu_abort(env, "BookE MMU model is not implemented\n");
1584 case POWERPC_MMU_BOOKE_FSL:
1586 cpu_abort(env, "BookE FSL MMU model is not implemented\n");
1588 case POWERPC_MMU_REAL:
1589 cpu_abort(env, "PowerPC in real mode should never raise "
1590 "any MMU exceptions\n");
1593 cpu_abort(env, "Unknown or invalid MMU model\n");
1598 /* Access rights violation */
1599 env->exception_index = POWERPC_EXCP_DSI;
1600 env->error_code = 0;
1601 env->spr[SPR_DAR] = address;
1603 env->spr[SPR_DSISR] = 0x0A000000;
1605 env->spr[SPR_DSISR] = 0x08000000;
1608 /* Direct store exception */
1609 switch (access_type) {
1611 /* Floating point load/store */
1612 env->exception_index = POWERPC_EXCP_ALIGN;
1613 env->error_code = POWERPC_EXCP_ALIGN_FP;
1614 env->spr[SPR_DAR] = address;
1617 /* lwarx, ldarx or stwcx. */
1618 env->exception_index = POWERPC_EXCP_DSI;
1619 env->error_code = 0;
1620 env->spr[SPR_DAR] = address;
1622 env->spr[SPR_DSISR] = 0x06000000;
1624 env->spr[SPR_DSISR] = 0x04000000;
1627 /* eciwx or ecowx */
1628 env->exception_index = POWERPC_EXCP_DSI;
1629 env->error_code = 0;
1630 env->spr[SPR_DAR] = address;
1632 env->spr[SPR_DSISR] = 0x06100000;
1634 env->spr[SPR_DSISR] = 0x04100000;
1637 printf("DSI: invalid exception (%d)\n", ret);
1638 env->exception_index = POWERPC_EXCP_PROGRAM;
1640 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL;
1641 env->spr[SPR_DAR] = address;
1645 #if defined(TARGET_PPC64)
1647 /* No match in segment table */
1648 if (env->mmu_model == POWERPC_MMU_620) {
1649 env->exception_index = POWERPC_EXCP_DSI;
1650 env->error_code = 0;
1651 env->spr[SPR_DAR] = address;
1652 /* XXX: this might be incorrect */
1654 env->spr[SPR_DSISR] = 0x42000000;
1656 env->spr[SPR_DSISR] = 0x40000000;
1658 env->exception_index = POWERPC_EXCP_DSEG;
1659 env->error_code = 0;
1660 env->spr[SPR_DAR] = address;
1667 printf("%s: set exception to %d %02x\n", __func__,
1668 env->exception, env->error_code);
1676 /*****************************************************************************/
1677 /* BATs management */
1678 #if !defined(FLUSH_ALL_TLBS)
1679 static always_inline void do_invalidate_BAT (CPUPPCState *env,
1683 target_ulong base, end, page;
1685 base = BATu & ~0x0001FFFF;
1686 end = base + mask + 0x00020000;
1687 LOG_BATS("Flush BAT from " ADDRX " to " ADDRX " (" ADDRX ")\n",
1689 for (page = base; page != end; page += TARGET_PAGE_SIZE)
1690 tlb_flush_page(env, page);
1691 LOG_BATS("Flush done\n");
1695 static always_inline void dump_store_bat (CPUPPCState *env, char ID,
1696 int ul, int nr, target_ulong value)
1698 LOG_BATS("Set %cBAT%d%c to " ADDRX " (" ADDRX ")\n",
1699 ID, nr, ul == 0 ? 'u' : 'l', value, env->nip);
1702 void ppc_store_ibatu (CPUPPCState *env, int nr, target_ulong value)
1706 dump_store_bat(env, 'I', 0, nr, value);
1707 if (env->IBAT[0][nr] != value) {
1708 mask = (value << 15) & 0x0FFE0000UL;
1709 #if !defined(FLUSH_ALL_TLBS)
1710 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1712 /* When storing valid upper BAT, mask BEPI and BRPN
1713 * and invalidate all TLBs covered by this BAT
1715 mask = (value << 15) & 0x0FFE0000UL;
1716 env->IBAT[0][nr] = (value & 0x00001FFFUL) |
1717 (value & ~0x0001FFFFUL & ~mask);
1718 env->IBAT[1][nr] = (env->IBAT[1][nr] & 0x0000007B) |
1719 (env->IBAT[1][nr] & ~0x0001FFFF & ~mask);
1720 #if !defined(FLUSH_ALL_TLBS)
1721 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1728 void ppc_store_ibatl (CPUPPCState *env, int nr, target_ulong value)
1730 dump_store_bat(env, 'I', 1, nr, value);
1731 env->IBAT[1][nr] = value;
1734 void ppc_store_dbatu (CPUPPCState *env, int nr, target_ulong value)
1738 dump_store_bat(env, 'D', 0, nr, value);
1739 if (env->DBAT[0][nr] != value) {
1740 /* When storing valid upper BAT, mask BEPI and BRPN
1741 * and invalidate all TLBs covered by this BAT
1743 mask = (value << 15) & 0x0FFE0000UL;
1744 #if !defined(FLUSH_ALL_TLBS)
1745 do_invalidate_BAT(env, env->DBAT[0][nr], mask);
1747 mask = (value << 15) & 0x0FFE0000UL;
1748 env->DBAT[0][nr] = (value & 0x00001FFFUL) |
1749 (value & ~0x0001FFFFUL & ~mask);
1750 env->DBAT[1][nr] = (env->DBAT[1][nr] & 0x0000007B) |
1751 (env->DBAT[1][nr] & ~0x0001FFFF & ~mask);
1752 #if !defined(FLUSH_ALL_TLBS)
1753 do_invalidate_BAT(env, env->DBAT[0][nr], mask);
1760 void ppc_store_dbatl (CPUPPCState *env, int nr, target_ulong value)
1762 dump_store_bat(env, 'D', 1, nr, value);
1763 env->DBAT[1][nr] = value;
1766 void ppc_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value)
1771 dump_store_bat(env, 'I', 0, nr, value);
1772 if (env->IBAT[0][nr] != value) {
1774 mask = (env->IBAT[1][nr] << 17) & 0x0FFE0000UL;
1775 if (env->IBAT[1][nr] & 0x40) {
1776 /* Invalidate BAT only if it is valid */
1777 #if !defined(FLUSH_ALL_TLBS)
1778 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1783 /* When storing valid upper BAT, mask BEPI and BRPN
1784 * and invalidate all TLBs covered by this BAT
1786 env->IBAT[0][nr] = (value & 0x00001FFFUL) |
1787 (value & ~0x0001FFFFUL & ~mask);
1788 env->DBAT[0][nr] = env->IBAT[0][nr];
1789 if (env->IBAT[1][nr] & 0x40) {
1790 #if !defined(FLUSH_ALL_TLBS)
1791 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1796 #if defined(FLUSH_ALL_TLBS)
1803 void ppc_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value)
1808 dump_store_bat(env, 'I', 1, nr, value);
1809 if (env->IBAT[1][nr] != value) {
1811 if (env->IBAT[1][nr] & 0x40) {
1812 #if !defined(FLUSH_ALL_TLBS)
1813 mask = (env->IBAT[1][nr] << 17) & 0x0FFE0000UL;
1814 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1820 #if !defined(FLUSH_ALL_TLBS)
1821 mask = (value << 17) & 0x0FFE0000UL;
1822 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1827 env->IBAT[1][nr] = value;
1828 env->DBAT[1][nr] = value;
1829 #if defined(FLUSH_ALL_TLBS)
1836 /*****************************************************************************/
1837 /* TLB management */
1838 void ppc_tlb_invalidate_all (CPUPPCState *env)
1840 switch (env->mmu_model) {
1841 case POWERPC_MMU_SOFT_6xx:
1842 case POWERPC_MMU_SOFT_74xx:
1843 ppc6xx_tlb_invalidate_all(env);
1845 case POWERPC_MMU_SOFT_4xx:
1846 case POWERPC_MMU_SOFT_4xx_Z:
1847 ppc4xx_tlb_invalidate_all(env);
1849 case POWERPC_MMU_REAL:
1850 cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
1852 case POWERPC_MMU_MPC8xx:
1854 cpu_abort(env, "MPC8xx MMU model is not implemented\n");
1856 case POWERPC_MMU_BOOKE:
1858 cpu_abort(env, "BookE MMU model is not implemented\n");
1860 case POWERPC_MMU_BOOKE_FSL:
1863 cpu_abort(env, "BookE MMU model is not implemented\n");
1865 case POWERPC_MMU_32B:
1866 case POWERPC_MMU_601:
1867 #if defined(TARGET_PPC64)
1868 case POWERPC_MMU_620:
1869 case POWERPC_MMU_64B:
1870 #endif /* defined(TARGET_PPC64) */
1875 cpu_abort(env, "Unknown MMU model\n");
1880 void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr)
1882 #if !defined(FLUSH_ALL_TLBS)
1883 addr &= TARGET_PAGE_MASK;
1884 switch (env->mmu_model) {
1885 case POWERPC_MMU_SOFT_6xx:
1886 case POWERPC_MMU_SOFT_74xx:
1887 ppc6xx_tlb_invalidate_virt(env, addr, 0);
1888 if (env->id_tlbs == 1)
1889 ppc6xx_tlb_invalidate_virt(env, addr, 1);
1891 case POWERPC_MMU_SOFT_4xx:
1892 case POWERPC_MMU_SOFT_4xx_Z:
1893 ppc4xx_tlb_invalidate_virt(env, addr, env->spr[SPR_40x_PID]);
1895 case POWERPC_MMU_REAL:
1896 cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
1898 case POWERPC_MMU_MPC8xx:
1900 cpu_abort(env, "MPC8xx MMU model is not implemented\n");
1902 case POWERPC_MMU_BOOKE:
1904 cpu_abort(env, "BookE MMU model is not implemented\n");
1906 case POWERPC_MMU_BOOKE_FSL:
1908 cpu_abort(env, "BookE FSL MMU model is not implemented\n");
1910 case POWERPC_MMU_32B:
1911 case POWERPC_MMU_601:
1912 /* tlbie invalidate TLBs for all segments */
1913 addr &= ~((target_ulong)-1ULL << 28);
1914 /* XXX: this case should be optimized,
1915 * giving a mask to tlb_flush_page
1917 tlb_flush_page(env, addr | (0x0 << 28));
1918 tlb_flush_page(env, addr | (0x1 << 28));
1919 tlb_flush_page(env, addr | (0x2 << 28));
1920 tlb_flush_page(env, addr | (0x3 << 28));
1921 tlb_flush_page(env, addr | (0x4 << 28));
1922 tlb_flush_page(env, addr | (0x5 << 28));
1923 tlb_flush_page(env, addr | (0x6 << 28));
1924 tlb_flush_page(env, addr | (0x7 << 28));
1925 tlb_flush_page(env, addr | (0x8 << 28));
1926 tlb_flush_page(env, addr | (0x9 << 28));
1927 tlb_flush_page(env, addr | (0xA << 28));
1928 tlb_flush_page(env, addr | (0xB << 28));
1929 tlb_flush_page(env, addr | (0xC << 28));
1930 tlb_flush_page(env, addr | (0xD << 28));
1931 tlb_flush_page(env, addr | (0xE << 28));
1932 tlb_flush_page(env, addr | (0xF << 28));
1934 #if defined(TARGET_PPC64)
1935 case POWERPC_MMU_620:
1936 case POWERPC_MMU_64B:
1937 /* tlbie invalidate TLBs for all segments */
1938 /* XXX: given the fact that there are too many segments to invalidate,
1939 * and we still don't have a tlb_flush_mask(env, n, mask) in Qemu,
1940 * we just invalidate all TLBs
1944 #endif /* defined(TARGET_PPC64) */
1947 cpu_abort(env, "Unknown MMU model\n");
1951 ppc_tlb_invalidate_all(env);
1955 /*****************************************************************************/
1956 /* Special registers manipulation */
1957 #if defined(TARGET_PPC64)
1958 void ppc_store_asr (CPUPPCState *env, target_ulong value)
1960 if (env->asr != value) {
1967 void ppc_store_sdr1 (CPUPPCState *env, target_ulong value)
1969 LOG_MMU("%s: " ADDRX "\n", __func__, value);
1970 if (env->sdr1 != value) {
1971 /* XXX: for PowerPC 64, should check that the HTABSIZE value
1979 #if defined(TARGET_PPC64)
1980 target_ulong ppc_load_sr (CPUPPCState *env, int slb_nr)
1987 void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value)
1989 LOG_MMU("%s: reg=%d " ADDRX " " ADDRX "\n",
1990 __func__, srnum, value, env->sr[srnum]);
1991 #if defined(TARGET_PPC64)
1992 if (env->mmu_model & POWERPC_MMU_64) {
1993 uint64_t rb = 0, rs = 0;
1996 rb |= ((uint32_t)srnum & 0xf) << 28;
1997 /* Set the valid bit */
2000 rb |= (uint32_t)srnum;
2003 rs |= (value & 0xfffffff) << 12;
2005 rs |= ((value >> 27) & 0xf) << 9;
2007 ppc_store_slb(env, rb, rs);
2010 if (env->sr[srnum] != value) {
2011 env->sr[srnum] = value;
2012 #if !defined(FLUSH_ALL_TLBS) && 0
2014 target_ulong page, end;
2015 /* Invalidate 256 MB of virtual memory */
2016 page = (16 << 20) * srnum;
2017 end = page + (16 << 20);
2018 for (; page != end; page += TARGET_PAGE_SIZE)
2019 tlb_flush_page(env, page);
2026 #endif /* !defined (CONFIG_USER_ONLY) */
2028 /* GDBstub can read and write MSR... */
2029 void ppc_store_msr (CPUPPCState *env, target_ulong value)
2031 hreg_store_msr(env, value, 0);
2034 /*****************************************************************************/
2035 /* Exception processing */
2036 #if defined (CONFIG_USER_ONLY)
2037 void do_interrupt (CPUState *env)
2039 env->exception_index = POWERPC_EXCP_NONE;
2040 env->error_code = 0;
2043 void ppc_hw_interrupt (CPUState *env)
2045 env->exception_index = POWERPC_EXCP_NONE;
2046 env->error_code = 0;
2048 #else /* defined (CONFIG_USER_ONLY) */
2049 static always_inline void dump_syscall (CPUState *env)
2051 qemu_log_mask(CPU_LOG_INT, "syscall r0=" REGX " r3=" REGX " r4=" REGX
2052 " r5=" REGX " r6=" REGX " nip=" ADDRX "\n",
2053 ppc_dump_gpr(env, 0), ppc_dump_gpr(env, 3), ppc_dump_gpr(env, 4),
2054 ppc_dump_gpr(env, 5), ppc_dump_gpr(env, 6), env->nip);
2057 /* Note that this function should be greatly optimized
2058 * when called with a constant excp, from ppc_hw_interrupt
2060 static always_inline void powerpc_excp (CPUState *env,
2061 int excp_model, int excp)
2063 target_ulong msr, new_msr, vector;
2064 int srr0, srr1, asrr0, asrr1;
2065 int lpes0, lpes1, lev;
2068 /* XXX: find a suitable condition to enable the hypervisor mode */
2069 lpes0 = (env->spr[SPR_LPCR] >> 1) & 1;
2070 lpes1 = (env->spr[SPR_LPCR] >> 2) & 1;
2072 /* Those values ensure we won't enter the hypervisor mode */
2077 qemu_log_mask(CPU_LOG_INT, "Raise exception at " ADDRX " => %08x (%02x)\n",
2078 env->nip, excp, env->error_code);
2085 msr &= ~((target_ulong)0x783F0000);
2087 case POWERPC_EXCP_NONE:
2088 /* Should never happen */
2090 case POWERPC_EXCP_CRITICAL: /* Critical input */
2091 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2092 switch (excp_model) {
2093 case POWERPC_EXCP_40x:
2094 srr0 = SPR_40x_SRR2;
2095 srr1 = SPR_40x_SRR3;
2097 case POWERPC_EXCP_BOOKE:
2098 srr0 = SPR_BOOKE_CSRR0;
2099 srr1 = SPR_BOOKE_CSRR1;
2101 case POWERPC_EXCP_G2:
2107 case POWERPC_EXCP_MCHECK: /* Machine check exception */
2109 /* Machine check exception is not enabled.
2110 * Enter checkstop state.
2112 if (qemu_log_enabled()) {
2113 qemu_log("Machine check while not allowed. "
2114 "Entering checkstop state\n");
2116 fprintf(stderr, "Machine check while not allowed. "
2117 "Entering checkstop state\n");
2120 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
2122 new_msr &= ~((target_ulong)1 << MSR_RI);
2123 new_msr &= ~((target_ulong)1 << MSR_ME);
2125 /* XXX: find a suitable condition to enable the hypervisor mode */
2126 new_msr |= (target_ulong)MSR_HVB;
2128 /* XXX: should also have something loaded in DAR / DSISR */
2129 switch (excp_model) {
2130 case POWERPC_EXCP_40x:
2131 srr0 = SPR_40x_SRR2;
2132 srr1 = SPR_40x_SRR3;
2134 case POWERPC_EXCP_BOOKE:
2135 srr0 = SPR_BOOKE_MCSRR0;
2136 srr1 = SPR_BOOKE_MCSRR1;
2137 asrr0 = SPR_BOOKE_CSRR0;
2138 asrr1 = SPR_BOOKE_CSRR1;
2144 case POWERPC_EXCP_DSI: /* Data storage exception */
2145 LOG_EXCP("DSI exception: DSISR=" ADDRX" DAR=" ADDRX "\n",
2146 env->spr[SPR_DSISR], env->spr[SPR_DAR]);
2147 new_msr &= ~((target_ulong)1 << MSR_RI);
2149 new_msr |= (target_ulong)MSR_HVB;
2151 case POWERPC_EXCP_ISI: /* Instruction storage exception */
2152 LOG_EXCP("ISI exception: msr=" ADDRX ", nip=" ADDRX "\n",
2154 new_msr &= ~((target_ulong)1 << MSR_RI);
2156 new_msr |= (target_ulong)MSR_HVB;
2157 msr |= env->error_code;
2159 case POWERPC_EXCP_EXTERNAL: /* External input */
2160 new_msr &= ~((target_ulong)1 << MSR_RI);
2162 new_msr |= (target_ulong)MSR_HVB;
2164 case POWERPC_EXCP_ALIGN: /* Alignment exception */
2165 new_msr &= ~((target_ulong)1 << MSR_RI);
2167 new_msr |= (target_ulong)MSR_HVB;
2168 /* XXX: this is false */
2169 /* Get rS/rD and rA from faulting opcode */
2170 env->spr[SPR_DSISR] |= (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16;
2172 case POWERPC_EXCP_PROGRAM: /* Program exception */
2173 switch (env->error_code & ~0xF) {
2174 case POWERPC_EXCP_FP:
2175 if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
2176 LOG_EXCP("Ignore floating point exception\n");
2177 env->exception_index = POWERPC_EXCP_NONE;
2178 env->error_code = 0;
2181 new_msr &= ~((target_ulong)1 << MSR_RI);
2183 new_msr |= (target_ulong)MSR_HVB;
2185 if (msr_fe0 == msr_fe1)
2189 case POWERPC_EXCP_INVAL:
2190 LOG_EXCP("Invalid instruction at " ADDRX "\n",
2192 new_msr &= ~((target_ulong)1 << MSR_RI);
2194 new_msr |= (target_ulong)MSR_HVB;
2197 case POWERPC_EXCP_PRIV:
2198 new_msr &= ~((target_ulong)1 << MSR_RI);
2200 new_msr |= (target_ulong)MSR_HVB;
2203 case POWERPC_EXCP_TRAP:
2204 new_msr &= ~((target_ulong)1 << MSR_RI);
2206 new_msr |= (target_ulong)MSR_HVB;
2210 /* Should never occur */
2211 cpu_abort(env, "Invalid program exception %d. Aborting\n",
2216 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
2217 new_msr &= ~((target_ulong)1 << MSR_RI);
2219 new_msr |= (target_ulong)MSR_HVB;
2221 case POWERPC_EXCP_SYSCALL: /* System call exception */
2222 /* NOTE: this is a temporary hack to support graphics OSI
2223 calls from the MOL driver */
2224 /* XXX: To be removed */
2225 if (env->gpr[3] == 0x113724fa && env->gpr[4] == 0x77810f9b &&
2227 if (env->osi_call(env) != 0) {
2228 env->exception_index = POWERPC_EXCP_NONE;
2229 env->error_code = 0;
2234 new_msr &= ~((target_ulong)1 << MSR_RI);
2235 lev = env->error_code;
2236 if (lev == 1 || (lpes0 == 0 && lpes1 == 0))
2237 new_msr |= (target_ulong)MSR_HVB;
2239 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
2240 new_msr &= ~((target_ulong)1 << MSR_RI);
2242 case POWERPC_EXCP_DECR: /* Decrementer exception */
2243 new_msr &= ~((target_ulong)1 << MSR_RI);
2245 new_msr |= (target_ulong)MSR_HVB;
2247 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
2249 LOG_EXCP("FIT exception\n");
2250 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2252 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
2253 LOG_EXCP("WDT exception\n");
2254 switch (excp_model) {
2255 case POWERPC_EXCP_BOOKE:
2256 srr0 = SPR_BOOKE_CSRR0;
2257 srr1 = SPR_BOOKE_CSRR1;
2262 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2264 case POWERPC_EXCP_DTLB: /* Data TLB error */
2265 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2267 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
2268 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2270 case POWERPC_EXCP_DEBUG: /* Debug interrupt */
2271 switch (excp_model) {
2272 case POWERPC_EXCP_BOOKE:
2273 srr0 = SPR_BOOKE_DSRR0;
2274 srr1 = SPR_BOOKE_DSRR1;
2275 asrr0 = SPR_BOOKE_CSRR0;
2276 asrr1 = SPR_BOOKE_CSRR1;
2282 cpu_abort(env, "Debug exception is not implemented yet !\n");
2284 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable */
2285 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2287 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */
2289 cpu_abort(env, "Embedded floating point data exception "
2290 "is not implemented yet !\n");
2292 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */
2294 cpu_abort(env, "Embedded floating point round exception "
2295 "is not implemented yet !\n");
2297 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */
2298 new_msr &= ~((target_ulong)1 << MSR_RI);
2301 "Performance counter exception is not implemented yet !\n");
2303 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
2306 "Embedded doorbell interrupt is not implemented yet !\n");
2308 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
2309 switch (excp_model) {
2310 case POWERPC_EXCP_BOOKE:
2311 srr0 = SPR_BOOKE_CSRR0;
2312 srr1 = SPR_BOOKE_CSRR1;
2318 cpu_abort(env, "Embedded doorbell critical interrupt "
2319 "is not implemented yet !\n");
2321 case POWERPC_EXCP_RESET: /* System reset exception */
2322 new_msr &= ~((target_ulong)1 << MSR_RI);
2324 /* XXX: find a suitable condition to enable the hypervisor mode */
2325 new_msr |= (target_ulong)MSR_HVB;
2328 case POWERPC_EXCP_DSEG: /* Data segment exception */
2329 new_msr &= ~((target_ulong)1 << MSR_RI);
2331 new_msr |= (target_ulong)MSR_HVB;
2333 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
2334 new_msr &= ~((target_ulong)1 << MSR_RI);
2336 new_msr |= (target_ulong)MSR_HVB;
2338 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
2341 new_msr |= (target_ulong)MSR_HVB;
2343 case POWERPC_EXCP_TRACE: /* Trace exception */
2344 new_msr &= ~((target_ulong)1 << MSR_RI);
2346 new_msr |= (target_ulong)MSR_HVB;
2348 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
2351 new_msr |= (target_ulong)MSR_HVB;
2353 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */
2356 new_msr |= (target_ulong)MSR_HVB;
2358 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
2361 new_msr |= (target_ulong)MSR_HVB;
2363 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */
2366 new_msr |= (target_ulong)MSR_HVB;
2368 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
2369 new_msr &= ~((target_ulong)1 << MSR_RI);
2371 new_msr |= (target_ulong)MSR_HVB;
2373 case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
2374 LOG_EXCP("PIT exception\n");
2375 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2377 case POWERPC_EXCP_IO: /* IO error exception */
2379 cpu_abort(env, "601 IO error exception is not implemented yet !\n");
2381 case POWERPC_EXCP_RUNM: /* Run mode exception */
2383 cpu_abort(env, "601 run mode exception is not implemented yet !\n");
2385 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
2387 cpu_abort(env, "602 emulation trap exception "
2388 "is not implemented yet !\n");
2390 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
2391 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2392 if (lpes1 == 0) /* XXX: check this */
2393 new_msr |= (target_ulong)MSR_HVB;
2394 switch (excp_model) {
2395 case POWERPC_EXCP_602:
2396 case POWERPC_EXCP_603:
2397 case POWERPC_EXCP_603E:
2398 case POWERPC_EXCP_G2:
2400 case POWERPC_EXCP_7x5:
2402 case POWERPC_EXCP_74xx:
2405 cpu_abort(env, "Invalid instruction TLB miss exception\n");
2409 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
2410 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2411 if (lpes1 == 0) /* XXX: check this */
2412 new_msr |= (target_ulong)MSR_HVB;
2413 switch (excp_model) {
2414 case POWERPC_EXCP_602:
2415 case POWERPC_EXCP_603:
2416 case POWERPC_EXCP_603E:
2417 case POWERPC_EXCP_G2:
2419 case POWERPC_EXCP_7x5:
2421 case POWERPC_EXCP_74xx:
2424 cpu_abort(env, "Invalid data load TLB miss exception\n");
2428 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
2429 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2430 if (lpes1 == 0) /* XXX: check this */
2431 new_msr |= (target_ulong)MSR_HVB;
2432 switch (excp_model) {
2433 case POWERPC_EXCP_602:
2434 case POWERPC_EXCP_603:
2435 case POWERPC_EXCP_603E:
2436 case POWERPC_EXCP_G2:
2438 /* Swap temporary saved registers with GPRs */
2439 if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
2440 new_msr |= (target_ulong)1 << MSR_TGPR;
2441 hreg_swap_gpr_tgpr(env);
2444 case POWERPC_EXCP_7x5:
2446 #if defined (DEBUG_SOFTWARE_TLB)
2447 if (qemu_log_enabled()) {
2448 const unsigned char *es;
2449 target_ulong *miss, *cmp;
2451 if (excp == POWERPC_EXCP_IFTLB) {
2454 miss = &env->spr[SPR_IMISS];
2455 cmp = &env->spr[SPR_ICMP];
2457 if (excp == POWERPC_EXCP_DLTLB)
2462 miss = &env->spr[SPR_DMISS];
2463 cmp = &env->spr[SPR_DCMP];
2465 qemu_log("6xx %sTLB miss: %cM " ADDRX " %cC " ADDRX
2466 " H1 " ADDRX " H2 " ADDRX " %08x\n",
2467 es, en, *miss, en, *cmp,
2468 env->spr[SPR_HASH1], env->spr[SPR_HASH2],
2472 msr |= env->crf[0] << 28;
2473 msr |= env->error_code; /* key, D/I, S/L bits */
2474 /* Set way using a LRU mechanism */
2475 msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
2477 case POWERPC_EXCP_74xx:
2479 #if defined (DEBUG_SOFTWARE_TLB)
2480 if (qemu_log_enabled()) {
2481 const unsigned char *es;
2482 target_ulong *miss, *cmp;
2484 if (excp == POWERPC_EXCP_IFTLB) {
2487 miss = &env->spr[SPR_TLBMISS];
2488 cmp = &env->spr[SPR_PTEHI];
2490 if (excp == POWERPC_EXCP_DLTLB)
2495 miss = &env->spr[SPR_TLBMISS];
2496 cmp = &env->spr[SPR_PTEHI];
2498 qemu_log("74xx %sTLB miss: %cM " ADDRX " %cC " ADDRX
2500 es, en, *miss, en, *cmp, env->error_code);
2503 msr |= env->error_code; /* key bit */
2506 cpu_abort(env, "Invalid data store TLB miss exception\n");
2510 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
2512 cpu_abort(env, "Floating point assist exception "
2513 "is not implemented yet !\n");
2515 case POWERPC_EXCP_DABR: /* Data address breakpoint */
2517 cpu_abort(env, "DABR exception is not implemented yet !\n");
2519 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
2521 cpu_abort(env, "IABR exception is not implemented yet !\n");
2523 case POWERPC_EXCP_SMI: /* System management interrupt */
2525 cpu_abort(env, "SMI exception is not implemented yet !\n");
2527 case POWERPC_EXCP_THERM: /* Thermal interrupt */
2529 cpu_abort(env, "Thermal management exception "
2530 "is not implemented yet !\n");
2532 case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
2533 new_msr &= ~((target_ulong)1 << MSR_RI);
2535 new_msr |= (target_ulong)MSR_HVB;
2538 "Performance counter exception is not implemented yet !\n");
2540 case POWERPC_EXCP_VPUA: /* Vector assist exception */
2542 cpu_abort(env, "VPU assist exception is not implemented yet !\n");
2544 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
2547 "970 soft-patch exception is not implemented yet !\n");
2549 case POWERPC_EXCP_MAINT: /* Maintenance exception */
2552 "970 maintenance exception is not implemented yet !\n");
2554 case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */
2556 cpu_abort(env, "Maskable external exception "
2557 "is not implemented yet !\n");
2559 case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */
2561 cpu_abort(env, "Non maskable external exception "
2562 "is not implemented yet !\n");
2566 cpu_abort(env, "Invalid PowerPC exception %d. Aborting\n", excp);
2569 /* save current instruction location */
2570 env->spr[srr0] = env->nip - 4;
2573 /* save next instruction location */
2574 env->spr[srr0] = env->nip;
2578 env->spr[srr1] = msr;
2579 /* If any alternate SRR register are defined, duplicate saved values */
2581 env->spr[asrr0] = env->spr[srr0];
2583 env->spr[asrr1] = env->spr[srr1];
2584 /* If we disactivated any translation, flush TLBs */
2585 if (new_msr & ((1 << MSR_IR) | (1 << MSR_DR)))
2587 /* reload MSR with correct bits */
2588 new_msr &= ~((target_ulong)1 << MSR_EE);
2589 new_msr &= ~((target_ulong)1 << MSR_PR);
2590 new_msr &= ~((target_ulong)1 << MSR_FP);
2591 new_msr &= ~((target_ulong)1 << MSR_FE0);
2592 new_msr &= ~((target_ulong)1 << MSR_SE);
2593 new_msr &= ~((target_ulong)1 << MSR_BE);
2594 new_msr &= ~((target_ulong)1 << MSR_FE1);
2595 new_msr &= ~((target_ulong)1 << MSR_IR);
2596 new_msr &= ~((target_ulong)1 << MSR_DR);
2597 #if 0 /* Fix this: not on all targets */
2598 new_msr &= ~((target_ulong)1 << MSR_PMM);
2600 new_msr &= ~((target_ulong)1 << MSR_LE);
2602 new_msr |= (target_ulong)1 << MSR_LE;
2604 new_msr &= ~((target_ulong)1 << MSR_LE);
2605 /* Jump to handler */
2606 vector = env->excp_vectors[excp];
2607 if (vector == (target_ulong)-1ULL) {
2608 cpu_abort(env, "Raised an exception without defined vector %d\n",
2611 vector |= env->excp_prefix;
2612 #if defined(TARGET_PPC64)
2613 if (excp_model == POWERPC_EXCP_BOOKE) {
2615 new_msr &= ~((target_ulong)1 << MSR_CM);
2616 vector = (uint32_t)vector;
2618 new_msr |= (target_ulong)1 << MSR_CM;
2621 if (!msr_isf && !(env->mmu_model & POWERPC_MMU_64)) {
2622 new_msr &= ~((target_ulong)1 << MSR_SF);
2623 vector = (uint32_t)vector;
2625 new_msr |= (target_ulong)1 << MSR_SF;
2629 /* XXX: we don't use hreg_store_msr here as already have treated
2630 * any special case that could occur. Just store MSR and update hflags
2632 env->msr = new_msr & env->msr_mask;
2633 hreg_compute_hflags(env);
2635 /* Reset exception state */
2636 env->exception_index = POWERPC_EXCP_NONE;
2637 env->error_code = 0;
2640 void do_interrupt (CPUState *env)
2642 powerpc_excp(env, env->excp_model, env->exception_index);
2645 void ppc_hw_interrupt (CPUPPCState *env)
2650 qemu_log_mask(CPU_LOG_INT, "%s: %p pending %08x req %08x me %d ee %d\n",
2651 __func__, env, env->pending_interrupts,
2652 env->interrupt_request, (int)msr_me, (int)msr_ee);
2654 /* External reset */
2655 if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) {
2656 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET);
2657 powerpc_excp(env, env->excp_model, POWERPC_EXCP_RESET);
2660 /* Machine check exception */
2661 if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) {
2662 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK);
2663 powerpc_excp(env, env->excp_model, POWERPC_EXCP_MCHECK);
2667 /* External debug exception */
2668 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) {
2669 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG);
2670 powerpc_excp(env, env->excp_model, POWERPC_EXCP_DEBUG);
2675 /* XXX: find a suitable condition to enable the hypervisor mode */
2676 hdice = env->spr[SPR_LPCR] & 1;
2680 if ((msr_ee != 0 || msr_hv == 0 || msr_pr != 0) && hdice != 0) {
2681 /* Hypervisor decrementer exception */
2682 if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) {
2683 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
2684 powerpc_excp(env, env->excp_model, POWERPC_EXCP_HDECR);
2689 /* External critical interrupt */
2690 if (env->pending_interrupts & (1 << PPC_INTERRUPT_CEXT)) {
2691 /* Taking a critical external interrupt does not clear the external
2692 * critical interrupt status
2695 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CEXT);
2697 powerpc_excp(env, env->excp_model, POWERPC_EXCP_CRITICAL);
2702 /* Watchdog timer on embedded PowerPC */
2703 if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) {
2704 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT);
2705 powerpc_excp(env, env->excp_model, POWERPC_EXCP_WDT);
2708 if (env->pending_interrupts & (1 << PPC_INTERRUPT_CDOORBELL)) {
2709 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CDOORBELL);
2710 powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORCI);
2713 /* Fixed interval timer on embedded PowerPC */
2714 if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) {
2715 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT);
2716 powerpc_excp(env, env->excp_model, POWERPC_EXCP_FIT);
2719 /* Programmable interval timer on embedded PowerPC */
2720 if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) {
2721 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT);
2722 powerpc_excp(env, env->excp_model, POWERPC_EXCP_PIT);
2725 /* Decrementer exception */
2726 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) {
2727 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR);
2728 powerpc_excp(env, env->excp_model, POWERPC_EXCP_DECR);
2731 /* External interrupt */
2732 if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) {
2733 /* Taking an external interrupt does not clear the external
2737 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT);
2739 powerpc_excp(env, env->excp_model, POWERPC_EXCP_EXTERNAL);
2742 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) {
2743 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL);
2744 powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORI);
2747 if (env->pending_interrupts & (1 << PPC_INTERRUPT_PERFM)) {
2748 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PERFM);
2749 powerpc_excp(env, env->excp_model, POWERPC_EXCP_PERFM);
2752 /* Thermal interrupt */
2753 if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) {
2754 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM);
2755 powerpc_excp(env, env->excp_model, POWERPC_EXCP_THERM);
2760 #endif /* !CONFIG_USER_ONLY */
2762 void cpu_dump_rfi (target_ulong RA, target_ulong msr)
2764 qemu_log("Return from exception at " ADDRX " with flags " ADDRX "\n",
2768 void cpu_ppc_reset (void *opaque)
2770 CPUPPCState *env = opaque;
2773 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
2774 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
2775 log_cpu_state(env, 0);
2778 msr = (target_ulong)0;
2780 /* XXX: find a suitable condition to enable the hypervisor mode */
2781 msr |= (target_ulong)MSR_HVB;
2783 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
2784 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
2785 msr |= (target_ulong)1 << MSR_EP;
2786 #if defined (DO_SINGLE_STEP) && 0
2787 /* Single step trace mode */
2788 msr |= (target_ulong)1 << MSR_SE;
2789 msr |= (target_ulong)1 << MSR_BE;
2791 #if defined(CONFIG_USER_ONLY)
2792 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
2793 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
2794 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
2795 msr |= (target_ulong)1 << MSR_PR;
2797 env->nip = env->hreset_vector | env->excp_prefix;
2798 if (env->mmu_model != POWERPC_MMU_REAL)
2799 ppc_tlb_invalidate_all(env);
2801 env->msr = msr & env->msr_mask;
2802 #if defined(TARGET_PPC64)
2803 if (env->mmu_model & POWERPC_MMU_64)
2804 env->msr |= (1ULL << MSR_SF);
2806 hreg_compute_hflags(env);
2807 env->reserve = (target_ulong)-1ULL;
2808 /* Be sure no exception or interrupt is pending */
2809 env->pending_interrupts = 0;
2810 env->exception_index = POWERPC_EXCP_NONE;
2811 env->error_code = 0;
2812 /* Flush all TLBs */
2816 CPUPPCState *cpu_ppc_init (const char *cpu_model)
2819 const ppc_def_t *def;
2821 def = cpu_ppc_find_by_name(cpu_model);
2825 env = qemu_mallocz(sizeof(CPUPPCState));
2827 ppc_translate_init();
2828 env->cpu_model_str = cpu_model;
2829 cpu_ppc_register_internal(env, def);
2838 void cpu_ppc_close (CPUPPCState *env)
2840 /* Should also remove all opcode tables... */