2 * PPC emulation helpers for qemu.
4 * Copyright (c) 2003 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #if defined (USE_OPEN_FIRMWARE)
28 //#define DEBUG_EXCEPTIONS
30 /*****************************************************************************/
31 /* PPC MMU emulation */
33 /* Perform BAT hit & translation */
34 static int get_bat (CPUState *env, uint32_t *real, int *prot,
35 uint32_t virtual, int rw, int type)
37 uint32_t *BATlt, *BATut, *BATu, *BATl;
38 uint32_t base, BEPIl, BEPIu, bl;
42 #if defined (DEBUG_BATS)
44 fprintf(logfile, "%s: %cBAT v 0x%08x\n", __func__,
45 type == ACCESS_CODE ? 'I' : 'D', virtual);
58 #if defined (DEBUG_BATS)
60 fprintf(logfile, "%s...: %cBAT v 0x%08x\n", __func__,
61 type == ACCESS_CODE ? 'I' : 'D', virtual);
64 base = virtual & 0xFFFC0000;
65 for (i = 0; i < 4; i++) {
68 BEPIu = *BATu & 0xF0000000;
69 BEPIl = *BATu & 0x0FFE0000;
70 bl = (*BATu & 0x00001FFC) << 15;
71 #if defined (DEBUG_BATS)
73 fprintf(logfile, "%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x\n",
74 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
78 if ((virtual & 0xF0000000) == BEPIu &&
79 ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
81 if ((msr_pr == 0 && (*BATu & 0x00000002)) ||
82 (msr_pr == 1 && (*BATu & 0x00000001))) {
83 /* Get physical address */
84 *real = (*BATl & 0xF0000000) |
85 ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) |
86 (virtual & 0x0001F000);
87 if (*BATl & 0x00000001)
89 if (*BATl & 0x00000002)
90 *prot = PAGE_WRITE | PAGE_READ;
91 #if defined (DEBUG_BATS)
93 fprintf(logfile, "BAT %d match: r 0x%08x prot=%c%c\n",
94 i, *real, *prot & PAGE_READ ? 'R' : '-',
95 *prot & PAGE_WRITE ? 'W' : '-');
104 #if defined (DEBUG_BATS)
105 printf("no BAT match for 0x%08x:\n", virtual);
106 for (i = 0; i < 4; i++) {
109 BEPIu = *BATu & 0xF0000000;
110 BEPIl = *BATu & 0x0FFE0000;
111 bl = (*BATu & 0x00001FFC) << 15;
112 printf("%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x \n\t"
113 "0x%08x 0x%08x 0x%08x\n",
114 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
115 *BATu, *BATl, BEPIu, BEPIl, bl);
123 /* PTE table lookup */
124 static int find_pte (uint32_t *RPN, int *prot, uint32_t base, uint32_t va,
125 int h, int key, int rw)
127 uint32_t pte0, pte1, keep = 0, access = 0;
128 int i, good = -1, store = 0;
129 int ret = -1; /* No entry found */
131 for (i = 0; i < 8; i++) {
132 pte0 = ldl_raw(phys_ram_base + base + (i * 8));
133 pte1 = ldl_raw(phys_ram_base + base + (i * 8) + 4);
134 #if defined (DEBUG_MMU)
136 fprintf(logfile, "Load pte from 0x%08x => 0x%08x 0x%08x "
137 "%d %d %d 0x%08x\n", base + (i * 8), pte0, pte1,
138 pte0 >> 31, h, (pte0 >> 6) & 1, va);
141 /* Check validity and table match */
142 if (pte0 & 0x80000000 && (h == ((pte0 >> 6) & 1))) {
143 /* Check vsid & api */
144 if ((pte0 & 0x7FFFFFBF) == va) {
149 /* All matches should have equal RPN, WIMG & PP */
150 if ((keep & 0xFFFFF07B) != (pte1 & 0xFFFFF07B)) {
152 fprintf(logfile, "Bad RPN/WIMG/PP\n");
156 /* Check access rights */
159 if ((pte1 & 0x00000003) != 0x3)
160 access |= PAGE_WRITE;
162 switch (pte1 & 0x00000003) {
171 access = PAGE_READ | PAGE_WRITE;
176 if ((rw == 0 && (access & PAGE_READ)) ||
177 (rw == 1 && (access & PAGE_WRITE))) {
178 #if defined (DEBUG_MMU)
180 fprintf(logfile, "PTE access granted !\n");
186 /* Access right violation */
188 #if defined (DEBUG_MMU)
190 fprintf(logfile, "PTE access rejected\n");
199 *RPN = keep & 0xFFFFF000;
200 #if defined (DEBUG_MMU)
202 fprintf(logfile, "found PTE at addr 0x%08x prot=0x%01x ret=%d\n",
206 /* Update page flags */
207 if (!(keep & 0x00000100)) {
212 if (!(keep & 0x00000080)) {
213 if (rw && ret == 0) {
218 /* Force page fault for first write access */
219 *prot &= ~PAGE_WRITE;
223 stl_raw(phys_ram_base + base + (good * 8) + 4, keep);
230 static inline uint32_t get_pgaddr (uint32_t sdr1, uint32_t hash, uint32_t mask)
232 return (sdr1 & 0xFFFF0000) | (hash & mask);
235 /* Perform segment based translation */
236 static int get_segment (CPUState *env, uint32_t *real, int *prot,
237 uint32_t virtual, int rw, int type)
239 uint32_t pg_addr, sdr, ptem, vsid, pgidx;
245 sr = env->sr[virtual >> 28];
246 #if defined (DEBUG_MMU)
248 fprintf(logfile, "Check segment v=0x%08x %d 0x%08x nip=0x%08x "
249 "lr=0x%08x ir=%d dr=%d pr=%d %d t=%d\n",
250 virtual, virtual >> 28, sr, env->nip,
251 env->lr, msr_ir, msr_dr, msr_pr, rw, type);
254 key = (((sr & 0x20000000) && msr_pr == 1) ||
255 ((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0;
256 if ((sr & 0x80000000) == 0) {
257 #if defined (DEBUG_MMU)
259 fprintf(logfile, "pte segment: key=%d n=0x%08x\n",
260 key, sr & 0x10000000);
262 /* Check if instruction fetch is allowed, if needed */
263 if (type != ACCESS_CODE || (sr & 0x10000000) == 0) {
264 /* Page address translation */
265 vsid = sr & 0x00FFFFFF;
266 pgidx = (virtual >> 12) & 0xFFFF;
268 hash = ((vsid ^ pgidx) & 0x0007FFFF) << 6;
269 mask = ((sdr & 0x000001FF) << 16) | 0xFFC0;
270 pg_addr = get_pgaddr(sdr, hash, mask);
271 ptem = (vsid << 7) | (pgidx >> 10);
272 #if defined (DEBUG_MMU)
274 fprintf(logfile, "0 sdr1=0x%08x vsid=0x%06x api=0x%04x "
275 "hash=0x%07x pg_addr=0x%08x\n", sdr, vsid, pgidx, hash,
279 /* Primary table lookup */
280 ret = find_pte(real, prot, pg_addr, ptem, 0, key, rw);
282 /* Secondary table lookup */
283 hash = (~hash) & 0x01FFFFC0;
284 pg_addr = get_pgaddr(sdr, hash, mask);
285 #if defined (DEBUG_MMU)
286 if (virtual != 0xEFFFFFFF && loglevel > 0) {
287 fprintf(logfile, "1 sdr1=0x%08x vsid=0x%06x api=0x%04x "
288 "hash=0x%05x pg_addr=0x%08x\n", sdr, vsid, pgidx,
292 ret2 = find_pte(real, prot, pg_addr, ptem, 1, key, rw);
297 #if defined (DEBUG_MMU)
299 fprintf(logfile, "No access allowed\n");
304 #if defined (DEBUG_MMU)
306 fprintf(logfile, "direct store...\n");
308 /* Direct-store segment : absolutely *BUGGY* for now */
311 /* Integer load/store : only access allowed */
314 /* No code fetch is allowed in direct-store areas */
317 /* Floating point load/store */
320 /* lwarx, ldarx or srwcx. */
323 /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
324 /* Should make the instruction do no-op.
325 * As it already do no-op, it's quite easy :-)
334 fprintf(logfile, "ERROR: instruction should not need "
335 "address translation\n");
337 printf("ERROR: instruction should not need "
338 "address translation\n");
341 if ((rw == 1 || key != 1) && (rw == 0 || key != 0)) {
352 int get_physical_address (CPUState *env, uint32_t *physical, int *prot,
353 uint32_t address, int rw, int access_type)
358 fprintf(logfile, "%s\n", __func__);
361 if ((access_type == ACCESS_CODE && msr_ir == 0) ||
362 (access_type != ACCESS_CODE && msr_dr == 0)) {
363 /* No address translation */
364 *physical = address & ~0xFFF;
365 *prot = PAGE_READ | PAGE_WRITE;
368 /* Try to find a BAT */
369 ret = get_bat(env, physical, prot, address, rw, access_type);
371 /* We didn't match any BAT entry */
372 ret = get_segment(env, physical, prot, address, rw, access_type);
377 fprintf(logfile, "%s address %08x => %08x\n",
378 __func__, address, *physical);
384 #if defined(CONFIG_USER_ONLY)
385 target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
390 target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
395 if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
401 #if !defined(CONFIG_USER_ONLY)
403 #define MMUSUFFIX _mmu
404 #define GETPC() (__builtin_return_address(0))
407 #include "softmmu_template.h"
410 #include "softmmu_template.h"
413 #include "softmmu_template.h"
416 #include "softmmu_template.h"
418 /* try to fill the TLB and return an exception if error. If retaddr is
419 NULL, it means that the function was called in C code (i.e. not
420 from generated code or from helper.c) */
421 /* XXX: fix it to restore all registers */
422 void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr)
424 TranslationBlock *tb;
429 /* XXX: hack to restore env in all cases, even if not called from
432 env = cpu_single_env;
435 unsigned long tlb_addrr, tlb_addrw;
437 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
438 tlb_addrr = env->tlb_read[is_user][index].address;
439 tlb_addrw = env->tlb_write[is_user][index].address;
442 "%s 1 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
443 "(0x%08lx 0x%08lx)\n", __func__, env,
444 &env->tlb_read[is_user][index], index, addr,
445 tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
446 tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
450 ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, is_user, 1);
453 /* now we have a real cpu fault */
454 pc = (unsigned long)retaddr;
457 /* the PC is inside the translated code. It means that we have
458 a virtual CPU fault */
459 cpu_restore_state(tb, env, pc, NULL);
462 do_raise_exception_err(env->exception_index, env->error_code);
466 unsigned long tlb_addrr, tlb_addrw;
468 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
469 tlb_addrr = env->tlb_read[is_user][index].address;
470 tlb_addrw = env->tlb_write[is_user][index].address;
471 printf("%s 2 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
472 "(0x%08lx 0x%08lx)\n", __func__, env,
473 &env->tlb_read[is_user][index], index, addr,
474 tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
475 tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
481 void cpu_ppc_init_mmu(CPUState *env)
483 /* Nothing to do: all translation are disabled */
487 /* Perform address translation */
488 int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
489 int is_user, int is_softmmu)
493 int exception = 0, error_code = 0;
500 access_type = ACCESS_CODE;
503 /* XXX: put correct access by using cpu_restore_state()
505 access_type = ACCESS_INT;
506 // access_type = env->access_type;
508 if (env->user_mode_only) {
509 /* user mode only emulation */
513 ret = get_physical_address(env, &physical, &prot,
514 address, rw, access_type);
516 ret = tlb_set_page(env, address & ~0xFFF, physical, prot,
517 is_user, is_softmmu);
518 } else if (ret < 0) {
520 #if defined (DEBUG_MMU)
522 cpu_dump_state(env, logfile, fprintf, 0);
524 if (access_type == ACCESS_CODE) {
525 exception = EXCP_ISI;
528 /* No matches in page tables */
529 error_code = EXCP_ISI_TRANSLATE;
532 /* Access rights violation */
533 error_code = EXCP_ISI_PROT;
536 /* No execute protection violation */
537 error_code = EXCP_ISI_NOEXEC;
540 /* Direct store exception */
541 /* No code fetch is allowed in direct-store areas */
542 error_code = EXCP_ISI_DIRECT;
546 exception = EXCP_DSI;
549 /* No matches in page tables */
550 error_code = EXCP_DSI_TRANSLATE;
553 /* Access rights violation */
554 error_code = EXCP_DSI_PROT;
557 /* Direct store exception */
558 switch (access_type) {
560 /* Floating point load/store */
561 exception = EXCP_ALIGN;
562 error_code = EXCP_ALIGN_FP;
565 /* lwarx, ldarx or srwcx. */
566 exception = EXCP_DSI;
567 error_code = EXCP_DSI_NOTSUP | EXCP_DSI_DIRECT;
571 exception = EXCP_DSI;
572 error_code = EXCP_DSI_NOTSUP | EXCP_DSI_DIRECT |
576 printf("DSI: invalid exception (%d)\n", ret);
577 exception = EXCP_PROGRAM;
578 error_code = EXCP_INVAL | EXCP_INVAL_INVAL;
583 error_code |= EXCP_DSI_STORE;
584 /* Store fault address */
585 env->spr[DAR] = address;
588 printf("%s: set exception to %d %02x\n",
589 __func__, exception, error_code);
591 env->exception_index = exception;
592 env->error_code = error_code;
598 uint32_t _load_xer (CPUState *env)
600 return (xer_so << XER_SO) |
606 void _store_xer (CPUState *env, uint32_t value)
608 xer_so = (value >> XER_SO) & 0x01;
609 xer_ov = (value >> XER_OV) & 0x01;
610 xer_ca = (value >> XER_CA) & 0x01;
611 xer_bc = (value >> XER_BC) & 0x1f;
614 uint32_t _load_msr (CPUState *env)
616 return (msr_pow << MSR_POW) |
617 (msr_ile << MSR_ILE) |
622 (msr_fe0 << MSR_FE0) |
625 (msr_fe1 << MSR_FE1) |
633 void _store_msr (CPUState *env, uint32_t value)
636 if (((value >> MSR_IR) & 0x01) != msr_ir ||
637 ((value >> MSR_DR) & 0x01) != msr_dr)
639 /* Flush all tlb when changing translation mode or privilege level */
643 msr_pow = (value >> MSR_POW) & 0x03;
644 msr_ile = (value >> MSR_ILE) & 0x01;
645 msr_ee = (value >> MSR_EE) & 0x01;
646 msr_pr = (value >> MSR_PR) & 0x01;
647 msr_fp = (value >> MSR_FP) & 0x01;
648 msr_me = (value >> MSR_ME) & 0x01;
649 msr_fe0 = (value >> MSR_FE0) & 0x01;
650 msr_se = (value >> MSR_SE) & 0x01;
651 msr_be = (value >> MSR_BE) & 0x01;
652 msr_fe1 = (value >> MSR_FE1) & 0x01;
653 msr_ip = (value >> MSR_IP) & 0x01;
654 msr_ir = (value >> MSR_IR) & 0x01;
655 msr_dr = (value >> MSR_DR) & 0x01;
656 msr_ri = (value >> MSR_RI) & 0x01;
657 msr_le = (value >> MSR_LE) & 0x01;
660 void do_interrupt (CPUState *env)
662 #if defined (CONFIG_USER_ONLY)
663 env->exception_index |= 0x100;
666 int excp = env->exception_index;
668 msr = _load_msr(env);
669 #if defined (DEBUG_EXCEPTIONS)
670 if ((excp == EXCP_PROGRAM || excp == EXCP_DSI) && msr_pr == 1)
673 fprintf(logfile, "Raise exception at 0x%08x => 0x%08x (%02x)\n",
674 env->nip, excp << 8, env->error_code);
677 cpu_dump_state(env, logfile, fprintf, 0);
680 if (loglevel & CPU_LOG_INT) {
681 fprintf(logfile, "Raise exception at 0x%08x => 0x%08x (%02x)\n",
682 env->nip, excp << 8, env->error_code);
684 /* Generate informations in save/restore registers */
687 #if defined (USE_OPEN_FIRMWARE)
688 env->gpr[3] = OF_client_entry((void *)env->gpr[3]);
692 #if defined (USE_OPEN_FIRMWARE)
693 printf("RTAS call !\n");
694 env->gpr[3] = RTAS_entry((void *)env->gpr[3]);
695 printf("RTAS call done\n");
700 #if defined (DEBUG_EXCEPTIONS)
701 printf("%s: escape EXCP_NONE\n", __func__);
708 case EXCP_MACHINE_CHECK:
710 cpu_abort(env, "Machine check exception while not allowed\n");
715 /* Store exception cause */
716 /* data location address has been stored
717 * when the fault has been detected
721 if (env->error_code & EXCP_DSI_TRANSLATE)
722 env->spr[DSISR] |= 0x40000000;
723 else if (env->error_code & EXCP_DSI_PROT)
724 env->spr[DSISR] |= 0x08000000;
725 else if (env->error_code & EXCP_DSI_NOTSUP) {
726 env->spr[DSISR] |= 0x80000000;
727 if (env->error_code & EXCP_DSI_DIRECT)
728 env->spr[DSISR] |= 0x04000000;
730 if (env->error_code & EXCP_DSI_STORE)
731 env->spr[DSISR] |= 0x02000000;
732 if ((env->error_code & 0xF) == EXCP_DSI_DABR)
733 env->spr[DSISR] |= 0x00400000;
734 if (env->error_code & EXCP_DSI_ECXW)
735 env->spr[DSISR] |= 0x00100000;
736 #if defined (DEBUG_EXCEPTIONS)
738 fprintf(logfile, "DSI exception: DSISR=0x%08x, DAR=0x%08x\n",
739 env->spr[DSISR], env->spr[DAR]);
741 printf("DSI exception: DSISR=0x%08x, DAR=0x%08x nip=0x%08x\n",
742 env->spr[DSISR], env->spr[DAR], env->nip);
747 /* Store exception cause */
749 if (env->error_code == EXCP_ISI_TRANSLATE)
751 else if (env->error_code == EXCP_ISI_NOEXEC ||
752 env->error_code == EXCP_ISI_GUARD ||
753 env->error_code == EXCP_ISI_DIRECT)
757 #if defined (DEBUG_EXCEPTIONS)
759 fprintf(logfile, "ISI exception: msr=0x%08x, nip=0x%08x\n",
762 printf("ISI exception: msr=0x%08x, nip=0x%08x tbl:0x%08x\n",
763 msr, env->nip, env->spr[V_TBL]);
769 #if defined (DEBUG_EXCEPTIONS)
771 fprintf(logfile, "Skipping hardware interrupt\n");
775 do_raise_exception(EXCP_EXTERNAL);
780 /* Store exception cause */
781 /* Get rS/rD and rA from faulting opcode */
783 (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16;
784 /* data location address has been stored
785 * when the fault has been detected
790 switch (env->error_code & ~0xF) {
792 if (msr_fe0 == 0 && msr_fe1 == 0) {
793 #if defined (DEBUG_EXCEPTIONS)
794 printf("Ignore floating point exception\n");
800 env->fpscr[7] |= 0x8;
801 /* Finally, update FEX */
802 if ((((env->fpscr[7] & 0x3) << 3) | (env->fpscr[6] >> 1)) &
803 ((env->fpscr[1] << 1) | (env->fpscr[0] >> 3)))
804 env->fpscr[7] |= 0x4;
807 // printf("Invalid instruction at 0x%08x\n", env->nip);
817 /* Should never occur */
827 do_raise_exception(EXCP_DECR);
832 if (loglevel & CPU_LOG_INT) {
833 fprintf(logfile, "syscall %d 0x%08x 0x%08x 0x%08x 0x%08x\n",
834 env->gpr[0], env->gpr[3], env->gpr[4],
835 env->gpr[5], env->gpr[6]);
836 if (env->gpr[0] == 4 && env->gpr[3] == 1) {
840 fprintf(logfile, "write: ");
845 for(i = 0; i < len; i++) {
847 cpu_memory_rw_debug(env, addr + i, &c, 1, 0);
848 if (c < 32 || c > 126)
850 fprintf(logfile, "%c", c);
852 fprintf(logfile, "\n");
867 /* Restore user-mode state */
869 #if defined (DEBUG_EXCEPTIONS)
871 printf("Return from exception => 0x%08x\n", (uint32_t)env->nip);
875 /* SRR0 is set to current instruction */
876 env->spr[SRR0] = (uint32_t)env->nip - 4;
879 /* SRR0 is set to next instruction */
880 env->spr[SRR0] = (uint32_t)env->nip;
883 env->spr[SRR1] = msr;
884 /* reload MSR with correct bits */
897 /* Jump to handler */
898 env->nip = excp << 8;
899 env->exception_index = EXCP_NONE;
900 /* Invalidate all TLB as we may have changed translation mode */
902 /* ensure that no TB jump will be modified as
903 the program flow was changed */
910 env->exception_index = -1;