2 * PPC emulation helpers for qemu.
4 * Copyright (c) 2003 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 //#define DEBUG_EXCEPTIONS
26 /*****************************************************************************/
27 /* PPC MMU emulation */
29 /* Perform BAT hit & translation */
30 static int get_bat (CPUState *env, uint32_t *real, int *prot,
31 uint32_t virtual, int rw, int type)
33 uint32_t *BATlt, *BATut, *BATu, *BATl;
34 uint32_t base, BEPIl, BEPIu, bl;
38 #if defined (DEBUG_BATS)
40 fprintf(logfile, "%s: %cBAT v 0x%08x\n", __func__,
41 type == ACCESS_CODE ? 'I' : 'D', virtual);
54 #if defined (DEBUG_BATS)
56 fprintf(logfile, "%s...: %cBAT v 0x%08x\n", __func__,
57 type == ACCESS_CODE ? 'I' : 'D', virtual);
60 base = virtual & 0xFFFC0000;
61 for (i = 0; i < 4; i++) {
64 BEPIu = *BATu & 0xF0000000;
65 BEPIl = *BATu & 0x0FFE0000;
66 bl = (*BATu & 0x00001FFC) << 15;
67 #if defined (DEBUG_BATS)
69 fprintf(logfile, "%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x\n",
70 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
74 if ((virtual & 0xF0000000) == BEPIu &&
75 ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
77 if ((msr_pr == 0 && (*BATu & 0x00000002)) ||
78 (msr_pr == 1 && (*BATu & 0x00000001))) {
79 /* Get physical address */
80 *real = (*BATl & 0xF0000000) |
81 ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) |
82 (virtual & 0x0001F000);
83 if (*BATl & 0x00000001)
85 if (*BATl & 0x00000002)
86 *prot = PAGE_WRITE | PAGE_READ;
87 #if defined (DEBUG_BATS)
89 fprintf(logfile, "BAT %d match: r 0x%08x prot=%c%c\n",
90 i, *real, *prot & PAGE_READ ? 'R' : '-',
91 *prot & PAGE_WRITE ? 'W' : '-');
100 #if defined (DEBUG_BATS)
101 printf("no BAT match for 0x%08x:\n", virtual);
102 for (i = 0; i < 4; i++) {
105 BEPIu = *BATu & 0xF0000000;
106 BEPIl = *BATu & 0x0FFE0000;
107 bl = (*BATu & 0x00001FFC) << 15;
108 printf("%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x \n\t"
109 "0x%08x 0x%08x 0x%08x\n",
110 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
111 *BATu, *BATl, BEPIu, BEPIl, bl);
119 /* PTE table lookup */
120 static int find_pte (uint32_t *RPN, int *prot, uint32_t base, uint32_t va,
121 int h, int key, int rw)
123 uint32_t pte0, pte1, keep = 0, access = 0;
124 int i, good = -1, store = 0;
125 int ret = -1; /* No entry found */
127 for (i = 0; i < 8; i++) {
128 pte0 = ldl_phys(base + (i * 8));
129 pte1 = ldl_phys(base + (i * 8) + 4);
130 #if defined (DEBUG_MMU)
132 fprintf(logfile, "Load pte from 0x%08x => 0x%08x 0x%08x "
133 "%d %d %d 0x%08x\n", base + (i * 8), pte0, pte1,
134 pte0 >> 31, h, (pte0 >> 6) & 1, va);
137 /* Check validity and table match */
138 if (pte0 & 0x80000000 && (h == ((pte0 >> 6) & 1))) {
139 /* Check vsid & api */
140 if ((pte0 & 0x7FFFFFBF) == va) {
145 /* All matches should have equal RPN, WIMG & PP */
146 if ((keep & 0xFFFFF07B) != (pte1 & 0xFFFFF07B)) {
148 fprintf(logfile, "Bad RPN/WIMG/PP\n");
152 /* Check access rights */
155 if ((pte1 & 0x00000003) != 0x3)
156 access |= PAGE_WRITE;
158 switch (pte1 & 0x00000003) {
167 access = PAGE_READ | PAGE_WRITE;
172 if ((rw == 0 && (access & PAGE_READ)) ||
173 (rw == 1 && (access & PAGE_WRITE))) {
174 #if defined (DEBUG_MMU)
176 fprintf(logfile, "PTE access granted !\n");
182 /* Access right violation */
184 #if defined (DEBUG_MMU)
186 fprintf(logfile, "PTE access rejected\n");
195 *RPN = keep & 0xFFFFF000;
196 #if defined (DEBUG_MMU)
198 fprintf(logfile, "found PTE at addr 0x%08x prot=0x%01x ret=%d\n",
202 /* Update page flags */
203 if (!(keep & 0x00000100)) {
208 if (!(keep & 0x00000080)) {
209 if (rw && ret == 0) {
214 /* Force page fault for first write access */
215 *prot &= ~PAGE_WRITE;
219 stl_phys_notdirty(base + (good * 8) + 4, keep);
226 static inline uint32_t get_pgaddr (uint32_t sdr1, uint32_t hash, uint32_t mask)
228 return (sdr1 & 0xFFFF0000) | (hash & mask);
231 /* Perform segment based translation */
232 static int get_segment (CPUState *env, uint32_t *real, int *prot,
233 uint32_t virtual, int rw, int type)
235 uint32_t pg_addr, sdr, ptem, vsid, pgidx;
241 sr = env->sr[virtual >> 28];
242 #if defined (DEBUG_MMU)
244 fprintf(logfile, "Check segment v=0x%08x %d 0x%08x nip=0x%08x "
245 "lr=0x%08x ir=%d dr=%d pr=%d %d t=%d\n",
246 virtual, virtual >> 28, sr, env->nip,
247 env->lr, msr_ir, msr_dr, msr_pr, rw, type);
250 key = (((sr & 0x20000000) && msr_pr == 1) ||
251 ((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0;
252 if ((sr & 0x80000000) == 0) {
253 #if defined (DEBUG_MMU)
255 fprintf(logfile, "pte segment: key=%d n=0x%08x\n",
256 key, sr & 0x10000000);
258 /* Check if instruction fetch is allowed, if needed */
259 if (type != ACCESS_CODE || (sr & 0x10000000) == 0) {
260 /* Page address translation */
261 vsid = sr & 0x00FFFFFF;
262 pgidx = (virtual >> 12) & 0xFFFF;
264 hash = ((vsid ^ pgidx) & 0x0007FFFF) << 6;
265 mask = ((sdr & 0x000001FF) << 16) | 0xFFC0;
266 pg_addr = get_pgaddr(sdr, hash, mask);
267 ptem = (vsid << 7) | (pgidx >> 10);
268 #if defined (DEBUG_MMU)
270 fprintf(logfile, "0 sdr1=0x%08x vsid=0x%06x api=0x%04x "
271 "hash=0x%07x pg_addr=0x%08x\n", sdr, vsid, pgidx, hash,
275 /* Primary table lookup */
276 ret = find_pte(real, prot, pg_addr, ptem, 0, key, rw);
278 /* Secondary table lookup */
279 hash = (~hash) & 0x01FFFFC0;
280 pg_addr = get_pgaddr(sdr, hash, mask);
281 #if defined (DEBUG_MMU)
282 if (virtual != 0xEFFFFFFF && loglevel > 0) {
283 fprintf(logfile, "1 sdr1=0x%08x vsid=0x%06x api=0x%04x "
284 "hash=0x%05x pg_addr=0x%08x\n", sdr, vsid, pgidx,
288 ret2 = find_pte(real, prot, pg_addr, ptem, 1, key, rw);
293 #if defined (DEBUG_MMU)
295 fprintf(logfile, "No access allowed\n");
300 #if defined (DEBUG_MMU)
302 fprintf(logfile, "direct store...\n");
304 /* Direct-store segment : absolutely *BUGGY* for now */
307 /* Integer load/store : only access allowed */
310 /* No code fetch is allowed in direct-store areas */
313 /* Floating point load/store */
316 /* lwarx, ldarx or srwcx. */
319 /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
320 /* Should make the instruction do no-op.
321 * As it already do no-op, it's quite easy :-)
330 fprintf(logfile, "ERROR: instruction should not need "
331 "address translation\n");
333 printf("ERROR: instruction should not need "
334 "address translation\n");
337 if ((rw == 1 || key != 1) && (rw == 0 || key != 0)) {
348 int get_physical_address (CPUState *env, uint32_t *physical, int *prot,
349 uint32_t address, int rw, int access_type)
354 fprintf(logfile, "%s\n", __func__);
357 if ((access_type == ACCESS_CODE && msr_ir == 0) ||
358 (access_type != ACCESS_CODE && msr_dr == 0)) {
359 /* No address translation */
360 *physical = address & ~0xFFF;
361 *prot = PAGE_READ | PAGE_WRITE;
364 /* Try to find a BAT */
365 ret = get_bat(env, physical, prot, address, rw, access_type);
367 /* We didn't match any BAT entry */
368 ret = get_segment(env, physical, prot, address, rw, access_type);
373 fprintf(logfile, "%s address %08x => %08x\n",
374 __func__, address, *physical);
380 #if defined(CONFIG_USER_ONLY)
381 target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
386 target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
391 if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
397 #if !defined(CONFIG_USER_ONLY)
399 #define MMUSUFFIX _mmu
400 #define GETPC() (__builtin_return_address(0))
403 #include "softmmu_template.h"
406 #include "softmmu_template.h"
409 #include "softmmu_template.h"
412 #include "softmmu_template.h"
414 /* try to fill the TLB and return an exception if error. If retaddr is
415 NULL, it means that the function was called in C code (i.e. not
416 from generated code or from helper.c) */
417 /* XXX: fix it to restore all registers */
418 void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr)
420 TranslationBlock *tb;
425 /* XXX: hack to restore env in all cases, even if not called from
428 env = cpu_single_env;
431 unsigned long tlb_addrr, tlb_addrw;
433 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
434 tlb_addrr = env->tlb_read[is_user][index].address;
435 tlb_addrw = env->tlb_write[is_user][index].address;
438 "%s 1 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
439 "(0x%08lx 0x%08lx)\n", __func__, env,
440 &env->tlb_read[is_user][index], index, addr,
441 tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
442 tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
446 ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, is_user, 1);
449 /* now we have a real cpu fault */
450 pc = (unsigned long)retaddr;
453 /* the PC is inside the translated code. It means that we have
454 a virtual CPU fault */
455 cpu_restore_state(tb, env, pc, NULL);
458 do_raise_exception_err(env->exception_index, env->error_code);
462 unsigned long tlb_addrr, tlb_addrw;
464 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
465 tlb_addrr = env->tlb_read[is_user][index].address;
466 tlb_addrw = env->tlb_write[is_user][index].address;
467 printf("%s 2 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
468 "(0x%08lx 0x%08lx)\n", __func__, env,
469 &env->tlb_read[is_user][index], index, addr,
470 tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
471 tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
477 void cpu_ppc_init_mmu(CPUState *env)
479 /* Nothing to do: all translation are disabled */
483 /* Perform address translation */
484 int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
485 int is_user, int is_softmmu)
489 int exception = 0, error_code = 0;
496 access_type = ACCESS_CODE;
499 /* XXX: put correct access by using cpu_restore_state()
501 access_type = ACCESS_INT;
502 // access_type = env->access_type;
504 if (env->user_mode_only) {
505 /* user mode only emulation */
509 ret = get_physical_address(env, &physical, &prot,
510 address, rw, access_type);
512 ret = tlb_set_page(env, address & ~0xFFF, physical, prot,
513 is_user, is_softmmu);
514 } else if (ret < 0) {
516 #if defined (DEBUG_MMU)
518 cpu_dump_state(env, logfile, fprintf, 0);
520 if (access_type == ACCESS_CODE) {
521 exception = EXCP_ISI;
524 /* No matches in page tables */
525 error_code = EXCP_ISI_TRANSLATE;
528 /* Access rights violation */
529 error_code = EXCP_ISI_PROT;
532 /* No execute protection violation */
533 error_code = EXCP_ISI_NOEXEC;
536 /* Direct store exception */
537 /* No code fetch is allowed in direct-store areas */
538 error_code = EXCP_ISI_DIRECT;
542 exception = EXCP_DSI;
545 /* No matches in page tables */
546 error_code = EXCP_DSI_TRANSLATE;
549 /* Access rights violation */
550 error_code = EXCP_DSI_PROT;
553 /* Direct store exception */
554 switch (access_type) {
556 /* Floating point load/store */
557 exception = EXCP_ALIGN;
558 error_code = EXCP_ALIGN_FP;
561 /* lwarx, ldarx or srwcx. */
562 exception = EXCP_DSI;
563 error_code = EXCP_DSI_NOTSUP | EXCP_DSI_DIRECT;
567 exception = EXCP_DSI;
568 error_code = EXCP_DSI_NOTSUP | EXCP_DSI_DIRECT |
572 printf("DSI: invalid exception (%d)\n", ret);
573 exception = EXCP_PROGRAM;
574 error_code = EXCP_INVAL | EXCP_INVAL_INVAL;
579 error_code |= EXCP_DSI_STORE;
580 /* Store fault address */
581 env->spr[DAR] = address;
584 printf("%s: set exception to %d %02x\n",
585 __func__, exception, error_code);
587 env->exception_index = exception;
588 env->error_code = error_code;
594 uint32_t _load_xer (CPUState *env)
596 return (xer_so << XER_SO) |
602 void _store_xer (CPUState *env, uint32_t value)
604 xer_so = (value >> XER_SO) & 0x01;
605 xer_ov = (value >> XER_OV) & 0x01;
606 xer_ca = (value >> XER_CA) & 0x01;
607 xer_bc = (value >> XER_BC) & 0x1f;
610 uint32_t _load_msr (CPUState *env)
612 return (msr_pow << MSR_POW) |
613 (msr_ile << MSR_ILE) |
618 (msr_fe0 << MSR_FE0) |
621 (msr_fe1 << MSR_FE1) |
629 void _store_msr (CPUState *env, uint32_t value)
632 if (((value >> MSR_IR) & 0x01) != msr_ir ||
633 ((value >> MSR_DR) & 0x01) != msr_dr)
635 /* Flush all tlb when changing translation mode or privilege level */
639 msr_pow = (value >> MSR_POW) & 0x03;
640 msr_ile = (value >> MSR_ILE) & 0x01;
641 msr_ee = (value >> MSR_EE) & 0x01;
642 msr_pr = (value >> MSR_PR) & 0x01;
643 msr_fp = (value >> MSR_FP) & 0x01;
644 msr_me = (value >> MSR_ME) & 0x01;
645 msr_fe0 = (value >> MSR_FE0) & 0x01;
646 msr_se = (value >> MSR_SE) & 0x01;
647 msr_be = (value >> MSR_BE) & 0x01;
648 msr_fe1 = (value >> MSR_FE1) & 0x01;
649 msr_ip = (value >> MSR_IP) & 0x01;
650 msr_ir = (value >> MSR_IR) & 0x01;
651 msr_dr = (value >> MSR_DR) & 0x01;
652 msr_ri = (value >> MSR_RI) & 0x01;
653 msr_le = (value >> MSR_LE) & 0x01;
654 /* XXX: should enter PM state if msr_pow has been set */
657 #if defined (CONFIG_USER_ONLY)
658 void do_interrupt (CPUState *env)
660 env->exception_index = -1;
663 void do_interrupt (CPUState *env)
668 excp = env->exception_index;
669 msr = _load_msr(env);
670 #if defined (DEBUG_EXCEPTIONS)
671 if ((excp == EXCP_PROGRAM || excp == EXCP_DSI) && msr_pr == 1)
674 fprintf(logfile, "Raise exception at 0x%08x => 0x%08x (%02x)\n",
675 env->nip, excp << 8, env->error_code);
678 cpu_dump_state(env, logfile, fprintf, 0);
681 if (loglevel & CPU_LOG_INT) {
682 fprintf(logfile, "Raise exception at 0x%08x => 0x%08x (%02x)\n",
683 env->nip, excp << 8, env->error_code);
685 /* Generate informations in save/restore registers */
689 #if defined (DEBUG_EXCEPTIONS)
690 printf("%s: escape EXCP_NONE\n", __func__);
697 case EXCP_MACHINE_CHECK:
699 cpu_abort(env, "Machine check exception while not allowed\n");
704 /* Store exception cause */
705 /* data location address has been stored
706 * when the fault has been detected
710 if (env->error_code & EXCP_DSI_TRANSLATE)
711 env->spr[DSISR] |= 0x40000000;
712 else if (env->error_code & EXCP_DSI_PROT)
713 env->spr[DSISR] |= 0x08000000;
714 else if (env->error_code & EXCP_DSI_NOTSUP) {
715 env->spr[DSISR] |= 0x80000000;
716 if (env->error_code & EXCP_DSI_DIRECT)
717 env->spr[DSISR] |= 0x04000000;
719 if (env->error_code & EXCP_DSI_STORE)
720 env->spr[DSISR] |= 0x02000000;
721 if ((env->error_code & 0xF) == EXCP_DSI_DABR)
722 env->spr[DSISR] |= 0x00400000;
723 if (env->error_code & EXCP_DSI_ECXW)
724 env->spr[DSISR] |= 0x00100000;
725 #if defined (DEBUG_EXCEPTIONS)
727 fprintf(logfile, "DSI exception: DSISR=0x%08x, DAR=0x%08x\n",
728 env->spr[DSISR], env->spr[DAR]);
730 printf("DSI exception: DSISR=0x%08x, DAR=0x%08x nip=0x%08x\n",
731 env->spr[DSISR], env->spr[DAR], env->nip);
736 /* Store exception cause */
738 if (env->error_code == EXCP_ISI_TRANSLATE)
740 else if (env->error_code == EXCP_ISI_NOEXEC ||
741 env->error_code == EXCP_ISI_GUARD ||
742 env->error_code == EXCP_ISI_DIRECT)
746 #if defined (DEBUG_EXCEPTIONS)
748 fprintf(logfile, "ISI exception: msr=0x%08x, nip=0x%08x\n",
751 printf("ISI exception: msr=0x%08x, nip=0x%08x tbl:0x%08x\n",
752 msr, env->nip, env->spr[V_TBL]);
758 #if defined (DEBUG_EXCEPTIONS)
760 fprintf(logfile, "Skipping hardware interrupt\n");
764 do_raise_exception(EXCP_EXTERNAL);
769 /* Store exception cause */
770 /* Get rS/rD and rA from faulting opcode */
772 (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16;
773 /* data location address has been stored
774 * when the fault has been detected
779 switch (env->error_code & ~0xF) {
781 if (msr_fe0 == 0 && msr_fe1 == 0) {
782 #if defined (DEBUG_EXCEPTIONS)
783 printf("Ignore floating point exception\n");
789 env->fpscr[7] |= 0x8;
790 /* Finally, update FEX */
791 if ((((env->fpscr[7] & 0x3) << 3) | (env->fpscr[6] >> 1)) &
792 ((env->fpscr[1] << 1) | (env->fpscr[0] >> 3)))
793 env->fpscr[7] |= 0x4;
796 // printf("Invalid instruction at 0x%08x\n", env->nip);
806 /* Should never occur */
817 do_raise_exception(EXCP_DECR);
822 if (loglevel & CPU_LOG_INT) {
823 fprintf(logfile, "syscall %d 0x%08x 0x%08x 0x%08x 0x%08x\n",
824 env->gpr[0], env->gpr[3], env->gpr[4],
825 env->gpr[5], env->gpr[6]);
826 if (env->gpr[0] == 4 && env->gpr[3] == 1) {
830 fprintf(logfile, "write: ");
835 for(i = 0; i < len; i++) {
837 cpu_memory_rw_debug(env, addr + i, &c, 1, 0);
838 if (c < 32 || c > 126)
840 fprintf(logfile, "%c", c);
842 fprintf(logfile, "\n");
857 /* Restore user-mode state */
858 #if defined (DEBUG_EXCEPTIONS)
860 printf("Return from exception => 0x%08x\n", (uint32_t)env->nip);
864 /* SRR0 is set to current instruction */
865 env->spr[SRR0] = (uint32_t)env->nip - 4;
868 /* SRR0 is set to next instruction */
869 env->spr[SRR0] = (uint32_t)env->nip;
872 env->spr[SRR1] = msr;
873 /* reload MSR with correct bits */
886 /* Jump to handler */
887 env->nip = excp << 8;
888 env->exception_index = EXCP_NONE;
889 /* Invalidate all TLB as we may have changed translation mode */
890 /* ensure that no TB jump will be modified as
891 the program flow was changed */
897 env->exception_index = -1;
899 #endif /* !CONFIG_USER_ONLY */