2 * PPC emulation helpers for qemu.
4 * Copyright (c) 2003 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #if defined (USE_OPEN_FIRMWARE)
28 //#define DEBUG_EXCEPTIONS
30 extern FILE *stdout, *stderr;
33 /*****************************************************************************/
35 /*****************************************************************************/
36 /* PPC MMU emulation */
37 int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
38 int is_user, int is_softmmu);
40 /* Perform BAT hit & translation */
41 static int get_bat (CPUState *env, uint32_t *real, int *prot,
42 uint32_t virtual, int rw, int type)
44 uint32_t *BATlt, *BATut, *BATu, *BATl;
45 uint32_t base, BEPIl, BEPIu, bl;
49 #if defined (DEBUG_BATS)
51 fprintf(logfile, "%s: %cBAT v 0x%08x\n", __func__,
52 type == ACCESS_CODE ? 'I' : 'D', virtual);
65 #if defined (DEBUG_BATS)
67 fprintf(logfile, "%s...: %cBAT v 0x%08x\n", __func__,
68 type == ACCESS_CODE ? 'I' : 'D', virtual);
71 base = virtual & 0xFFFC0000;
72 for (i = 0; i < 4; i++) {
75 BEPIu = *BATu & 0xF0000000;
76 BEPIl = *BATu & 0x0FFE0000;
77 bl = (*BATu & 0x00001FFC) << 15;
78 #if defined (DEBUG_BATS)
80 fprintf(logfile, "%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x\n",
81 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
85 if ((virtual & 0xF0000000) == BEPIu &&
86 ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
88 if ((msr_pr == 0 && (*BATu & 0x00000002)) ||
89 (msr_pr == 1 && (*BATu & 0x00000001))) {
90 /* Get physical address */
91 *real = (*BATl & 0xF0000000) |
92 ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) |
93 (virtual & 0x0001F000);
94 if (*BATl & 0x00000001)
96 if (*BATl & 0x00000002)
97 *prot = PAGE_WRITE | PAGE_READ;
98 #if defined (DEBUG_BATS)
100 fprintf(logfile, "BAT %d match: r 0x%08x prot=%c%c\n",
101 i, *real, *prot & PAGE_READ ? 'R' : '-',
102 *prot & PAGE_WRITE ? 'W' : '-');
111 #if defined (DEBUG_BATS)
112 printf("no BAT match for 0x%08x:\n", virtual);
113 for (i = 0; i < 4; i++) {
116 BEPIu = *BATu & 0xF0000000;
117 BEPIl = *BATu & 0x0FFE0000;
118 bl = (*BATu & 0x00001FFC) << 15;
119 printf("%s: %cBAT%d v 0x%08x BATu 0x%08x BATl 0x%08x \n\t"
120 "0x%08x 0x%08x 0x%08x\n",
121 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
122 *BATu, *BATl, BEPIu, BEPIl, bl);
130 /* PTE table lookup */
131 static int find_pte (uint32_t *RPN, int *prot, uint32_t base, uint32_t va,
132 int h, int key, int rw)
134 uint32_t pte0, pte1, keep = 0, access = 0;
135 int i, good = -1, store = 0;
136 int ret = -1; /* No entry found */
138 for (i = 0; i < 8; i++) {
139 pte0 = ldl_raw(phys_ram_base + base + (i * 8));
140 pte1 = ldl_raw(phys_ram_base + base + (i * 8) + 4);
141 #if defined (DEBUG_MMU)
143 fprintf(logfile, "Load pte from 0x%08x => 0x%08x 0x%08x "
144 "%d %d %d 0x%08x\n", base + (i * 8), pte0, pte1,
145 pte0 >> 31, h, (pte0 >> 6) & 1, va);
148 /* Check validity and table match */
149 if (pte0 & 0x80000000 && (h == ((pte0 >> 6) & 1))) {
150 /* Check vsid & api */
151 if ((pte0 & 0x7FFFFFBF) == va) {
156 /* All matches should have equal RPN, WIMG & PP */
157 if ((keep & 0xFFFFF07B) != (pte1 & 0xFFFFF07B)) {
159 fprintf(logfile, "Bad RPN/WIMG/PP\n");
163 /* Check access rights */
166 if ((pte1 & 0x00000003) != 0x3)
167 access |= PAGE_WRITE;
169 switch (pte1 & 0x00000003) {
178 access = PAGE_READ | PAGE_WRITE;
183 if ((rw == 0 && (access & PAGE_READ)) ||
184 (rw == 1 && (access & PAGE_WRITE))) {
185 #if defined (DEBUG_MMU)
187 fprintf(logfile, "PTE access granted !\n");
193 /* Access right violation */
195 #if defined (DEBUG_MMU)
197 fprintf(logfile, "PTE access rejected\n");
206 *RPN = keep & 0xFFFFF000;
207 #if defined (DEBUG_MMU)
209 fprintf(logfile, "found PTE at addr 0x%08x prot=0x%01x ret=%d\n",
213 /* Update page flags */
214 if (!(keep & 0x00000100)) {
219 if (!(keep & 0x00000080)) {
220 if (rw && ret == 0) {
225 /* Force page fault for first write access */
226 *prot &= ~PAGE_WRITE;
230 stl_raw(phys_ram_base + base + (good * 8) + 4, keep);
237 static inline uint32_t get_pgaddr (uint32_t sdr1, uint32_t hash, uint32_t mask)
239 return (sdr1 & 0xFFFF0000) | (hash & mask);
242 /* Perform segment based translation */
243 static int get_segment (CPUState *env, uint32_t *real, int *prot,
244 uint32_t virtual, int rw, int type)
246 uint32_t pg_addr, sdr, ptem, vsid, pgidx;
252 sr = env->sr[virtual >> 28];
253 #if defined (DEBUG_MMU)
255 fprintf(logfile, "Check segment v=0x%08x %d 0x%08x nip=0x%08x "
256 "lr=0x%08x ir=%d dr=%d pr=%d %d t=%d\n",
257 virtual, virtual >> 28, sr, env->nip,
258 env->lr, msr_ir, msr_dr, msr_pr, rw, type);
261 key = (((sr & 0x20000000) && msr_pr == 1) ||
262 ((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0;
263 if ((sr & 0x80000000) == 0) {
264 #if defined (DEBUG_MMU)
266 fprintf(logfile, "pte segment: key=%d n=0x%08x\n",
267 key, sr & 0x10000000);
269 /* Check if instruction fetch is allowed, if needed */
270 if (type != ACCESS_CODE || (sr & 0x10000000) == 0) {
271 /* Page address translation */
272 vsid = sr & 0x00FFFFFF;
273 pgidx = (virtual >> 12) & 0xFFFF;
275 hash = ((vsid ^ pgidx) & 0x0007FFFF) << 6;
276 mask = ((sdr & 0x000001FF) << 16) | 0xFFC0;
277 pg_addr = get_pgaddr(sdr, hash, mask);
278 ptem = (vsid << 7) | (pgidx >> 10);
279 #if defined (DEBUG_MMU)
281 fprintf(logfile, "0 sdr1=0x%08x vsid=0x%06x api=0x%04x "
282 "hash=0x%07x pg_addr=0x%08x\n", sdr, vsid, pgidx, hash,
286 /* Primary table lookup */
287 ret = find_pte(real, prot, pg_addr, ptem, 0, key, rw);
289 /* Secondary table lookup */
290 hash = (~hash) & 0x01FFFFC0;
291 pg_addr = get_pgaddr(sdr, hash, mask);
292 #if defined (DEBUG_MMU)
293 if (virtual != 0xEFFFFFFF && loglevel > 0) {
294 fprintf(logfile, "1 sdr1=0x%08x vsid=0x%06x api=0x%04x "
295 "hash=0x%05x pg_addr=0x%08x\n", sdr, vsid, pgidx,
299 ret2 = find_pte(real, prot, pg_addr, ptem, 1, key, rw);
304 #if defined (DEBUG_MMU)
306 fprintf(logfile, "No access allowed\n");
311 #if defined (DEBUG_MMU)
313 fprintf(logfile, "direct store...\n");
315 /* Direct-store segment : absolutely *BUGGY* for now */
318 /* Integer load/store : only access allowed */
321 /* No code fetch is allowed in direct-store areas */
324 /* Floating point load/store */
327 /* lwarx, ldarx or srwcx. */
330 /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
331 /* Should make the instruction do no-op.
332 * As it already do no-op, it's quite easy :-)
341 fprintf(logfile, "ERROR: instruction should not need "
342 "address translation\n");
344 printf("ERROR: instruction should not need "
345 "address translation\n");
348 if ((rw == 1 || key != 1) && (rw == 0 || key != 0)) {
359 int get_physical_address (CPUState *env, uint32_t *physical, int *prot,
360 uint32_t address, int rw, int access_type)
365 fprintf(logfile, "%s\n", __func__);
368 if ((access_type == ACCESS_CODE && msr_ir == 0) || msr_dr == 0) {
369 /* No address translation */
370 *physical = address & ~0xFFF;
371 *prot = PAGE_READ | PAGE_WRITE;
374 /* Try to find a BAT */
375 ret = get_bat(env, physical, prot, address, rw, access_type);
377 /* We didn't match any BAT entry */
378 ret = get_segment(env, physical, prot, address, rw, access_type);
382 fprintf(logfile, "%s address %08x => %08x\n",
383 __func__, address, *physical);
389 #if defined(CONFIG_USER_ONLY)
390 target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
395 target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
400 if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
406 #if !defined(CONFIG_USER_ONLY)
408 #define MMUSUFFIX _mmu
409 #define GETPC() (__builtin_return_address(0))
412 #include "softmmu_template.h"
415 #include "softmmu_template.h"
418 #include "softmmu_template.h"
421 #include "softmmu_template.h"
423 /* try to fill the TLB and return an exception if error. If retaddr is
424 NULL, it means that the function was called in C code (i.e. not
425 from generated code or from helper.c) */
426 /* XXX: fix it to restore all registers */
427 void tlb_fill(unsigned long addr, int is_write, int is_user, void *retaddr)
429 TranslationBlock *tb;
434 /* XXX: hack to restore env in all cases, even if not called from
437 env = cpu_single_env;
439 unsigned long tlb_addrr, tlb_addrw;
441 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
442 tlb_addrr = env->tlb_read[is_user][index].address;
443 tlb_addrw = env->tlb_write[is_user][index].address;
445 printf("%s 1 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
446 "(0x%08lx 0x%08lx)\n", __func__, env,
447 &env->tlb_read[is_user][index], index, addr,
448 tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
449 tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
452 ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, is_user, 1);
455 /* now we have a real cpu fault */
456 pc = (unsigned long)retaddr;
459 /* the PC is inside the translated code. It means that we have
460 a virtual CPU fault */
461 cpu_restore_state(tb, env, pc, NULL);
464 do_raise_exception_err(env->exception_index, env->error_code);
467 unsigned long tlb_addrr, tlb_addrw;
469 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
470 tlb_addrr = env->tlb_read[is_user][index].address;
471 tlb_addrw = env->tlb_write[is_user][index].address;
473 printf("%s 2 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
474 "(0x%08lx 0x%08lx)\n", __func__, env,
475 &env->tlb_read[is_user][index], index, addr,
476 tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
477 tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
483 void cpu_ppc_init_mmu(CPUState *env)
485 /* Nothing to do: all translation are disabled */
489 /* Perform address translation */
490 int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
491 int is_user, int is_softmmu)
495 int exception = 0, error_code = 0;
499 // printf("%s 0\n", __func__);
500 access_type = env->access_type;
501 if (env->user_mode_only) {
502 /* user mode only emulation */
506 /* NASTY BUG workaround */
507 if (access_type == ACCESS_CODE && rw) {
508 printf("%s: ERROR WRITE CODE ACCESS\n", __func__);
509 access_type = ACCESS_INT;
511 ret = get_physical_address(env, &physical, &prot,
512 address, rw, access_type);
514 ret = tlb_set_page(env, address & ~0xFFF, physical, prot,
515 is_user, is_softmmu);
516 } else if (ret < 0) {
518 #if defined (DEBUG_MMU)
520 cpu_ppc_dump_state(env, logfile, 0);
522 if (access_type == ACCESS_CODE) {
523 exception = EXCP_ISI;
526 /* No matches in page tables */
527 error_code = EXCP_ISI_TRANSLATE;
530 /* Access rights violation */
531 error_code = EXCP_ISI_PROT;
534 /* No execute protection violation */
535 error_code = EXCP_ISI_NOEXEC;
538 /* Direct store exception */
539 /* No code fetch is allowed in direct-store areas */
540 error_code = EXCP_ISI_DIRECT;
544 exception = EXCP_DSI;
547 /* No matches in page tables */
548 error_code = EXCP_DSI_TRANSLATE;
551 /* Access rights violation */
552 error_code = EXCP_DSI_PROT;
555 /* Direct store exception */
556 switch (access_type) {
558 /* Floating point load/store */
559 exception = EXCP_ALIGN;
560 error_code = EXCP_ALIGN_FP;
563 /* lwarx, ldarx or srwcx. */
564 exception = EXCP_DSI;
565 error_code = EXCP_DSI_NOTSUP | EXCP_DSI_DIRECT;
569 exception = EXCP_DSI;
570 error_code = EXCP_DSI_NOTSUP | EXCP_DSI_DIRECT |
574 printf("DSI: invalid exception (%d)\n", ret);
575 exception = EXCP_PROGRAM;
576 error_code = EXCP_INVAL | EXCP_INVAL_INVAL;
581 error_code |= EXCP_DSI_STORE;
582 /* Store fault address */
583 env->spr[DAR] = address;
586 printf("%s: set exception to %d %02x\n",
587 __func__, exception, error_code);
589 env->exception_index = exception;
590 env->error_code = error_code;
597 uint32_t _load_xer (CPUState *env)
599 return (xer_so << XER_SO) |
605 void _store_xer (CPUState *env, uint32_t value)
607 xer_so = (value >> XER_SO) & 0x01;
608 xer_ov = (value >> XER_OV) & 0x01;
609 xer_ca = (value >> XER_CA) & 0x01;
610 xer_bc = (value >> XER_BC) & 0x1f;
613 uint32_t _load_msr (CPUState *env)
615 return (msr_pow << MSR_POW) |
616 (msr_ile << MSR_ILE) |
621 (msr_fe0 << MSR_FE0) |
624 (msr_fe1 << MSR_FE1) |
632 void _store_msr (CPUState *env, uint32_t value)
634 if (((value >> MSR_IR) & 0x01) != msr_ir ||
635 ((value >> MSR_DR) & 0x01) != msr_dr) {
636 /* Flush all tlb when changing translation mode or privilege level */
639 msr_pow = (value >> MSR_POW) & 0x03;
640 msr_ile = (value >> MSR_ILE) & 0x01;
641 msr_ee = (value >> MSR_EE) & 0x01;
642 msr_pr = (value >> MSR_PR) & 0x01;
643 msr_fp = (value >> MSR_FP) & 0x01;
644 msr_me = (value >> MSR_ME) & 0x01;
645 msr_fe0 = (value >> MSR_FE0) & 0x01;
646 msr_se = (value >> MSR_SE) & 0x01;
647 msr_be = (value >> MSR_BE) & 0x01;
648 msr_fe1 = (value >> MSR_FE1) & 0x01;
649 msr_ip = (value >> MSR_IP) & 0x01;
650 msr_ir = (value >> MSR_IR) & 0x01;
651 msr_dr = (value >> MSR_DR) & 0x01;
652 msr_ri = (value >> MSR_RI) & 0x01;
653 msr_le = (value >> MSR_LE) & 0x01;
656 void do_interrupt (CPUState *env)
658 #if defined (CONFIG_USER_ONLY)
659 env->exception_index |= 0x100;
662 int excp = env->exception_index;
664 msr = _load_msr(env);
665 #if defined (DEBUG_EXCEPTIONS)
666 if ((excp == EXCP_PROGRAM || excp == EXCP_DSI) && msr_pr == 1)
669 fprintf(logfile, "Raise exception at 0x%08x => 0x%08x (%02x)\n",
670 env->nip, excp << 8, env->error_code);
673 cpu_ppc_dump_state(env, logfile, 0);
676 /* Generate informations in save/restore registers */
679 #if defined (USE_OPEN_FIRMWARE)
680 env->gpr[3] = OF_client_entry((void *)env->gpr[3]);
684 #if defined (USE_OPEN_FIRMWARE)
685 printf("RTAS call !\n");
686 env->gpr[3] = RTAS_entry((void *)env->gpr[3]);
687 printf("RTAS call done\n");
692 #if defined (DEBUG_EXCEPTIONS)
693 printf("%s: escape EXCP_NONE\n", __func__);
700 case EXCP_MACHINE_CHECK:
702 printf("Machine check exception while not allowed !\n");
705 "Machine check exception while not allowed !\n");
712 /* Store exception cause */
713 /* data location address has been stored
714 * when the fault has been detected
718 if (env->error_code & EXCP_DSI_TRANSLATE)
719 env->spr[DSISR] |= 0x40000000;
720 else if (env->error_code & EXCP_DSI_PROT)
721 env->spr[DSISR] |= 0x08000000;
722 else if (env->error_code & EXCP_DSI_NOTSUP) {
723 env->spr[DSISR] |= 0x80000000;
724 if (env->error_code & EXCP_DSI_DIRECT)
725 env->spr[DSISR] |= 0x04000000;
727 if (env->error_code & EXCP_DSI_STORE)
728 env->spr[DSISR] |= 0x02000000;
729 if ((env->error_code & 0xF) == EXCP_DSI_DABR)
730 env->spr[DSISR] |= 0x00400000;
731 if (env->error_code & EXCP_DSI_ECXW)
732 env->spr[DSISR] |= 0x00100000;
733 #if defined (DEBUG_EXCEPTIONS)
735 fprintf(logfile, "DSI exception: DSISR=0x%08x, DAR=0x%08x\n",
736 env->spr[DSISR], env->spr[DAR]);
738 printf("DSI exception: DSISR=0x%08x, DAR=0x%08x nip=0x%08x\n",
739 env->spr[DSISR], env->spr[DAR], env->nip);
744 /* Store exception cause */
746 if (env->error_code == EXCP_ISI_TRANSLATE)
748 else if (env->error_code == EXCP_ISI_NOEXEC ||
749 env->error_code == EXCP_ISI_GUARD ||
750 env->error_code == EXCP_ISI_DIRECT)
754 #if defined (DEBUG_EXCEPTIONS)
756 fprintf(logfile, "ISI exception: msr=0x%08x, nip=0x%08x\n",
759 printf("ISI exception: msr=0x%08x, nip=0x%08x tbl:0x%08x\n",
760 msr, env->nip, env->spr[V_TBL]);
766 #if defined (DEBUG_EXCEPTIONS)
768 fprintf(logfile, "Skipping hardware interrupt\n");
772 do_raise_exception(EXCP_EXTERNAL);
777 /* Store exception cause */
778 /* Get rS/rD and rA from faulting opcode */
780 (ldl_code((void *)(env->nip - 4)) & 0x03FF0000) >> 16;
781 /* data location address has been stored
782 * when the fault has been detected
787 switch (env->error_code & ~0xF) {
789 if (msr_fe0 == 0 && msr_fe1 == 0) {
790 #if defined (DEBUG_EXCEPTIONS)
791 printf("Ignore floating point exception\n");
797 env->fpscr[7] |= 0x8;
798 /* Finally, update FEX */
799 if ((((env->fpscr[7] & 0x3) << 3) | (env->fpscr[6] >> 1)) &
800 ((env->fpscr[1] << 1) | (env->fpscr[0] >> 3)))
801 env->fpscr[7] |= 0x4;
804 printf("Invalid instruction at 0x%08x\n", env->nip);
814 /* Should never occur */
824 do_raise_exception(EXCP_DECR);
829 #if defined (DEBUG_EXCEPTIONS)
832 fprintf(logfile, "syscall %d 0x%08x 0x%08x 0x%08x 0x%08x\n",
833 env->gpr[0], env->gpr[3], env->gpr[4],
834 env->gpr[5], env->gpr[6]);
836 printf("syscall %d from 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
837 env->gpr[0], env->nip, env->gpr[3], env->gpr[4],
838 env->gpr[5], env->gpr[6]);
854 /* Restore user-mode state */
856 #if defined (DEBUG_EXCEPTIONS)
858 printf("Return from exception => 0x%08x\n", (uint32_t)env->nip);
862 /* SRR0 is set to current instruction */
863 env->spr[SRR0] = (uint32_t)env->nip - 4;
866 /* SRR0 is set to next instruction */
867 env->spr[SRR0] = (uint32_t)env->nip;
870 env->spr[SRR1] = msr;
871 /* reload MSR with correct bits */
884 /* Jump to handler */
885 env->nip = excp << 8;
886 env->exception_index = EXCP_NONE;
887 /* Invalidate all TLB as we may have changed translation mode */
889 /* ensure that no TB jump will be modified as
890 the program flow was changed */
897 env->exception_index = -1;