2 * PowerPC emulation helpers for qemu.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include "host-utils.h"
24 #include "helper_regs.h"
27 //#define DEBUG_EXCEPTIONS
28 //#define DEBUG_SOFTWARE_TLB
30 /*****************************************************************************/
31 /* Exceptions processing helpers */
33 void helper_raise_exception_err (uint32_t exception, uint32_t error_code)
36 printf("Raise exception %3x code : %d\n", exception, error_code);
38 env->exception_index = exception;
39 env->error_code = error_code;
43 void helper_raise_exception (uint32_t exception)
45 helper_raise_exception_err(exception, 0);
48 /*****************************************************************************/
49 /* Registers load and stores */
50 target_ulong helper_load_cr (void)
52 return (env->crf[0] << 28) |
62 void helper_store_cr (target_ulong val, uint32_t mask)
66 for (i = 0, sh = 7; i < 8; i++, sh--) {
68 env->crf[i] = (val >> (sh * 4)) & 0xFUL;
72 /*****************************************************************************/
74 void helper_load_dump_spr (uint32_t sprn)
77 fprintf(logfile, "Read SPR %d %03x => " ADDRX "\n",
78 sprn, sprn, env->spr[sprn]);
82 void helper_store_dump_spr (uint32_t sprn)
85 fprintf(logfile, "Write SPR %d %03x <= " ADDRX "\n",
86 sprn, sprn, env->spr[sprn]);
90 target_ulong helper_load_tbl (void)
92 return cpu_ppc_load_tbl(env);
95 target_ulong helper_load_tbu (void)
97 return cpu_ppc_load_tbu(env);
100 target_ulong helper_load_atbl (void)
102 return cpu_ppc_load_atbl(env);
105 target_ulong helper_load_atbu (void)
107 return cpu_ppc_load_atbu(env);
110 target_ulong helper_load_601_rtcl (void)
112 return cpu_ppc601_load_rtcl(env);
115 target_ulong helper_load_601_rtcu (void)
117 return cpu_ppc601_load_rtcu(env);
120 #if !defined(CONFIG_USER_ONLY)
121 #if defined (TARGET_PPC64)
122 void helper_store_asr (target_ulong val)
124 ppc_store_asr(env, val);
128 void helper_store_sdr1 (target_ulong val)
130 ppc_store_sdr1(env, val);
133 void helper_store_tbl (target_ulong val)
135 cpu_ppc_store_tbl(env, val);
138 void helper_store_tbu (target_ulong val)
140 cpu_ppc_store_tbu(env, val);
143 void helper_store_atbl (target_ulong val)
145 cpu_ppc_store_atbl(env, val);
148 void helper_store_atbu (target_ulong val)
150 cpu_ppc_store_atbu(env, val);
153 void helper_store_601_rtcl (target_ulong val)
155 cpu_ppc601_store_rtcl(env, val);
158 void helper_store_601_rtcu (target_ulong val)
160 cpu_ppc601_store_rtcu(env, val);
163 target_ulong helper_load_decr (void)
165 return cpu_ppc_load_decr(env);
168 void helper_store_decr (target_ulong val)
170 cpu_ppc_store_decr(env, val);
173 void helper_store_hid0_601 (target_ulong val)
177 hid0 = env->spr[SPR_HID0];
178 if ((val ^ hid0) & 0x00000008) {
179 /* Change current endianness */
180 env->hflags &= ~(1 << MSR_LE);
181 env->hflags_nmsr &= ~(1 << MSR_LE);
182 env->hflags_nmsr |= (1 << MSR_LE) & (((val >> 3) & 1) << MSR_LE);
183 env->hflags |= env->hflags_nmsr;
185 fprintf(logfile, "%s: set endianness to %c => " ADDRX "\n",
186 __func__, val & 0x8 ? 'l' : 'b', env->hflags);
189 env->spr[SPR_HID0] = (uint32_t)val;
192 void helper_store_403_pbr (uint32_t num, target_ulong value)
194 if (likely(env->pb[num] != value)) {
195 env->pb[num] = value;
196 /* Should be optimized */
201 target_ulong helper_load_40x_pit (void)
203 return load_40x_pit(env);
206 void helper_store_40x_pit (target_ulong val)
208 store_40x_pit(env, val);
211 void helper_store_40x_dbcr0 (target_ulong val)
213 store_40x_dbcr0(env, val);
216 void helper_store_40x_sler (target_ulong val)
218 store_40x_sler(env, val);
221 void helper_store_booke_tcr (target_ulong val)
223 store_booke_tcr(env, val);
226 void helper_store_booke_tsr (target_ulong val)
228 store_booke_tsr(env, val);
231 void helper_store_ibatu (uint32_t nr, target_ulong val)
233 ppc_store_ibatu(env, nr, val);
236 void helper_store_ibatl (uint32_t nr, target_ulong val)
238 ppc_store_ibatl(env, nr, val);
241 void helper_store_dbatu (uint32_t nr, target_ulong val)
243 ppc_store_dbatu(env, nr, val);
246 void helper_store_dbatl (uint32_t nr, target_ulong val)
248 ppc_store_dbatl(env, nr, val);
251 void helper_store_601_batl (uint32_t nr, target_ulong val)
253 ppc_store_ibatl_601(env, nr, val);
256 void helper_store_601_batu (uint32_t nr, target_ulong val)
258 ppc_store_ibatu_601(env, nr, val);
262 /*****************************************************************************/
263 /* Memory load and stores */
265 static always_inline target_ulong addr_add(target_ulong addr, target_long arg)
267 #if defined(TARGET_PPC64)
269 return (uint32_t)(addr + arg);
275 void helper_lmw (target_ulong addr, uint32_t reg)
277 for (; reg < 32; reg++) {
279 env->gpr[reg] = bswap32(ldl(addr));
281 env->gpr[reg] = ldl(addr);
282 addr = addr_add(addr, 4);
286 void helper_stmw (target_ulong addr, uint32_t reg)
288 for (; reg < 32; reg++) {
290 stl(addr, bswap32((uint32_t)env->gpr[reg]));
292 stl(addr, (uint32_t)env->gpr[reg]);
293 addr = addr_add(addr, 4);
297 void helper_lsw(target_ulong addr, uint32_t nb, uint32_t reg)
300 for (; nb > 3; nb -= 4) {
301 env->gpr[reg] = ldl(addr);
302 reg = (reg + 1) % 32;
303 addr = addr_add(addr, 4);
305 if (unlikely(nb > 0)) {
307 for (sh = 24; nb > 0; nb--, sh -= 8) {
308 env->gpr[reg] |= ldub(addr) << sh;
309 addr = addr_add(addr, 1);
313 /* PPC32 specification says we must generate an exception if
314 * rA is in the range of registers to be loaded.
315 * In an other hand, IBM says this is valid, but rA won't be loaded.
316 * For now, I'll follow the spec...
318 void helper_lswx(target_ulong addr, uint32_t reg, uint32_t ra, uint32_t rb)
320 if (likely(xer_bc != 0)) {
321 if (unlikely((ra != 0 && reg < ra && (reg + xer_bc) > ra) ||
322 (reg < rb && (reg + xer_bc) > rb))) {
323 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
325 POWERPC_EXCP_INVAL_LSWX);
327 helper_lsw(addr, xer_bc, reg);
332 void helper_stsw(target_ulong addr, uint32_t nb, uint32_t reg)
335 for (; nb > 3; nb -= 4) {
336 stl(addr, env->gpr[reg]);
337 reg = (reg + 1) % 32;
338 addr = addr_add(addr, 4);
340 if (unlikely(nb > 0)) {
341 for (sh = 24; nb > 0; nb--, sh -= 8)
342 stb(addr, (env->gpr[reg] >> sh) & 0xFF);
343 addr = addr_add(addr, 1);
347 static void do_dcbz(target_ulong addr, int dcache_line_size)
349 addr &= ~(dcache_line_size - 1);
351 for (i = 0 ; i < dcache_line_size ; i += 4) {
354 if (env->reserve == addr)
355 env->reserve = (target_ulong)-1ULL;
358 void helper_dcbz(target_ulong addr)
360 do_dcbz(addr, env->dcache_line_size);
363 void helper_dcbz_970(target_ulong addr)
365 if (((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1)
368 do_dcbz(addr, env->dcache_line_size);
371 void helper_icbi(target_ulong addr)
375 addr &= ~(env->dcache_line_size - 1);
376 /* Invalidate one cache line :
377 * PowerPC specification says this is to be treated like a load
378 * (not a fetch) by the MMU. To be sure it will be so,
379 * do the load "by hand".
382 tb_invalidate_page_range(addr, addr + env->icache_line_size);
386 target_ulong helper_lscbx (target_ulong addr, uint32_t reg, uint32_t ra, uint32_t rb)
390 for (i = 0; i < xer_bc; i++) {
392 addr = addr_add(addr, 1);
393 /* ra (if not 0) and rb are never modified */
394 if (likely(reg != rb && (ra == 0 || reg != ra))) {
395 env->gpr[reg] = (env->gpr[reg] & ~(0xFF << d)) | (c << d);
397 if (unlikely(c == xer_cmp))
399 if (likely(d != 0)) {
410 /*****************************************************************************/
411 /* Fixed point operations helpers */
412 #if defined(TARGET_PPC64)
414 /* multiply high word */
415 uint64_t helper_mulhd (uint64_t arg1, uint64_t arg2)
419 muls64(&tl, &th, arg1, arg2);
423 /* multiply high word unsigned */
424 uint64_t helper_mulhdu (uint64_t arg1, uint64_t arg2)
428 mulu64(&tl, &th, arg1, arg2);
432 uint64_t helper_mulldo (uint64_t arg1, uint64_t arg2)
437 muls64(&tl, (uint64_t *)&th, arg1, arg2);
438 /* If th != 0 && th != -1, then we had an overflow */
439 if (likely((uint64_t)(th + 1) <= 1)) {
440 env->xer &= ~(1 << XER_OV);
442 env->xer |= (1 << XER_OV) | (1 << XER_SO);
448 target_ulong helper_cntlzw (target_ulong t)
453 #if defined(TARGET_PPC64)
454 target_ulong helper_cntlzd (target_ulong t)
460 /* shift right arithmetic helper */
461 target_ulong helper_sraw (target_ulong value, target_ulong shift)
465 if (likely(!(shift & 0x20))) {
466 if (likely((uint32_t)shift != 0)) {
468 ret = (int32_t)value >> shift;
469 if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
470 env->xer &= ~(1 << XER_CA);
472 env->xer |= (1 << XER_CA);
475 ret = (int32_t)value;
476 env->xer &= ~(1 << XER_CA);
479 ret = (int32_t)value >> 31;
481 env->xer |= (1 << XER_CA);
483 env->xer &= ~(1 << XER_CA);
486 return (target_long)ret;
489 #if defined(TARGET_PPC64)
490 target_ulong helper_srad (target_ulong value, target_ulong shift)
494 if (likely(!(shift & 0x40))) {
495 if (likely((uint64_t)shift != 0)) {
497 ret = (int64_t)value >> shift;
498 if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
499 env->xer &= ~(1 << XER_CA);
501 env->xer |= (1 << XER_CA);
504 ret = (int64_t)value;
505 env->xer &= ~(1 << XER_CA);
508 ret = (int64_t)value >> 63;
510 env->xer |= (1 << XER_CA);
512 env->xer &= ~(1 << XER_CA);
519 target_ulong helper_popcntb (target_ulong val)
521 val = (val & 0x55555555) + ((val >> 1) & 0x55555555);
522 val = (val & 0x33333333) + ((val >> 2) & 0x33333333);
523 val = (val & 0x0f0f0f0f) + ((val >> 4) & 0x0f0f0f0f);
527 #if defined(TARGET_PPC64)
528 target_ulong helper_popcntb_64 (target_ulong val)
530 val = (val & 0x5555555555555555ULL) + ((val >> 1) & 0x5555555555555555ULL);
531 val = (val & 0x3333333333333333ULL) + ((val >> 2) & 0x3333333333333333ULL);
532 val = (val & 0x0f0f0f0f0f0f0f0fULL) + ((val >> 4) & 0x0f0f0f0f0f0f0f0fULL);
537 /*****************************************************************************/
538 /* Floating point operations helpers */
539 uint64_t helper_float32_to_float64(uint32_t arg)
544 d.d = float32_to_float64(f.f, &env->fp_status);
548 uint32_t helper_float64_to_float32(uint64_t arg)
553 f.f = float64_to_float32(d.d, &env->fp_status);
557 static always_inline int fpisneg (float64 d)
563 return u.ll >> 63 != 0;
566 static always_inline int isden (float64 d)
572 return ((u.ll >> 52) & 0x7FF) == 0;
575 static always_inline int iszero (float64 d)
581 return (u.ll & ~0x8000000000000000ULL) == 0;
584 static always_inline int isinfinity (float64 d)
590 return ((u.ll >> 52) & 0x7FF) == 0x7FF &&
591 (u.ll & 0x000FFFFFFFFFFFFFULL) == 0;
594 #ifdef CONFIG_SOFTFLOAT
595 static always_inline int isfinite (float64 d)
601 return (((u.ll >> 52) & 0x7FF) != 0x7FF);
604 static always_inline int isnormal (float64 d)
610 uint32_t exp = (u.ll >> 52) & 0x7FF;
611 return ((0 < exp) && (exp < 0x7FF));
615 uint32_t helper_compute_fprf (uint64_t arg, uint32_t set_fprf)
621 isneg = fpisneg(farg.d);
622 if (unlikely(float64_is_nan(farg.d))) {
623 if (float64_is_signaling_nan(farg.d)) {
624 /* Signaling NaN: flags are undefined */
630 } else if (unlikely(isinfinity(farg.d))) {
637 if (iszero(farg.d)) {
645 /* Denormalized numbers */
648 /* Normalized numbers */
659 /* We update FPSCR_FPRF */
660 env->fpscr &= ~(0x1F << FPSCR_FPRF);
661 env->fpscr |= ret << FPSCR_FPRF;
663 /* We just need fpcc to update Rc1 */
667 /* Floating-point invalid operations exception */
668 static always_inline uint64_t fload_invalid_op_excp (int op)
674 if (op & POWERPC_EXCP_FP_VXSNAN) {
675 /* Operation on signaling NaN */
676 env->fpscr |= 1 << FPSCR_VXSNAN;
678 if (op & POWERPC_EXCP_FP_VXSOFT) {
679 /* Software-defined condition */
680 env->fpscr |= 1 << FPSCR_VXSOFT;
682 switch (op & ~(POWERPC_EXCP_FP_VXSOFT | POWERPC_EXCP_FP_VXSNAN)) {
683 case POWERPC_EXCP_FP_VXISI:
684 /* Magnitude subtraction of infinities */
685 env->fpscr |= 1 << FPSCR_VXISI;
687 case POWERPC_EXCP_FP_VXIDI:
688 /* Division of infinity by infinity */
689 env->fpscr |= 1 << FPSCR_VXIDI;
691 case POWERPC_EXCP_FP_VXZDZ:
692 /* Division of zero by zero */
693 env->fpscr |= 1 << FPSCR_VXZDZ;
695 case POWERPC_EXCP_FP_VXIMZ:
696 /* Multiplication of zero by infinity */
697 env->fpscr |= 1 << FPSCR_VXIMZ;
699 case POWERPC_EXCP_FP_VXVC:
700 /* Ordered comparison of NaN */
701 env->fpscr |= 1 << FPSCR_VXVC;
702 env->fpscr &= ~(0xF << FPSCR_FPCC);
703 env->fpscr |= 0x11 << FPSCR_FPCC;
704 /* We must update the target FPR before raising the exception */
706 env->exception_index = POWERPC_EXCP_PROGRAM;
707 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
708 /* Update the floating-point enabled exception summary */
709 env->fpscr |= 1 << FPSCR_FEX;
710 /* Exception is differed */
714 case POWERPC_EXCP_FP_VXSQRT:
715 /* Square root of a negative number */
716 env->fpscr |= 1 << FPSCR_VXSQRT;
718 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
720 /* Set the result to quiet NaN */
722 env->fpscr &= ~(0xF << FPSCR_FPCC);
723 env->fpscr |= 0x11 << FPSCR_FPCC;
726 case POWERPC_EXCP_FP_VXCVI:
727 /* Invalid conversion */
728 env->fpscr |= 1 << FPSCR_VXCVI;
729 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
731 /* Set the result to quiet NaN */
733 env->fpscr &= ~(0xF << FPSCR_FPCC);
734 env->fpscr |= 0x11 << FPSCR_FPCC;
738 /* Update the floating-point invalid operation summary */
739 env->fpscr |= 1 << FPSCR_VX;
740 /* Update the floating-point exception summary */
741 env->fpscr |= 1 << FPSCR_FX;
743 /* Update the floating-point enabled exception summary */
744 env->fpscr |= 1 << FPSCR_FEX;
745 if (msr_fe0 != 0 || msr_fe1 != 0)
746 helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_FP | op);
751 static always_inline uint64_t float_zero_divide_excp (uint64_t arg1, uint64_t arg2)
753 env->fpscr |= 1 << FPSCR_ZX;
754 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
755 /* Update the floating-point exception summary */
756 env->fpscr |= 1 << FPSCR_FX;
758 /* Update the floating-point enabled exception summary */
759 env->fpscr |= 1 << FPSCR_FEX;
760 if (msr_fe0 != 0 || msr_fe1 != 0) {
761 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
762 POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX);
765 /* Set the result to infinity */
766 arg1 = ((arg1 ^ arg2) & 0x8000000000000000ULL);
767 arg1 |= 0x7FFULL << 52;
772 static always_inline void float_overflow_excp (void)
774 env->fpscr |= 1 << FPSCR_OX;
775 /* Update the floating-point exception summary */
776 env->fpscr |= 1 << FPSCR_FX;
778 /* XXX: should adjust the result */
779 /* Update the floating-point enabled exception summary */
780 env->fpscr |= 1 << FPSCR_FEX;
781 /* We must update the target FPR before raising the exception */
782 env->exception_index = POWERPC_EXCP_PROGRAM;
783 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
785 env->fpscr |= 1 << FPSCR_XX;
786 env->fpscr |= 1 << FPSCR_FI;
790 static always_inline void float_underflow_excp (void)
792 env->fpscr |= 1 << FPSCR_UX;
793 /* Update the floating-point exception summary */
794 env->fpscr |= 1 << FPSCR_FX;
796 /* XXX: should adjust the result */
797 /* Update the floating-point enabled exception summary */
798 env->fpscr |= 1 << FPSCR_FEX;
799 /* We must update the target FPR before raising the exception */
800 env->exception_index = POWERPC_EXCP_PROGRAM;
801 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
805 static always_inline void float_inexact_excp (void)
807 env->fpscr |= 1 << FPSCR_XX;
808 /* Update the floating-point exception summary */
809 env->fpscr |= 1 << FPSCR_FX;
811 /* Update the floating-point enabled exception summary */
812 env->fpscr |= 1 << FPSCR_FEX;
813 /* We must update the target FPR before raising the exception */
814 env->exception_index = POWERPC_EXCP_PROGRAM;
815 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
819 static always_inline void fpscr_set_rounding_mode (void)
823 /* Set rounding mode */
826 /* Best approximation (round to nearest) */
827 rnd_type = float_round_nearest_even;
830 /* Smaller magnitude (round toward zero) */
831 rnd_type = float_round_to_zero;
834 /* Round toward +infinite */
835 rnd_type = float_round_up;
839 /* Round toward -infinite */
840 rnd_type = float_round_down;
843 set_float_rounding_mode(rnd_type, &env->fp_status);
846 void helper_fpscr_clrbit (uint32_t bit)
850 prev = (env->fpscr >> bit) & 1;
851 env->fpscr &= ~(1 << bit);
856 fpscr_set_rounding_mode();
864 void helper_fpscr_setbit (uint32_t bit)
868 prev = (env->fpscr >> bit) & 1;
869 env->fpscr |= 1 << bit;
873 env->fpscr |= 1 << FPSCR_FX;
877 env->fpscr |= 1 << FPSCR_FX;
882 env->fpscr |= 1 << FPSCR_FX;
887 env->fpscr |= 1 << FPSCR_FX;
892 env->fpscr |= 1 << FPSCR_FX;
905 env->fpscr |= 1 << FPSCR_VX;
906 env->fpscr |= 1 << FPSCR_FX;
913 env->error_code = POWERPC_EXCP_FP;
915 env->error_code |= POWERPC_EXCP_FP_VXSNAN;
917 env->error_code |= POWERPC_EXCP_FP_VXISI;
919 env->error_code |= POWERPC_EXCP_FP_VXIDI;
921 env->error_code |= POWERPC_EXCP_FP_VXZDZ;
923 env->error_code |= POWERPC_EXCP_FP_VXIMZ;
925 env->error_code |= POWERPC_EXCP_FP_VXVC;
927 env->error_code |= POWERPC_EXCP_FP_VXSOFT;
929 env->error_code |= POWERPC_EXCP_FP_VXSQRT;
931 env->error_code |= POWERPC_EXCP_FP_VXCVI;
938 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
945 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
952 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX;
959 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
965 fpscr_set_rounding_mode();
970 /* Update the floating-point enabled exception summary */
971 env->fpscr |= 1 << FPSCR_FEX;
972 /* We have to update Rc1 before raising the exception */
973 env->exception_index = POWERPC_EXCP_PROGRAM;
979 void helper_store_fpscr (uint64_t arg, uint32_t mask)
982 * We use only the 32 LSB of the incoming fpr
990 new |= prev & 0x60000000;
991 for (i = 0; i < 8; i++) {
992 if (mask & (1 << i)) {
993 env->fpscr &= ~(0xF << (4 * i));
994 env->fpscr |= new & (0xF << (4 * i));
997 /* Update VX and FEX */
999 env->fpscr |= 1 << FPSCR_VX;
1001 env->fpscr &= ~(1 << FPSCR_VX);
1002 if ((fpscr_ex & fpscr_eex) != 0) {
1003 env->fpscr |= 1 << FPSCR_FEX;
1004 env->exception_index = POWERPC_EXCP_PROGRAM;
1005 /* XXX: we should compute it properly */
1006 env->error_code = POWERPC_EXCP_FP;
1009 env->fpscr &= ~(1 << FPSCR_FEX);
1010 fpscr_set_rounding_mode();
1013 void helper_float_check_status (void)
1015 #ifdef CONFIG_SOFTFLOAT
1016 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
1017 (env->error_code & POWERPC_EXCP_FP)) {
1018 /* Differred floating-point exception after target FPR update */
1019 if (msr_fe0 != 0 || msr_fe1 != 0)
1020 helper_raise_exception_err(env->exception_index, env->error_code);
1022 int status = get_float_exception_flags(&env->fp_status);
1023 if (status & float_flag_overflow) {
1024 float_overflow_excp();
1025 } else if (status & float_flag_underflow) {
1026 float_underflow_excp();
1027 } else if (status & float_flag_inexact) {
1028 float_inexact_excp();
1032 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
1033 (env->error_code & POWERPC_EXCP_FP)) {
1034 /* Differred floating-point exception after target FPR update */
1035 if (msr_fe0 != 0 || msr_fe1 != 0)
1036 helper_raise_exception_err(env->exception_index, env->error_code);
1041 #ifdef CONFIG_SOFTFLOAT
1042 void helper_reset_fpstatus (void)
1044 set_float_exception_flags(0, &env->fp_status);
1049 uint64_t helper_fadd (uint64_t arg1, uint64_t arg2)
1051 CPU_DoubleU farg1, farg2;
1055 #if USE_PRECISE_EMULATION
1056 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1057 float64_is_signaling_nan(farg2.d))) {
1059 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1060 } else if (likely(isfinite(farg1.d) || isfinite(farg2.d) ||
1061 fpisneg(farg1.d) == fpisneg(farg2.d))) {
1062 farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
1064 /* Magnitude subtraction of infinities */
1065 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
1068 farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
1074 uint64_t helper_fsub (uint64_t arg1, uint64_t arg2)
1076 CPU_DoubleU farg1, farg2;
1080 #if USE_PRECISE_EMULATION
1082 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1083 float64_is_signaling_nan(farg2.d))) {
1084 /* sNaN subtraction */
1085 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1086 } else if (likely(isfinite(farg1.d) || isfinite(farg2.d) ||
1087 fpisneg(farg1.d) != fpisneg(farg2.d))) {
1088 farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
1090 /* Magnitude subtraction of infinities */
1091 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
1095 farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
1101 uint64_t helper_fmul (uint64_t arg1, uint64_t arg2)
1103 CPU_DoubleU farg1, farg2;
1107 #if USE_PRECISE_EMULATION
1108 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1109 float64_is_signaling_nan(farg2.d))) {
1110 /* sNaN multiplication */
1111 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1112 } else if (unlikely((isinfinity(farg1.d) && iszero(farg2.d)) ||
1113 (iszero(farg1.d) && isinfinity(farg2.d)))) {
1114 /* Multiplication of zero by infinity */
1115 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
1117 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1120 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1126 uint64_t helper_fdiv (uint64_t arg1, uint64_t arg2)
1128 CPU_DoubleU farg1, farg2;
1132 #if USE_PRECISE_EMULATION
1133 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1134 float64_is_signaling_nan(farg2.d))) {
1136 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1137 } else if (unlikely(isinfinity(farg1.d) && isinfinity(farg2.d))) {
1138 /* Division of infinity by infinity */
1139 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIDI);
1140 } else if (unlikely(iszero(farg2.d))) {
1141 if (iszero(farg1.d)) {
1142 /* Division of zero by zero */
1143 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXZDZ);
1145 /* Division by zero */
1146 farg1.ll = float_zero_divide_excp(farg1.d, farg2.d);
1149 farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
1152 farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
1158 uint64_t helper_fabs (uint64_t arg)
1163 farg.d = float64_abs(farg.d);
1168 uint64_t helper_fnabs (uint64_t arg)
1173 farg.d = float64_abs(farg.d);
1174 farg.d = float64_chs(farg.d);
1179 uint64_t helper_fneg (uint64_t arg)
1184 farg.d = float64_chs(farg.d);
1188 /* fctiw - fctiw. */
1189 uint64_t helper_fctiw (uint64_t arg)
1194 if (unlikely(float64_is_signaling_nan(farg.d))) {
1195 /* sNaN conversion */
1196 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1197 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
1198 /* qNan / infinity conversion */
1199 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1201 farg.ll = float64_to_int32(farg.d, &env->fp_status);
1202 #if USE_PRECISE_EMULATION
1203 /* XXX: higher bits are not supposed to be significant.
1204 * to make tests easier, return the same as a real PowerPC 750
1206 farg.ll |= 0xFFF80000ULL << 32;
1212 /* fctiwz - fctiwz. */
1213 uint64_t helper_fctiwz (uint64_t arg)
1218 if (unlikely(float64_is_signaling_nan(farg.d))) {
1219 /* sNaN conversion */
1220 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1221 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
1222 /* qNan / infinity conversion */
1223 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1225 farg.ll = float64_to_int32_round_to_zero(farg.d, &env->fp_status);
1226 #if USE_PRECISE_EMULATION
1227 /* XXX: higher bits are not supposed to be significant.
1228 * to make tests easier, return the same as a real PowerPC 750
1230 farg.ll |= 0xFFF80000ULL << 32;
1236 #if defined(TARGET_PPC64)
1237 /* fcfid - fcfid. */
1238 uint64_t helper_fcfid (uint64_t arg)
1241 farg.d = int64_to_float64(arg, &env->fp_status);
1245 /* fctid - fctid. */
1246 uint64_t helper_fctid (uint64_t arg)
1251 if (unlikely(float64_is_signaling_nan(farg.d))) {
1252 /* sNaN conversion */
1253 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1254 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
1255 /* qNan / infinity conversion */
1256 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1258 farg.ll = float64_to_int64(farg.d, &env->fp_status);
1263 /* fctidz - fctidz. */
1264 uint64_t helper_fctidz (uint64_t arg)
1269 if (unlikely(float64_is_signaling_nan(farg.d))) {
1270 /* sNaN conversion */
1271 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1272 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
1273 /* qNan / infinity conversion */
1274 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1276 farg.ll = float64_to_int64_round_to_zero(farg.d, &env->fp_status);
1283 static always_inline uint64_t do_fri (uint64_t arg, int rounding_mode)
1288 if (unlikely(float64_is_signaling_nan(farg.d))) {
1290 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1291 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
1292 /* qNan / infinity round */
1293 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1295 set_float_rounding_mode(rounding_mode, &env->fp_status);
1296 farg.ll = float64_round_to_int(farg.d, &env->fp_status);
1297 /* Restore rounding mode from FPSCR */
1298 fpscr_set_rounding_mode();
1303 uint64_t helper_frin (uint64_t arg)
1305 return do_fri(arg, float_round_nearest_even);
1308 uint64_t helper_friz (uint64_t arg)
1310 return do_fri(arg, float_round_to_zero);
1313 uint64_t helper_frip (uint64_t arg)
1315 return do_fri(arg, float_round_up);
1318 uint64_t helper_frim (uint64_t arg)
1320 return do_fri(arg, float_round_down);
1323 /* fmadd - fmadd. */
1324 uint64_t helper_fmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1326 CPU_DoubleU farg1, farg2, farg3;
1331 #if USE_PRECISE_EMULATION
1332 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1333 float64_is_signaling_nan(farg2.d) ||
1334 float64_is_signaling_nan(farg3.d))) {
1335 /* sNaN operation */
1336 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1339 /* This is the way the PowerPC specification defines it */
1340 float128 ft0_128, ft1_128;
1342 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1343 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1344 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1345 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1346 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1347 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1349 /* This is OK on x86 hosts */
1350 farg1.d = (farg1.d * farg2.d) + farg3.d;
1354 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1355 farg1.d = float64_add(farg1.d, farg3.d, &env->fp_status);
1360 /* fmsub - fmsub. */
1361 uint64_t helper_fmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1363 CPU_DoubleU farg1, farg2, farg3;
1368 #if USE_PRECISE_EMULATION
1369 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1370 float64_is_signaling_nan(farg2.d) ||
1371 float64_is_signaling_nan(farg3.d))) {
1372 /* sNaN operation */
1373 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1376 /* This is the way the PowerPC specification defines it */
1377 float128 ft0_128, ft1_128;
1379 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1380 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1381 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1382 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1383 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1384 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1386 /* This is OK on x86 hosts */
1387 farg1.d = (farg1.d * farg2.d) - farg3.d;
1391 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1392 farg1.d = float64_sub(farg1.d, farg3.d, &env->fp_status);
1397 /* fnmadd - fnmadd. */
1398 uint64_t helper_fnmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1400 CPU_DoubleU farg1, farg2, farg3;
1406 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1407 float64_is_signaling_nan(farg2.d) ||
1408 float64_is_signaling_nan(farg3.d))) {
1409 /* sNaN operation */
1410 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1412 #if USE_PRECISE_EMULATION
1414 /* This is the way the PowerPC specification defines it */
1415 float128 ft0_128, ft1_128;
1417 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1418 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1419 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1420 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1421 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1422 farg1.d= float128_to_float64(ft0_128, &env->fp_status);
1424 /* This is OK on x86 hosts */
1425 farg1.d = (farg1.d * farg2.d) + farg3.d;
1428 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1429 farg1.d = float64_add(farg1.d, farg3.d, &env->fp_status);
1431 if (likely(!float64_is_nan(farg1.d)))
1432 farg1.d = float64_chs(farg1.d);
1437 /* fnmsub - fnmsub. */
1438 uint64_t helper_fnmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1440 CPU_DoubleU farg1, farg2, farg3;
1446 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1447 float64_is_signaling_nan(farg2.d) ||
1448 float64_is_signaling_nan(farg3.d))) {
1449 /* sNaN operation */
1450 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1452 #if USE_PRECISE_EMULATION
1454 /* This is the way the PowerPC specification defines it */
1455 float128 ft0_128, ft1_128;
1457 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1458 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1459 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1460 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1461 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1462 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1464 /* This is OK on x86 hosts */
1465 farg1.d = (farg1.d * farg2.d) - farg3.d;
1468 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1469 farg1.d = float64_sub(farg1.d, farg3.d, &env->fp_status);
1471 if (likely(!float64_is_nan(farg1.d)))
1472 farg1.d = float64_chs(farg1.d);
1478 uint64_t helper_frsp (uint64_t arg)
1483 #if USE_PRECISE_EMULATION
1484 if (unlikely(float64_is_signaling_nan(farg.d))) {
1485 /* sNaN square root */
1486 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1488 farg.d = float64_to_float32(farg.d, &env->fp_status);
1491 farg.d = float64_to_float32(farg.d, &env->fp_status);
1496 /* fsqrt - fsqrt. */
1497 uint64_t helper_fsqrt (uint64_t arg)
1502 if (unlikely(float64_is_signaling_nan(farg.d))) {
1503 /* sNaN square root */
1504 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1505 } else if (unlikely(fpisneg(farg.d) && !iszero(farg.d))) {
1506 /* Square root of a negative nonzero number */
1507 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1509 farg.d = float64_sqrt(farg.d, &env->fp_status);
1515 uint64_t helper_fre (uint64_t arg)
1520 if (unlikely(float64_is_signaling_nan(farg.d))) {
1521 /* sNaN reciprocal */
1522 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1523 } else if (unlikely(iszero(farg.d))) {
1524 /* Zero reciprocal */
1525 farg.ll = float_zero_divide_excp(1.0, farg.d);
1526 } else if (likely(isnormal(farg.d))) {
1527 farg.d = float64_div(1.0, farg.d, &env->fp_status);
1529 if (farg.ll == 0x8000000000000000ULL) {
1530 farg.ll = 0xFFF0000000000000ULL;
1531 } else if (farg.ll == 0x0000000000000000ULL) {
1532 farg.ll = 0x7FF0000000000000ULL;
1533 } else if (float64_is_nan(farg.d)) {
1534 farg.ll = 0x7FF8000000000000ULL;
1535 } else if (fpisneg(farg.d)) {
1536 farg.ll = 0x8000000000000000ULL;
1538 farg.ll = 0x0000000000000000ULL;
1545 uint64_t helper_fres (uint64_t arg)
1550 if (unlikely(float64_is_signaling_nan(farg.d))) {
1551 /* sNaN reciprocal */
1552 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1553 } else if (unlikely(iszero(farg.d))) {
1554 /* Zero reciprocal */
1555 farg.ll = float_zero_divide_excp(1.0, farg.d);
1556 } else if (likely(isnormal(farg.d))) {
1557 #if USE_PRECISE_EMULATION
1558 farg.d = float64_div(1.0, farg.d, &env->fp_status);
1559 farg.d = float64_to_float32(farg.d, &env->fp_status);
1561 farg.d = float32_div(1.0, farg.d, &env->fp_status);
1564 if (farg.ll == 0x8000000000000000ULL) {
1565 farg.ll = 0xFFF0000000000000ULL;
1566 } else if (farg.ll == 0x0000000000000000ULL) {
1567 farg.ll = 0x7FF0000000000000ULL;
1568 } else if (float64_is_nan(farg.d)) {
1569 farg.ll = 0x7FF8000000000000ULL;
1570 } else if (fpisneg(farg.d)) {
1571 farg.ll = 0x8000000000000000ULL;
1573 farg.ll = 0x0000000000000000ULL;
1579 /* frsqrte - frsqrte. */
1580 uint64_t helper_frsqrte (uint64_t arg)
1585 if (unlikely(float64_is_signaling_nan(farg.d))) {
1586 /* sNaN reciprocal square root */
1587 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1588 } else if (unlikely(fpisneg(farg.d) && !iszero(farg.d))) {
1589 /* Reciprocal square root of a negative nonzero number */
1590 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1591 } else if (likely(isnormal(farg.d))) {
1592 farg.d = float64_sqrt(farg.d, &env->fp_status);
1593 farg.d = float32_div(1.0, farg.d, &env->fp_status);
1595 if (farg.ll == 0x8000000000000000ULL) {
1596 farg.ll = 0xFFF0000000000000ULL;
1597 } else if (farg.ll == 0x0000000000000000ULL) {
1598 farg.ll = 0x7FF0000000000000ULL;
1599 } else if (float64_is_nan(farg.d)) {
1600 farg.ll |= 0x000FFFFFFFFFFFFFULL;
1601 } else if (fpisneg(farg.d)) {
1602 farg.ll = 0x7FF8000000000000ULL;
1604 farg.ll = 0x0000000000000000ULL;
1611 uint64_t helper_fsel (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1617 if (!fpisneg(farg1.d) || iszero(farg1.d))
1623 void helper_fcmpu (uint64_t arg1, uint64_t arg2, uint32_t crfD)
1625 CPU_DoubleU farg1, farg2;
1630 if (unlikely(float64_is_nan(farg1.d) ||
1631 float64_is_nan(farg2.d))) {
1633 } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1635 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1641 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1642 env->fpscr |= ret << FPSCR_FPRF;
1643 env->crf[crfD] = ret;
1644 if (unlikely(ret == 0x01UL
1645 && (float64_is_signaling_nan(farg1.d) ||
1646 float64_is_signaling_nan(farg2.d)))) {
1647 /* sNaN comparison */
1648 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1652 void helper_fcmpo (uint64_t arg1, uint64_t arg2, uint32_t crfD)
1654 CPU_DoubleU farg1, farg2;
1659 if (unlikely(float64_is_nan(farg1.d) ||
1660 float64_is_nan(farg2.d))) {
1662 } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1664 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1670 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1671 env->fpscr |= ret << FPSCR_FPRF;
1672 env->crf[crfD] = ret;
1673 if (unlikely (ret == 0x01UL)) {
1674 if (float64_is_signaling_nan(farg1.d) ||
1675 float64_is_signaling_nan(farg2.d)) {
1676 /* sNaN comparison */
1677 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN |
1678 POWERPC_EXCP_FP_VXVC);
1680 /* qNaN comparison */
1681 fload_invalid_op_excp(POWERPC_EXCP_FP_VXVC);
1686 #if !defined (CONFIG_USER_ONLY)
1687 void helper_store_msr (target_ulong val)
1689 val = hreg_store_msr(env, val, 0);
1691 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1692 helper_raise_exception(val);
1696 static always_inline void do_rfi (target_ulong nip, target_ulong msr,
1697 target_ulong msrm, int keep_msrh)
1699 #if defined(TARGET_PPC64)
1700 if (msr & (1ULL << MSR_SF)) {
1701 nip = (uint64_t)nip;
1702 msr &= (uint64_t)msrm;
1704 nip = (uint32_t)nip;
1705 msr = (uint32_t)(msr & msrm);
1707 msr |= env->msr & ~((uint64_t)0xFFFFFFFF);
1710 nip = (uint32_t)nip;
1711 msr &= (uint32_t)msrm;
1713 /* XXX: beware: this is false if VLE is supported */
1714 env->nip = nip & ~((target_ulong)0x00000003);
1715 hreg_store_msr(env, msr, 1);
1716 #if defined (DEBUG_OP)
1717 cpu_dump_rfi(env->nip, env->msr);
1719 /* No need to raise an exception here,
1720 * as rfi is always the last insn of a TB
1722 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1725 void helper_rfi (void)
1727 do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1728 ~((target_ulong)0xFFFF0000), 1);
1731 #if defined(TARGET_PPC64)
1732 void helper_rfid (void)
1734 do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1735 ~((target_ulong)0xFFFF0000), 0);
1738 void helper_hrfid (void)
1740 do_rfi(env->spr[SPR_HSRR0], env->spr[SPR_HSRR1],
1741 ~((target_ulong)0xFFFF0000), 0);
1746 void helper_tw (target_ulong arg1, target_ulong arg2, uint32_t flags)
1748 if (!likely(!(((int32_t)arg1 < (int32_t)arg2 && (flags & 0x10)) ||
1749 ((int32_t)arg1 > (int32_t)arg2 && (flags & 0x08)) ||
1750 ((int32_t)arg1 == (int32_t)arg2 && (flags & 0x04)) ||
1751 ((uint32_t)arg1 < (uint32_t)arg2 && (flags & 0x02)) ||
1752 ((uint32_t)arg1 > (uint32_t)arg2 && (flags & 0x01))))) {
1753 helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1757 #if defined(TARGET_PPC64)
1758 void helper_td (target_ulong arg1, target_ulong arg2, uint32_t flags)
1760 if (!likely(!(((int64_t)arg1 < (int64_t)arg2 && (flags & 0x10)) ||
1761 ((int64_t)arg1 > (int64_t)arg2 && (flags & 0x08)) ||
1762 ((int64_t)arg1 == (int64_t)arg2 && (flags & 0x04)) ||
1763 ((uint64_t)arg1 < (uint64_t)arg2 && (flags & 0x02)) ||
1764 ((uint64_t)arg1 > (uint64_t)arg2 && (flags & 0x01)))))
1765 helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1769 /*****************************************************************************/
1770 /* PowerPC 601 specific instructions (POWER bridge) */
1772 target_ulong helper_clcs (uint32_t arg)
1776 /* Instruction cache line size */
1777 return env->icache_line_size;
1780 /* Data cache line size */
1781 return env->dcache_line_size;
1784 /* Minimum cache line size */
1785 return (env->icache_line_size < env->dcache_line_size) ?
1786 env->icache_line_size : env->dcache_line_size;
1789 /* Maximum cache line size */
1790 return (env->icache_line_size > env->dcache_line_size) ?
1791 env->icache_line_size : env->dcache_line_size;
1800 target_ulong helper_div (target_ulong arg1, target_ulong arg2)
1802 uint64_t tmp = (uint64_t)arg1 << 32 | env->spr[SPR_MQ];
1804 if (((int32_t)tmp == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1805 (int32_t)arg2 == 0) {
1806 env->spr[SPR_MQ] = 0;
1809 env->spr[SPR_MQ] = tmp % arg2;
1810 return tmp / (int32_t)arg2;
1814 target_ulong helper_divo (target_ulong arg1, target_ulong arg2)
1816 uint64_t tmp = (uint64_t)arg1 << 32 | env->spr[SPR_MQ];
1818 if (((int32_t)tmp == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1819 (int32_t)arg2 == 0) {
1820 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1821 env->spr[SPR_MQ] = 0;
1824 env->spr[SPR_MQ] = tmp % arg2;
1825 tmp /= (int32_t)arg2;
1826 if ((int32_t)tmp != tmp) {
1827 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1829 env->xer &= ~(1 << XER_OV);
1835 target_ulong helper_divs (target_ulong arg1, target_ulong arg2)
1837 if (((int32_t)arg1 == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1838 (int32_t)arg2 == 0) {
1839 env->spr[SPR_MQ] = 0;
1842 env->spr[SPR_MQ] = (int32_t)arg1 % (int32_t)arg2;
1843 return (int32_t)arg1 / (int32_t)arg2;
1847 target_ulong helper_divso (target_ulong arg1, target_ulong arg2)
1849 if (((int32_t)arg1 == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1850 (int32_t)arg2 == 0) {
1851 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1852 env->spr[SPR_MQ] = 0;
1855 env->xer &= ~(1 << XER_OV);
1856 env->spr[SPR_MQ] = (int32_t)arg1 % (int32_t)arg2;
1857 return (int32_t)arg1 / (int32_t)arg2;
1861 #if !defined (CONFIG_USER_ONLY)
1862 target_ulong helper_rac (target_ulong addr)
1866 target_ulong ret = 0;
1868 /* We don't have to generate many instances of this instruction,
1869 * as rac is supervisor only.
1871 /* XXX: FIX THIS: Pretend we have no BAT */
1872 nb_BATs = env->nb_BATs;
1874 if (get_physical_address(env, &ctx, addr, 0, ACCESS_INT) == 0)
1876 env->nb_BATs = nb_BATs;
1880 void helper_rfsvc (void)
1882 do_rfi(env->lr, env->ctr, 0x0000FFFF, 0);
1886 /*****************************************************************************/
1887 /* 602 specific instructions */
1888 /* mfrom is the most crazy instruction ever seen, imho ! */
1889 /* Real implementation uses a ROM table. Do the same */
1890 /* Extremly decomposed:
1892 * return 256 * log10(10 + 1.0) + 0.5
1894 #if !defined (CONFIG_USER_ONLY)
1895 target_ulong helper_602_mfrom (target_ulong arg)
1897 if (likely(arg < 602)) {
1898 #include "mfrom_table.c"
1899 return mfrom_ROM_table[arg];
1906 /*****************************************************************************/
1907 /* Embedded PowerPC specific helpers */
1909 /* XXX: to be improved to check access rights when in user-mode */
1910 target_ulong helper_load_dcr (target_ulong dcrn)
1912 target_ulong val = 0;
1914 if (unlikely(env->dcr_env == NULL)) {
1915 if (loglevel != 0) {
1916 fprintf(logfile, "No DCR environment\n");
1918 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1919 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
1920 } else if (unlikely(ppc_dcr_read(env->dcr_env, dcrn, &val) != 0)) {
1921 if (loglevel != 0) {
1922 fprintf(logfile, "DCR read error %d %03x\n", (int)dcrn, (int)dcrn);
1924 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1925 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
1930 void helper_store_dcr (target_ulong dcrn, target_ulong val)
1932 if (unlikely(env->dcr_env == NULL)) {
1933 if (loglevel != 0) {
1934 fprintf(logfile, "No DCR environment\n");
1936 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1937 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
1938 } else if (unlikely(ppc_dcr_write(env->dcr_env, dcrn, val) != 0)) {
1939 if (loglevel != 0) {
1940 fprintf(logfile, "DCR write error %d %03x\n", (int)dcrn, (int)dcrn);
1942 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1943 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
1947 #if !defined(CONFIG_USER_ONLY)
1948 void helper_40x_rfci (void)
1950 do_rfi(env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3],
1951 ~((target_ulong)0xFFFF0000), 0);
1954 void helper_rfci (void)
1956 do_rfi(env->spr[SPR_BOOKE_CSRR0], SPR_BOOKE_CSRR1,
1957 ~((target_ulong)0x3FFF0000), 0);
1960 void helper_rfdi (void)
1962 do_rfi(env->spr[SPR_BOOKE_DSRR0], SPR_BOOKE_DSRR1,
1963 ~((target_ulong)0x3FFF0000), 0);
1966 void helper_rfmci (void)
1968 do_rfi(env->spr[SPR_BOOKE_MCSRR0], SPR_BOOKE_MCSRR1,
1969 ~((target_ulong)0x3FFF0000), 0);
1974 target_ulong helper_dlmzb (target_ulong high, target_ulong low, uint32_t update_Rc)
1980 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1981 if ((high & mask) == 0) {
1989 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1990 if ((low & mask) == 0) {
2002 env->xer = (env->xer & ~0x7F) | i;
2004 env->crf[0] |= xer_so;
2009 /*****************************************************************************/
2010 /* SPE extension helpers */
2011 /* Use a table to make this quicker */
2012 static uint8_t hbrev[16] = {
2013 0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE,
2014 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF,
2017 static always_inline uint8_t byte_reverse (uint8_t val)
2019 return hbrev[val >> 4] | (hbrev[val & 0xF] << 4);
2022 static always_inline uint32_t word_reverse (uint32_t val)
2024 return byte_reverse(val >> 24) | (byte_reverse(val >> 16) << 8) |
2025 (byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24);
2028 #define MASKBITS 16 // Random value - to be fixed (implementation dependant)
2029 target_ulong helper_brinc (target_ulong arg1, target_ulong arg2)
2031 uint32_t a, b, d, mask;
2033 mask = UINT32_MAX >> (32 - MASKBITS);
2036 d = word_reverse(1 + word_reverse(a | ~b));
2037 return (arg1 & ~mask) | (d & b);
2040 uint32_t helper_cntlsw32 (uint32_t val)
2042 if (val & 0x80000000)
2048 uint32_t helper_cntlzw32 (uint32_t val)
2053 /* Single-precision floating-point conversions */
2054 static always_inline uint32_t efscfsi (uint32_t val)
2058 u.f = int32_to_float32(val, &env->spe_status);
2063 static always_inline uint32_t efscfui (uint32_t val)
2067 u.f = uint32_to_float32(val, &env->spe_status);
2072 static always_inline int32_t efsctsi (uint32_t val)
2077 /* NaN are not treated the same way IEEE 754 does */
2078 if (unlikely(float32_is_nan(u.f)))
2081 return float32_to_int32(u.f, &env->spe_status);
2084 static always_inline uint32_t efsctui (uint32_t val)
2089 /* NaN are not treated the same way IEEE 754 does */
2090 if (unlikely(float32_is_nan(u.f)))
2093 return float32_to_uint32(u.f, &env->spe_status);
2096 static always_inline uint32_t efsctsiz (uint32_t val)
2101 /* NaN are not treated the same way IEEE 754 does */
2102 if (unlikely(float32_is_nan(u.f)))
2105 return float32_to_int32_round_to_zero(u.f, &env->spe_status);
2108 static always_inline uint32_t efsctuiz (uint32_t val)
2113 /* NaN are not treated the same way IEEE 754 does */
2114 if (unlikely(float32_is_nan(u.f)))
2117 return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
2120 static always_inline uint32_t efscfsf (uint32_t val)
2125 u.f = int32_to_float32(val, &env->spe_status);
2126 tmp = int64_to_float32(1ULL << 32, &env->spe_status);
2127 u.f = float32_div(u.f, tmp, &env->spe_status);
2132 static always_inline uint32_t efscfuf (uint32_t val)
2137 u.f = uint32_to_float32(val, &env->spe_status);
2138 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2139 u.f = float32_div(u.f, tmp, &env->spe_status);
2144 static always_inline uint32_t efsctsf (uint32_t val)
2150 /* NaN are not treated the same way IEEE 754 does */
2151 if (unlikely(float32_is_nan(u.f)))
2153 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2154 u.f = float32_mul(u.f, tmp, &env->spe_status);
2156 return float32_to_int32(u.f, &env->spe_status);
2159 static always_inline uint32_t efsctuf (uint32_t val)
2165 /* NaN are not treated the same way IEEE 754 does */
2166 if (unlikely(float32_is_nan(u.f)))
2168 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2169 u.f = float32_mul(u.f, tmp, &env->spe_status);
2171 return float32_to_uint32(u.f, &env->spe_status);
2174 #define HELPER_SPE_SINGLE_CONV(name) \
2175 uint32_t helper_e##name (uint32_t val) \
2177 return e##name(val); \
2180 HELPER_SPE_SINGLE_CONV(fscfsi);
2182 HELPER_SPE_SINGLE_CONV(fscfui);
2184 HELPER_SPE_SINGLE_CONV(fscfuf);
2186 HELPER_SPE_SINGLE_CONV(fscfsf);
2188 HELPER_SPE_SINGLE_CONV(fsctsi);
2190 HELPER_SPE_SINGLE_CONV(fsctui);
2192 HELPER_SPE_SINGLE_CONV(fsctsiz);
2194 HELPER_SPE_SINGLE_CONV(fsctuiz);
2196 HELPER_SPE_SINGLE_CONV(fsctsf);
2198 HELPER_SPE_SINGLE_CONV(fsctuf);
2200 #define HELPER_SPE_VECTOR_CONV(name) \
2201 uint64_t helper_ev##name (uint64_t val) \
2203 return ((uint64_t)e##name(val >> 32) << 32) | \
2204 (uint64_t)e##name(val); \
2207 HELPER_SPE_VECTOR_CONV(fscfsi);
2209 HELPER_SPE_VECTOR_CONV(fscfui);
2211 HELPER_SPE_VECTOR_CONV(fscfuf);
2213 HELPER_SPE_VECTOR_CONV(fscfsf);
2215 HELPER_SPE_VECTOR_CONV(fsctsi);
2217 HELPER_SPE_VECTOR_CONV(fsctui);
2219 HELPER_SPE_VECTOR_CONV(fsctsiz);
2221 HELPER_SPE_VECTOR_CONV(fsctuiz);
2223 HELPER_SPE_VECTOR_CONV(fsctsf);
2225 HELPER_SPE_VECTOR_CONV(fsctuf);
2227 /* Single-precision floating-point arithmetic */
2228 static always_inline uint32_t efsadd (uint32_t op1, uint32_t op2)
2233 u1.f = float32_add(u1.f, u2.f, &env->spe_status);
2237 static always_inline uint32_t efssub (uint32_t op1, uint32_t op2)
2242 u1.f = float32_sub(u1.f, u2.f, &env->spe_status);
2246 static always_inline uint32_t efsmul (uint32_t op1, uint32_t op2)
2251 u1.f = float32_mul(u1.f, u2.f, &env->spe_status);
2255 static always_inline uint32_t efsdiv (uint32_t op1, uint32_t op2)
2260 u1.f = float32_div(u1.f, u2.f, &env->spe_status);
2264 #define HELPER_SPE_SINGLE_ARITH(name) \
2265 uint32_t helper_e##name (uint32_t op1, uint32_t op2) \
2267 return e##name(op1, op2); \
2270 HELPER_SPE_SINGLE_ARITH(fsadd);
2272 HELPER_SPE_SINGLE_ARITH(fssub);
2274 HELPER_SPE_SINGLE_ARITH(fsmul);
2276 HELPER_SPE_SINGLE_ARITH(fsdiv);
2278 #define HELPER_SPE_VECTOR_ARITH(name) \
2279 uint64_t helper_ev##name (uint64_t op1, uint64_t op2) \
2281 return ((uint64_t)e##name(op1 >> 32, op2 >> 32) << 32) | \
2282 (uint64_t)e##name(op1, op2); \
2285 HELPER_SPE_VECTOR_ARITH(fsadd);
2287 HELPER_SPE_VECTOR_ARITH(fssub);
2289 HELPER_SPE_VECTOR_ARITH(fsmul);
2291 HELPER_SPE_VECTOR_ARITH(fsdiv);
2293 /* Single-precision floating-point comparisons */
2294 static always_inline uint32_t efststlt (uint32_t op1, uint32_t op2)
2299 return float32_lt(u1.f, u2.f, &env->spe_status) ? 4 : 0;
2302 static always_inline uint32_t efststgt (uint32_t op1, uint32_t op2)
2307 return float32_le(u1.f, u2.f, &env->spe_status) ? 0 : 4;
2310 static always_inline uint32_t efststeq (uint32_t op1, uint32_t op2)
2315 return float32_eq(u1.f, u2.f, &env->spe_status) ? 4 : 0;
2318 static always_inline uint32_t efscmplt (uint32_t op1, uint32_t op2)
2320 /* XXX: TODO: test special values (NaN, infinites, ...) */
2321 return efststlt(op1, op2);
2324 static always_inline uint32_t efscmpgt (uint32_t op1, uint32_t op2)
2326 /* XXX: TODO: test special values (NaN, infinites, ...) */
2327 return efststgt(op1, op2);
2330 static always_inline uint32_t efscmpeq (uint32_t op1, uint32_t op2)
2332 /* XXX: TODO: test special values (NaN, infinites, ...) */
2333 return efststeq(op1, op2);
2336 #define HELPER_SINGLE_SPE_CMP(name) \
2337 uint32_t helper_e##name (uint32_t op1, uint32_t op2) \
2339 return e##name(op1, op2) << 2; \
2342 HELPER_SINGLE_SPE_CMP(fststlt);
2344 HELPER_SINGLE_SPE_CMP(fststgt);
2346 HELPER_SINGLE_SPE_CMP(fststeq);
2348 HELPER_SINGLE_SPE_CMP(fscmplt);
2350 HELPER_SINGLE_SPE_CMP(fscmpgt);
2352 HELPER_SINGLE_SPE_CMP(fscmpeq);
2354 static always_inline uint32_t evcmp_merge (int t0, int t1)
2356 return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
2359 #define HELPER_VECTOR_SPE_CMP(name) \
2360 uint32_t helper_ev##name (uint64_t op1, uint64_t op2) \
2362 return evcmp_merge(e##name(op1 >> 32, op2 >> 32), e##name(op1, op2)); \
2365 HELPER_VECTOR_SPE_CMP(fststlt);
2367 HELPER_VECTOR_SPE_CMP(fststgt);
2369 HELPER_VECTOR_SPE_CMP(fststeq);
2371 HELPER_VECTOR_SPE_CMP(fscmplt);
2373 HELPER_VECTOR_SPE_CMP(fscmpgt);
2375 HELPER_VECTOR_SPE_CMP(fscmpeq);
2377 /* Double-precision floating-point conversion */
2378 uint64_t helper_efdcfsi (uint32_t val)
2382 u.d = int32_to_float64(val, &env->spe_status);
2387 uint64_t helper_efdcfsid (uint64_t val)
2391 u.d = int64_to_float64(val, &env->spe_status);
2396 uint64_t helper_efdcfui (uint32_t val)
2400 u.d = uint32_to_float64(val, &env->spe_status);
2405 uint64_t helper_efdcfuid (uint64_t val)
2409 u.d = uint64_to_float64(val, &env->spe_status);
2414 uint32_t helper_efdctsi (uint64_t val)
2419 /* NaN are not treated the same way IEEE 754 does */
2420 if (unlikely(float64_is_nan(u.d)))
2423 return float64_to_int32(u.d, &env->spe_status);
2426 uint32_t helper_efdctui (uint64_t val)
2431 /* NaN are not treated the same way IEEE 754 does */
2432 if (unlikely(float64_is_nan(u.d)))
2435 return float64_to_uint32(u.d, &env->spe_status);
2438 uint32_t helper_efdctsiz (uint64_t val)
2443 /* NaN are not treated the same way IEEE 754 does */
2444 if (unlikely(float64_is_nan(u.d)))
2447 return float64_to_int32_round_to_zero(u.d, &env->spe_status);
2450 uint64_t helper_efdctsidz (uint64_t val)
2455 /* NaN are not treated the same way IEEE 754 does */
2456 if (unlikely(float64_is_nan(u.d)))
2459 return float64_to_int64_round_to_zero(u.d, &env->spe_status);
2462 uint32_t helper_efdctuiz (uint64_t val)
2467 /* NaN are not treated the same way IEEE 754 does */
2468 if (unlikely(float64_is_nan(u.d)))
2471 return float64_to_uint32_round_to_zero(u.d, &env->spe_status);
2474 uint64_t helper_efdctuidz (uint64_t val)
2479 /* NaN are not treated the same way IEEE 754 does */
2480 if (unlikely(float64_is_nan(u.d)))
2483 return float64_to_uint64_round_to_zero(u.d, &env->spe_status);
2486 uint64_t helper_efdcfsf (uint32_t val)
2491 u.d = int32_to_float64(val, &env->spe_status);
2492 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
2493 u.d = float64_div(u.d, tmp, &env->spe_status);
2498 uint64_t helper_efdcfuf (uint32_t val)
2503 u.d = uint32_to_float64(val, &env->spe_status);
2504 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
2505 u.d = float64_div(u.d, tmp, &env->spe_status);
2510 uint32_t helper_efdctsf (uint64_t val)
2516 /* NaN are not treated the same way IEEE 754 does */
2517 if (unlikely(float64_is_nan(u.d)))
2519 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2520 u.d = float64_mul(u.d, tmp, &env->spe_status);
2522 return float64_to_int32(u.d, &env->spe_status);
2525 uint32_t helper_efdctuf (uint64_t val)
2531 /* NaN are not treated the same way IEEE 754 does */
2532 if (unlikely(float64_is_nan(u.d)))
2534 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2535 u.d = float64_mul(u.d, tmp, &env->spe_status);
2537 return float64_to_uint32(u.d, &env->spe_status);
2540 uint32_t helper_efscfd (uint64_t val)
2546 u2.f = float64_to_float32(u1.d, &env->spe_status);
2551 uint64_t helper_efdcfs (uint32_t val)
2557 u2.d = float32_to_float64(u1.f, &env->spe_status);
2562 /* Double precision fixed-point arithmetic */
2563 uint64_t helper_efdadd (uint64_t op1, uint64_t op2)
2568 u1.d = float64_add(u1.d, u2.d, &env->spe_status);
2572 uint64_t helper_efdsub (uint64_t op1, uint64_t op2)
2577 u1.d = float64_sub(u1.d, u2.d, &env->spe_status);
2581 uint64_t helper_efdmul (uint64_t op1, uint64_t op2)
2586 u1.d = float64_mul(u1.d, u2.d, &env->spe_status);
2590 uint64_t helper_efddiv (uint64_t op1, uint64_t op2)
2595 u1.d = float64_div(u1.d, u2.d, &env->spe_status);
2599 /* Double precision floating point helpers */
2600 uint32_t helper_efdtstlt (uint64_t op1, uint64_t op2)
2605 return float64_lt(u1.d, u2.d, &env->spe_status) ? 4 : 0;
2608 uint32_t helper_efdtstgt (uint64_t op1, uint64_t op2)
2613 return float64_le(u1.d, u2.d, &env->spe_status) ? 0 : 4;
2616 uint32_t helper_efdtsteq (uint64_t op1, uint64_t op2)
2621 return float64_eq(u1.d, u2.d, &env->spe_status) ? 4 : 0;
2624 uint32_t helper_efdcmplt (uint64_t op1, uint64_t op2)
2626 /* XXX: TODO: test special values (NaN, infinites, ...) */
2627 return helper_efdtstlt(op1, op2);
2630 uint32_t helper_efdcmpgt (uint64_t op1, uint64_t op2)
2632 /* XXX: TODO: test special values (NaN, infinites, ...) */
2633 return helper_efdtstgt(op1, op2);
2636 uint32_t helper_efdcmpeq (uint64_t op1, uint64_t op2)
2638 /* XXX: TODO: test special values (NaN, infinites, ...) */
2639 return helper_efdtsteq(op1, op2);
2642 /*****************************************************************************/
2643 /* Softmmu support */
2644 #if !defined (CONFIG_USER_ONLY)
2646 #define MMUSUFFIX _mmu
2649 #include "softmmu_template.h"
2652 #include "softmmu_template.h"
2655 #include "softmmu_template.h"
2658 #include "softmmu_template.h"
2660 /* try to fill the TLB and return an exception if error. If retaddr is
2661 NULL, it means that the function was called in C code (i.e. not
2662 from generated code or from helper.c) */
2663 /* XXX: fix it to restore all registers */
2664 void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
2666 TranslationBlock *tb;
2667 CPUState *saved_env;
2671 /* XXX: hack to restore env in all cases, even if not called from
2674 env = cpu_single_env;
2675 ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
2676 if (unlikely(ret != 0)) {
2677 if (likely(retaddr)) {
2678 /* now we have a real cpu fault */
2679 pc = (unsigned long)retaddr;
2680 tb = tb_find_pc(pc);
2682 /* the PC is inside the translated code. It means that we have
2683 a virtual CPU fault */
2684 cpu_restore_state(tb, env, pc, NULL);
2687 helper_raise_exception_err(env->exception_index, env->error_code);
2692 /* Segment registers load and store */
2693 target_ulong helper_load_sr (target_ulong sr_num)
2695 return env->sr[sr_num];
2698 void helper_store_sr (target_ulong sr_num, target_ulong val)
2700 ppc_store_sr(env, sr_num, val);
2703 /* SLB management */
2704 #if defined(TARGET_PPC64)
2705 target_ulong helper_load_slb (target_ulong slb_nr)
2707 return ppc_load_slb(env, slb_nr);
2710 void helper_store_slb (target_ulong slb_nr, target_ulong rs)
2712 ppc_store_slb(env, slb_nr, rs);
2715 void helper_slbia (void)
2717 ppc_slb_invalidate_all(env);
2720 void helper_slbie (target_ulong addr)
2722 ppc_slb_invalidate_one(env, addr);
2725 #endif /* defined(TARGET_PPC64) */
2727 /* TLB management */
2728 void helper_tlbia (void)
2730 ppc_tlb_invalidate_all(env);
2733 void helper_tlbie (target_ulong addr)
2735 ppc_tlb_invalidate_one(env, addr);
2738 /* Software driven TLBs management */
2739 /* PowerPC 602/603 software TLB load instructions helpers */
2740 static void do_6xx_tlb (target_ulong new_EPN, int is_code)
2742 target_ulong RPN, CMP, EPN;
2745 RPN = env->spr[SPR_RPA];
2747 CMP = env->spr[SPR_ICMP];
2748 EPN = env->spr[SPR_IMISS];
2750 CMP = env->spr[SPR_DCMP];
2751 EPN = env->spr[SPR_DMISS];
2753 way = (env->spr[SPR_SRR1] >> 17) & 1;
2754 #if defined (DEBUG_SOFTWARE_TLB)
2755 if (loglevel != 0) {
2756 fprintf(logfile, "%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX
2757 " PTE1 " ADDRX " way %d\n",
2758 __func__, new_EPN, EPN, CMP, RPN, way);
2761 /* Store this TLB */
2762 ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
2763 way, is_code, CMP, RPN);
2766 void helper_6xx_tlbd (target_ulong EPN)
2771 void helper_6xx_tlbi (target_ulong EPN)
2776 /* PowerPC 74xx software TLB load instructions helpers */
2777 static void do_74xx_tlb (target_ulong new_EPN, int is_code)
2779 target_ulong RPN, CMP, EPN;
2782 RPN = env->spr[SPR_PTELO];
2783 CMP = env->spr[SPR_PTEHI];
2784 EPN = env->spr[SPR_TLBMISS] & ~0x3;
2785 way = env->spr[SPR_TLBMISS] & 0x3;
2786 #if defined (DEBUG_SOFTWARE_TLB)
2787 if (loglevel != 0) {
2788 fprintf(logfile, "%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX
2789 " PTE1 " ADDRX " way %d\n",
2790 __func__, new_EPN, EPN, CMP, RPN, way);
2793 /* Store this TLB */
2794 ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
2795 way, is_code, CMP, RPN);
2798 void helper_74xx_tlbd (target_ulong EPN)
2800 do_74xx_tlb(EPN, 0);
2803 void helper_74xx_tlbi (target_ulong EPN)
2805 do_74xx_tlb(EPN, 1);
2808 static always_inline target_ulong booke_tlb_to_page_size (int size)
2810 return 1024 << (2 * size);
2813 static always_inline int booke_page_size_to_tlb (target_ulong page_size)
2817 switch (page_size) {
2851 #if defined (TARGET_PPC64)
2852 case 0x000100000000ULL:
2855 case 0x000400000000ULL:
2858 case 0x001000000000ULL:
2861 case 0x004000000000ULL:
2864 case 0x010000000000ULL:
2876 /* Helpers for 4xx TLB management */
2877 target_ulong helper_4xx_tlbre_lo (target_ulong entry)
2884 tlb = &env->tlb[entry].tlbe;
2886 if (tlb->prot & PAGE_VALID)
2888 size = booke_page_size_to_tlb(tlb->size);
2889 if (size < 0 || size > 0x7)
2892 env->spr[SPR_40x_PID] = tlb->PID;
2896 target_ulong helper_4xx_tlbre_hi (target_ulong entry)
2902 tlb = &env->tlb[entry].tlbe;
2904 if (tlb->prot & PAGE_EXEC)
2906 if (tlb->prot & PAGE_WRITE)
2911 void helper_4xx_tlbwe_hi (target_ulong entry, target_ulong val)
2914 target_ulong page, end;
2916 #if defined (DEBUG_SOFTWARE_TLB)
2917 if (loglevel != 0) {
2918 fprintf(logfile, "%s entry %d val " ADDRX "\n", __func__, (int)entry, val);
2922 tlb = &env->tlb[entry].tlbe;
2923 /* Invalidate previous TLB (if it's valid) */
2924 if (tlb->prot & PAGE_VALID) {
2925 end = tlb->EPN + tlb->size;
2926 #if defined (DEBUG_SOFTWARE_TLB)
2927 if (loglevel != 0) {
2928 fprintf(logfile, "%s: invalidate old TLB %d start " ADDRX
2929 " end " ADDRX "\n", __func__, (int)entry, tlb->EPN, end);
2932 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2933 tlb_flush_page(env, page);
2935 tlb->size = booke_tlb_to_page_size((val >> 7) & 0x7);
2936 /* We cannot handle TLB size < TARGET_PAGE_SIZE.
2937 * If this ever occurs, one should use the ppcemb target instead
2938 * of the ppc or ppc64 one
2940 if ((val & 0x40) && tlb->size < TARGET_PAGE_SIZE) {
2941 cpu_abort(env, "TLB size " TARGET_FMT_lu " < %u "
2942 "are not supported (%d)\n",
2943 tlb->size, TARGET_PAGE_SIZE, (int)((val >> 7) & 0x7));
2945 tlb->EPN = val & ~(tlb->size - 1);
2947 tlb->prot |= PAGE_VALID;
2949 tlb->prot &= ~PAGE_VALID;
2951 /* XXX: TO BE FIXED */
2952 cpu_abort(env, "Little-endian TLB entries are not supported by now\n");
2954 tlb->PID = env->spr[SPR_40x_PID]; /* PID */
2955 tlb->attr = val & 0xFF;
2956 #if defined (DEBUG_SOFTWARE_TLB)
2957 if (loglevel != 0) {
2958 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
2959 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
2960 (int)entry, tlb->RPN, tlb->EPN, tlb->size,
2961 tlb->prot & PAGE_READ ? 'r' : '-',
2962 tlb->prot & PAGE_WRITE ? 'w' : '-',
2963 tlb->prot & PAGE_EXEC ? 'x' : '-',
2964 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
2967 /* Invalidate new TLB (if valid) */
2968 if (tlb->prot & PAGE_VALID) {
2969 end = tlb->EPN + tlb->size;
2970 #if defined (DEBUG_SOFTWARE_TLB)
2971 if (loglevel != 0) {
2972 fprintf(logfile, "%s: invalidate TLB %d start " ADDRX
2973 " end " ADDRX "\n", __func__, (int)entry, tlb->EPN, end);
2976 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2977 tlb_flush_page(env, page);
2981 void helper_4xx_tlbwe_lo (target_ulong entry, target_ulong val)
2985 #if defined (DEBUG_SOFTWARE_TLB)
2986 if (loglevel != 0) {
2987 fprintf(logfile, "%s entry %i val " ADDRX "\n", __func__, (int)entry, val);
2991 tlb = &env->tlb[entry].tlbe;
2992 tlb->RPN = val & 0xFFFFFC00;
2993 tlb->prot = PAGE_READ;
2995 tlb->prot |= PAGE_EXEC;
2997 tlb->prot |= PAGE_WRITE;
2998 #if defined (DEBUG_SOFTWARE_TLB)
2999 if (loglevel != 0) {
3000 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
3001 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
3002 (int)entry, tlb->RPN, tlb->EPN, tlb->size,
3003 tlb->prot & PAGE_READ ? 'r' : '-',
3004 tlb->prot & PAGE_WRITE ? 'w' : '-',
3005 tlb->prot & PAGE_EXEC ? 'x' : '-',
3006 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
3011 target_ulong helper_4xx_tlbsx (target_ulong address)
3013 return ppcemb_tlb_search(env, address, env->spr[SPR_40x_PID]);
3016 /* PowerPC 440 TLB management */
3017 void helper_440_tlbwe (uint32_t word, target_ulong entry, target_ulong value)
3020 target_ulong EPN, RPN, size;
3023 #if defined (DEBUG_SOFTWARE_TLB)
3024 if (loglevel != 0) {
3025 fprintf(logfile, "%s word %d entry %d value " ADDRX "\n",
3026 __func__, word, (int)entry, value);
3031 tlb = &env->tlb[entry].tlbe;
3034 /* Just here to please gcc */
3036 EPN = value & 0xFFFFFC00;
3037 if ((tlb->prot & PAGE_VALID) && EPN != tlb->EPN)
3040 size = booke_tlb_to_page_size((value >> 4) & 0xF);
3041 if ((tlb->prot & PAGE_VALID) && tlb->size < size)
3045 tlb->attr |= (value >> 8) & 1;
3046 if (value & 0x200) {
3047 tlb->prot |= PAGE_VALID;
3049 if (tlb->prot & PAGE_VALID) {
3050 tlb->prot &= ~PAGE_VALID;
3054 tlb->PID = env->spr[SPR_440_MMUCR] & 0x000000FF;
3059 RPN = value & 0xFFFFFC0F;
3060 if ((tlb->prot & PAGE_VALID) && tlb->RPN != RPN)
3065 tlb->attr = (tlb->attr & 0x1) | (value & 0x0000FF00);
3066 tlb->prot = tlb->prot & PAGE_VALID;
3068 tlb->prot |= PAGE_READ << 4;
3070 tlb->prot |= PAGE_WRITE << 4;
3072 tlb->prot |= PAGE_EXEC << 4;
3074 tlb->prot |= PAGE_READ;
3076 tlb->prot |= PAGE_WRITE;
3078 tlb->prot |= PAGE_EXEC;
3083 target_ulong helper_440_tlbre (uint32_t word, target_ulong entry)
3090 tlb = &env->tlb[entry].tlbe;
3093 /* Just here to please gcc */
3096 size = booke_page_size_to_tlb(tlb->size);
3097 if (size < 0 || size > 0xF)
3100 if (tlb->attr & 0x1)
3102 if (tlb->prot & PAGE_VALID)
3104 env->spr[SPR_440_MMUCR] &= ~0x000000FF;
3105 env->spr[SPR_440_MMUCR] |= tlb->PID;
3111 ret = tlb->attr & ~0x1;
3112 if (tlb->prot & (PAGE_READ << 4))
3114 if (tlb->prot & (PAGE_WRITE << 4))
3116 if (tlb->prot & (PAGE_EXEC << 4))
3118 if (tlb->prot & PAGE_READ)
3120 if (tlb->prot & PAGE_WRITE)
3122 if (tlb->prot & PAGE_EXEC)
3129 target_ulong helper_440_tlbsx (target_ulong address)
3131 return ppcemb_tlb_search(env, address, env->spr[SPR_440_MMUCR] & 0xFF);
3134 #endif /* !CONFIG_USER_ONLY */