2 * PowerPC emulation helpers for qemu.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include "host-utils.h"
24 #include "helper_regs.h"
27 //#define DEBUG_EXCEPTIONS
28 //#define DEBUG_SOFTWARE_TLB
30 /*****************************************************************************/
31 /* Exceptions processing helpers */
33 void helper_raise_exception_err (uint32_t exception, uint32_t error_code)
36 printf("Raise exception %3x code : %d\n", exception, error_code);
38 env->exception_index = exception;
39 env->error_code = error_code;
43 void helper_raise_exception (uint32_t exception)
45 helper_raise_exception_err(exception, 0);
48 /*****************************************************************************/
49 /* Registers load and stores */
50 target_ulong helper_load_cr (void)
52 return (env->crf[0] << 28) |
62 void helper_store_cr (target_ulong val, uint32_t mask)
66 for (i = 0, sh = 7; i < 8; i++, sh--) {
68 env->crf[i] = (val >> (sh * 4)) & 0xFUL;
72 /*****************************************************************************/
74 void helper_load_dump_spr (uint32_t sprn)
77 fprintf(logfile, "Read SPR %d %03x => " ADDRX "\n",
78 sprn, sprn, env->spr[sprn]);
82 void helper_store_dump_spr (uint32_t sprn)
85 fprintf(logfile, "Write SPR %d %03x <= " ADDRX "\n",
86 sprn, sprn, env->spr[sprn]);
90 target_ulong helper_load_tbl (void)
92 return cpu_ppc_load_tbl(env);
95 target_ulong helper_load_tbu (void)
97 return cpu_ppc_load_tbu(env);
100 target_ulong helper_load_atbl (void)
102 return cpu_ppc_load_atbl(env);
105 target_ulong helper_load_atbu (void)
107 return cpu_ppc_load_atbu(env);
110 target_ulong helper_load_601_rtcl (void)
112 return cpu_ppc601_load_rtcl(env);
115 target_ulong helper_load_601_rtcu (void)
117 return cpu_ppc601_load_rtcu(env);
120 #if !defined(CONFIG_USER_ONLY)
121 #if defined (TARGET_PPC64)
122 void helper_store_asr (target_ulong val)
124 ppc_store_asr(env, val);
128 void helper_store_sdr1 (target_ulong val)
130 ppc_store_sdr1(env, val);
133 void helper_store_tbl (target_ulong val)
135 cpu_ppc_store_tbl(env, val);
138 void helper_store_tbu (target_ulong val)
140 cpu_ppc_store_tbu(env, val);
143 void helper_store_atbl (target_ulong val)
145 cpu_ppc_store_atbl(env, val);
148 void helper_store_atbu (target_ulong val)
150 cpu_ppc_store_atbu(env, val);
153 void helper_store_601_rtcl (target_ulong val)
155 cpu_ppc601_store_rtcl(env, val);
158 void helper_store_601_rtcu (target_ulong val)
160 cpu_ppc601_store_rtcu(env, val);
163 target_ulong helper_load_decr (void)
165 return cpu_ppc_load_decr(env);
168 void helper_store_decr (target_ulong val)
170 cpu_ppc_store_decr(env, val);
173 void helper_store_hid0_601 (target_ulong val)
177 hid0 = env->spr[SPR_HID0];
178 if ((val ^ hid0) & 0x00000008) {
179 /* Change current endianness */
180 env->hflags &= ~(1 << MSR_LE);
181 env->hflags_nmsr &= ~(1 << MSR_LE);
182 env->hflags_nmsr |= (1 << MSR_LE) & (((val >> 3) & 1) << MSR_LE);
183 env->hflags |= env->hflags_nmsr;
185 fprintf(logfile, "%s: set endianness to %c => " ADDRX "\n",
186 __func__, val & 0x8 ? 'l' : 'b', env->hflags);
189 env->spr[SPR_HID0] = (uint32_t)val;
192 void helper_store_403_pbr (uint32_t num, target_ulong value)
194 if (likely(env->pb[num] != value)) {
195 env->pb[num] = value;
196 /* Should be optimized */
201 target_ulong helper_load_40x_pit (void)
203 return load_40x_pit(env);
206 void helper_store_40x_pit (target_ulong val)
208 store_40x_pit(env, val);
211 void helper_store_40x_dbcr0 (target_ulong val)
213 store_40x_dbcr0(env, val);
216 void helper_store_40x_sler (target_ulong val)
218 store_40x_sler(env, val);
221 void helper_store_booke_tcr (target_ulong val)
223 store_booke_tcr(env, val);
226 void helper_store_booke_tsr (target_ulong val)
228 store_booke_tsr(env, val);
231 void helper_store_ibatu (uint32_t nr, target_ulong val)
233 ppc_store_ibatu(env, nr, val);
236 void helper_store_ibatl (uint32_t nr, target_ulong val)
238 ppc_store_ibatl(env, nr, val);
241 void helper_store_dbatu (uint32_t nr, target_ulong val)
243 ppc_store_dbatu(env, nr, val);
246 void helper_store_dbatl (uint32_t nr, target_ulong val)
248 ppc_store_dbatl(env, nr, val);
251 void helper_store_601_batl (uint32_t nr, target_ulong val)
253 ppc_store_ibatl_601(env, nr, val);
256 void helper_store_601_batu (uint32_t nr, target_ulong val)
258 ppc_store_ibatu_601(env, nr, val);
262 /*****************************************************************************/
263 /* Memory load and stores */
265 static always_inline target_ulong addr_add(target_ulong addr, target_long arg)
267 #if defined(TARGET_PPC64)
269 return (uint32_t)(addr + arg);
275 void helper_lmw (target_ulong addr, uint32_t reg)
277 for (; reg < 32; reg++) {
279 env->gpr[reg] = bswap32(ldl(addr));
281 env->gpr[reg] = ldl(addr);
282 addr = addr_add(addr, 4);
286 void helper_stmw (target_ulong addr, uint32_t reg)
288 for (; reg < 32; reg++) {
290 stl(addr, bswap32((uint32_t)env->gpr[reg]));
292 stl(addr, (uint32_t)env->gpr[reg]);
293 addr = addr_add(addr, 4);
297 void helper_lsw(target_ulong addr, uint32_t nb, uint32_t reg)
300 for (; nb > 3; nb -= 4) {
301 env->gpr[reg] = ldl(addr);
302 reg = (reg + 1) % 32;
303 addr = addr_add(addr, 4);
305 if (unlikely(nb > 0)) {
307 for (sh = 24; nb > 0; nb--, sh -= 8) {
308 env->gpr[reg] |= ldub(addr) << sh;
309 addr = addr_add(addr, 1);
313 /* PPC32 specification says we must generate an exception if
314 * rA is in the range of registers to be loaded.
315 * In an other hand, IBM says this is valid, but rA won't be loaded.
316 * For now, I'll follow the spec...
318 void helper_lswx(target_ulong addr, uint32_t reg, uint32_t ra, uint32_t rb)
320 if (likely(xer_bc != 0)) {
321 if (unlikely((ra != 0 && reg < ra && (reg + xer_bc) > ra) ||
322 (reg < rb && (reg + xer_bc) > rb))) {
323 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
325 POWERPC_EXCP_INVAL_LSWX);
327 helper_lsw(addr, xer_bc, reg);
332 void helper_stsw(target_ulong addr, uint32_t nb, uint32_t reg)
335 for (; nb > 3; nb -= 4) {
336 stl(addr, env->gpr[reg]);
337 reg = (reg + 1) % 32;
338 addr = addr_add(addr, 4);
340 if (unlikely(nb > 0)) {
341 for (sh = 24; nb > 0; nb--, sh -= 8)
342 stb(addr, (env->gpr[reg] >> sh) & 0xFF);
343 addr = addr_add(addr, 1);
347 static void do_dcbz(target_ulong addr, int dcache_line_size)
349 addr &= ~(dcache_line_size - 1);
351 for (i = 0 ; i < dcache_line_size ; i += 4) {
354 if (env->reserve == addr)
355 env->reserve = (target_ulong)-1ULL;
358 void helper_dcbz(target_ulong addr)
360 do_dcbz(addr, env->dcache_line_size);
363 void helper_dcbz_970(target_ulong addr)
365 if (((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1)
368 do_dcbz(addr, env->dcache_line_size);
371 void helper_icbi(target_ulong addr)
375 addr &= ~(env->dcache_line_size - 1);
376 /* Invalidate one cache line :
377 * PowerPC specification says this is to be treated like a load
378 * (not a fetch) by the MMU. To be sure it will be so,
379 * do the load "by hand".
382 tb_invalidate_page_range(addr, addr + env->icache_line_size);
386 target_ulong helper_lscbx (target_ulong addr, uint32_t reg, uint32_t ra, uint32_t rb)
390 for (i = 0; i < xer_bc; i++) {
392 addr = addr_add(addr, 1);
393 /* ra (if not 0) and rb are never modified */
394 if (likely(reg != rb && (ra == 0 || reg != ra))) {
395 env->gpr[reg] = (env->gpr[reg] & ~(0xFF << d)) | (c << d);
397 if (unlikely(c == xer_cmp))
399 if (likely(d != 0)) {
410 /*****************************************************************************/
411 /* Fixed point operations helpers */
412 #if defined(TARGET_PPC64)
414 /* multiply high word */
415 uint64_t helper_mulhd (uint64_t arg1, uint64_t arg2)
419 muls64(&tl, &th, arg1, arg2);
423 /* multiply high word unsigned */
424 uint64_t helper_mulhdu (uint64_t arg1, uint64_t arg2)
428 mulu64(&tl, &th, arg1, arg2);
432 uint64_t helper_mulldo (uint64_t arg1, uint64_t arg2)
437 muls64(&tl, (uint64_t *)&th, arg1, arg2);
438 /* If th != 0 && th != -1, then we had an overflow */
439 if (likely((uint64_t)(th + 1) <= 1)) {
440 env->xer &= ~(1 << XER_OV);
442 env->xer |= (1 << XER_OV) | (1 << XER_SO);
448 target_ulong helper_cntlzw (target_ulong t)
453 #if defined(TARGET_PPC64)
454 target_ulong helper_cntlzd (target_ulong t)
460 /* shift right arithmetic helper */
461 target_ulong helper_sraw (target_ulong value, target_ulong shift)
465 if (likely(!(shift & 0x20))) {
466 if (likely((uint32_t)shift != 0)) {
468 ret = (int32_t)value >> shift;
469 if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
470 env->xer &= ~(1 << XER_CA);
472 env->xer |= (1 << XER_CA);
475 ret = (int32_t)value;
476 env->xer &= ~(1 << XER_CA);
479 ret = (int32_t)value >> 31;
481 env->xer |= (1 << XER_CA);
483 env->xer &= ~(1 << XER_CA);
486 return (target_long)ret;
489 #if defined(TARGET_PPC64)
490 target_ulong helper_srad (target_ulong value, target_ulong shift)
494 if (likely(!(shift & 0x40))) {
495 if (likely((uint64_t)shift != 0)) {
497 ret = (int64_t)value >> shift;
498 if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
499 env->xer &= ~(1 << XER_CA);
501 env->xer |= (1 << XER_CA);
504 ret = (int64_t)value;
505 env->xer &= ~(1 << XER_CA);
508 ret = (int64_t)value >> 63;
510 env->xer |= (1 << XER_CA);
512 env->xer &= ~(1 << XER_CA);
519 target_ulong helper_popcntb (target_ulong val)
521 val = (val & 0x55555555) + ((val >> 1) & 0x55555555);
522 val = (val & 0x33333333) + ((val >> 2) & 0x33333333);
523 val = (val & 0x0f0f0f0f) + ((val >> 4) & 0x0f0f0f0f);
527 #if defined(TARGET_PPC64)
528 target_ulong helper_popcntb_64 (target_ulong val)
530 val = (val & 0x5555555555555555ULL) + ((val >> 1) & 0x5555555555555555ULL);
531 val = (val & 0x3333333333333333ULL) + ((val >> 2) & 0x3333333333333333ULL);
532 val = (val & 0x0f0f0f0f0f0f0f0fULL) + ((val >> 4) & 0x0f0f0f0f0f0f0f0fULL);
537 /*****************************************************************************/
538 /* Floating point operations helpers */
539 uint64_t helper_float32_to_float64(uint32_t arg)
544 d.d = float32_to_float64(f.f, &env->fp_status);
548 uint32_t helper_float64_to_float32(uint64_t arg)
553 f.f = float64_to_float32(d.d, &env->fp_status);
557 static always_inline int fpisneg (float64 d)
563 return u.ll >> 63 != 0;
566 static always_inline int isden (float64 d)
572 return ((u.ll >> 52) & 0x7FF) == 0;
575 static always_inline int iszero (float64 d)
581 return (u.ll & ~0x8000000000000000ULL) == 0;
584 static always_inline int isinfinity (float64 d)
590 return ((u.ll >> 52) & 0x7FF) == 0x7FF &&
591 (u.ll & 0x000FFFFFFFFFFFFFULL) == 0;
594 #ifdef CONFIG_SOFTFLOAT
595 static always_inline int isfinite (float64 d)
601 return (((u.ll >> 52) & 0x7FF) != 0x7FF);
604 static always_inline int isnormal (float64 d)
610 uint32_t exp = (u.ll >> 52) & 0x7FF;
611 return ((0 < exp) && (exp < 0x7FF));
615 uint32_t helper_compute_fprf (uint64_t arg, uint32_t set_fprf)
621 isneg = fpisneg(farg.d);
622 if (unlikely(float64_is_nan(farg.d))) {
623 if (float64_is_signaling_nan(farg.d)) {
624 /* Signaling NaN: flags are undefined */
630 } else if (unlikely(isinfinity(farg.d))) {
637 if (iszero(farg.d)) {
645 /* Denormalized numbers */
648 /* Normalized numbers */
659 /* We update FPSCR_FPRF */
660 env->fpscr &= ~(0x1F << FPSCR_FPRF);
661 env->fpscr |= ret << FPSCR_FPRF;
663 /* We just need fpcc to update Rc1 */
667 /* Floating-point invalid operations exception */
668 static always_inline uint64_t fload_invalid_op_excp (int op)
674 if (op & POWERPC_EXCP_FP_VXSNAN) {
675 /* Operation on signaling NaN */
676 env->fpscr |= 1 << FPSCR_VXSNAN;
678 if (op & POWERPC_EXCP_FP_VXSOFT) {
679 /* Software-defined condition */
680 env->fpscr |= 1 << FPSCR_VXSOFT;
682 switch (op & ~(POWERPC_EXCP_FP_VXSOFT | POWERPC_EXCP_FP_VXSNAN)) {
683 case POWERPC_EXCP_FP_VXISI:
684 /* Magnitude subtraction of infinities */
685 env->fpscr |= 1 << FPSCR_VXISI;
687 case POWERPC_EXCP_FP_VXIDI:
688 /* Division of infinity by infinity */
689 env->fpscr |= 1 << FPSCR_VXIDI;
691 case POWERPC_EXCP_FP_VXZDZ:
692 /* Division of zero by zero */
693 env->fpscr |= 1 << FPSCR_VXZDZ;
695 case POWERPC_EXCP_FP_VXIMZ:
696 /* Multiplication of zero by infinity */
697 env->fpscr |= 1 << FPSCR_VXIMZ;
699 case POWERPC_EXCP_FP_VXVC:
700 /* Ordered comparison of NaN */
701 env->fpscr |= 1 << FPSCR_VXVC;
702 env->fpscr &= ~(0xF << FPSCR_FPCC);
703 env->fpscr |= 0x11 << FPSCR_FPCC;
704 /* We must update the target FPR before raising the exception */
706 env->exception_index = POWERPC_EXCP_PROGRAM;
707 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
708 /* Update the floating-point enabled exception summary */
709 env->fpscr |= 1 << FPSCR_FEX;
710 /* Exception is differed */
714 case POWERPC_EXCP_FP_VXSQRT:
715 /* Square root of a negative number */
716 env->fpscr |= 1 << FPSCR_VXSQRT;
718 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
720 /* Set the result to quiet NaN */
722 env->fpscr &= ~(0xF << FPSCR_FPCC);
723 env->fpscr |= 0x11 << FPSCR_FPCC;
726 case POWERPC_EXCP_FP_VXCVI:
727 /* Invalid conversion */
728 env->fpscr |= 1 << FPSCR_VXCVI;
729 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
731 /* Set the result to quiet NaN */
733 env->fpscr &= ~(0xF << FPSCR_FPCC);
734 env->fpscr |= 0x11 << FPSCR_FPCC;
738 /* Update the floating-point invalid operation summary */
739 env->fpscr |= 1 << FPSCR_VX;
740 /* Update the floating-point exception summary */
741 env->fpscr |= 1 << FPSCR_FX;
743 /* Update the floating-point enabled exception summary */
744 env->fpscr |= 1 << FPSCR_FEX;
745 if (msr_fe0 != 0 || msr_fe1 != 0)
746 helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_FP | op);
751 static always_inline uint64_t float_zero_divide_excp (uint64_t arg1, uint64_t arg2)
753 env->fpscr |= 1 << FPSCR_ZX;
754 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
755 /* Update the floating-point exception summary */
756 env->fpscr |= 1 << FPSCR_FX;
758 /* Update the floating-point enabled exception summary */
759 env->fpscr |= 1 << FPSCR_FEX;
760 if (msr_fe0 != 0 || msr_fe1 != 0) {
761 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
762 POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX);
765 /* Set the result to infinity */
766 arg1 = ((arg1 ^ arg2) & 0x8000000000000000ULL);
767 arg1 |= 0x7FFULL << 52;
772 static always_inline void float_overflow_excp (void)
774 env->fpscr |= 1 << FPSCR_OX;
775 /* Update the floating-point exception summary */
776 env->fpscr |= 1 << FPSCR_FX;
778 /* XXX: should adjust the result */
779 /* Update the floating-point enabled exception summary */
780 env->fpscr |= 1 << FPSCR_FEX;
781 /* We must update the target FPR before raising the exception */
782 env->exception_index = POWERPC_EXCP_PROGRAM;
783 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
785 env->fpscr |= 1 << FPSCR_XX;
786 env->fpscr |= 1 << FPSCR_FI;
790 static always_inline void float_underflow_excp (void)
792 env->fpscr |= 1 << FPSCR_UX;
793 /* Update the floating-point exception summary */
794 env->fpscr |= 1 << FPSCR_FX;
796 /* XXX: should adjust the result */
797 /* Update the floating-point enabled exception summary */
798 env->fpscr |= 1 << FPSCR_FEX;
799 /* We must update the target FPR before raising the exception */
800 env->exception_index = POWERPC_EXCP_PROGRAM;
801 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
805 static always_inline void float_inexact_excp (void)
807 env->fpscr |= 1 << FPSCR_XX;
808 /* Update the floating-point exception summary */
809 env->fpscr |= 1 << FPSCR_FX;
811 /* Update the floating-point enabled exception summary */
812 env->fpscr |= 1 << FPSCR_FEX;
813 /* We must update the target FPR before raising the exception */
814 env->exception_index = POWERPC_EXCP_PROGRAM;
815 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
819 static always_inline void fpscr_set_rounding_mode (void)
823 /* Set rounding mode */
826 /* Best approximation (round to nearest) */
827 rnd_type = float_round_nearest_even;
830 /* Smaller magnitude (round toward zero) */
831 rnd_type = float_round_to_zero;
834 /* Round toward +infinite */
835 rnd_type = float_round_up;
839 /* Round toward -infinite */
840 rnd_type = float_round_down;
843 set_float_rounding_mode(rnd_type, &env->fp_status);
846 void helper_fpscr_setbit (uint32_t bit)
850 prev = (env->fpscr >> bit) & 1;
851 env->fpscr |= 1 << bit;
855 env->fpscr |= 1 << FPSCR_FX;
859 env->fpscr |= 1 << FPSCR_FX;
864 env->fpscr |= 1 << FPSCR_FX;
869 env->fpscr |= 1 << FPSCR_FX;
874 env->fpscr |= 1 << FPSCR_FX;
887 env->fpscr |= 1 << FPSCR_VX;
888 env->fpscr |= 1 << FPSCR_FX;
895 env->error_code = POWERPC_EXCP_FP;
897 env->error_code |= POWERPC_EXCP_FP_VXSNAN;
899 env->error_code |= POWERPC_EXCP_FP_VXISI;
901 env->error_code |= POWERPC_EXCP_FP_VXIDI;
903 env->error_code |= POWERPC_EXCP_FP_VXZDZ;
905 env->error_code |= POWERPC_EXCP_FP_VXIMZ;
907 env->error_code |= POWERPC_EXCP_FP_VXVC;
909 env->error_code |= POWERPC_EXCP_FP_VXSOFT;
911 env->error_code |= POWERPC_EXCP_FP_VXSQRT;
913 env->error_code |= POWERPC_EXCP_FP_VXCVI;
920 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
927 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
934 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX;
941 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
947 fpscr_set_rounding_mode();
952 /* Update the floating-point enabled exception summary */
953 env->fpscr |= 1 << FPSCR_FEX;
954 /* We have to update Rc1 before raising the exception */
955 env->exception_index = POWERPC_EXCP_PROGRAM;
961 void helper_store_fpscr (uint64_t arg, uint32_t mask)
964 * We use only the 32 LSB of the incoming fpr
972 new |= prev & 0x90000000;
973 for (i = 0; i < 7; i++) {
974 if (mask & (1 << i)) {
975 env->fpscr &= ~(0xF << (4 * i));
976 env->fpscr |= new & (0xF << (4 * i));
979 /* Update VX and FEX */
981 env->fpscr |= 1 << FPSCR_VX;
983 env->fpscr &= ~(1 << FPSCR_VX);
984 if ((fpscr_ex & fpscr_eex) != 0) {
985 env->fpscr |= 1 << FPSCR_FEX;
986 env->exception_index = POWERPC_EXCP_PROGRAM;
987 /* XXX: we should compute it properly */
988 env->error_code = POWERPC_EXCP_FP;
991 env->fpscr &= ~(1 << FPSCR_FEX);
992 fpscr_set_rounding_mode();
995 void helper_float_check_status (void)
997 #ifdef CONFIG_SOFTFLOAT
998 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
999 (env->error_code & POWERPC_EXCP_FP)) {
1000 /* Differred floating-point exception after target FPR update */
1001 if (msr_fe0 != 0 || msr_fe1 != 0)
1002 helper_raise_exception_err(env->exception_index, env->error_code);
1003 } else if (env->fp_status.float_exception_flags & float_flag_overflow) {
1004 float_overflow_excp();
1005 } else if (env->fp_status.float_exception_flags & float_flag_underflow) {
1006 float_underflow_excp();
1007 } else if (env->fp_status.float_exception_flags & float_flag_inexact) {
1008 float_inexact_excp();
1011 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
1012 (env->error_code & POWERPC_EXCP_FP)) {
1013 /* Differred floating-point exception after target FPR update */
1014 if (msr_fe0 != 0 || msr_fe1 != 0)
1015 helper_raise_exception_err(env->exception_index, env->error_code);
1020 #ifdef CONFIG_SOFTFLOAT
1021 void helper_reset_fpstatus (void)
1023 env->fp_status.float_exception_flags = 0;
1028 uint64_t helper_fadd (uint64_t arg1, uint64_t arg2)
1030 CPU_DoubleU farg1, farg2;
1034 #if USE_PRECISE_EMULATION
1035 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1036 float64_is_signaling_nan(farg2.d))) {
1038 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1039 } else if (likely(isfinite(farg1.d) || isfinite(farg2.d) ||
1040 fpisneg(farg1.d) == fpisneg(farg2.d))) {
1041 farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
1043 /* Magnitude subtraction of infinities */
1044 farg1.ll == fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
1047 farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
1053 uint64_t helper_fsub (uint64_t arg1, uint64_t arg2)
1055 CPU_DoubleU farg1, farg2;
1059 #if USE_PRECISE_EMULATION
1061 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1062 float64_is_signaling_nan(farg2.d))) {
1063 /* sNaN subtraction */
1064 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1065 } else if (likely(isfinite(farg1.d) || isfinite(farg2.d) ||
1066 fpisneg(farg1.d) != fpisneg(farg2.d))) {
1067 farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
1069 /* Magnitude subtraction of infinities */
1070 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
1074 farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
1080 uint64_t helper_fmul (uint64_t arg1, uint64_t arg2)
1082 CPU_DoubleU farg1, farg2;
1086 #if USE_PRECISE_EMULATION
1087 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1088 float64_is_signaling_nan(farg2.d))) {
1089 /* sNaN multiplication */
1090 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1091 } else if (unlikely((isinfinity(farg1.d) && iszero(farg2.d)) ||
1092 (iszero(farg1.d) && isinfinity(farg2.d)))) {
1093 /* Multiplication of zero by infinity */
1094 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
1096 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1100 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1106 uint64_t helper_fdiv (uint64_t arg1, uint64_t arg2)
1108 CPU_DoubleU farg1, farg2;
1112 #if USE_PRECISE_EMULATION
1113 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1114 float64_is_signaling_nan(farg2.d))) {
1116 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1117 } else if (unlikely(isinfinity(farg1.d) && isinfinity(farg2.d))) {
1118 /* Division of infinity by infinity */
1119 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIDI);
1120 } else if (unlikely(iszero(farg2.d))) {
1121 if (iszero(farg1.d)) {
1122 /* Division of zero by zero */
1123 farg1.ll fload_invalid_op_excp(POWERPC_EXCP_FP_VXZDZ);
1125 /* Division by zero */
1126 farg1.ll = float_zero_divide_excp(farg1.d, farg2.d);
1129 farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
1132 farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
1138 uint64_t helper_fabs (uint64_t arg)
1143 farg.d = float64_abs(farg.d);
1148 uint64_t helper_fnabs (uint64_t arg)
1153 farg.d = float64_abs(farg.d);
1154 farg.d = float64_chs(farg.d);
1159 uint64_t helper_fneg (uint64_t arg)
1164 farg.d = float64_chs(farg.d);
1168 /* fctiw - fctiw. */
1169 uint64_t helper_fctiw (uint64_t arg)
1174 if (unlikely(float64_is_signaling_nan(farg.d))) {
1175 /* sNaN conversion */
1176 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1177 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
1178 /* qNan / infinity conversion */
1179 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1181 farg.ll = float64_to_int32(farg.d, &env->fp_status);
1182 #if USE_PRECISE_EMULATION
1183 /* XXX: higher bits are not supposed to be significant.
1184 * to make tests easier, return the same as a real PowerPC 750
1186 farg.ll |= 0xFFF80000ULL << 32;
1192 /* fctiwz - fctiwz. */
1193 uint64_t helper_fctiwz (uint64_t arg)
1198 if (unlikely(float64_is_signaling_nan(farg.d))) {
1199 /* sNaN conversion */
1200 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1201 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
1202 /* qNan / infinity conversion */
1203 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1205 farg.ll = float64_to_int32_round_to_zero(farg.d, &env->fp_status);
1206 #if USE_PRECISE_EMULATION
1207 /* XXX: higher bits are not supposed to be significant.
1208 * to make tests easier, return the same as a real PowerPC 750
1210 farg.ll |= 0xFFF80000ULL << 32;
1216 #if defined(TARGET_PPC64)
1217 /* fcfid - fcfid. */
1218 uint64_t helper_fcfid (uint64_t arg)
1221 farg.d = int64_to_float64(arg, &env->fp_status);
1225 /* fctid - fctid. */
1226 uint64_t helper_fctid (uint64_t arg)
1231 if (unlikely(float64_is_signaling_nan(farg.d))) {
1232 /* sNaN conversion */
1233 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1234 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
1235 /* qNan / infinity conversion */
1236 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1238 farg.ll = float64_to_int64(farg.d, &env->fp_status);
1243 /* fctidz - fctidz. */
1244 uint64_t helper_fctidz (uint64_t arg)
1249 if (unlikely(float64_is_signaling_nan(farg.d))) {
1250 /* sNaN conversion */
1251 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1252 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
1253 /* qNan / infinity conversion */
1254 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1256 farg.ll = float64_to_int64_round_to_zero(farg.d, &env->fp_status);
1263 static always_inline uint64_t do_fri (uint64_t arg, int rounding_mode)
1268 if (unlikely(float64_is_signaling_nan(farg.d))) {
1270 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1271 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
1272 /* qNan / infinity round */
1273 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1275 set_float_rounding_mode(rounding_mode, &env->fp_status);
1276 farg.ll = float64_round_to_int(farg.d, &env->fp_status);
1277 /* Restore rounding mode from FPSCR */
1278 fpscr_set_rounding_mode();
1283 uint64_t helper_frin (uint64_t arg)
1285 return do_fri(arg, float_round_nearest_even);
1288 uint64_t helper_friz (uint64_t arg)
1290 return do_fri(arg, float_round_to_zero);
1293 uint64_t helper_frip (uint64_t arg)
1295 return do_fri(arg, float_round_up);
1298 uint64_t helper_frim (uint64_t arg)
1300 return do_fri(arg, float_round_down);
1303 /* fmadd - fmadd. */
1304 uint64_t helper_fmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1306 CPU_DoubleU farg1, farg2, farg3;
1311 #if USE_PRECISE_EMULATION
1312 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1313 float64_is_signaling_nan(farg2.d) ||
1314 float64_is_signaling_nan(farg3.d))) {
1315 /* sNaN operation */
1316 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1319 /* This is the way the PowerPC specification defines it */
1320 float128 ft0_128, ft1_128;
1322 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1323 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1324 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1325 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1326 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1327 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1329 /* This is OK on x86 hosts */
1330 farg1.d = (farg1.d * farg2.d) + farg3.d;
1334 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1335 farg1.d = float64_add(farg1.d, farg3.d, &env->fp_status);
1340 /* fmsub - fmsub. */
1341 uint64_t helper_fmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1343 CPU_DoubleU farg1, farg2, farg3;
1348 #if USE_PRECISE_EMULATION
1349 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1350 float64_is_signaling_nan(farg2.d) ||
1351 float64_is_signaling_nan(farg3.d))) {
1352 /* sNaN operation */
1353 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1356 /* This is the way the PowerPC specification defines it */
1357 float128 ft0_128, ft1_128;
1359 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1360 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1361 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1362 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1363 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1364 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1366 /* This is OK on x86 hosts */
1367 farg1.d = (farg1.d * farg2.d) - farg3.d;
1371 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1372 farg1.d = float64_sub(farg1.d, farg3.d, &env->fp_status);
1377 /* fnmadd - fnmadd. */
1378 uint64_t helper_fnmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1380 CPU_DoubleU farg1, farg2, farg3;
1386 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1387 float64_is_signaling_nan(farg2.d) ||
1388 float64_is_signaling_nan(farg3.d))) {
1389 /* sNaN operation */
1390 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1392 #if USE_PRECISE_EMULATION
1394 /* This is the way the PowerPC specification defines it */
1395 float128 ft0_128, ft1_128;
1397 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1398 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1399 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1400 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1401 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1402 farg1.d= float128_to_float64(ft0_128, &env->fp_status);
1404 /* This is OK on x86 hosts */
1405 farg1.d = (farg1.d * farg2.d) + farg3.d;
1408 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1409 farg1.d = float64_add(farg1.d, farg3.d, &env->fp_status);
1411 if (likely(!isnan(farg1.d)))
1412 farg1.d = float64_chs(farg1.d);
1417 /* fnmsub - fnmsub. */
1418 uint64_t helper_fnmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1420 CPU_DoubleU farg1, farg2, farg3;
1426 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1427 float64_is_signaling_nan(farg2.d) ||
1428 float64_is_signaling_nan(farg3.d))) {
1429 /* sNaN operation */
1430 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1432 #if USE_PRECISE_EMULATION
1434 /* This is the way the PowerPC specification defines it */
1435 float128 ft0_128, ft1_128;
1437 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1438 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1439 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1440 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1441 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1442 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1444 /* This is OK on x86 hosts */
1445 farg1.d = (farg1.d * farg2.d) - farg3.d;
1448 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1449 farg1.d = float64_sub(farg1.d, farg3.d, &env->fp_status);
1451 if (likely(!isnan(farg1.d)))
1452 farg1.d = float64_chs(farg1.d);
1458 uint64_t helper_frsp (uint64_t arg)
1463 #if USE_PRECISE_EMULATION
1464 if (unlikely(float64_is_signaling_nan(farg.d))) {
1465 /* sNaN square root */
1466 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1468 fard.d = float64_to_float32(farg.d, &env->fp_status);
1471 farg.d = float64_to_float32(farg.d, &env->fp_status);
1476 /* fsqrt - fsqrt. */
1477 uint64_t helper_fsqrt (uint64_t arg)
1482 if (unlikely(float64_is_signaling_nan(farg.d))) {
1483 /* sNaN square root */
1484 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1485 } else if (unlikely(fpisneg(farg.d) && !iszero(farg.d))) {
1486 /* Square root of a negative nonzero number */
1487 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1489 farg.d = float64_sqrt(farg.d, &env->fp_status);
1495 uint64_t helper_fre (uint64_t arg)
1500 if (unlikely(float64_is_signaling_nan(farg.d))) {
1501 /* sNaN reciprocal */
1502 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1503 } else if (unlikely(iszero(farg.d))) {
1504 /* Zero reciprocal */
1505 farg.ll = float_zero_divide_excp(1.0, farg.d);
1506 } else if (likely(isnormal(farg.d))) {
1507 farg.d = float64_div(1.0, farg.d, &env->fp_status);
1509 if (farg.ll == 0x8000000000000000ULL) {
1510 farg.ll = 0xFFF0000000000000ULL;
1511 } else if (farg.ll == 0x0000000000000000ULL) {
1512 farg.ll = 0x7FF0000000000000ULL;
1513 } else if (isnan(farg.d)) {
1514 farg.ll = 0x7FF8000000000000ULL;
1515 } else if (fpisneg(farg.d)) {
1516 farg.ll = 0x8000000000000000ULL;
1518 farg.ll = 0x0000000000000000ULL;
1525 uint64_t helper_fres (uint64_t arg)
1530 if (unlikely(float64_is_signaling_nan(farg.d))) {
1531 /* sNaN reciprocal */
1532 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1533 } else if (unlikely(iszero(farg.d))) {
1534 /* Zero reciprocal */
1535 farg.ll = float_zero_divide_excp(1.0, farg.d);
1536 } else if (likely(isnormal(farg.d))) {
1537 #if USE_PRECISE_EMULATION
1538 farg.d = float64_div(1.0, farg.d, &env->fp_status);
1539 farg.d = float64_to_float32(farg.d, &env->fp_status);
1541 farg.d = float32_div(1.0, farg.d, &env->fp_status);
1544 if (farg.ll == 0x8000000000000000ULL) {
1545 farg.ll = 0xFFF0000000000000ULL;
1546 } else if (farg.ll == 0x0000000000000000ULL) {
1547 farg.ll = 0x7FF0000000000000ULL;
1548 } else if (isnan(farg.d)) {
1549 farg.ll = 0x7FF8000000000000ULL;
1550 } else if (fpisneg(farg.d)) {
1551 farg.ll = 0x8000000000000000ULL;
1553 farg.ll = 0x0000000000000000ULL;
1559 /* frsqrte - frsqrte. */
1560 uint64_t helper_frsqrte (uint64_t arg)
1565 if (unlikely(float64_is_signaling_nan(farg.d))) {
1566 /* sNaN reciprocal square root */
1567 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1568 } else if (unlikely(fpisneg(farg.d) && !iszero(farg.d))) {
1569 /* Reciprocal square root of a negative nonzero number */
1570 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1571 } else if (likely(isnormal(farg.d))) {
1572 farg.d = float64_sqrt(farg.d, &env->fp_status);
1573 farg.d = float32_div(1.0, farg.d, &env->fp_status);
1575 if (farg.ll == 0x8000000000000000ULL) {
1576 farg.ll = 0xFFF0000000000000ULL;
1577 } else if (farg.ll == 0x0000000000000000ULL) {
1578 farg.ll = 0x7FF0000000000000ULL;
1579 } else if (isnan(farg.d)) {
1580 farg.ll |= 0x000FFFFFFFFFFFFFULL;
1581 } else if (fpisneg(farg.d)) {
1582 farg.ll = 0x7FF8000000000000ULL;
1584 farg.ll = 0x0000000000000000ULL;
1591 uint64_t helper_fsel (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1593 CPU_DoubleU farg1, farg2, farg3;
1599 if (!fpisneg(farg1.d) || iszero(farg1.d))
1605 uint32_t helper_fcmpu (uint64_t arg1, uint64_t arg2)
1607 CPU_DoubleU farg1, farg2;
1612 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1613 float64_is_signaling_nan(farg2.d))) {
1614 /* sNaN comparison */
1615 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1617 if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1619 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1625 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1626 env->fpscr |= ret << FPSCR_FPRF;
1630 uint32_t helper_fcmpo (uint64_t arg1, uint64_t arg2)
1632 CPU_DoubleU farg1, farg2;
1637 if (unlikely(float64_is_nan(farg1.d) ||
1638 float64_is_nan(farg2.d))) {
1639 if (float64_is_signaling_nan(farg1.d) ||
1640 float64_is_signaling_nan(farg2.d)) {
1641 /* sNaN comparison */
1642 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN |
1643 POWERPC_EXCP_FP_VXVC);
1645 /* qNaN comparison */
1646 fload_invalid_op_excp(POWERPC_EXCP_FP_VXVC);
1649 if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1651 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1657 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1658 env->fpscr |= ret << FPSCR_FPRF;
1662 #if !defined (CONFIG_USER_ONLY)
1663 void helper_store_msr (target_ulong val)
1665 val = hreg_store_msr(env, val, 0);
1667 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1668 helper_raise_exception(val);
1672 static always_inline void do_rfi (target_ulong nip, target_ulong msr,
1673 target_ulong msrm, int keep_msrh)
1675 #if defined(TARGET_PPC64)
1676 if (msr & (1ULL << MSR_SF)) {
1677 nip = (uint64_t)nip;
1678 msr &= (uint64_t)msrm;
1680 nip = (uint32_t)nip;
1681 msr = (uint32_t)(msr & msrm);
1683 msr |= env->msr & ~((uint64_t)0xFFFFFFFF);
1686 nip = (uint32_t)nip;
1687 msr &= (uint32_t)msrm;
1689 /* XXX: beware: this is false if VLE is supported */
1690 env->nip = nip & ~((target_ulong)0x00000003);
1691 hreg_store_msr(env, msr, 1);
1692 #if defined (DEBUG_OP)
1693 cpu_dump_rfi(env->nip, env->msr);
1695 /* No need to raise an exception here,
1696 * as rfi is always the last insn of a TB
1698 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1701 void helper_rfi (void)
1703 do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1704 ~((target_ulong)0xFFFF0000), 1);
1707 #if defined(TARGET_PPC64)
1708 void helper_rfid (void)
1710 do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1711 ~((target_ulong)0xFFFF0000), 0);
1714 void helper_hrfid (void)
1716 do_rfi(env->spr[SPR_HSRR0], env->spr[SPR_HSRR1],
1717 ~((target_ulong)0xFFFF0000), 0);
1722 void helper_tw (target_ulong arg1, target_ulong arg2, uint32_t flags)
1724 if (!likely(!(((int32_t)arg1 < (int32_t)arg2 && (flags & 0x10)) ||
1725 ((int32_t)arg1 > (int32_t)arg2 && (flags & 0x08)) ||
1726 ((int32_t)arg1 == (int32_t)arg2 && (flags & 0x04)) ||
1727 ((uint32_t)arg1 < (uint32_t)arg2 && (flags & 0x02)) ||
1728 ((uint32_t)arg1 > (uint32_t)arg2 && (flags & 0x01))))) {
1729 helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1733 #if defined(TARGET_PPC64)
1734 void helper_td (target_ulong arg1, target_ulong arg2, uint32_t flags)
1736 if (!likely(!(((int64_t)arg1 < (int64_t)arg2 && (flags & 0x10)) ||
1737 ((int64_t)arg1 > (int64_t)arg2 && (flags & 0x08)) ||
1738 ((int64_t)arg1 == (int64_t)arg2 && (flags & 0x04)) ||
1739 ((uint64_t)arg1 < (uint64_t)arg2 && (flags & 0x02)) ||
1740 ((uint64_t)arg1 > (uint64_t)arg2 && (flags & 0x01)))))
1741 helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1745 /*****************************************************************************/
1746 /* PowerPC 601 specific instructions (POWER bridge) */
1748 target_ulong helper_clcs (uint32_t arg)
1752 /* Instruction cache line size */
1753 return env->icache_line_size;
1756 /* Data cache line size */
1757 return env->dcache_line_size;
1760 /* Minimum cache line size */
1761 return (env->icache_line_size < env->dcache_line_size) ?
1762 env->icache_line_size : env->dcache_line_size;
1765 /* Maximum cache line size */
1766 return (env->icache_line_size > env->dcache_line_size) ?
1767 env->icache_line_size : env->dcache_line_size;
1776 target_ulong helper_div (target_ulong arg1, target_ulong arg2)
1778 uint64_t tmp = (uint64_t)arg1 << 32 | env->spr[SPR_MQ];
1780 if (((int32_t)tmp == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1781 (int32_t)arg2 == 0) {
1782 env->spr[SPR_MQ] = 0;
1785 env->spr[SPR_MQ] = tmp % arg2;
1786 return tmp / (int32_t)arg2;
1790 target_ulong helper_divo (target_ulong arg1, target_ulong arg2)
1792 uint64_t tmp = (uint64_t)arg1 << 32 | env->spr[SPR_MQ];
1794 if (((int32_t)tmp == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1795 (int32_t)arg2 == 0) {
1796 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1797 env->spr[SPR_MQ] = 0;
1800 env->spr[SPR_MQ] = tmp % arg2;
1801 tmp /= (int32_t)arg2;
1802 if ((int32_t)tmp != tmp) {
1803 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1805 env->xer &= ~(1 << XER_OV);
1811 target_ulong helper_divs (target_ulong arg1, target_ulong arg2)
1813 if (((int32_t)arg1 == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1814 (int32_t)arg2 == 0) {
1815 env->spr[SPR_MQ] = 0;
1818 env->spr[SPR_MQ] = (int32_t)arg1 % (int32_t)arg2;
1819 return (int32_t)arg1 / (int32_t)arg2;
1823 target_ulong helper_divso (target_ulong arg1, target_ulong arg2)
1825 if (((int32_t)arg1 == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1826 (int32_t)arg2 == 0) {
1827 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1828 env->spr[SPR_MQ] = 0;
1831 env->xer &= ~(1 << XER_OV);
1832 env->spr[SPR_MQ] = (int32_t)arg1 % (int32_t)arg2;
1833 return (int32_t)arg1 / (int32_t)arg2;
1837 #if !defined (CONFIG_USER_ONLY)
1838 target_ulong helper_rac (target_ulong addr)
1842 target_ulong ret = 0;
1844 /* We don't have to generate many instances of this instruction,
1845 * as rac is supervisor only.
1847 /* XXX: FIX THIS: Pretend we have no BAT */
1848 nb_BATs = env->nb_BATs;
1850 if (get_physical_address(env, &ctx, addr, 0, ACCESS_INT) == 0)
1852 env->nb_BATs = nb_BATs;
1856 void helper_rfsvc (void)
1858 do_rfi(env->lr, env->ctr, 0x0000FFFF, 0);
1862 /*****************************************************************************/
1863 /* 602 specific instructions */
1864 /* mfrom is the most crazy instruction ever seen, imho ! */
1865 /* Real implementation uses a ROM table. Do the same */
1866 #if !defined (CONFIG_USER_ONLY)
1867 #define USE_MFROM_ROM_TABLE
1868 target_ulong helper_602_mfrom (target_ulong arg)
1870 if (likely(arg < 602)) {
1871 #if defined(USE_MFROM_ROM_TABLE)
1872 #include "mfrom_table.c"
1873 return mfrom_ROM_table[arg];
1876 /* Extremly decomposed:
1878 * return 256 * log10(10 + 1.0) + 0.5
1881 d = float64_div(d, 256, &env->fp_status);
1883 d = exp10(d); // XXX: use float emulation function
1884 d = float64_add(d, 1.0, &env->fp_status);
1885 d = log10(d); // XXX: use float emulation function
1886 d = float64_mul(d, 256, &env->fp_status);
1887 d = float64_add(d, 0.5, &env->fp_status);
1888 return float64_round_to_int(d, &env->fp_status);
1896 /*****************************************************************************/
1897 /* Embedded PowerPC specific helpers */
1899 /* XXX: to be improved to check access rights when in user-mode */
1900 target_ulong helper_load_dcr (target_ulong dcrn)
1902 target_ulong val = 0;
1904 if (unlikely(env->dcr_env == NULL)) {
1905 if (loglevel != 0) {
1906 fprintf(logfile, "No DCR environment\n");
1908 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1909 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
1910 } else if (unlikely(ppc_dcr_read(env->dcr_env, dcrn, &val) != 0)) {
1911 if (loglevel != 0) {
1912 fprintf(logfile, "DCR read error %d %03x\n", (int)dcrn, (int)dcrn);
1914 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1915 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
1920 void helper_store_dcr (target_ulong dcrn, target_ulong val)
1922 if (unlikely(env->dcr_env == NULL)) {
1923 if (loglevel != 0) {
1924 fprintf(logfile, "No DCR environment\n");
1926 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1927 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
1928 } else if (unlikely(ppc_dcr_write(env->dcr_env, dcrn, val) != 0)) {
1929 if (loglevel != 0) {
1930 fprintf(logfile, "DCR write error %d %03x\n", (int)dcrn, (int)dcrn);
1932 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1933 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
1937 #if !defined(CONFIG_USER_ONLY)
1938 void helper_40x_rfci (void)
1940 do_rfi(env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3],
1941 ~((target_ulong)0xFFFF0000), 0);
1944 void helper_rfci (void)
1946 do_rfi(env->spr[SPR_BOOKE_CSRR0], SPR_BOOKE_CSRR1,
1947 ~((target_ulong)0x3FFF0000), 0);
1950 void helper_rfdi (void)
1952 do_rfi(env->spr[SPR_BOOKE_DSRR0], SPR_BOOKE_DSRR1,
1953 ~((target_ulong)0x3FFF0000), 0);
1956 void helper_rfmci (void)
1958 do_rfi(env->spr[SPR_BOOKE_MCSRR0], SPR_BOOKE_MCSRR1,
1959 ~((target_ulong)0x3FFF0000), 0);
1964 target_ulong helper_dlmzb (target_ulong high, target_ulong low, uint32_t update_Rc)
1970 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1971 if ((high & mask) == 0) {
1979 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1980 if ((low & mask) == 0) {
1992 env->xer = (env->xer & ~0x7F) | i;
1994 env->crf[0] |= xer_so;
1999 /*****************************************************************************/
2000 /* SPE extension helpers */
2001 /* Use a table to make this quicker */
2002 static uint8_t hbrev[16] = {
2003 0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE,
2004 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF,
2007 static always_inline uint8_t byte_reverse (uint8_t val)
2009 return hbrev[val >> 4] | (hbrev[val & 0xF] << 4);
2012 static always_inline uint32_t word_reverse (uint32_t val)
2014 return byte_reverse(val >> 24) | (byte_reverse(val >> 16) << 8) |
2015 (byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24);
2018 #define MASKBITS 16 // Random value - to be fixed (implementation dependant)
2019 target_ulong helper_brinc (target_ulong arg1, target_ulong arg2)
2021 uint32_t a, b, d, mask;
2023 mask = UINT32_MAX >> (32 - MASKBITS);
2026 d = word_reverse(1 + word_reverse(a | ~b));
2027 return (arg1 & ~mask) | (d & b);
2030 uint32_t helper_cntlsw32 (uint32_t val)
2032 if (val & 0x80000000)
2038 uint32_t helper_cntlzw32 (uint32_t val)
2043 /* Single-precision floating-point conversions */
2044 static always_inline uint32_t efscfsi (uint32_t val)
2048 u.f = int32_to_float32(val, &env->spe_status);
2053 static always_inline uint32_t efscfui (uint32_t val)
2057 u.f = uint32_to_float32(val, &env->spe_status);
2062 static always_inline int32_t efsctsi (uint32_t val)
2067 /* NaN are not treated the same way IEEE 754 does */
2068 if (unlikely(isnan(u.f)))
2071 return float32_to_int32(u.f, &env->spe_status);
2074 static always_inline uint32_t efsctui (uint32_t val)
2079 /* NaN are not treated the same way IEEE 754 does */
2080 if (unlikely(isnan(u.f)))
2083 return float32_to_uint32(u.f, &env->spe_status);
2086 static always_inline uint32_t efsctsiz (uint32_t val)
2091 /* NaN are not treated the same way IEEE 754 does */
2092 if (unlikely(isnan(u.f)))
2095 return float32_to_int32_round_to_zero(u.f, &env->spe_status);
2098 static always_inline uint32_t efsctuiz (uint32_t val)
2103 /* NaN are not treated the same way IEEE 754 does */
2104 if (unlikely(isnan(u.f)))
2107 return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
2110 static always_inline uint32_t efscfsf (uint32_t val)
2115 u.f = int32_to_float32(val, &env->spe_status);
2116 tmp = int64_to_float32(1ULL << 32, &env->spe_status);
2117 u.f = float32_div(u.f, tmp, &env->spe_status);
2122 static always_inline uint32_t efscfuf (uint32_t val)
2127 u.f = uint32_to_float32(val, &env->spe_status);
2128 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2129 u.f = float32_div(u.f, tmp, &env->spe_status);
2134 static always_inline uint32_t efsctsf (uint32_t val)
2140 /* NaN are not treated the same way IEEE 754 does */
2141 if (unlikely(isnan(u.f)))
2143 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2144 u.f = float32_mul(u.f, tmp, &env->spe_status);
2146 return float32_to_int32(u.f, &env->spe_status);
2149 static always_inline uint32_t efsctuf (uint32_t val)
2155 /* NaN are not treated the same way IEEE 754 does */
2156 if (unlikely(isnan(u.f)))
2158 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2159 u.f = float32_mul(u.f, tmp, &env->spe_status);
2161 return float32_to_uint32(u.f, &env->spe_status);
2164 #define HELPER_SPE_SINGLE_CONV(name) \
2165 uint32_t helper_e##name (uint32_t val) \
2167 return e##name(val); \
2170 HELPER_SPE_SINGLE_CONV(fscfsi);
2172 HELPER_SPE_SINGLE_CONV(fscfui);
2174 HELPER_SPE_SINGLE_CONV(fscfuf);
2176 HELPER_SPE_SINGLE_CONV(fscfsf);
2178 HELPER_SPE_SINGLE_CONV(fsctsi);
2180 HELPER_SPE_SINGLE_CONV(fsctui);
2182 HELPER_SPE_SINGLE_CONV(fsctsiz);
2184 HELPER_SPE_SINGLE_CONV(fsctuiz);
2186 HELPER_SPE_SINGLE_CONV(fsctsf);
2188 HELPER_SPE_SINGLE_CONV(fsctuf);
2190 #define HELPER_SPE_VECTOR_CONV(name) \
2191 uint64_t helper_ev##name (uint64_t val) \
2193 return ((uint64_t)e##name(val >> 32) << 32) | \
2194 (uint64_t)e##name(val); \
2197 HELPER_SPE_VECTOR_CONV(fscfsi);
2199 HELPER_SPE_VECTOR_CONV(fscfui);
2201 HELPER_SPE_VECTOR_CONV(fscfuf);
2203 HELPER_SPE_VECTOR_CONV(fscfsf);
2205 HELPER_SPE_VECTOR_CONV(fsctsi);
2207 HELPER_SPE_VECTOR_CONV(fsctui);
2209 HELPER_SPE_VECTOR_CONV(fsctsiz);
2211 HELPER_SPE_VECTOR_CONV(fsctuiz);
2213 HELPER_SPE_VECTOR_CONV(fsctsf);
2215 HELPER_SPE_VECTOR_CONV(fsctuf);
2217 /* Single-precision floating-point arithmetic */
2218 static always_inline uint32_t efsadd (uint32_t op1, uint32_t op2)
2223 u1.f = float32_add(u1.f, u2.f, &env->spe_status);
2227 static always_inline uint32_t efssub (uint32_t op1, uint32_t op2)
2232 u1.f = float32_sub(u1.f, u2.f, &env->spe_status);
2236 static always_inline uint32_t efsmul (uint32_t op1, uint32_t op2)
2241 u1.f = float32_mul(u1.f, u2.f, &env->spe_status);
2245 static always_inline uint32_t efsdiv (uint32_t op1, uint32_t op2)
2250 u1.f = float32_div(u1.f, u2.f, &env->spe_status);
2254 #define HELPER_SPE_SINGLE_ARITH(name) \
2255 uint32_t helper_e##name (uint32_t op1, uint32_t op2) \
2257 return e##name(op1, op2); \
2260 HELPER_SPE_SINGLE_ARITH(fsadd);
2262 HELPER_SPE_SINGLE_ARITH(fssub);
2264 HELPER_SPE_SINGLE_ARITH(fsmul);
2266 HELPER_SPE_SINGLE_ARITH(fsdiv);
2268 #define HELPER_SPE_VECTOR_ARITH(name) \
2269 uint64_t helper_ev##name (uint64_t op1, uint64_t op2) \
2271 return ((uint64_t)e##name(op1 >> 32, op2 >> 32) << 32) | \
2272 (uint64_t)e##name(op1, op2); \
2275 HELPER_SPE_VECTOR_ARITH(fsadd);
2277 HELPER_SPE_VECTOR_ARITH(fssub);
2279 HELPER_SPE_VECTOR_ARITH(fsmul);
2281 HELPER_SPE_VECTOR_ARITH(fsdiv);
2283 /* Single-precision floating-point comparisons */
2284 static always_inline uint32_t efststlt (uint32_t op1, uint32_t op2)
2289 return float32_lt(u1.f, u2.f, &env->spe_status) ? 4 : 0;
2292 static always_inline uint32_t efststgt (uint32_t op1, uint32_t op2)
2297 return float32_le(u1.f, u2.f, &env->spe_status) ? 0 : 4;
2300 static always_inline uint32_t efststeq (uint32_t op1, uint32_t op2)
2305 return float32_eq(u1.f, u2.f, &env->spe_status) ? 4 : 0;
2308 static always_inline uint32_t efscmplt (uint32_t op1, uint32_t op2)
2310 /* XXX: TODO: test special values (NaN, infinites, ...) */
2311 return efststlt(op1, op2);
2314 static always_inline uint32_t efscmpgt (uint32_t op1, uint32_t op2)
2316 /* XXX: TODO: test special values (NaN, infinites, ...) */
2317 return efststgt(op1, op2);
2320 static always_inline uint32_t efscmpeq (uint32_t op1, uint32_t op2)
2322 /* XXX: TODO: test special values (NaN, infinites, ...) */
2323 return efststeq(op1, op2);
2326 #define HELPER_SINGLE_SPE_CMP(name) \
2327 uint32_t helper_e##name (uint32_t op1, uint32_t op2) \
2329 return e##name(op1, op2) << 2; \
2332 HELPER_SINGLE_SPE_CMP(fststlt);
2334 HELPER_SINGLE_SPE_CMP(fststgt);
2336 HELPER_SINGLE_SPE_CMP(fststeq);
2338 HELPER_SINGLE_SPE_CMP(fscmplt);
2340 HELPER_SINGLE_SPE_CMP(fscmpgt);
2342 HELPER_SINGLE_SPE_CMP(fscmpeq);
2344 static always_inline uint32_t evcmp_merge (int t0, int t1)
2346 return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
2349 #define HELPER_VECTOR_SPE_CMP(name) \
2350 uint32_t helper_ev##name (uint64_t op1, uint64_t op2) \
2352 return evcmp_merge(e##name(op1 >> 32, op2 >> 32), e##name(op1, op2)); \
2355 HELPER_VECTOR_SPE_CMP(fststlt);
2357 HELPER_VECTOR_SPE_CMP(fststgt);
2359 HELPER_VECTOR_SPE_CMP(fststeq);
2361 HELPER_VECTOR_SPE_CMP(fscmplt);
2363 HELPER_VECTOR_SPE_CMP(fscmpgt);
2365 HELPER_VECTOR_SPE_CMP(fscmpeq);
2367 /* Double-precision floating-point conversion */
2368 uint64_t helper_efdcfsi (uint32_t val)
2372 u.d = int32_to_float64(val, &env->spe_status);
2377 uint64_t helper_efdcfsid (uint64_t val)
2381 u.d = int64_to_float64(val, &env->spe_status);
2386 uint64_t helper_efdcfui (uint32_t val)
2390 u.d = uint32_to_float64(val, &env->spe_status);
2395 uint64_t helper_efdcfuid (uint64_t val)
2399 u.d = uint64_to_float64(val, &env->spe_status);
2404 uint32_t helper_efdctsi (uint64_t val)
2409 /* NaN are not treated the same way IEEE 754 does */
2410 if (unlikely(isnan(u.d)))
2413 return float64_to_int32(u.d, &env->spe_status);
2416 uint32_t helper_efdctui (uint64_t val)
2421 /* NaN are not treated the same way IEEE 754 does */
2422 if (unlikely(isnan(u.d)))
2425 return float64_to_uint32(u.d, &env->spe_status);
2428 uint32_t helper_efdctsiz (uint64_t val)
2433 /* NaN are not treated the same way IEEE 754 does */
2434 if (unlikely(isnan(u.d)))
2437 return float64_to_int32_round_to_zero(u.d, &env->spe_status);
2440 uint64_t helper_efdctsidz (uint64_t val)
2445 /* NaN are not treated the same way IEEE 754 does */
2446 if (unlikely(isnan(u.d)))
2449 return float64_to_int64_round_to_zero(u.d, &env->spe_status);
2452 uint32_t helper_efdctuiz (uint64_t val)
2457 /* NaN are not treated the same way IEEE 754 does */
2458 if (unlikely(isnan(u.d)))
2461 return float64_to_uint32_round_to_zero(u.d, &env->spe_status);
2464 uint64_t helper_efdctuidz (uint64_t val)
2469 /* NaN are not treated the same way IEEE 754 does */
2470 if (unlikely(isnan(u.d)))
2473 return float64_to_uint64_round_to_zero(u.d, &env->spe_status);
2476 uint64_t helper_efdcfsf (uint32_t val)
2481 u.d = int32_to_float64(val, &env->spe_status);
2482 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
2483 u.d = float64_div(u.d, tmp, &env->spe_status);
2488 uint64_t helper_efdcfuf (uint32_t val)
2493 u.d = uint32_to_float64(val, &env->spe_status);
2494 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
2495 u.d = float64_div(u.d, tmp, &env->spe_status);
2500 uint32_t helper_efdctsf (uint64_t val)
2506 /* NaN are not treated the same way IEEE 754 does */
2507 if (unlikely(isnan(u.d)))
2509 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2510 u.d = float64_mul(u.d, tmp, &env->spe_status);
2512 return float64_to_int32(u.d, &env->spe_status);
2515 uint32_t helper_efdctuf (uint64_t val)
2521 /* NaN are not treated the same way IEEE 754 does */
2522 if (unlikely(isnan(u.d)))
2524 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2525 u.d = float64_mul(u.d, tmp, &env->spe_status);
2527 return float64_to_uint32(u.d, &env->spe_status);
2530 uint32_t helper_efscfd (uint64_t val)
2536 u2.f = float64_to_float32(u1.d, &env->spe_status);
2541 uint64_t helper_efdcfs (uint32_t val)
2547 u2.d = float32_to_float64(u1.f, &env->spe_status);
2552 /* Double precision fixed-point arithmetic */
2553 uint64_t helper_efdadd (uint64_t op1, uint64_t op2)
2558 u1.d = float64_add(u1.d, u2.d, &env->spe_status);
2562 uint64_t helper_efdsub (uint64_t op1, uint64_t op2)
2567 u1.d = float64_sub(u1.d, u2.d, &env->spe_status);
2571 uint64_t helper_efdmul (uint64_t op1, uint64_t op2)
2576 u1.d = float64_mul(u1.d, u2.d, &env->spe_status);
2580 uint64_t helper_efddiv (uint64_t op1, uint64_t op2)
2585 u1.d = float64_div(u1.d, u2.d, &env->spe_status);
2589 /* Double precision floating point helpers */
2590 uint32_t helper_efdtstlt (uint64_t op1, uint64_t op2)
2595 return float64_lt(u1.d, u2.d, &env->spe_status) ? 4 : 0;
2598 uint32_t helper_efdtstgt (uint64_t op1, uint64_t op2)
2603 return float64_le(u1.d, u2.d, &env->spe_status) ? 0 : 4;
2606 uint32_t helper_efdtsteq (uint64_t op1, uint64_t op2)
2611 return float64_eq(u1.d, u2.d, &env->spe_status) ? 4 : 0;
2614 uint32_t helper_efdcmplt (uint64_t op1, uint64_t op2)
2616 /* XXX: TODO: test special values (NaN, infinites, ...) */
2617 return helper_efdtstlt(op1, op2);
2620 uint32_t helper_efdcmpgt (uint64_t op1, uint64_t op2)
2622 /* XXX: TODO: test special values (NaN, infinites, ...) */
2623 return helper_efdtstgt(op1, op2);
2626 uint32_t helper_efdcmpeq (uint64_t op1, uint64_t op2)
2628 /* XXX: TODO: test special values (NaN, infinites, ...) */
2629 return helper_efdtsteq(op1, op2);
2632 /*****************************************************************************/
2633 /* Softmmu support */
2634 #if !defined (CONFIG_USER_ONLY)
2636 #define MMUSUFFIX _mmu
2639 #include "softmmu_template.h"
2642 #include "softmmu_template.h"
2645 #include "softmmu_template.h"
2648 #include "softmmu_template.h"
2650 /* try to fill the TLB and return an exception if error. If retaddr is
2651 NULL, it means that the function was called in C code (i.e. not
2652 from generated code or from helper.c) */
2653 /* XXX: fix it to restore all registers */
2654 void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
2656 TranslationBlock *tb;
2657 CPUState *saved_env;
2661 /* XXX: hack to restore env in all cases, even if not called from
2664 env = cpu_single_env;
2665 ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
2666 if (unlikely(ret != 0)) {
2667 if (likely(retaddr)) {
2668 /* now we have a real cpu fault */
2669 pc = (unsigned long)retaddr;
2670 tb = tb_find_pc(pc);
2672 /* the PC is inside the translated code. It means that we have
2673 a virtual CPU fault */
2674 cpu_restore_state(tb, env, pc, NULL);
2677 helper_raise_exception_err(env->exception_index, env->error_code);
2682 /* Segment registers load and store */
2683 target_ulong helper_load_sr (target_ulong sr_num)
2685 return env->sr[sr_num];
2688 void helper_store_sr (target_ulong sr_num, target_ulong val)
2690 ppc_store_sr(env, sr_num, val);
2693 /* SLB management */
2694 #if defined(TARGET_PPC64)
2695 target_ulong helper_load_slb (target_ulong slb_nr)
2697 return ppc_load_slb(env, slb_nr);
2700 void helper_store_slb (target_ulong slb_nr, target_ulong rs)
2702 ppc_store_slb(env, slb_nr, rs);
2705 void helper_slbia (void)
2707 ppc_slb_invalidate_all(env);
2710 void helper_slbie (target_ulong addr)
2712 ppc_slb_invalidate_one(env, addr);
2715 #endif /* defined(TARGET_PPC64) */
2717 /* TLB management */
2718 void helper_tlbia (void)
2720 ppc_tlb_invalidate_all(env);
2723 void helper_tlbie (target_ulong addr)
2725 ppc_tlb_invalidate_one(env, addr);
2728 /* Software driven TLBs management */
2729 /* PowerPC 602/603 software TLB load instructions helpers */
2730 static void do_6xx_tlb (target_ulong new_EPN, int is_code)
2732 target_ulong RPN, CMP, EPN;
2735 RPN = env->spr[SPR_RPA];
2737 CMP = env->spr[SPR_ICMP];
2738 EPN = env->spr[SPR_IMISS];
2740 CMP = env->spr[SPR_DCMP];
2741 EPN = env->spr[SPR_DMISS];
2743 way = (env->spr[SPR_SRR1] >> 17) & 1;
2744 #if defined (DEBUG_SOFTWARE_TLB)
2745 if (loglevel != 0) {
2746 fprintf(logfile, "%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX
2747 " PTE1 " ADDRX " way %d\n",
2748 __func__, new_EPN, EPN, CMP, RPN, way);
2751 /* Store this TLB */
2752 ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
2753 way, is_code, CMP, RPN);
2756 void helper_6xx_tlbd (target_ulong EPN)
2761 void helper_6xx_tlbi (target_ulong EPN)
2766 /* PowerPC 74xx software TLB load instructions helpers */
2767 static void do_74xx_tlb (target_ulong new_EPN, int is_code)
2769 target_ulong RPN, CMP, EPN;
2772 RPN = env->spr[SPR_PTELO];
2773 CMP = env->spr[SPR_PTEHI];
2774 EPN = env->spr[SPR_TLBMISS] & ~0x3;
2775 way = env->spr[SPR_TLBMISS] & 0x3;
2776 #if defined (DEBUG_SOFTWARE_TLB)
2777 if (loglevel != 0) {
2778 fprintf(logfile, "%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX
2779 " PTE1 " ADDRX " way %d\n",
2780 __func__, new_EPN, EPN, CMP, RPN, way);
2783 /* Store this TLB */
2784 ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
2785 way, is_code, CMP, RPN);
2788 void helper_74xx_tlbd (target_ulong EPN)
2790 do_74xx_tlb(EPN, 0);
2793 void helper_74xx_tlbi (target_ulong EPN)
2795 do_74xx_tlb(EPN, 1);
2798 static always_inline target_ulong booke_tlb_to_page_size (int size)
2800 return 1024 << (2 * size);
2803 static always_inline int booke_page_size_to_tlb (target_ulong page_size)
2807 switch (page_size) {
2841 #if defined (TARGET_PPC64)
2842 case 0x000100000000ULL:
2845 case 0x000400000000ULL:
2848 case 0x001000000000ULL:
2851 case 0x004000000000ULL:
2854 case 0x010000000000ULL:
2866 /* Helpers for 4xx TLB management */
2867 target_ulong helper_4xx_tlbre_lo (target_ulong entry)
2874 tlb = &env->tlb[entry].tlbe;
2876 if (tlb->prot & PAGE_VALID)
2878 size = booke_page_size_to_tlb(tlb->size);
2879 if (size < 0 || size > 0x7)
2882 env->spr[SPR_40x_PID] = tlb->PID;
2886 target_ulong helper_4xx_tlbre_hi (target_ulong entry)
2892 tlb = &env->tlb[entry].tlbe;
2894 if (tlb->prot & PAGE_EXEC)
2896 if (tlb->prot & PAGE_WRITE)
2901 void helper_4xx_tlbwe_hi (target_ulong entry, target_ulong val)
2904 target_ulong page, end;
2906 #if defined (DEBUG_SOFTWARE_TLB)
2907 if (loglevel != 0) {
2908 fprintf(logfile, "%s entry %d val " ADDRX "\n", __func__, (int)entry, val);
2912 tlb = &env->tlb[entry].tlbe;
2913 /* Invalidate previous TLB (if it's valid) */
2914 if (tlb->prot & PAGE_VALID) {
2915 end = tlb->EPN + tlb->size;
2916 #if defined (DEBUG_SOFTWARE_TLB)
2917 if (loglevel != 0) {
2918 fprintf(logfile, "%s: invalidate old TLB %d start " ADDRX
2919 " end " ADDRX "\n", __func__, (int)entry, tlb->EPN, end);
2922 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2923 tlb_flush_page(env, page);
2925 tlb->size = booke_tlb_to_page_size((val >> 7) & 0x7);
2926 /* We cannot handle TLB size < TARGET_PAGE_SIZE.
2927 * If this ever occurs, one should use the ppcemb target instead
2928 * of the ppc or ppc64 one
2930 if ((val & 0x40) && tlb->size < TARGET_PAGE_SIZE) {
2931 cpu_abort(env, "TLB size " TARGET_FMT_lu " < %u "
2932 "are not supported (%d)\n",
2933 tlb->size, TARGET_PAGE_SIZE, (int)((val >> 7) & 0x7));
2935 tlb->EPN = val & ~(tlb->size - 1);
2937 tlb->prot |= PAGE_VALID;
2939 tlb->prot &= ~PAGE_VALID;
2941 /* XXX: TO BE FIXED */
2942 cpu_abort(env, "Little-endian TLB entries are not supported by now\n");
2944 tlb->PID = env->spr[SPR_40x_PID]; /* PID */
2945 tlb->attr = val & 0xFF;
2946 #if defined (DEBUG_SOFTWARE_TLB)
2947 if (loglevel != 0) {
2948 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
2949 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
2950 (int)entry, tlb->RPN, tlb->EPN, tlb->size,
2951 tlb->prot & PAGE_READ ? 'r' : '-',
2952 tlb->prot & PAGE_WRITE ? 'w' : '-',
2953 tlb->prot & PAGE_EXEC ? 'x' : '-',
2954 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
2957 /* Invalidate new TLB (if valid) */
2958 if (tlb->prot & PAGE_VALID) {
2959 end = tlb->EPN + tlb->size;
2960 #if defined (DEBUG_SOFTWARE_TLB)
2961 if (loglevel != 0) {
2962 fprintf(logfile, "%s: invalidate TLB %d start " ADDRX
2963 " end " ADDRX "\n", __func__, (int)entry, tlb->EPN, end);
2966 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2967 tlb_flush_page(env, page);
2971 void helper_4xx_tlbwe_lo (target_ulong entry, target_ulong val)
2975 #if defined (DEBUG_SOFTWARE_TLB)
2976 if (loglevel != 0) {
2977 fprintf(logfile, "%s entry %i val " ADDRX "\n", __func__, (int)entry, val);
2981 tlb = &env->tlb[entry].tlbe;
2982 tlb->RPN = val & 0xFFFFFC00;
2983 tlb->prot = PAGE_READ;
2985 tlb->prot |= PAGE_EXEC;
2987 tlb->prot |= PAGE_WRITE;
2988 #if defined (DEBUG_SOFTWARE_TLB)
2989 if (loglevel != 0) {
2990 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
2991 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
2992 (int)entry, tlb->RPN, tlb->EPN, tlb->size,
2993 tlb->prot & PAGE_READ ? 'r' : '-',
2994 tlb->prot & PAGE_WRITE ? 'w' : '-',
2995 tlb->prot & PAGE_EXEC ? 'x' : '-',
2996 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
3001 target_ulong helper_4xx_tlbsx (target_ulong address)
3003 return ppcemb_tlb_search(env, address, env->spr[SPR_40x_PID]);
3006 /* PowerPC 440 TLB management */
3007 void helper_440_tlbwe (uint32_t word, target_ulong entry, target_ulong value)
3010 target_ulong EPN, RPN, size;
3013 #if defined (DEBUG_SOFTWARE_TLB)
3014 if (loglevel != 0) {
3015 fprintf(logfile, "%s word %d entry %d value " ADDRX "\n",
3016 __func__, word, (int)entry, value);
3021 tlb = &env->tlb[entry].tlbe;
3024 /* Just here to please gcc */
3026 EPN = value & 0xFFFFFC00;
3027 if ((tlb->prot & PAGE_VALID) && EPN != tlb->EPN)
3030 size = booke_tlb_to_page_size((value >> 4) & 0xF);
3031 if ((tlb->prot & PAGE_VALID) && tlb->size < size)
3035 tlb->attr |= (value >> 8) & 1;
3036 if (value & 0x200) {
3037 tlb->prot |= PAGE_VALID;
3039 if (tlb->prot & PAGE_VALID) {
3040 tlb->prot &= ~PAGE_VALID;
3044 tlb->PID = env->spr[SPR_440_MMUCR] & 0x000000FF;
3049 RPN = value & 0xFFFFFC0F;
3050 if ((tlb->prot & PAGE_VALID) && tlb->RPN != RPN)
3055 tlb->attr = (tlb->attr & 0x1) | (value & 0x0000FF00);
3056 tlb->prot = tlb->prot & PAGE_VALID;
3058 tlb->prot |= PAGE_READ << 4;
3060 tlb->prot |= PAGE_WRITE << 4;
3062 tlb->prot |= PAGE_EXEC << 4;
3064 tlb->prot |= PAGE_READ;
3066 tlb->prot |= PAGE_WRITE;
3068 tlb->prot |= PAGE_EXEC;
3073 target_ulong helper_440_tlbre (uint32_t word, target_ulong entry)
3080 tlb = &env->tlb[entry].tlbe;
3083 /* Just here to please gcc */
3086 size = booke_page_size_to_tlb(tlb->size);
3087 if (size < 0 || size > 0xF)
3090 if (tlb->attr & 0x1)
3092 if (tlb->prot & PAGE_VALID)
3094 env->spr[SPR_440_MMUCR] &= ~0x000000FF;
3095 env->spr[SPR_440_MMUCR] |= tlb->PID;
3101 ret = tlb->attr & ~0x1;
3102 if (tlb->prot & (PAGE_READ << 4))
3104 if (tlb->prot & (PAGE_WRITE << 4))
3106 if (tlb->prot & (PAGE_EXEC << 4))
3108 if (tlb->prot & PAGE_READ)
3110 if (tlb->prot & PAGE_WRITE)
3112 if (tlb->prot & PAGE_EXEC)
3119 target_ulong helper_440_tlbsx (target_ulong address)
3121 return ppcemb_tlb_search(env, address, env->spr[SPR_440_MMUCR] & 0xFF);
3124 #endif /* !CONFIG_USER_ONLY */