2 * PowerPC emulation helpers for qemu.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
22 #include "host-utils.h"
25 #include "helper_regs.h"
28 //#define DEBUG_EXCEPTIONS
29 //#define DEBUG_SOFTWARE_TLB
31 #ifdef DEBUG_SOFTWARE_TLB
32 # define LOG_SWTLB(...) qemu_log(__VA_ARGS__)
34 # define LOG_SWTLB(...) do { } while (0)
38 /*****************************************************************************/
39 /* Exceptions processing helpers */
41 void helper_raise_exception_err (uint32_t exception, uint32_t error_code)
44 printf("Raise exception %3x code : %d\n", exception, error_code);
46 env->exception_index = exception;
47 env->error_code = error_code;
51 void helper_raise_exception (uint32_t exception)
53 helper_raise_exception_err(exception, 0);
56 /*****************************************************************************/
57 /* Registers load and stores */
58 target_ulong helper_load_cr (void)
60 return (env->crf[0] << 28) |
70 void helper_store_cr (target_ulong val, uint32_t mask)
74 for (i = 0, sh = 7; i < 8; i++, sh--) {
76 env->crf[i] = (val >> (sh * 4)) & 0xFUL;
80 /*****************************************************************************/
82 void helper_load_dump_spr (uint32_t sprn)
84 qemu_log("Read SPR %d %03x => " ADDRX "\n",
85 sprn, sprn, env->spr[sprn]);
88 void helper_store_dump_spr (uint32_t sprn)
90 qemu_log("Write SPR %d %03x <= " ADDRX "\n",
91 sprn, sprn, env->spr[sprn]);
94 target_ulong helper_load_tbl (void)
96 return cpu_ppc_load_tbl(env);
99 target_ulong helper_load_tbu (void)
101 return cpu_ppc_load_tbu(env);
104 target_ulong helper_load_atbl (void)
106 return cpu_ppc_load_atbl(env);
109 target_ulong helper_load_atbu (void)
111 return cpu_ppc_load_atbu(env);
114 target_ulong helper_load_601_rtcl (void)
116 return cpu_ppc601_load_rtcl(env);
119 target_ulong helper_load_601_rtcu (void)
121 return cpu_ppc601_load_rtcu(env);
124 #if !defined(CONFIG_USER_ONLY)
125 #if defined (TARGET_PPC64)
126 void helper_store_asr (target_ulong val)
128 ppc_store_asr(env, val);
132 void helper_store_sdr1 (target_ulong val)
134 ppc_store_sdr1(env, val);
137 void helper_store_tbl (target_ulong val)
139 cpu_ppc_store_tbl(env, val);
142 void helper_store_tbu (target_ulong val)
144 cpu_ppc_store_tbu(env, val);
147 void helper_store_atbl (target_ulong val)
149 cpu_ppc_store_atbl(env, val);
152 void helper_store_atbu (target_ulong val)
154 cpu_ppc_store_atbu(env, val);
157 void helper_store_601_rtcl (target_ulong val)
159 cpu_ppc601_store_rtcl(env, val);
162 void helper_store_601_rtcu (target_ulong val)
164 cpu_ppc601_store_rtcu(env, val);
167 target_ulong helper_load_decr (void)
169 return cpu_ppc_load_decr(env);
172 void helper_store_decr (target_ulong val)
174 cpu_ppc_store_decr(env, val);
177 void helper_store_hid0_601 (target_ulong val)
181 hid0 = env->spr[SPR_HID0];
182 if ((val ^ hid0) & 0x00000008) {
183 /* Change current endianness */
184 env->hflags &= ~(1 << MSR_LE);
185 env->hflags_nmsr &= ~(1 << MSR_LE);
186 env->hflags_nmsr |= (1 << MSR_LE) & (((val >> 3) & 1) << MSR_LE);
187 env->hflags |= env->hflags_nmsr;
188 qemu_log("%s: set endianness to %c => " ADDRX "\n",
189 __func__, val & 0x8 ? 'l' : 'b', env->hflags);
191 env->spr[SPR_HID0] = (uint32_t)val;
194 void helper_store_403_pbr (uint32_t num, target_ulong value)
196 if (likely(env->pb[num] != value)) {
197 env->pb[num] = value;
198 /* Should be optimized */
203 target_ulong helper_load_40x_pit (void)
205 return load_40x_pit(env);
208 void helper_store_40x_pit (target_ulong val)
210 store_40x_pit(env, val);
213 void helper_store_40x_dbcr0 (target_ulong val)
215 store_40x_dbcr0(env, val);
218 void helper_store_40x_sler (target_ulong val)
220 store_40x_sler(env, val);
223 void helper_store_booke_tcr (target_ulong val)
225 store_booke_tcr(env, val);
228 void helper_store_booke_tsr (target_ulong val)
230 store_booke_tsr(env, val);
233 void helper_store_ibatu (uint32_t nr, target_ulong val)
235 ppc_store_ibatu(env, nr, val);
238 void helper_store_ibatl (uint32_t nr, target_ulong val)
240 ppc_store_ibatl(env, nr, val);
243 void helper_store_dbatu (uint32_t nr, target_ulong val)
245 ppc_store_dbatu(env, nr, val);
248 void helper_store_dbatl (uint32_t nr, target_ulong val)
250 ppc_store_dbatl(env, nr, val);
253 void helper_store_601_batl (uint32_t nr, target_ulong val)
255 ppc_store_ibatl_601(env, nr, val);
258 void helper_store_601_batu (uint32_t nr, target_ulong val)
260 ppc_store_ibatu_601(env, nr, val);
264 /*****************************************************************************/
265 /* Memory load and stores */
267 static always_inline target_ulong addr_add(target_ulong addr, target_long arg)
269 #if defined(TARGET_PPC64)
271 return (uint32_t)(addr + arg);
277 void helper_lmw (target_ulong addr, uint32_t reg)
279 for (; reg < 32; reg++) {
281 env->gpr[reg] = bswap32(ldl(addr));
283 env->gpr[reg] = ldl(addr);
284 addr = addr_add(addr, 4);
288 void helper_stmw (target_ulong addr, uint32_t reg)
290 for (; reg < 32; reg++) {
292 stl(addr, bswap32((uint32_t)env->gpr[reg]));
294 stl(addr, (uint32_t)env->gpr[reg]);
295 addr = addr_add(addr, 4);
299 void helper_lsw(target_ulong addr, uint32_t nb, uint32_t reg)
302 for (; nb > 3; nb -= 4) {
303 env->gpr[reg] = ldl(addr);
304 reg = (reg + 1) % 32;
305 addr = addr_add(addr, 4);
307 if (unlikely(nb > 0)) {
309 for (sh = 24; nb > 0; nb--, sh -= 8) {
310 env->gpr[reg] |= ldub(addr) << sh;
311 addr = addr_add(addr, 1);
315 /* PPC32 specification says we must generate an exception if
316 * rA is in the range of registers to be loaded.
317 * In an other hand, IBM says this is valid, but rA won't be loaded.
318 * For now, I'll follow the spec...
320 void helper_lswx(target_ulong addr, uint32_t reg, uint32_t ra, uint32_t rb)
322 if (likely(xer_bc != 0)) {
323 if (unlikely((ra != 0 && reg < ra && (reg + xer_bc) > ra) ||
324 (reg < rb && (reg + xer_bc) > rb))) {
325 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
327 POWERPC_EXCP_INVAL_LSWX);
329 helper_lsw(addr, xer_bc, reg);
334 void helper_stsw(target_ulong addr, uint32_t nb, uint32_t reg)
337 for (; nb > 3; nb -= 4) {
338 stl(addr, env->gpr[reg]);
339 reg = (reg + 1) % 32;
340 addr = addr_add(addr, 4);
342 if (unlikely(nb > 0)) {
343 for (sh = 24; nb > 0; nb--, sh -= 8) {
344 stb(addr, (env->gpr[reg] >> sh) & 0xFF);
345 addr = addr_add(addr, 1);
350 static void do_dcbz(target_ulong addr, int dcache_line_size)
352 addr &= ~(dcache_line_size - 1);
354 for (i = 0 ; i < dcache_line_size ; i += 4) {
357 if (env->reserve == addr)
358 env->reserve = (target_ulong)-1ULL;
361 void helper_dcbz(target_ulong addr)
363 do_dcbz(addr, env->dcache_line_size);
366 void helper_dcbz_970(target_ulong addr)
368 if (((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1)
371 do_dcbz(addr, env->dcache_line_size);
374 void helper_icbi(target_ulong addr)
378 addr &= ~(env->dcache_line_size - 1);
379 /* Invalidate one cache line :
380 * PowerPC specification says this is to be treated like a load
381 * (not a fetch) by the MMU. To be sure it will be so,
382 * do the load "by hand".
385 tb_invalidate_page_range(addr, addr + env->icache_line_size);
389 target_ulong helper_lscbx (target_ulong addr, uint32_t reg, uint32_t ra, uint32_t rb)
393 for (i = 0; i < xer_bc; i++) {
395 addr = addr_add(addr, 1);
396 /* ra (if not 0) and rb are never modified */
397 if (likely(reg != rb && (ra == 0 || reg != ra))) {
398 env->gpr[reg] = (env->gpr[reg] & ~(0xFF << d)) | (c << d);
400 if (unlikely(c == xer_cmp))
402 if (likely(d != 0)) {
413 /*****************************************************************************/
414 /* Fixed point operations helpers */
415 #if defined(TARGET_PPC64)
417 /* multiply high word */
418 uint64_t helper_mulhd (uint64_t arg1, uint64_t arg2)
422 muls64(&tl, &th, arg1, arg2);
426 /* multiply high word unsigned */
427 uint64_t helper_mulhdu (uint64_t arg1, uint64_t arg2)
431 mulu64(&tl, &th, arg1, arg2);
435 uint64_t helper_mulldo (uint64_t arg1, uint64_t arg2)
440 muls64(&tl, (uint64_t *)&th, arg1, arg2);
441 /* If th != 0 && th != -1, then we had an overflow */
442 if (likely((uint64_t)(th + 1) <= 1)) {
443 env->xer &= ~(1 << XER_OV);
445 env->xer |= (1 << XER_OV) | (1 << XER_SO);
451 target_ulong helper_cntlzw (target_ulong t)
456 #if defined(TARGET_PPC64)
457 target_ulong helper_cntlzd (target_ulong t)
463 /* shift right arithmetic helper */
464 target_ulong helper_sraw (target_ulong value, target_ulong shift)
468 if (likely(!(shift & 0x20))) {
469 if (likely((uint32_t)shift != 0)) {
471 ret = (int32_t)value >> shift;
472 if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
473 env->xer &= ~(1 << XER_CA);
475 env->xer |= (1 << XER_CA);
478 ret = (int32_t)value;
479 env->xer &= ~(1 << XER_CA);
482 ret = (int32_t)value >> 31;
484 env->xer |= (1 << XER_CA);
486 env->xer &= ~(1 << XER_CA);
489 return (target_long)ret;
492 #if defined(TARGET_PPC64)
493 target_ulong helper_srad (target_ulong value, target_ulong shift)
497 if (likely(!(shift & 0x40))) {
498 if (likely((uint64_t)shift != 0)) {
500 ret = (int64_t)value >> shift;
501 if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
502 env->xer &= ~(1 << XER_CA);
504 env->xer |= (1 << XER_CA);
507 ret = (int64_t)value;
508 env->xer &= ~(1 << XER_CA);
511 ret = (int64_t)value >> 63;
513 env->xer |= (1 << XER_CA);
515 env->xer &= ~(1 << XER_CA);
522 target_ulong helper_popcntb (target_ulong val)
524 val = (val & 0x55555555) + ((val >> 1) & 0x55555555);
525 val = (val & 0x33333333) + ((val >> 2) & 0x33333333);
526 val = (val & 0x0f0f0f0f) + ((val >> 4) & 0x0f0f0f0f);
530 #if defined(TARGET_PPC64)
531 target_ulong helper_popcntb_64 (target_ulong val)
533 val = (val & 0x5555555555555555ULL) + ((val >> 1) & 0x5555555555555555ULL);
534 val = (val & 0x3333333333333333ULL) + ((val >> 2) & 0x3333333333333333ULL);
535 val = (val & 0x0f0f0f0f0f0f0f0fULL) + ((val >> 4) & 0x0f0f0f0f0f0f0f0fULL);
540 /*****************************************************************************/
541 /* Floating point operations helpers */
542 uint64_t helper_float32_to_float64(uint32_t arg)
547 d.d = float32_to_float64(f.f, &env->fp_status);
551 uint32_t helper_float64_to_float32(uint64_t arg)
556 f.f = float64_to_float32(d.d, &env->fp_status);
560 static always_inline int isden (float64 d)
566 return ((u.ll >> 52) & 0x7FF) == 0;
569 uint32_t helper_compute_fprf (uint64_t arg, uint32_t set_fprf)
575 isneg = float64_is_neg(farg.d);
576 if (unlikely(float64_is_nan(farg.d))) {
577 if (float64_is_signaling_nan(farg.d)) {
578 /* Signaling NaN: flags are undefined */
584 } else if (unlikely(float64_is_infinity(farg.d))) {
591 if (float64_is_zero(farg.d)) {
599 /* Denormalized numbers */
602 /* Normalized numbers */
613 /* We update FPSCR_FPRF */
614 env->fpscr &= ~(0x1F << FPSCR_FPRF);
615 env->fpscr |= ret << FPSCR_FPRF;
617 /* We just need fpcc to update Rc1 */
621 /* Floating-point invalid operations exception */
622 static always_inline uint64_t fload_invalid_op_excp (int op)
629 case POWERPC_EXCP_FP_VXSNAN:
630 env->fpscr |= 1 << FPSCR_VXSNAN;
632 case POWERPC_EXCP_FP_VXSOFT:
633 env->fpscr |= 1 << FPSCR_VXSOFT;
635 case POWERPC_EXCP_FP_VXISI:
636 /* Magnitude subtraction of infinities */
637 env->fpscr |= 1 << FPSCR_VXISI;
639 case POWERPC_EXCP_FP_VXIDI:
640 /* Division of infinity by infinity */
641 env->fpscr |= 1 << FPSCR_VXIDI;
643 case POWERPC_EXCP_FP_VXZDZ:
644 /* Division of zero by zero */
645 env->fpscr |= 1 << FPSCR_VXZDZ;
647 case POWERPC_EXCP_FP_VXIMZ:
648 /* Multiplication of zero by infinity */
649 env->fpscr |= 1 << FPSCR_VXIMZ;
651 case POWERPC_EXCP_FP_VXVC:
652 /* Ordered comparison of NaN */
653 env->fpscr |= 1 << FPSCR_VXVC;
654 env->fpscr &= ~(0xF << FPSCR_FPCC);
655 env->fpscr |= 0x11 << FPSCR_FPCC;
656 /* We must update the target FPR before raising the exception */
658 env->exception_index = POWERPC_EXCP_PROGRAM;
659 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
660 /* Update the floating-point enabled exception summary */
661 env->fpscr |= 1 << FPSCR_FEX;
662 /* Exception is differed */
666 case POWERPC_EXCP_FP_VXSQRT:
667 /* Square root of a negative number */
668 env->fpscr |= 1 << FPSCR_VXSQRT;
670 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
672 /* Set the result to quiet NaN */
673 ret = 0xFFF8000000000000ULL;
674 env->fpscr &= ~(0xF << FPSCR_FPCC);
675 env->fpscr |= 0x11 << FPSCR_FPCC;
678 case POWERPC_EXCP_FP_VXCVI:
679 /* Invalid conversion */
680 env->fpscr |= 1 << FPSCR_VXCVI;
681 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
683 /* Set the result to quiet NaN */
684 ret = 0xFFF8000000000000ULL;
685 env->fpscr &= ~(0xF << FPSCR_FPCC);
686 env->fpscr |= 0x11 << FPSCR_FPCC;
690 /* Update the floating-point invalid operation summary */
691 env->fpscr |= 1 << FPSCR_VX;
692 /* Update the floating-point exception summary */
693 env->fpscr |= 1 << FPSCR_FX;
695 /* Update the floating-point enabled exception summary */
696 env->fpscr |= 1 << FPSCR_FEX;
697 if (msr_fe0 != 0 || msr_fe1 != 0)
698 helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_FP | op);
703 static always_inline void float_zero_divide_excp (void)
705 env->fpscr |= 1 << FPSCR_ZX;
706 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
707 /* Update the floating-point exception summary */
708 env->fpscr |= 1 << FPSCR_FX;
710 /* Update the floating-point enabled exception summary */
711 env->fpscr |= 1 << FPSCR_FEX;
712 if (msr_fe0 != 0 || msr_fe1 != 0) {
713 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
714 POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX);
719 static always_inline void float_overflow_excp (void)
721 env->fpscr |= 1 << FPSCR_OX;
722 /* Update the floating-point exception summary */
723 env->fpscr |= 1 << FPSCR_FX;
725 /* XXX: should adjust the result */
726 /* Update the floating-point enabled exception summary */
727 env->fpscr |= 1 << FPSCR_FEX;
728 /* We must update the target FPR before raising the exception */
729 env->exception_index = POWERPC_EXCP_PROGRAM;
730 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
732 env->fpscr |= 1 << FPSCR_XX;
733 env->fpscr |= 1 << FPSCR_FI;
737 static always_inline void float_underflow_excp (void)
739 env->fpscr |= 1 << FPSCR_UX;
740 /* Update the floating-point exception summary */
741 env->fpscr |= 1 << FPSCR_FX;
743 /* XXX: should adjust the result */
744 /* Update the floating-point enabled exception summary */
745 env->fpscr |= 1 << FPSCR_FEX;
746 /* We must update the target FPR before raising the exception */
747 env->exception_index = POWERPC_EXCP_PROGRAM;
748 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
752 static always_inline void float_inexact_excp (void)
754 env->fpscr |= 1 << FPSCR_XX;
755 /* Update the floating-point exception summary */
756 env->fpscr |= 1 << FPSCR_FX;
758 /* Update the floating-point enabled exception summary */
759 env->fpscr |= 1 << FPSCR_FEX;
760 /* We must update the target FPR before raising the exception */
761 env->exception_index = POWERPC_EXCP_PROGRAM;
762 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
766 static always_inline void fpscr_set_rounding_mode (void)
770 /* Set rounding mode */
773 /* Best approximation (round to nearest) */
774 rnd_type = float_round_nearest_even;
777 /* Smaller magnitude (round toward zero) */
778 rnd_type = float_round_to_zero;
781 /* Round toward +infinite */
782 rnd_type = float_round_up;
786 /* Round toward -infinite */
787 rnd_type = float_round_down;
790 set_float_rounding_mode(rnd_type, &env->fp_status);
793 void helper_fpscr_clrbit (uint32_t bit)
797 prev = (env->fpscr >> bit) & 1;
798 env->fpscr &= ~(1 << bit);
803 fpscr_set_rounding_mode();
811 void helper_fpscr_setbit (uint32_t bit)
815 prev = (env->fpscr >> bit) & 1;
816 env->fpscr |= 1 << bit;
820 env->fpscr |= 1 << FPSCR_FX;
824 env->fpscr |= 1 << FPSCR_FX;
829 env->fpscr |= 1 << FPSCR_FX;
834 env->fpscr |= 1 << FPSCR_FX;
839 env->fpscr |= 1 << FPSCR_FX;
852 env->fpscr |= 1 << FPSCR_VX;
853 env->fpscr |= 1 << FPSCR_FX;
860 env->error_code = POWERPC_EXCP_FP;
862 env->error_code |= POWERPC_EXCP_FP_VXSNAN;
864 env->error_code |= POWERPC_EXCP_FP_VXISI;
866 env->error_code |= POWERPC_EXCP_FP_VXIDI;
868 env->error_code |= POWERPC_EXCP_FP_VXZDZ;
870 env->error_code |= POWERPC_EXCP_FP_VXIMZ;
872 env->error_code |= POWERPC_EXCP_FP_VXVC;
874 env->error_code |= POWERPC_EXCP_FP_VXSOFT;
876 env->error_code |= POWERPC_EXCP_FP_VXSQRT;
878 env->error_code |= POWERPC_EXCP_FP_VXCVI;
885 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
892 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
899 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX;
906 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
912 fpscr_set_rounding_mode();
917 /* Update the floating-point enabled exception summary */
918 env->fpscr |= 1 << FPSCR_FEX;
919 /* We have to update Rc1 before raising the exception */
920 env->exception_index = POWERPC_EXCP_PROGRAM;
926 void helper_store_fpscr (uint64_t arg, uint32_t mask)
929 * We use only the 32 LSB of the incoming fpr
937 new |= prev & 0x60000000;
938 for (i = 0; i < 8; i++) {
939 if (mask & (1 << i)) {
940 env->fpscr &= ~(0xF << (4 * i));
941 env->fpscr |= new & (0xF << (4 * i));
944 /* Update VX and FEX */
946 env->fpscr |= 1 << FPSCR_VX;
948 env->fpscr &= ~(1 << FPSCR_VX);
949 if ((fpscr_ex & fpscr_eex) != 0) {
950 env->fpscr |= 1 << FPSCR_FEX;
951 env->exception_index = POWERPC_EXCP_PROGRAM;
952 /* XXX: we should compute it properly */
953 env->error_code = POWERPC_EXCP_FP;
956 env->fpscr &= ~(1 << FPSCR_FEX);
957 fpscr_set_rounding_mode();
960 void helper_float_check_status (void)
962 #ifdef CONFIG_SOFTFLOAT
963 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
964 (env->error_code & POWERPC_EXCP_FP)) {
965 /* Differred floating-point exception after target FPR update */
966 if (msr_fe0 != 0 || msr_fe1 != 0)
967 helper_raise_exception_err(env->exception_index, env->error_code);
969 int status = get_float_exception_flags(&env->fp_status);
970 if (status & float_flag_divbyzero) {
971 float_zero_divide_excp();
972 } else if (status & float_flag_overflow) {
973 float_overflow_excp();
974 } else if (status & float_flag_underflow) {
975 float_underflow_excp();
976 } else if (status & float_flag_inexact) {
977 float_inexact_excp();
981 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
982 (env->error_code & POWERPC_EXCP_FP)) {
983 /* Differred floating-point exception after target FPR update */
984 if (msr_fe0 != 0 || msr_fe1 != 0)
985 helper_raise_exception_err(env->exception_index, env->error_code);
990 #ifdef CONFIG_SOFTFLOAT
991 void helper_reset_fpstatus (void)
993 set_float_exception_flags(0, &env->fp_status);
998 uint64_t helper_fadd (uint64_t arg1, uint64_t arg2)
1000 CPU_DoubleU farg1, farg2;
1004 #if USE_PRECISE_EMULATION
1005 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1006 float64_is_signaling_nan(farg2.d))) {
1008 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1009 } else if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d) &&
1010 float64_is_neg(farg1.d) != float64_is_neg(farg2.d))) {
1011 /* Magnitude subtraction of infinities */
1012 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
1014 farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
1017 farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
1023 uint64_t helper_fsub (uint64_t arg1, uint64_t arg2)
1025 CPU_DoubleU farg1, farg2;
1029 #if USE_PRECISE_EMULATION
1031 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1032 float64_is_signaling_nan(farg2.d))) {
1033 /* sNaN subtraction */
1034 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1035 } else if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d) &&
1036 float64_is_neg(farg1.d) == float64_is_neg(farg2.d))) {
1037 /* Magnitude subtraction of infinities */
1038 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
1040 farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
1044 farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
1050 uint64_t helper_fmul (uint64_t arg1, uint64_t arg2)
1052 CPU_DoubleU farg1, farg2;
1056 #if USE_PRECISE_EMULATION
1057 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1058 float64_is_signaling_nan(farg2.d))) {
1059 /* sNaN multiplication */
1060 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1061 } else if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
1062 (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
1063 /* Multiplication of zero by infinity */
1064 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
1066 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1069 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1075 uint64_t helper_fdiv (uint64_t arg1, uint64_t arg2)
1077 CPU_DoubleU farg1, farg2;
1081 #if USE_PRECISE_EMULATION
1082 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1083 float64_is_signaling_nan(farg2.d))) {
1085 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1086 } else if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d))) {
1087 /* Division of infinity by infinity */
1088 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIDI);
1089 } else if (unlikely(float64_is_zero(farg1.d) && float64_is_zero(farg2.d))) {
1090 /* Division of zero by zero */
1091 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXZDZ);
1093 farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
1096 farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
1102 uint64_t helper_fabs (uint64_t arg)
1107 farg.d = float64_abs(farg.d);
1112 uint64_t helper_fnabs (uint64_t arg)
1117 farg.d = float64_abs(farg.d);
1118 farg.d = float64_chs(farg.d);
1123 uint64_t helper_fneg (uint64_t arg)
1128 farg.d = float64_chs(farg.d);
1132 /* fctiw - fctiw. */
1133 uint64_t helper_fctiw (uint64_t arg)
1138 if (unlikely(float64_is_signaling_nan(farg.d))) {
1139 /* sNaN conversion */
1140 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1141 } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) {
1142 /* qNan / infinity conversion */
1143 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1145 farg.ll = float64_to_int32(farg.d, &env->fp_status);
1146 #if USE_PRECISE_EMULATION
1147 /* XXX: higher bits are not supposed to be significant.
1148 * to make tests easier, return the same as a real PowerPC 750
1150 farg.ll |= 0xFFF80000ULL << 32;
1156 /* fctiwz - fctiwz. */
1157 uint64_t helper_fctiwz (uint64_t arg)
1162 if (unlikely(float64_is_signaling_nan(farg.d))) {
1163 /* sNaN conversion */
1164 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1165 } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) {
1166 /* qNan / infinity conversion */
1167 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1169 farg.ll = float64_to_int32_round_to_zero(farg.d, &env->fp_status);
1170 #if USE_PRECISE_EMULATION
1171 /* XXX: higher bits are not supposed to be significant.
1172 * to make tests easier, return the same as a real PowerPC 750
1174 farg.ll |= 0xFFF80000ULL << 32;
1180 #if defined(TARGET_PPC64)
1181 /* fcfid - fcfid. */
1182 uint64_t helper_fcfid (uint64_t arg)
1185 farg.d = int64_to_float64(arg, &env->fp_status);
1189 /* fctid - fctid. */
1190 uint64_t helper_fctid (uint64_t arg)
1195 if (unlikely(float64_is_signaling_nan(farg.d))) {
1196 /* sNaN conversion */
1197 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1198 } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) {
1199 /* qNan / infinity conversion */
1200 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1202 farg.ll = float64_to_int64(farg.d, &env->fp_status);
1207 /* fctidz - fctidz. */
1208 uint64_t helper_fctidz (uint64_t arg)
1213 if (unlikely(float64_is_signaling_nan(farg.d))) {
1214 /* sNaN conversion */
1215 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1216 } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) {
1217 /* qNan / infinity conversion */
1218 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1220 farg.ll = float64_to_int64_round_to_zero(farg.d, &env->fp_status);
1227 static always_inline uint64_t do_fri (uint64_t arg, int rounding_mode)
1232 if (unlikely(float64_is_signaling_nan(farg.d))) {
1234 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1235 } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) {
1236 /* qNan / infinity round */
1237 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1239 set_float_rounding_mode(rounding_mode, &env->fp_status);
1240 farg.ll = float64_round_to_int(farg.d, &env->fp_status);
1241 /* Restore rounding mode from FPSCR */
1242 fpscr_set_rounding_mode();
1247 uint64_t helper_frin (uint64_t arg)
1249 return do_fri(arg, float_round_nearest_even);
1252 uint64_t helper_friz (uint64_t arg)
1254 return do_fri(arg, float_round_to_zero);
1257 uint64_t helper_frip (uint64_t arg)
1259 return do_fri(arg, float_round_up);
1262 uint64_t helper_frim (uint64_t arg)
1264 return do_fri(arg, float_round_down);
1267 /* fmadd - fmadd. */
1268 uint64_t helper_fmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1270 CPU_DoubleU farg1, farg2, farg3;
1275 #if USE_PRECISE_EMULATION
1276 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1277 float64_is_signaling_nan(farg2.d) ||
1278 float64_is_signaling_nan(farg3.d))) {
1279 /* sNaN operation */
1280 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1281 } else if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
1282 (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
1283 /* Multiplication of zero by infinity */
1284 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
1287 /* This is the way the PowerPC specification defines it */
1288 float128 ft0_128, ft1_128;
1290 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1291 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1292 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1293 if (unlikely(float128_is_infinity(ft0_128) && float64_is_infinity(farg3.d) &&
1294 float128_is_neg(ft0_128) != float64_is_neg(farg3.d))) {
1295 /* Magnitude subtraction of infinities */
1296 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
1298 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1299 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1300 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1303 /* This is OK on x86 hosts */
1304 farg1.d = (farg1.d * farg2.d) + farg3.d;
1308 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1309 farg1.d = float64_add(farg1.d, farg3.d, &env->fp_status);
1314 /* fmsub - fmsub. */
1315 uint64_t helper_fmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1317 CPU_DoubleU farg1, farg2, farg3;
1322 #if USE_PRECISE_EMULATION
1323 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1324 float64_is_signaling_nan(farg2.d) ||
1325 float64_is_signaling_nan(farg3.d))) {
1326 /* sNaN operation */
1327 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1328 } else if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
1329 (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
1330 /* Multiplication of zero by infinity */
1331 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
1334 /* This is the way the PowerPC specification defines it */
1335 float128 ft0_128, ft1_128;
1337 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1338 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1339 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1340 if (unlikely(float128_is_infinity(ft0_128) && float64_is_infinity(farg3.d) &&
1341 float128_is_neg(ft0_128) == float64_is_neg(farg3.d))) {
1342 /* Magnitude subtraction of infinities */
1343 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
1345 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1346 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1347 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1350 /* This is OK on x86 hosts */
1351 farg1.d = (farg1.d * farg2.d) - farg3.d;
1355 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1356 farg1.d = float64_sub(farg1.d, farg3.d, &env->fp_status);
1361 /* fnmadd - fnmadd. */
1362 uint64_t helper_fnmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1364 CPU_DoubleU farg1, farg2, farg3;
1370 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1371 float64_is_signaling_nan(farg2.d) ||
1372 float64_is_signaling_nan(farg3.d))) {
1373 /* sNaN operation */
1374 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1375 } else if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
1376 (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
1377 /* Multiplication of zero by infinity */
1378 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
1380 #if USE_PRECISE_EMULATION
1382 /* This is the way the PowerPC specification defines it */
1383 float128 ft0_128, ft1_128;
1385 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1386 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1387 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1388 if (unlikely(float128_is_infinity(ft0_128) && float64_is_infinity(farg3.d) &&
1389 float128_is_neg(ft0_128) != float64_is_neg(farg3.d))) {
1390 /* Magnitude subtraction of infinities */
1391 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
1393 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1394 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1395 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1398 /* This is OK on x86 hosts */
1399 farg1.d = (farg1.d * farg2.d) + farg3.d;
1402 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1403 farg1.d = float64_add(farg1.d, farg3.d, &env->fp_status);
1405 if (likely(!float64_is_nan(farg1.d)))
1406 farg1.d = float64_chs(farg1.d);
1411 /* fnmsub - fnmsub. */
1412 uint64_t helper_fnmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1414 CPU_DoubleU farg1, farg2, farg3;
1420 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1421 float64_is_signaling_nan(farg2.d) ||
1422 float64_is_signaling_nan(farg3.d))) {
1423 /* sNaN operation */
1424 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1425 } else if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
1426 (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
1427 /* Multiplication of zero by infinity */
1428 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
1430 #if USE_PRECISE_EMULATION
1432 /* This is the way the PowerPC specification defines it */
1433 float128 ft0_128, ft1_128;
1435 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1436 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1437 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1438 if (unlikely(float128_is_infinity(ft0_128) && float64_is_infinity(farg3.d) &&
1439 float128_is_neg(ft0_128) == float64_is_neg(farg3.d))) {
1440 /* Magnitude subtraction of infinities */
1441 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
1443 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1444 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1445 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1448 /* This is OK on x86 hosts */
1449 farg1.d = (farg1.d * farg2.d) - farg3.d;
1452 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1453 farg1.d = float64_sub(farg1.d, farg3.d, &env->fp_status);
1455 if (likely(!float64_is_nan(farg1.d)))
1456 farg1.d = float64_chs(farg1.d);
1462 uint64_t helper_frsp (uint64_t arg)
1468 #if USE_PRECISE_EMULATION
1469 if (unlikely(float64_is_signaling_nan(farg.d))) {
1470 /* sNaN square root */
1471 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1473 f32 = float64_to_float32(farg.d, &env->fp_status);
1474 farg.d = float32_to_float64(f32, &env->fp_status);
1477 f32 = float64_to_float32(farg.d, &env->fp_status);
1478 farg.d = float32_to_float64(f32, &env->fp_status);
1483 /* fsqrt - fsqrt. */
1484 uint64_t helper_fsqrt (uint64_t arg)
1489 if (unlikely(float64_is_signaling_nan(farg.d))) {
1490 /* sNaN square root */
1491 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1492 } else if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) {
1493 /* Square root of a negative nonzero number */
1494 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1496 farg.d = float64_sqrt(farg.d, &env->fp_status);
1502 uint64_t helper_fre (uint64_t arg)
1507 if (unlikely(float64_is_signaling_nan(farg.d))) {
1508 /* sNaN reciprocal */
1509 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1511 farg.d = float64_div(float64_one, farg.d, &env->fp_status);
1517 uint64_t helper_fres (uint64_t arg)
1523 if (unlikely(float64_is_signaling_nan(farg.d))) {
1524 /* sNaN reciprocal */
1525 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1527 farg.d = float64_div(float64_one, farg.d, &env->fp_status);
1528 f32 = float64_to_float32(farg.d, &env->fp_status);
1529 farg.d = float32_to_float64(f32, &env->fp_status);
1534 /* frsqrte - frsqrte. */
1535 uint64_t helper_frsqrte (uint64_t arg)
1541 if (unlikely(float64_is_signaling_nan(farg.d))) {
1542 /* sNaN reciprocal square root */
1543 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1544 } else if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) {
1545 /* Reciprocal square root of a negative nonzero number */
1546 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1548 farg.d = float64_sqrt(farg.d, &env->fp_status);
1549 farg.d = float64_div(float64_one, farg.d, &env->fp_status);
1550 f32 = float64_to_float32(farg.d, &env->fp_status);
1551 farg.d = float32_to_float64(f32, &env->fp_status);
1557 uint64_t helper_fsel (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1563 if ((!float64_is_neg(farg1.d) || float64_is_zero(farg1.d)) && !float64_is_nan(farg1.d))
1569 void helper_fcmpu (uint64_t arg1, uint64_t arg2, uint32_t crfD)
1571 CPU_DoubleU farg1, farg2;
1576 if (unlikely(float64_is_nan(farg1.d) ||
1577 float64_is_nan(farg2.d))) {
1579 } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1581 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1587 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1588 env->fpscr |= ret << FPSCR_FPRF;
1589 env->crf[crfD] = ret;
1590 if (unlikely(ret == 0x01UL
1591 && (float64_is_signaling_nan(farg1.d) ||
1592 float64_is_signaling_nan(farg2.d)))) {
1593 /* sNaN comparison */
1594 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1598 void helper_fcmpo (uint64_t arg1, uint64_t arg2, uint32_t crfD)
1600 CPU_DoubleU farg1, farg2;
1605 if (unlikely(float64_is_nan(farg1.d) ||
1606 float64_is_nan(farg2.d))) {
1608 } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1610 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1616 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1617 env->fpscr |= ret << FPSCR_FPRF;
1618 env->crf[crfD] = ret;
1619 if (unlikely (ret == 0x01UL)) {
1620 if (float64_is_signaling_nan(farg1.d) ||
1621 float64_is_signaling_nan(farg2.d)) {
1622 /* sNaN comparison */
1623 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN |
1624 POWERPC_EXCP_FP_VXVC);
1626 /* qNaN comparison */
1627 fload_invalid_op_excp(POWERPC_EXCP_FP_VXVC);
1632 #if !defined (CONFIG_USER_ONLY)
1633 void helper_store_msr (target_ulong val)
1635 val = hreg_store_msr(env, val, 0);
1637 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1638 helper_raise_exception(val);
1642 static always_inline void do_rfi (target_ulong nip, target_ulong msr,
1643 target_ulong msrm, int keep_msrh)
1645 #if defined(TARGET_PPC64)
1646 if (msr & (1ULL << MSR_SF)) {
1647 nip = (uint64_t)nip;
1648 msr &= (uint64_t)msrm;
1650 nip = (uint32_t)nip;
1651 msr = (uint32_t)(msr & msrm);
1653 msr |= env->msr & ~((uint64_t)0xFFFFFFFF);
1656 nip = (uint32_t)nip;
1657 msr &= (uint32_t)msrm;
1659 /* XXX: beware: this is false if VLE is supported */
1660 env->nip = nip & ~((target_ulong)0x00000003);
1661 hreg_store_msr(env, msr, 1);
1662 #if defined (DEBUG_OP)
1663 cpu_dump_rfi(env->nip, env->msr);
1665 /* No need to raise an exception here,
1666 * as rfi is always the last insn of a TB
1668 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1671 void helper_rfi (void)
1673 do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1674 ~((target_ulong)0xFFFF0000), 1);
1677 #if defined(TARGET_PPC64)
1678 void helper_rfid (void)
1680 do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1681 ~((target_ulong)0xFFFF0000), 0);
1684 void helper_hrfid (void)
1686 do_rfi(env->spr[SPR_HSRR0], env->spr[SPR_HSRR1],
1687 ~((target_ulong)0xFFFF0000), 0);
1692 void helper_tw (target_ulong arg1, target_ulong arg2, uint32_t flags)
1694 if (!likely(!(((int32_t)arg1 < (int32_t)arg2 && (flags & 0x10)) ||
1695 ((int32_t)arg1 > (int32_t)arg2 && (flags & 0x08)) ||
1696 ((int32_t)arg1 == (int32_t)arg2 && (flags & 0x04)) ||
1697 ((uint32_t)arg1 < (uint32_t)arg2 && (flags & 0x02)) ||
1698 ((uint32_t)arg1 > (uint32_t)arg2 && (flags & 0x01))))) {
1699 helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1703 #if defined(TARGET_PPC64)
1704 void helper_td (target_ulong arg1, target_ulong arg2, uint32_t flags)
1706 if (!likely(!(((int64_t)arg1 < (int64_t)arg2 && (flags & 0x10)) ||
1707 ((int64_t)arg1 > (int64_t)arg2 && (flags & 0x08)) ||
1708 ((int64_t)arg1 == (int64_t)arg2 && (flags & 0x04)) ||
1709 ((uint64_t)arg1 < (uint64_t)arg2 && (flags & 0x02)) ||
1710 ((uint64_t)arg1 > (uint64_t)arg2 && (flags & 0x01)))))
1711 helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1715 /*****************************************************************************/
1716 /* PowerPC 601 specific instructions (POWER bridge) */
1718 target_ulong helper_clcs (uint32_t arg)
1722 /* Instruction cache line size */
1723 return env->icache_line_size;
1726 /* Data cache line size */
1727 return env->dcache_line_size;
1730 /* Minimum cache line size */
1731 return (env->icache_line_size < env->dcache_line_size) ?
1732 env->icache_line_size : env->dcache_line_size;
1735 /* Maximum cache line size */
1736 return (env->icache_line_size > env->dcache_line_size) ?
1737 env->icache_line_size : env->dcache_line_size;
1746 target_ulong helper_div (target_ulong arg1, target_ulong arg2)
1748 uint64_t tmp = (uint64_t)arg1 << 32 | env->spr[SPR_MQ];
1750 if (((int32_t)tmp == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1751 (int32_t)arg2 == 0) {
1752 env->spr[SPR_MQ] = 0;
1755 env->spr[SPR_MQ] = tmp % arg2;
1756 return tmp / (int32_t)arg2;
1760 target_ulong helper_divo (target_ulong arg1, target_ulong arg2)
1762 uint64_t tmp = (uint64_t)arg1 << 32 | env->spr[SPR_MQ];
1764 if (((int32_t)tmp == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1765 (int32_t)arg2 == 0) {
1766 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1767 env->spr[SPR_MQ] = 0;
1770 env->spr[SPR_MQ] = tmp % arg2;
1771 tmp /= (int32_t)arg2;
1772 if ((int32_t)tmp != tmp) {
1773 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1775 env->xer &= ~(1 << XER_OV);
1781 target_ulong helper_divs (target_ulong arg1, target_ulong arg2)
1783 if (((int32_t)arg1 == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1784 (int32_t)arg2 == 0) {
1785 env->spr[SPR_MQ] = 0;
1788 env->spr[SPR_MQ] = (int32_t)arg1 % (int32_t)arg2;
1789 return (int32_t)arg1 / (int32_t)arg2;
1793 target_ulong helper_divso (target_ulong arg1, target_ulong arg2)
1795 if (((int32_t)arg1 == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1796 (int32_t)arg2 == 0) {
1797 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1798 env->spr[SPR_MQ] = 0;
1801 env->xer &= ~(1 << XER_OV);
1802 env->spr[SPR_MQ] = (int32_t)arg1 % (int32_t)arg2;
1803 return (int32_t)arg1 / (int32_t)arg2;
1807 #if !defined (CONFIG_USER_ONLY)
1808 target_ulong helper_rac (target_ulong addr)
1812 target_ulong ret = 0;
1814 /* We don't have to generate many instances of this instruction,
1815 * as rac is supervisor only.
1817 /* XXX: FIX THIS: Pretend we have no BAT */
1818 nb_BATs = env->nb_BATs;
1820 if (get_physical_address(env, &ctx, addr, 0, ACCESS_INT) == 0)
1822 env->nb_BATs = nb_BATs;
1826 void helper_rfsvc (void)
1828 do_rfi(env->lr, env->ctr, 0x0000FFFF, 0);
1832 /*****************************************************************************/
1833 /* 602 specific instructions */
1834 /* mfrom is the most crazy instruction ever seen, imho ! */
1835 /* Real implementation uses a ROM table. Do the same */
1836 /* Extremly decomposed:
1838 * return 256 * log10(10 + 1.0) + 0.5
1840 #if !defined (CONFIG_USER_ONLY)
1841 target_ulong helper_602_mfrom (target_ulong arg)
1843 if (likely(arg < 602)) {
1844 #include "mfrom_table.c"
1845 return mfrom_ROM_table[arg];
1852 /*****************************************************************************/
1853 /* Embedded PowerPC specific helpers */
1855 /* XXX: to be improved to check access rights when in user-mode */
1856 target_ulong helper_load_dcr (target_ulong dcrn)
1858 target_ulong val = 0;
1860 if (unlikely(env->dcr_env == NULL)) {
1861 qemu_log("No DCR environment\n");
1862 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1863 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
1864 } else if (unlikely(ppc_dcr_read(env->dcr_env, dcrn, &val) != 0)) {
1865 qemu_log("DCR read error %d %03x\n", (int)dcrn, (int)dcrn);
1866 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1867 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
1872 void helper_store_dcr (target_ulong dcrn, target_ulong val)
1874 if (unlikely(env->dcr_env == NULL)) {
1875 qemu_log("No DCR environment\n");
1876 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1877 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
1878 } else if (unlikely(ppc_dcr_write(env->dcr_env, dcrn, val) != 0)) {
1879 qemu_log("DCR write error %d %03x\n", (int)dcrn, (int)dcrn);
1880 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1881 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
1885 #if !defined(CONFIG_USER_ONLY)
1886 void helper_40x_rfci (void)
1888 do_rfi(env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3],
1889 ~((target_ulong)0xFFFF0000), 0);
1892 void helper_rfci (void)
1894 do_rfi(env->spr[SPR_BOOKE_CSRR0], SPR_BOOKE_CSRR1,
1895 ~((target_ulong)0x3FFF0000), 0);
1898 void helper_rfdi (void)
1900 do_rfi(env->spr[SPR_BOOKE_DSRR0], SPR_BOOKE_DSRR1,
1901 ~((target_ulong)0x3FFF0000), 0);
1904 void helper_rfmci (void)
1906 do_rfi(env->spr[SPR_BOOKE_MCSRR0], SPR_BOOKE_MCSRR1,
1907 ~((target_ulong)0x3FFF0000), 0);
1912 target_ulong helper_dlmzb (target_ulong high, target_ulong low, uint32_t update_Rc)
1918 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1919 if ((high & mask) == 0) {
1927 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1928 if ((low & mask) == 0) {
1940 env->xer = (env->xer & ~0x7F) | i;
1942 env->crf[0] |= xer_so;
1947 /*****************************************************************************/
1948 /* Altivec extension helpers */
1949 #if defined(WORDS_BIGENDIAN)
1957 #if defined(WORDS_BIGENDIAN)
1958 #define VECTOR_FOR_INORDER_I(index, element) \
1959 for (index = 0; index < ARRAY_SIZE(r->element); index++)
1961 #define VECTOR_FOR_INORDER_I(index, element) \
1962 for (index = ARRAY_SIZE(r->element)-1; index >= 0; index--)
1965 /* If X is a NaN, store the corresponding QNaN into RESULT. Otherwise,
1966 * execute the following block. */
1967 #define DO_HANDLE_NAN(result, x) \
1968 if (float32_is_nan(x) || float32_is_signaling_nan(x)) { \
1971 __f.l = __f.l | (1 << 22); /* Set QNaN bit. */ \
1975 #define HANDLE_NAN1(result, x) \
1976 DO_HANDLE_NAN(result, x)
1977 #define HANDLE_NAN2(result, x, y) \
1978 DO_HANDLE_NAN(result, x) DO_HANDLE_NAN(result, y)
1979 #define HANDLE_NAN3(result, x, y, z) \
1980 DO_HANDLE_NAN(result, x) DO_HANDLE_NAN(result, y) DO_HANDLE_NAN(result, z)
1982 /* Saturating arithmetic helpers. */
1983 #define SATCVT(from, to, from_type, to_type, min, max, use_min, use_max) \
1984 static always_inline to_type cvt##from##to (from_type x, int *sat) \
1987 if (use_min && x < min) { \
1990 } else if (use_max && x > max) { \
1998 SATCVT(sh, sb, int16_t, int8_t, INT8_MIN, INT8_MAX, 1, 1)
1999 SATCVT(sw, sh, int32_t, int16_t, INT16_MIN, INT16_MAX, 1, 1)
2000 SATCVT(sd, sw, int64_t, int32_t, INT32_MIN, INT32_MAX, 1, 1)
2001 SATCVT(uh, ub, uint16_t, uint8_t, 0, UINT8_MAX, 0, 1)
2002 SATCVT(uw, uh, uint32_t, uint16_t, 0, UINT16_MAX, 0, 1)
2003 SATCVT(ud, uw, uint64_t, uint32_t, 0, UINT32_MAX, 0, 1)
2004 SATCVT(sh, ub, int16_t, uint8_t, 0, UINT8_MAX, 1, 1)
2005 SATCVT(sw, uh, int32_t, uint16_t, 0, UINT16_MAX, 1, 1)
2006 SATCVT(sd, uw, int64_t, uint32_t, 0, UINT32_MAX, 1, 1)
2009 #define LVE(name, access, swap, element) \
2010 void helper_##name (ppc_avr_t *r, target_ulong addr) \
2012 size_t n_elems = ARRAY_SIZE(r->element); \
2013 int adjust = HI_IDX*(n_elems-1); \
2014 int sh = sizeof(r->element[0]) >> 1; \
2015 int index = (addr & 0xf) >> sh; \
2017 r->element[LO_IDX ? index : (adjust - index)] = swap(access(addr)); \
2019 r->element[LO_IDX ? index : (adjust - index)] = access(addr); \
2023 LVE(lvebx, ldub, I, u8)
2024 LVE(lvehx, lduw, bswap16, u16)
2025 LVE(lvewx, ldl, bswap32, u32)
2029 void helper_lvsl (ppc_avr_t *r, target_ulong sh)
2031 int i, j = (sh & 0xf);
2033 VECTOR_FOR_INORDER_I (i, u8) {
2038 void helper_lvsr (ppc_avr_t *r, target_ulong sh)
2040 int i, j = 0x10 - (sh & 0xf);
2042 VECTOR_FOR_INORDER_I (i, u8) {
2047 #define STVE(name, access, swap, element) \
2048 void helper_##name (ppc_avr_t *r, target_ulong addr) \
2050 size_t n_elems = ARRAY_SIZE(r->element); \
2051 int adjust = HI_IDX*(n_elems-1); \
2052 int sh = sizeof(r->element[0]) >> 1; \
2053 int index = (addr & 0xf) >> sh; \
2055 access(addr, swap(r->element[LO_IDX ? index : (adjust - index)])); \
2057 access(addr, r->element[LO_IDX ? index : (adjust - index)]); \
2061 STVE(stvebx, stb, I, u8)
2062 STVE(stvehx, stw, bswap16, u16)
2063 STVE(stvewx, stl, bswap32, u32)
2067 void helper_mtvscr (ppc_avr_t *r)
2069 #if defined(WORDS_BIGENDIAN)
2070 env->vscr = r->u32[3];
2072 env->vscr = r->u32[0];
2074 set_flush_to_zero(vscr_nj, &env->vec_status);
2077 void helper_vaddcuw (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
2080 for (i = 0; i < ARRAY_SIZE(r->u32); i++) {
2081 r->u32[i] = ~a->u32[i] < b->u32[i];
2085 #define VARITH_DO(name, op, element) \
2086 void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
2089 for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
2090 r->element[i] = a->element[i] op b->element[i]; \
2093 #define VARITH(suffix, element) \
2094 VARITH_DO(add##suffix, +, element) \
2095 VARITH_DO(sub##suffix, -, element)
2102 #define VARITHFP(suffix, func) \
2103 void helper_v##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
2106 for (i = 0; i < ARRAY_SIZE(r->f); i++) { \
2107 HANDLE_NAN2(r->f[i], a->f[i], b->f[i]) { \
2108 r->f[i] = func(a->f[i], b->f[i], &env->vec_status); \
2112 VARITHFP(addfp, float32_add)
2113 VARITHFP(subfp, float32_sub)
2116 #define VARITHSAT_CASE(type, op, cvt, element) \
2118 type result = (type)a->element[i] op (type)b->element[i]; \
2119 r->element[i] = cvt(result, &sat); \
2122 #define VARITHSAT_DO(name, op, optype, cvt, element) \
2123 void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
2127 for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
2128 switch (sizeof(r->element[0])) { \
2129 case 1: VARITHSAT_CASE(optype, op, cvt, element); break; \
2130 case 2: VARITHSAT_CASE(optype, op, cvt, element); break; \
2131 case 4: VARITHSAT_CASE(optype, op, cvt, element); break; \
2135 env->vscr |= (1 << VSCR_SAT); \
2138 #define VARITHSAT_SIGNED(suffix, element, optype, cvt) \
2139 VARITHSAT_DO(adds##suffix##s, +, optype, cvt, element) \
2140 VARITHSAT_DO(subs##suffix##s, -, optype, cvt, element)
2141 #define VARITHSAT_UNSIGNED(suffix, element, optype, cvt) \
2142 VARITHSAT_DO(addu##suffix##s, +, optype, cvt, element) \
2143 VARITHSAT_DO(subu##suffix##s, -, optype, cvt, element)
2144 VARITHSAT_SIGNED(b, s8, int16_t, cvtshsb)
2145 VARITHSAT_SIGNED(h, s16, int32_t, cvtswsh)
2146 VARITHSAT_SIGNED(w, s32, int64_t, cvtsdsw)
2147 VARITHSAT_UNSIGNED(b, u8, uint16_t, cvtshub)
2148 VARITHSAT_UNSIGNED(h, u16, uint32_t, cvtswuh)
2149 VARITHSAT_UNSIGNED(w, u32, uint64_t, cvtsduw)
2150 #undef VARITHSAT_CASE
2152 #undef VARITHSAT_SIGNED
2153 #undef VARITHSAT_UNSIGNED
2155 #define VAVG_DO(name, element, etype) \
2156 void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
2159 for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
2160 etype x = (etype)a->element[i] + (etype)b->element[i] + 1; \
2161 r->element[i] = x >> 1; \
2165 #define VAVG(type, signed_element, signed_type, unsigned_element, unsigned_type) \
2166 VAVG_DO(avgs##type, signed_element, signed_type) \
2167 VAVG_DO(avgu##type, unsigned_element, unsigned_type)
2168 VAVG(b, s8, int16_t, u8, uint16_t)
2169 VAVG(h, s16, int32_t, u16, uint32_t)
2170 VAVG(w, s32, int64_t, u32, uint64_t)
2174 #define VCF(suffix, cvt, element) \
2175 void helper_vcf##suffix (ppc_avr_t *r, ppc_avr_t *b, uint32_t uim) \
2178 for (i = 0; i < ARRAY_SIZE(r->f); i++) { \
2179 float32 t = cvt(b->element[i], &env->vec_status); \
2180 r->f[i] = float32_scalbn (t, -uim, &env->vec_status); \
2183 VCF(ux, uint32_to_float32, u32)
2184 VCF(sx, int32_to_float32, s32)
2187 #define VCMP_DO(suffix, compare, element, record) \
2188 void helper_vcmp##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
2190 uint32_t ones = (uint32_t)-1; \
2191 uint32_t all = ones; \
2192 uint32_t none = 0; \
2194 for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
2195 uint32_t result = (a->element[i] compare b->element[i] ? ones : 0x0); \
2196 switch (sizeof (a->element[0])) { \
2197 case 4: r->u32[i] = result; break; \
2198 case 2: r->u16[i] = result; break; \
2199 case 1: r->u8[i] = result; break; \
2205 env->crf[6] = ((all != 0) << 3) | ((none == 0) << 1); \
2208 #define VCMP(suffix, compare, element) \
2209 VCMP_DO(suffix, compare, element, 0) \
2210 VCMP_DO(suffix##_dot, compare, element, 1)
2223 #define VCMPFP_DO(suffix, compare, order, record) \
2224 void helper_vcmp##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
2226 uint32_t ones = (uint32_t)-1; \
2227 uint32_t all = ones; \
2228 uint32_t none = 0; \
2230 for (i = 0; i < ARRAY_SIZE(r->f); i++) { \
2232 int rel = float32_compare_quiet(a->f[i], b->f[i], &env->vec_status); \
2233 if (rel == float_relation_unordered) { \
2235 } else if (rel compare order) { \
2240 r->u32[i] = result; \
2245 env->crf[6] = ((all != 0) << 3) | ((none == 0) << 1); \
2248 #define VCMPFP(suffix, compare, order) \
2249 VCMPFP_DO(suffix, compare, order, 0) \
2250 VCMPFP_DO(suffix##_dot, compare, order, 1)
2251 VCMPFP(eqfp, ==, float_relation_equal)
2252 VCMPFP(gefp, !=, float_relation_less)
2253 VCMPFP(gtfp, ==, float_relation_greater)
2257 static always_inline void vcmpbfp_internal (ppc_avr_t *r, ppc_avr_t *a,
2258 ppc_avr_t *b, int record)
2262 for (i = 0; i < ARRAY_SIZE(r->f); i++) {
2263 int le_rel = float32_compare_quiet(a->f[i], b->f[i], &env->vec_status);
2264 if (le_rel == float_relation_unordered) {
2265 r->u32[i] = 0xc0000000;
2266 /* ALL_IN does not need to be updated here. */
2268 float32 bneg = float32_chs(b->f[i]);
2269 int ge_rel = float32_compare_quiet(a->f[i], bneg, &env->vec_status);
2270 int le = le_rel != float_relation_greater;
2271 int ge = ge_rel != float_relation_less;
2272 r->u32[i] = ((!le) << 31) | ((!ge) << 30);
2273 all_in |= (!le | !ge);
2277 env->crf[6] = (all_in == 0) << 1;
2281 void helper_vcmpbfp (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
2283 vcmpbfp_internal(r, a, b, 0);
2286 void helper_vcmpbfp_dot (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
2288 vcmpbfp_internal(r, a, b, 1);
2291 #define VCT(suffix, satcvt, element) \
2292 void helper_vct##suffix (ppc_avr_t *r, ppc_avr_t *b, uint32_t uim) \
2296 float_status s = env->vec_status; \
2297 set_float_rounding_mode(float_round_to_zero, &s); \
2298 for (i = 0; i < ARRAY_SIZE(r->f); i++) { \
2299 if (float32_is_nan(b->f[i]) || \
2300 float32_is_signaling_nan(b->f[i])) { \
2301 r->element[i] = 0; \
2303 float64 t = float32_to_float64(b->f[i], &s); \
2305 t = float64_scalbn(t, uim, &s); \
2306 j = float64_to_int64(t, &s); \
2307 r->element[i] = satcvt(j, &sat); \
2311 env->vscr |= (1 << VSCR_SAT); \
2314 VCT(uxs, cvtsduw, u32)
2315 VCT(sxs, cvtsdsw, s32)
2318 void helper_vmaddfp (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
2321 for (i = 0; i < ARRAY_SIZE(r->f); i++) {
2322 HANDLE_NAN3(r->f[i], a->f[i], b->f[i], c->f[i]) {
2323 /* Need to do the computation in higher precision and round
2324 * once at the end. */
2325 float64 af, bf, cf, t;
2326 af = float32_to_float64(a->f[i], &env->vec_status);
2327 bf = float32_to_float64(b->f[i], &env->vec_status);
2328 cf = float32_to_float64(c->f[i], &env->vec_status);
2329 t = float64_mul(af, cf, &env->vec_status);
2330 t = float64_add(t, bf, &env->vec_status);
2331 r->f[i] = float64_to_float32(t, &env->vec_status);
2336 void helper_vmhaddshs (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
2341 for (i = 0; i < ARRAY_SIZE(r->s16); i++) {
2342 int32_t prod = a->s16[i] * b->s16[i];
2343 int32_t t = (int32_t)c->s16[i] + (prod >> 15);
2344 r->s16[i] = cvtswsh (t, &sat);
2348 env->vscr |= (1 << VSCR_SAT);
2352 void helper_vmhraddshs (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
2357 for (i = 0; i < ARRAY_SIZE(r->s16); i++) {
2358 int32_t prod = a->s16[i] * b->s16[i] + 0x00004000;
2359 int32_t t = (int32_t)c->s16[i] + (prod >> 15);
2360 r->s16[i] = cvtswsh (t, &sat);
2364 env->vscr |= (1 << VSCR_SAT);
2368 #define VMINMAX_DO(name, compare, element) \
2369 void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
2372 for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
2373 if (a->element[i] compare b->element[i]) { \
2374 r->element[i] = b->element[i]; \
2376 r->element[i] = a->element[i]; \
2380 #define VMINMAX(suffix, element) \
2381 VMINMAX_DO(min##suffix, >, element) \
2382 VMINMAX_DO(max##suffix, <, element)
2392 #define VMINMAXFP(suffix, rT, rF) \
2393 void helper_v##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
2396 for (i = 0; i < ARRAY_SIZE(r->f); i++) { \
2397 HANDLE_NAN2(r->f[i], a->f[i], b->f[i]) { \
2398 if (float32_lt_quiet(a->f[i], b->f[i], &env->vec_status)) { \
2399 r->f[i] = rT->f[i]; \
2401 r->f[i] = rF->f[i]; \
2406 VMINMAXFP(minfp, a, b)
2407 VMINMAXFP(maxfp, b, a)
2410 void helper_vmladduhm (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
2413 for (i = 0; i < ARRAY_SIZE(r->s16); i++) {
2414 int32_t prod = a->s16[i] * b->s16[i];
2415 r->s16[i] = (int16_t) (prod + c->s16[i]);
2419 #define VMRG_DO(name, element, highp) \
2420 void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
2424 size_t n_elems = ARRAY_SIZE(r->element); \
2425 for (i = 0; i < n_elems/2; i++) { \
2427 result.element[i*2+HI_IDX] = a->element[i]; \
2428 result.element[i*2+LO_IDX] = b->element[i]; \
2430 result.element[n_elems - i*2 - (1+HI_IDX)] = b->element[n_elems - i - 1]; \
2431 result.element[n_elems - i*2 - (1+LO_IDX)] = a->element[n_elems - i - 1]; \
2436 #if defined(WORDS_BIGENDIAN)
2443 #define VMRG(suffix, element) \
2444 VMRG_DO(mrgl##suffix, element, MRGHI) \
2445 VMRG_DO(mrgh##suffix, element, MRGLO)
2454 void helper_vmsummbm (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
2459 for (i = 0; i < ARRAY_SIZE(r->s8); i++) {
2460 prod[i] = (int32_t)a->s8[i] * b->u8[i];
2463 VECTOR_FOR_INORDER_I(i, s32) {
2464 r->s32[i] = c->s32[i] + prod[4*i] + prod[4*i+1] + prod[4*i+2] + prod[4*i+3];
2468 void helper_vmsumshm (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
2473 for (i = 0; i < ARRAY_SIZE(r->s16); i++) {
2474 prod[i] = a->s16[i] * b->s16[i];
2477 VECTOR_FOR_INORDER_I(i, s32) {
2478 r->s32[i] = c->s32[i] + prod[2*i] + prod[2*i+1];
2482 void helper_vmsumshs (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
2488 for (i = 0; i < ARRAY_SIZE(r->s16); i++) {
2489 prod[i] = (int32_t)a->s16[i] * b->s16[i];
2492 VECTOR_FOR_INORDER_I (i, s32) {
2493 int64_t t = (int64_t)c->s32[i] + prod[2*i] + prod[2*i+1];
2494 r->u32[i] = cvtsdsw(t, &sat);
2498 env->vscr |= (1 << VSCR_SAT);
2502 void helper_vmsumubm (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
2507 for (i = 0; i < ARRAY_SIZE(r->u8); i++) {
2508 prod[i] = a->u8[i] * b->u8[i];
2511 VECTOR_FOR_INORDER_I(i, u32) {
2512 r->u32[i] = c->u32[i] + prod[4*i] + prod[4*i+1] + prod[4*i+2] + prod[4*i+3];
2516 void helper_vmsumuhm (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
2521 for (i = 0; i < ARRAY_SIZE(r->u16); i++) {
2522 prod[i] = a->u16[i] * b->u16[i];
2525 VECTOR_FOR_INORDER_I(i, u32) {
2526 r->u32[i] = c->u32[i] + prod[2*i] + prod[2*i+1];
2530 void helper_vmsumuhs (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
2536 for (i = 0; i < ARRAY_SIZE(r->u16); i++) {
2537 prod[i] = a->u16[i] * b->u16[i];
2540 VECTOR_FOR_INORDER_I (i, s32) {
2541 uint64_t t = (uint64_t)c->u32[i] + prod[2*i] + prod[2*i+1];
2542 r->u32[i] = cvtuduw(t, &sat);
2546 env->vscr |= (1 << VSCR_SAT);
2550 #define VMUL_DO(name, mul_element, prod_element, evenp) \
2551 void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
2554 VECTOR_FOR_INORDER_I(i, prod_element) { \
2556 r->prod_element[i] = a->mul_element[i*2+HI_IDX] * b->mul_element[i*2+HI_IDX]; \
2558 r->prod_element[i] = a->mul_element[i*2+LO_IDX] * b->mul_element[i*2+LO_IDX]; \
2562 #define VMUL(suffix, mul_element, prod_element) \
2563 VMUL_DO(mule##suffix, mul_element, prod_element, 1) \
2564 VMUL_DO(mulo##suffix, mul_element, prod_element, 0)
2572 void helper_vnmsubfp (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
2575 for (i = 0; i < ARRAY_SIZE(r->f); i++) {
2576 HANDLE_NAN3(r->f[i], a->f[i], b->f[i], c->f[i]) {
2577 /* Need to do the computation is higher precision and round
2578 * once at the end. */
2579 float64 af, bf, cf, t;
2580 af = float32_to_float64(a->f[i], &env->vec_status);
2581 bf = float32_to_float64(b->f[i], &env->vec_status);
2582 cf = float32_to_float64(c->f[i], &env->vec_status);
2583 t = float64_mul(af, cf, &env->vec_status);
2584 t = float64_sub(t, bf, &env->vec_status);
2586 r->f[i] = float64_to_float32(t, &env->vec_status);
2591 void helper_vperm (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
2595 VECTOR_FOR_INORDER_I (i, u8) {
2596 int s = c->u8[i] & 0x1f;
2597 #if defined(WORDS_BIGENDIAN)
2598 int index = s & 0xf;
2600 int index = 15 - (s & 0xf);
2603 result.u8[i] = b->u8[index];
2605 result.u8[i] = a->u8[index];
2611 #if defined(WORDS_BIGENDIAN)
2616 void helper_vpkpx (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
2620 #if defined(WORDS_BIGENDIAN)
2621 const ppc_avr_t *x[2] = { a, b };
2623 const ppc_avr_t *x[2] = { b, a };
2626 VECTOR_FOR_INORDER_I (i, u64) {
2627 VECTOR_FOR_INORDER_I (j, u32){
2628 uint32_t e = x[i]->u32[j];
2629 result.u16[4*i+j] = (((e >> 9) & 0xfc00) |
2630 ((e >> 6) & 0x3e0) |
2637 #define VPK(suffix, from, to, cvt, dosat) \
2638 void helper_vpk##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
2643 ppc_avr_t *a0 = PKBIG ? a : b; \
2644 ppc_avr_t *a1 = PKBIG ? b : a; \
2645 VECTOR_FOR_INORDER_I (i, from) { \
2646 result.to[i] = cvt(a0->from[i], &sat); \
2647 result.to[i+ARRAY_SIZE(r->from)] = cvt(a1->from[i], &sat); \
2650 if (dosat && sat) { \
2651 env->vscr |= (1 << VSCR_SAT); \
2655 VPK(shss, s16, s8, cvtshsb, 1)
2656 VPK(shus, s16, u8, cvtshub, 1)
2657 VPK(swss, s32, s16, cvtswsh, 1)
2658 VPK(swus, s32, u16, cvtswuh, 1)
2659 VPK(uhus, u16, u8, cvtuhub, 1)
2660 VPK(uwus, u32, u16, cvtuwuh, 1)
2661 VPK(uhum, u16, u8, I, 0)
2662 VPK(uwum, u32, u16, I, 0)
2667 void helper_vrefp (ppc_avr_t *r, ppc_avr_t *b)
2670 for (i = 0; i < ARRAY_SIZE(r->f); i++) {
2671 HANDLE_NAN1(r->f[i], b->f[i]) {
2672 r->f[i] = float32_div(float32_one, b->f[i], &env->vec_status);
2677 #define VRFI(suffix, rounding) \
2678 void helper_vrfi##suffix (ppc_avr_t *r, ppc_avr_t *b) \
2681 float_status s = env->vec_status; \
2682 set_float_rounding_mode(rounding, &s); \
2683 for (i = 0; i < ARRAY_SIZE(r->f); i++) { \
2684 HANDLE_NAN1(r->f[i], b->f[i]) { \
2685 r->f[i] = float32_round_to_int (b->f[i], &s); \
2689 VRFI(n, float_round_nearest_even)
2690 VRFI(m, float_round_down)
2691 VRFI(p, float_round_up)
2692 VRFI(z, float_round_to_zero)
2695 #define VROTATE(suffix, element) \
2696 void helper_vrl##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
2699 for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
2700 unsigned int mask = ((1 << (3 + (sizeof (a->element[0]) >> 1))) - 1); \
2701 unsigned int shift = b->element[i] & mask; \
2702 r->element[i] = (a->element[i] << shift) | (a->element[i] >> (sizeof(a->element[0]) * 8 - shift)); \
2710 void helper_vsel (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
2712 r->u64[0] = (a->u64[0] & ~c->u64[0]) | (b->u64[0] & c->u64[0]);
2713 r->u64[1] = (a->u64[1] & ~c->u64[1]) | (b->u64[1] & c->u64[1]);
2716 void helper_vlogefp (ppc_avr_t *r, ppc_avr_t *b)
2719 for (i = 0; i < ARRAY_SIZE(r->f); i++) {
2720 HANDLE_NAN1(r->f[i], b->f[i]) {
2721 r->f[i] = float32_log2(b->f[i], &env->vec_status);
2726 #if defined(WORDS_BIGENDIAN)
2733 /* The specification says that the results are undefined if all of the
2734 * shift counts are not identical. We check to make sure that they are
2735 * to conform to what real hardware appears to do. */
2736 #define VSHIFT(suffix, leftp) \
2737 void helper_vs##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
2739 int shift = b->u8[LO_IDX*0x15] & 0x7; \
2742 for (i = 0; i < ARRAY_SIZE(r->u8); i++) { \
2743 doit = doit && ((b->u8[i] & 0x7) == shift); \
2748 } else if (leftp) { \
2749 uint64_t carry = a->u64[LO_IDX] >> (64 - shift); \
2750 r->u64[HI_IDX] = (a->u64[HI_IDX] << shift) | carry; \
2751 r->u64[LO_IDX] = a->u64[LO_IDX] << shift; \
2753 uint64_t carry = a->u64[HI_IDX] << (64 - shift); \
2754 r->u64[LO_IDX] = (a->u64[LO_IDX] >> shift) | carry; \
2755 r->u64[HI_IDX] = a->u64[HI_IDX] >> shift; \
2765 #define VSL(suffix, element) \
2766 void helper_vsl##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
2769 for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
2770 unsigned int mask = ((1 << (3 + (sizeof (a->element[0]) >> 1))) - 1); \
2771 unsigned int shift = b->element[i] & mask; \
2772 r->element[i] = a->element[i] << shift; \
2780 void helper_vsldoi (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t shift)
2782 int sh = shift & 0xf;
2786 #if defined(WORDS_BIGENDIAN)
2787 for (i = 0; i < ARRAY_SIZE(r->u8); i++) {
2790 result.u8[i] = b->u8[index-0x10];
2792 result.u8[i] = a->u8[index];
2796 for (i = 0; i < ARRAY_SIZE(r->u8); i++) {
2797 int index = (16 - sh) + i;
2799 result.u8[i] = a->u8[index-0x10];
2801 result.u8[i] = b->u8[index];
2808 void helper_vslo (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
2810 int sh = (b->u8[LO_IDX*0xf] >> 3) & 0xf;
2812 #if defined (WORDS_BIGENDIAN)
2813 memmove (&r->u8[0], &a->u8[sh], 16-sh);
2814 memset (&r->u8[16-sh], 0, sh);
2816 memmove (&r->u8[sh], &a->u8[0], 16-sh);
2817 memset (&r->u8[0], 0, sh);
2821 /* Experimental testing shows that hardware masks the immediate. */
2822 #define _SPLAT_MASKED(element) (splat & (ARRAY_SIZE(r->element) - 1))
2823 #if defined(WORDS_BIGENDIAN)
2824 #define SPLAT_ELEMENT(element) _SPLAT_MASKED(element)
2826 #define SPLAT_ELEMENT(element) (ARRAY_SIZE(r->element)-1 - _SPLAT_MASKED(element))
2828 #define VSPLT(suffix, element) \
2829 void helper_vsplt##suffix (ppc_avr_t *r, ppc_avr_t *b, uint32_t splat) \
2831 uint32_t s = b->element[SPLAT_ELEMENT(element)]; \
2833 for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
2834 r->element[i] = s; \
2841 #undef SPLAT_ELEMENT
2842 #undef _SPLAT_MASKED
2844 #define VSPLTI(suffix, element, splat_type) \
2845 void helper_vspltis##suffix (ppc_avr_t *r, uint32_t splat) \
2847 splat_type x = (int8_t)(splat << 3) >> 3; \
2849 for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
2850 r->element[i] = x; \
2853 VSPLTI(b, s8, int8_t)
2854 VSPLTI(h, s16, int16_t)
2855 VSPLTI(w, s32, int32_t)
2858 #define VSR(suffix, element) \
2859 void helper_vsr##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
2862 for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
2863 unsigned int mask = ((1 << (3 + (sizeof (a->element[0]) >> 1))) - 1); \
2864 unsigned int shift = b->element[i] & mask; \
2865 r->element[i] = a->element[i] >> shift; \
2876 void helper_vsro (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
2878 int sh = (b->u8[LO_IDX*0xf] >> 3) & 0xf;
2880 #if defined (WORDS_BIGENDIAN)
2881 memmove (&r->u8[sh], &a->u8[0], 16-sh);
2882 memset (&r->u8[0], 0, sh);
2884 memmove (&r->u8[0], &a->u8[sh], 16-sh);
2885 memset (&r->u8[16-sh], 0, sh);
2889 void helper_vsubcuw (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
2892 for (i = 0; i < ARRAY_SIZE(r->u32); i++) {
2893 r->u32[i] = a->u32[i] >= b->u32[i];
2897 void helper_vsumsws (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
2904 #if defined(WORDS_BIGENDIAN)
2905 upper = ARRAY_SIZE(r->s32)-1;
2909 t = (int64_t)b->s32[upper];
2910 for (i = 0; i < ARRAY_SIZE(r->s32); i++) {
2914 result.s32[upper] = cvtsdsw(t, &sat);
2918 env->vscr |= (1 << VSCR_SAT);
2922 void helper_vsum2sws (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
2928 #if defined(WORDS_BIGENDIAN)
2933 for (i = 0; i < ARRAY_SIZE(r->u64); i++) {
2934 int64_t t = (int64_t)b->s32[upper+i*2];
2936 for (j = 0; j < ARRAY_SIZE(r->u64); j++) {
2939 result.s32[upper+i*2] = cvtsdsw(t, &sat);
2944 env->vscr |= (1 << VSCR_SAT);
2948 void helper_vsum4sbs (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
2953 for (i = 0; i < ARRAY_SIZE(r->s32); i++) {
2954 int64_t t = (int64_t)b->s32[i];
2955 for (j = 0; j < ARRAY_SIZE(r->s32); j++) {
2958 r->s32[i] = cvtsdsw(t, &sat);
2962 env->vscr |= (1 << VSCR_SAT);
2966 void helper_vsum4shs (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
2971 for (i = 0; i < ARRAY_SIZE(r->s32); i++) {
2972 int64_t t = (int64_t)b->s32[i];
2973 t += a->s16[2*i] + a->s16[2*i+1];
2974 r->s32[i] = cvtsdsw(t, &sat);
2978 env->vscr |= (1 << VSCR_SAT);
2982 void helper_vsum4ubs (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
2987 for (i = 0; i < ARRAY_SIZE(r->u32); i++) {
2988 uint64_t t = (uint64_t)b->u32[i];
2989 for (j = 0; j < ARRAY_SIZE(r->u32); j++) {
2992 r->u32[i] = cvtuduw(t, &sat);
2996 env->vscr |= (1 << VSCR_SAT);
3000 #if defined(WORDS_BIGENDIAN)
3007 #define VUPKPX(suffix, hi) \
3008 void helper_vupk##suffix (ppc_avr_t *r, ppc_avr_t *b) \
3012 for (i = 0; i < ARRAY_SIZE(r->u32); i++) { \
3013 uint16_t e = b->u16[hi ? i : i+4]; \
3014 uint8_t a = (e >> 15) ? 0xff : 0; \
3015 uint8_t r = (e >> 10) & 0x1f; \
3016 uint8_t g = (e >> 5) & 0x1f; \
3017 uint8_t b = e & 0x1f; \
3018 result.u32[i] = (a << 24) | (r << 16) | (g << 8) | b; \
3026 #define VUPK(suffix, unpacked, packee, hi) \
3027 void helper_vupk##suffix (ppc_avr_t *r, ppc_avr_t *b) \
3032 for (i = 0; i < ARRAY_SIZE(r->unpacked); i++) { \
3033 result.unpacked[i] = b->packee[i]; \
3036 for (i = ARRAY_SIZE(r->unpacked); i < ARRAY_SIZE(r->packee); i++) { \
3037 result.unpacked[i-ARRAY_SIZE(r->unpacked)] = b->packee[i]; \
3042 VUPK(hsb, s16, s8, UPKHI)
3043 VUPK(hsh, s32, s16, UPKHI)
3044 VUPK(lsb, s16, s8, UPKLO)
3045 VUPK(lsh, s32, s16, UPKLO)
3050 #undef DO_HANDLE_NAN
3054 #undef VECTOR_FOR_INORDER_I
3058 /*****************************************************************************/
3059 /* SPE extension helpers */
3060 /* Use a table to make this quicker */
3061 static uint8_t hbrev[16] = {
3062 0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE,
3063 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF,
3066 static always_inline uint8_t byte_reverse (uint8_t val)
3068 return hbrev[val >> 4] | (hbrev[val & 0xF] << 4);
3071 static always_inline uint32_t word_reverse (uint32_t val)
3073 return byte_reverse(val >> 24) | (byte_reverse(val >> 16) << 8) |
3074 (byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24);
3077 #define MASKBITS 16 // Random value - to be fixed (implementation dependant)
3078 target_ulong helper_brinc (target_ulong arg1, target_ulong arg2)
3080 uint32_t a, b, d, mask;
3082 mask = UINT32_MAX >> (32 - MASKBITS);
3085 d = word_reverse(1 + word_reverse(a | ~b));
3086 return (arg1 & ~mask) | (d & b);
3089 uint32_t helper_cntlsw32 (uint32_t val)
3091 if (val & 0x80000000)
3097 uint32_t helper_cntlzw32 (uint32_t val)
3102 /* Single-precision floating-point conversions */
3103 static always_inline uint32_t efscfsi (uint32_t val)
3107 u.f = int32_to_float32(val, &env->vec_status);
3112 static always_inline uint32_t efscfui (uint32_t val)
3116 u.f = uint32_to_float32(val, &env->vec_status);
3121 static always_inline int32_t efsctsi (uint32_t val)
3126 /* NaN are not treated the same way IEEE 754 does */
3127 if (unlikely(float32_is_nan(u.f)))
3130 return float32_to_int32(u.f, &env->vec_status);
3133 static always_inline uint32_t efsctui (uint32_t val)
3138 /* NaN are not treated the same way IEEE 754 does */
3139 if (unlikely(float32_is_nan(u.f)))
3142 return float32_to_uint32(u.f, &env->vec_status);
3145 static always_inline uint32_t efsctsiz (uint32_t val)
3150 /* NaN are not treated the same way IEEE 754 does */
3151 if (unlikely(float32_is_nan(u.f)))
3154 return float32_to_int32_round_to_zero(u.f, &env->vec_status);
3157 static always_inline uint32_t efsctuiz (uint32_t val)
3162 /* NaN are not treated the same way IEEE 754 does */
3163 if (unlikely(float32_is_nan(u.f)))
3166 return float32_to_uint32_round_to_zero(u.f, &env->vec_status);
3169 static always_inline uint32_t efscfsf (uint32_t val)
3174 u.f = int32_to_float32(val, &env->vec_status);
3175 tmp = int64_to_float32(1ULL << 32, &env->vec_status);
3176 u.f = float32_div(u.f, tmp, &env->vec_status);
3181 static always_inline uint32_t efscfuf (uint32_t val)
3186 u.f = uint32_to_float32(val, &env->vec_status);
3187 tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
3188 u.f = float32_div(u.f, tmp, &env->vec_status);
3193 static always_inline uint32_t efsctsf (uint32_t val)
3199 /* NaN are not treated the same way IEEE 754 does */
3200 if (unlikely(float32_is_nan(u.f)))
3202 tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
3203 u.f = float32_mul(u.f, tmp, &env->vec_status);
3205 return float32_to_int32(u.f, &env->vec_status);
3208 static always_inline uint32_t efsctuf (uint32_t val)
3214 /* NaN are not treated the same way IEEE 754 does */
3215 if (unlikely(float32_is_nan(u.f)))
3217 tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
3218 u.f = float32_mul(u.f, tmp, &env->vec_status);
3220 return float32_to_uint32(u.f, &env->vec_status);
3223 #define HELPER_SPE_SINGLE_CONV(name) \
3224 uint32_t helper_e##name (uint32_t val) \
3226 return e##name(val); \
3229 HELPER_SPE_SINGLE_CONV(fscfsi);
3231 HELPER_SPE_SINGLE_CONV(fscfui);
3233 HELPER_SPE_SINGLE_CONV(fscfuf);
3235 HELPER_SPE_SINGLE_CONV(fscfsf);
3237 HELPER_SPE_SINGLE_CONV(fsctsi);
3239 HELPER_SPE_SINGLE_CONV(fsctui);
3241 HELPER_SPE_SINGLE_CONV(fsctsiz);
3243 HELPER_SPE_SINGLE_CONV(fsctuiz);
3245 HELPER_SPE_SINGLE_CONV(fsctsf);
3247 HELPER_SPE_SINGLE_CONV(fsctuf);
3249 #define HELPER_SPE_VECTOR_CONV(name) \
3250 uint64_t helper_ev##name (uint64_t val) \
3252 return ((uint64_t)e##name(val >> 32) << 32) | \
3253 (uint64_t)e##name(val); \
3256 HELPER_SPE_VECTOR_CONV(fscfsi);
3258 HELPER_SPE_VECTOR_CONV(fscfui);
3260 HELPER_SPE_VECTOR_CONV(fscfuf);
3262 HELPER_SPE_VECTOR_CONV(fscfsf);
3264 HELPER_SPE_VECTOR_CONV(fsctsi);
3266 HELPER_SPE_VECTOR_CONV(fsctui);
3268 HELPER_SPE_VECTOR_CONV(fsctsiz);
3270 HELPER_SPE_VECTOR_CONV(fsctuiz);
3272 HELPER_SPE_VECTOR_CONV(fsctsf);
3274 HELPER_SPE_VECTOR_CONV(fsctuf);
3276 /* Single-precision floating-point arithmetic */
3277 static always_inline uint32_t efsadd (uint32_t op1, uint32_t op2)
3282 u1.f = float32_add(u1.f, u2.f, &env->vec_status);
3286 static always_inline uint32_t efssub (uint32_t op1, uint32_t op2)
3291 u1.f = float32_sub(u1.f, u2.f, &env->vec_status);
3295 static always_inline uint32_t efsmul (uint32_t op1, uint32_t op2)
3300 u1.f = float32_mul(u1.f, u2.f, &env->vec_status);
3304 static always_inline uint32_t efsdiv (uint32_t op1, uint32_t op2)
3309 u1.f = float32_div(u1.f, u2.f, &env->vec_status);
3313 #define HELPER_SPE_SINGLE_ARITH(name) \
3314 uint32_t helper_e##name (uint32_t op1, uint32_t op2) \
3316 return e##name(op1, op2); \
3319 HELPER_SPE_SINGLE_ARITH(fsadd);
3321 HELPER_SPE_SINGLE_ARITH(fssub);
3323 HELPER_SPE_SINGLE_ARITH(fsmul);
3325 HELPER_SPE_SINGLE_ARITH(fsdiv);
3327 #define HELPER_SPE_VECTOR_ARITH(name) \
3328 uint64_t helper_ev##name (uint64_t op1, uint64_t op2) \
3330 return ((uint64_t)e##name(op1 >> 32, op2 >> 32) << 32) | \
3331 (uint64_t)e##name(op1, op2); \
3334 HELPER_SPE_VECTOR_ARITH(fsadd);
3336 HELPER_SPE_VECTOR_ARITH(fssub);
3338 HELPER_SPE_VECTOR_ARITH(fsmul);
3340 HELPER_SPE_VECTOR_ARITH(fsdiv);
3342 /* Single-precision floating-point comparisons */
3343 static always_inline uint32_t efststlt (uint32_t op1, uint32_t op2)
3348 return float32_lt(u1.f, u2.f, &env->vec_status) ? 4 : 0;
3351 static always_inline uint32_t efststgt (uint32_t op1, uint32_t op2)
3356 return float32_le(u1.f, u2.f, &env->vec_status) ? 0 : 4;
3359 static always_inline uint32_t efststeq (uint32_t op1, uint32_t op2)
3364 return float32_eq(u1.f, u2.f, &env->vec_status) ? 4 : 0;
3367 static always_inline uint32_t efscmplt (uint32_t op1, uint32_t op2)
3369 /* XXX: TODO: test special values (NaN, infinites, ...) */
3370 return efststlt(op1, op2);
3373 static always_inline uint32_t efscmpgt (uint32_t op1, uint32_t op2)
3375 /* XXX: TODO: test special values (NaN, infinites, ...) */
3376 return efststgt(op1, op2);
3379 static always_inline uint32_t efscmpeq (uint32_t op1, uint32_t op2)
3381 /* XXX: TODO: test special values (NaN, infinites, ...) */
3382 return efststeq(op1, op2);
3385 #define HELPER_SINGLE_SPE_CMP(name) \
3386 uint32_t helper_e##name (uint32_t op1, uint32_t op2) \
3388 return e##name(op1, op2) << 2; \
3391 HELPER_SINGLE_SPE_CMP(fststlt);
3393 HELPER_SINGLE_SPE_CMP(fststgt);
3395 HELPER_SINGLE_SPE_CMP(fststeq);
3397 HELPER_SINGLE_SPE_CMP(fscmplt);
3399 HELPER_SINGLE_SPE_CMP(fscmpgt);
3401 HELPER_SINGLE_SPE_CMP(fscmpeq);
3403 static always_inline uint32_t evcmp_merge (int t0, int t1)
3405 return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
3408 #define HELPER_VECTOR_SPE_CMP(name) \
3409 uint32_t helper_ev##name (uint64_t op1, uint64_t op2) \
3411 return evcmp_merge(e##name(op1 >> 32, op2 >> 32), e##name(op1, op2)); \
3414 HELPER_VECTOR_SPE_CMP(fststlt);
3416 HELPER_VECTOR_SPE_CMP(fststgt);
3418 HELPER_VECTOR_SPE_CMP(fststeq);
3420 HELPER_VECTOR_SPE_CMP(fscmplt);
3422 HELPER_VECTOR_SPE_CMP(fscmpgt);
3424 HELPER_VECTOR_SPE_CMP(fscmpeq);
3426 /* Double-precision floating-point conversion */
3427 uint64_t helper_efdcfsi (uint32_t val)
3431 u.d = int32_to_float64(val, &env->vec_status);
3436 uint64_t helper_efdcfsid (uint64_t val)
3440 u.d = int64_to_float64(val, &env->vec_status);
3445 uint64_t helper_efdcfui (uint32_t val)
3449 u.d = uint32_to_float64(val, &env->vec_status);
3454 uint64_t helper_efdcfuid (uint64_t val)
3458 u.d = uint64_to_float64(val, &env->vec_status);
3463 uint32_t helper_efdctsi (uint64_t val)
3468 /* NaN are not treated the same way IEEE 754 does */
3469 if (unlikely(float64_is_nan(u.d)))
3472 return float64_to_int32(u.d, &env->vec_status);
3475 uint32_t helper_efdctui (uint64_t val)
3480 /* NaN are not treated the same way IEEE 754 does */
3481 if (unlikely(float64_is_nan(u.d)))
3484 return float64_to_uint32(u.d, &env->vec_status);
3487 uint32_t helper_efdctsiz (uint64_t val)
3492 /* NaN are not treated the same way IEEE 754 does */
3493 if (unlikely(float64_is_nan(u.d)))
3496 return float64_to_int32_round_to_zero(u.d, &env->vec_status);
3499 uint64_t helper_efdctsidz (uint64_t val)
3504 /* NaN are not treated the same way IEEE 754 does */
3505 if (unlikely(float64_is_nan(u.d)))
3508 return float64_to_int64_round_to_zero(u.d, &env->vec_status);
3511 uint32_t helper_efdctuiz (uint64_t val)
3516 /* NaN are not treated the same way IEEE 754 does */
3517 if (unlikely(float64_is_nan(u.d)))
3520 return float64_to_uint32_round_to_zero(u.d, &env->vec_status);
3523 uint64_t helper_efdctuidz (uint64_t val)
3528 /* NaN are not treated the same way IEEE 754 does */
3529 if (unlikely(float64_is_nan(u.d)))
3532 return float64_to_uint64_round_to_zero(u.d, &env->vec_status);
3535 uint64_t helper_efdcfsf (uint32_t val)
3540 u.d = int32_to_float64(val, &env->vec_status);
3541 tmp = int64_to_float64(1ULL << 32, &env->vec_status);
3542 u.d = float64_div(u.d, tmp, &env->vec_status);
3547 uint64_t helper_efdcfuf (uint32_t val)
3552 u.d = uint32_to_float64(val, &env->vec_status);
3553 tmp = int64_to_float64(1ULL << 32, &env->vec_status);
3554 u.d = float64_div(u.d, tmp, &env->vec_status);
3559 uint32_t helper_efdctsf (uint64_t val)
3565 /* NaN are not treated the same way IEEE 754 does */
3566 if (unlikely(float64_is_nan(u.d)))
3568 tmp = uint64_to_float64(1ULL << 32, &env->vec_status);
3569 u.d = float64_mul(u.d, tmp, &env->vec_status);
3571 return float64_to_int32(u.d, &env->vec_status);
3574 uint32_t helper_efdctuf (uint64_t val)
3580 /* NaN are not treated the same way IEEE 754 does */
3581 if (unlikely(float64_is_nan(u.d)))
3583 tmp = uint64_to_float64(1ULL << 32, &env->vec_status);
3584 u.d = float64_mul(u.d, tmp, &env->vec_status);
3586 return float64_to_uint32(u.d, &env->vec_status);
3589 uint32_t helper_efscfd (uint64_t val)
3595 u2.f = float64_to_float32(u1.d, &env->vec_status);
3600 uint64_t helper_efdcfs (uint32_t val)
3606 u2.d = float32_to_float64(u1.f, &env->vec_status);
3611 /* Double precision fixed-point arithmetic */
3612 uint64_t helper_efdadd (uint64_t op1, uint64_t op2)
3617 u1.d = float64_add(u1.d, u2.d, &env->vec_status);
3621 uint64_t helper_efdsub (uint64_t op1, uint64_t op2)
3626 u1.d = float64_sub(u1.d, u2.d, &env->vec_status);
3630 uint64_t helper_efdmul (uint64_t op1, uint64_t op2)
3635 u1.d = float64_mul(u1.d, u2.d, &env->vec_status);
3639 uint64_t helper_efddiv (uint64_t op1, uint64_t op2)
3644 u1.d = float64_div(u1.d, u2.d, &env->vec_status);
3648 /* Double precision floating point helpers */
3649 uint32_t helper_efdtstlt (uint64_t op1, uint64_t op2)
3654 return float64_lt(u1.d, u2.d, &env->vec_status) ? 4 : 0;
3657 uint32_t helper_efdtstgt (uint64_t op1, uint64_t op2)
3662 return float64_le(u1.d, u2.d, &env->vec_status) ? 0 : 4;
3665 uint32_t helper_efdtsteq (uint64_t op1, uint64_t op2)
3670 return float64_eq(u1.d, u2.d, &env->vec_status) ? 4 : 0;
3673 uint32_t helper_efdcmplt (uint64_t op1, uint64_t op2)
3675 /* XXX: TODO: test special values (NaN, infinites, ...) */
3676 return helper_efdtstlt(op1, op2);
3679 uint32_t helper_efdcmpgt (uint64_t op1, uint64_t op2)
3681 /* XXX: TODO: test special values (NaN, infinites, ...) */
3682 return helper_efdtstgt(op1, op2);
3685 uint32_t helper_efdcmpeq (uint64_t op1, uint64_t op2)
3687 /* XXX: TODO: test special values (NaN, infinites, ...) */
3688 return helper_efdtsteq(op1, op2);
3691 /*****************************************************************************/
3692 /* Softmmu support */
3693 #if !defined (CONFIG_USER_ONLY)
3695 #define MMUSUFFIX _mmu
3698 #include "softmmu_template.h"
3701 #include "softmmu_template.h"
3704 #include "softmmu_template.h"
3707 #include "softmmu_template.h"
3709 /* try to fill the TLB and return an exception if error. If retaddr is
3710 NULL, it means that the function was called in C code (i.e. not
3711 from generated code or from helper.c) */
3712 /* XXX: fix it to restore all registers */
3713 void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
3715 TranslationBlock *tb;
3716 CPUState *saved_env;
3720 /* XXX: hack to restore env in all cases, even if not called from
3723 env = cpu_single_env;
3724 ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
3725 if (unlikely(ret != 0)) {
3726 if (likely(retaddr)) {
3727 /* now we have a real cpu fault */
3728 pc = (unsigned long)retaddr;
3729 tb = tb_find_pc(pc);
3731 /* the PC is inside the translated code. It means that we have
3732 a virtual CPU fault */
3733 cpu_restore_state(tb, env, pc, NULL);
3736 helper_raise_exception_err(env->exception_index, env->error_code);
3741 /* Segment registers load and store */
3742 target_ulong helper_load_sr (target_ulong sr_num)
3744 return env->sr[sr_num];
3747 void helper_store_sr (target_ulong sr_num, target_ulong val)
3749 ppc_store_sr(env, sr_num, val);
3752 /* SLB management */
3753 #if defined(TARGET_PPC64)
3754 target_ulong helper_load_slb (target_ulong slb_nr)
3756 return ppc_load_slb(env, slb_nr);
3759 void helper_store_slb (target_ulong slb_nr, target_ulong rs)
3761 ppc_store_slb(env, slb_nr, rs);
3764 void helper_slbia (void)
3766 ppc_slb_invalidate_all(env);
3769 void helper_slbie (target_ulong addr)
3771 ppc_slb_invalidate_one(env, addr);
3774 #endif /* defined(TARGET_PPC64) */
3776 /* TLB management */
3777 void helper_tlbia (void)
3779 ppc_tlb_invalidate_all(env);
3782 void helper_tlbie (target_ulong addr)
3784 ppc_tlb_invalidate_one(env, addr);
3787 /* Software driven TLBs management */
3788 /* PowerPC 602/603 software TLB load instructions helpers */
3789 static void do_6xx_tlb (target_ulong new_EPN, int is_code)
3791 target_ulong RPN, CMP, EPN;
3794 RPN = env->spr[SPR_RPA];
3796 CMP = env->spr[SPR_ICMP];
3797 EPN = env->spr[SPR_IMISS];
3799 CMP = env->spr[SPR_DCMP];
3800 EPN = env->spr[SPR_DMISS];
3802 way = (env->spr[SPR_SRR1] >> 17) & 1;
3803 LOG_SWTLB("%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX
3804 " PTE1 " ADDRX " way %d\n",
3805 __func__, new_EPN, EPN, CMP, RPN, way);
3806 /* Store this TLB */
3807 ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
3808 way, is_code, CMP, RPN);
3811 void helper_6xx_tlbd (target_ulong EPN)
3816 void helper_6xx_tlbi (target_ulong EPN)
3821 /* PowerPC 74xx software TLB load instructions helpers */
3822 static void do_74xx_tlb (target_ulong new_EPN, int is_code)
3824 target_ulong RPN, CMP, EPN;
3827 RPN = env->spr[SPR_PTELO];
3828 CMP = env->spr[SPR_PTEHI];
3829 EPN = env->spr[SPR_TLBMISS] & ~0x3;
3830 way = env->spr[SPR_TLBMISS] & 0x3;
3831 LOG_SWTLB("%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX
3832 " PTE1 " ADDRX " way %d\n",
3833 __func__, new_EPN, EPN, CMP, RPN, way);
3834 /* Store this TLB */
3835 ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
3836 way, is_code, CMP, RPN);
3839 void helper_74xx_tlbd (target_ulong EPN)
3841 do_74xx_tlb(EPN, 0);
3844 void helper_74xx_tlbi (target_ulong EPN)
3846 do_74xx_tlb(EPN, 1);
3849 static always_inline target_ulong booke_tlb_to_page_size (int size)
3851 return 1024 << (2 * size);
3854 static always_inline int booke_page_size_to_tlb (target_ulong page_size)
3858 switch (page_size) {
3892 #if defined (TARGET_PPC64)
3893 case 0x000100000000ULL:
3896 case 0x000400000000ULL:
3899 case 0x001000000000ULL:
3902 case 0x004000000000ULL:
3905 case 0x010000000000ULL:
3917 /* Helpers for 4xx TLB management */
3918 target_ulong helper_4xx_tlbre_lo (target_ulong entry)
3925 tlb = &env->tlb[entry].tlbe;
3927 if (tlb->prot & PAGE_VALID)
3929 size = booke_page_size_to_tlb(tlb->size);
3930 if (size < 0 || size > 0x7)
3933 env->spr[SPR_40x_PID] = tlb->PID;
3937 target_ulong helper_4xx_tlbre_hi (target_ulong entry)
3943 tlb = &env->tlb[entry].tlbe;
3945 if (tlb->prot & PAGE_EXEC)
3947 if (tlb->prot & PAGE_WRITE)
3952 void helper_4xx_tlbwe_hi (target_ulong entry, target_ulong val)
3955 target_ulong page, end;
3957 LOG_SWTLB("%s entry %d val " ADDRX "\n", __func__, (int)entry, val);
3959 tlb = &env->tlb[entry].tlbe;
3960 /* Invalidate previous TLB (if it's valid) */
3961 if (tlb->prot & PAGE_VALID) {
3962 end = tlb->EPN + tlb->size;
3963 LOG_SWTLB("%s: invalidate old TLB %d start " ADDRX
3964 " end " ADDRX "\n", __func__, (int)entry, tlb->EPN, end);
3965 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
3966 tlb_flush_page(env, page);
3968 tlb->size = booke_tlb_to_page_size((val >> 7) & 0x7);
3969 /* We cannot handle TLB size < TARGET_PAGE_SIZE.
3970 * If this ever occurs, one should use the ppcemb target instead
3971 * of the ppc or ppc64 one
3973 if ((val & 0x40) && tlb->size < TARGET_PAGE_SIZE) {
3974 cpu_abort(env, "TLB size " TARGET_FMT_lu " < %u "
3975 "are not supported (%d)\n",
3976 tlb->size, TARGET_PAGE_SIZE, (int)((val >> 7) & 0x7));
3978 tlb->EPN = val & ~(tlb->size - 1);
3980 tlb->prot |= PAGE_VALID;
3982 tlb->prot &= ~PAGE_VALID;
3984 /* XXX: TO BE FIXED */
3985 cpu_abort(env, "Little-endian TLB entries are not supported by now\n");
3987 tlb->PID = env->spr[SPR_40x_PID]; /* PID */
3988 tlb->attr = val & 0xFF;
3989 LOG_SWTLB("%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
3990 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
3991 (int)entry, tlb->RPN, tlb->EPN, tlb->size,
3992 tlb->prot & PAGE_READ ? 'r' : '-',
3993 tlb->prot & PAGE_WRITE ? 'w' : '-',
3994 tlb->prot & PAGE_EXEC ? 'x' : '-',
3995 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
3996 /* Invalidate new TLB (if valid) */
3997 if (tlb->prot & PAGE_VALID) {
3998 end = tlb->EPN + tlb->size;
3999 LOG_SWTLB("%s: invalidate TLB %d start " ADDRX
4000 " end " ADDRX "\n", __func__, (int)entry, tlb->EPN, end);
4001 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
4002 tlb_flush_page(env, page);
4006 void helper_4xx_tlbwe_lo (target_ulong entry, target_ulong val)
4010 LOG_SWTLB("%s entry %i val " ADDRX "\n", __func__, (int)entry, val);
4012 tlb = &env->tlb[entry].tlbe;
4013 tlb->RPN = val & 0xFFFFFC00;
4014 tlb->prot = PAGE_READ;
4016 tlb->prot |= PAGE_EXEC;
4018 tlb->prot |= PAGE_WRITE;
4019 LOG_SWTLB("%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
4020 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
4021 (int)entry, tlb->RPN, tlb->EPN, tlb->size,
4022 tlb->prot & PAGE_READ ? 'r' : '-',
4023 tlb->prot & PAGE_WRITE ? 'w' : '-',
4024 tlb->prot & PAGE_EXEC ? 'x' : '-',
4025 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
4028 target_ulong helper_4xx_tlbsx (target_ulong address)
4030 return ppcemb_tlb_search(env, address, env->spr[SPR_40x_PID]);
4033 /* PowerPC 440 TLB management */
4034 void helper_440_tlbwe (uint32_t word, target_ulong entry, target_ulong value)
4037 target_ulong EPN, RPN, size;
4040 LOG_SWTLB("%s word %d entry %d value " ADDRX "\n",
4041 __func__, word, (int)entry, value);
4044 tlb = &env->tlb[entry].tlbe;
4047 /* Just here to please gcc */
4049 EPN = value & 0xFFFFFC00;
4050 if ((tlb->prot & PAGE_VALID) && EPN != tlb->EPN)
4053 size = booke_tlb_to_page_size((value >> 4) & 0xF);
4054 if ((tlb->prot & PAGE_VALID) && tlb->size < size)
4058 tlb->attr |= (value >> 8) & 1;
4059 if (value & 0x200) {
4060 tlb->prot |= PAGE_VALID;
4062 if (tlb->prot & PAGE_VALID) {
4063 tlb->prot &= ~PAGE_VALID;
4067 tlb->PID = env->spr[SPR_440_MMUCR] & 0x000000FF;
4072 RPN = value & 0xFFFFFC0F;
4073 if ((tlb->prot & PAGE_VALID) && tlb->RPN != RPN)
4078 tlb->attr = (tlb->attr & 0x1) | (value & 0x0000FF00);
4079 tlb->prot = tlb->prot & PAGE_VALID;
4081 tlb->prot |= PAGE_READ << 4;
4083 tlb->prot |= PAGE_WRITE << 4;
4085 tlb->prot |= PAGE_EXEC << 4;
4087 tlb->prot |= PAGE_READ;
4089 tlb->prot |= PAGE_WRITE;
4091 tlb->prot |= PAGE_EXEC;
4096 target_ulong helper_440_tlbre (uint32_t word, target_ulong entry)
4103 tlb = &env->tlb[entry].tlbe;
4106 /* Just here to please gcc */
4109 size = booke_page_size_to_tlb(tlb->size);
4110 if (size < 0 || size > 0xF)
4113 if (tlb->attr & 0x1)
4115 if (tlb->prot & PAGE_VALID)
4117 env->spr[SPR_440_MMUCR] &= ~0x000000FF;
4118 env->spr[SPR_440_MMUCR] |= tlb->PID;
4124 ret = tlb->attr & ~0x1;
4125 if (tlb->prot & (PAGE_READ << 4))
4127 if (tlb->prot & (PAGE_WRITE << 4))
4129 if (tlb->prot & (PAGE_EXEC << 4))
4131 if (tlb->prot & PAGE_READ)
4133 if (tlb->prot & PAGE_WRITE)
4135 if (tlb->prot & PAGE_EXEC)
4142 target_ulong helper_440_tlbsx (target_ulong address)
4144 return ppcemb_tlb_search(env, address, env->spr[SPR_440_MMUCR] & 0xFF);
4147 #endif /* !CONFIG_USER_ONLY */