2 * PowerPC emulation helpers for qemu.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include "host-utils.h"
24 #include "helper_regs.h"
25 #include "op_helper.h"
27 #define MEMSUFFIX _raw
28 #include "op_helper.h"
29 #include "op_helper_mem.h"
30 #if !defined(CONFIG_USER_ONLY)
31 #define MEMSUFFIX _user
32 #include "op_helper.h"
33 #include "op_helper_mem.h"
34 #define MEMSUFFIX _kernel
35 #include "op_helper.h"
36 #include "op_helper_mem.h"
37 #define MEMSUFFIX _hypv
38 #include "op_helper.h"
39 #include "op_helper_mem.h"
43 //#define DEBUG_EXCEPTIONS
44 //#define DEBUG_SOFTWARE_TLB
46 /*****************************************************************************/
47 /* Exceptions processing helpers */
49 void helper_raise_exception_err (uint32_t exception, uint32_t error_code)
51 raise_exception_err(env, exception, error_code);
54 void helper_raise_debug (void)
56 raise_exception(env, EXCP_DEBUG);
60 /*****************************************************************************/
61 /* Registers load and stores */
62 target_ulong helper_load_cr (void)
64 return (env->crf[0] << 28) |
74 void helper_store_cr (target_ulong val, uint32_t mask)
78 for (i = 0, sh = 7; i < 8; i++, sh--) {
80 env->crf[i] = (val >> (sh * 4)) & 0xFUL;
84 #if defined(TARGET_PPC64)
85 void do_store_pri (int prio)
87 env->spr[SPR_PPR] &= ~0x001C000000000000ULL;
88 env->spr[SPR_PPR] |= ((uint64_t)prio & 0x7) << 50;
92 target_ulong ppc_load_dump_spr (int sprn)
95 fprintf(logfile, "Read SPR %d %03x => " ADDRX "\n",
96 sprn, sprn, env->spr[sprn]);
99 return env->spr[sprn];
102 void ppc_store_dump_spr (int sprn, target_ulong val)
105 fprintf(logfile, "Write SPR %d %03x => " ADDRX " <= " ADDRX "\n",
106 sprn, sprn, env->spr[sprn], val);
108 env->spr[sprn] = val;
111 /*****************************************************************************/
112 /* Fixed point operations helpers */
113 #if defined(TARGET_PPC64)
115 /* multiply high word */
116 uint64_t helper_mulhd (uint64_t arg1, uint64_t arg2)
120 muls64(&tl, &th, arg1, arg2);
124 /* multiply high word unsigned */
125 uint64_t helper_mulhdu (uint64_t arg1, uint64_t arg2)
129 mulu64(&tl, &th, arg1, arg2);
133 uint64_t helper_mulldo (uint64_t arg1, uint64_t arg2)
138 muls64(&tl, (uint64_t *)&th, arg1, arg2);
139 /* If th != 0 && th != -1, then we had an overflow */
140 if (likely((uint64_t)(th + 1) <= 1)) {
141 env->xer &= ~(1 << XER_OV);
143 env->xer |= (1 << XER_OV) | (1 << XER_SO);
149 target_ulong helper_cntlzw (target_ulong t)
154 #if defined(TARGET_PPC64)
155 target_ulong helper_cntlzd (target_ulong t)
161 /* shift right arithmetic helper */
162 target_ulong helper_sraw (target_ulong value, target_ulong shift)
166 if (likely(!(shift & 0x20))) {
167 if (likely((uint32_t)shift != 0)) {
169 ret = (int32_t)value >> shift;
170 if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
171 env->xer &= ~(1 << XER_CA);
173 env->xer |= (1 << XER_CA);
176 ret = (int32_t)value;
177 env->xer &= ~(1 << XER_CA);
180 ret = (int32_t)value >> 31;
182 env->xer |= (1 << XER_CA);
184 env->xer &= ~(1 << XER_CA);
187 return (target_long)ret;
190 #if defined(TARGET_PPC64)
191 target_ulong helper_srad (target_ulong value, target_ulong shift)
195 if (likely(!(shift & 0x40))) {
196 if (likely((uint64_t)shift != 0)) {
198 ret = (int64_t)value >> shift;
199 if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
200 env->xer &= ~(1 << XER_CA);
202 env->xer |= (1 << XER_CA);
205 ret = (int64_t)value;
206 env->xer &= ~(1 << XER_CA);
209 ret = (int64_t)value >> 63;
211 env->xer |= (1 << XER_CA);
213 env->xer &= ~(1 << XER_CA);
220 target_ulong helper_popcntb (target_ulong val)
222 val = (val & 0x55555555) + ((val >> 1) & 0x55555555);
223 val = (val & 0x33333333) + ((val >> 2) & 0x33333333);
224 val = (val & 0x0f0f0f0f) + ((val >> 4) & 0x0f0f0f0f);
228 #if defined(TARGET_PPC64)
229 target_ulong helper_popcntb_64 (target_ulong val)
231 val = (val & 0x5555555555555555ULL) + ((val >> 1) & 0x5555555555555555ULL);
232 val = (val & 0x3333333333333333ULL) + ((val >> 2) & 0x3333333333333333ULL);
233 val = (val & 0x0f0f0f0f0f0f0f0fULL) + ((val >> 4) & 0x0f0f0f0f0f0f0f0fULL);
238 /*****************************************************************************/
239 /* Floating point operations helpers */
240 uint64_t helper_float32_to_float64(uint32_t arg)
245 d.d = float32_to_float64(f.f, &env->fp_status);
249 uint32_t helper_float64_to_float32(uint64_t arg)
254 f.f = float64_to_float32(d.d, &env->fp_status);
258 static always_inline int fpisneg (float64 d)
264 return u.ll >> 63 != 0;
267 static always_inline int isden (float64 d)
273 return ((u.ll >> 52) & 0x7FF) == 0;
276 static always_inline int iszero (float64 d)
282 return (u.ll & ~0x8000000000000000ULL) == 0;
285 static always_inline int isinfinity (float64 d)
291 return ((u.ll >> 52) & 0x7FF) == 0x7FF &&
292 (u.ll & 0x000FFFFFFFFFFFFFULL) == 0;
295 #ifdef CONFIG_SOFTFLOAT
296 static always_inline int isfinite (float64 d)
302 return (((u.ll >> 52) & 0x7FF) != 0x7FF);
305 static always_inline int isnormal (float64 d)
311 uint32_t exp = (u.ll >> 52) & 0x7FF;
312 return ((0 < exp) && (exp < 0x7FF));
316 uint32_t helper_compute_fprf (uint64_t arg, uint32_t set_fprf)
322 isneg = fpisneg(farg.d);
323 if (unlikely(float64_is_nan(farg.d))) {
324 if (float64_is_signaling_nan(farg.d)) {
325 /* Signaling NaN: flags are undefined */
331 } else if (unlikely(isinfinity(farg.d))) {
338 if (iszero(farg.d)) {
346 /* Denormalized numbers */
349 /* Normalized numbers */
360 /* We update FPSCR_FPRF */
361 env->fpscr &= ~(0x1F << FPSCR_FPRF);
362 env->fpscr |= ret << FPSCR_FPRF;
364 /* We just need fpcc to update Rc1 */
368 /* Floating-point invalid operations exception */
369 static always_inline uint64_t fload_invalid_op_excp (int op)
375 if (op & POWERPC_EXCP_FP_VXSNAN) {
376 /* Operation on signaling NaN */
377 env->fpscr |= 1 << FPSCR_VXSNAN;
379 if (op & POWERPC_EXCP_FP_VXSOFT) {
380 /* Software-defined condition */
381 env->fpscr |= 1 << FPSCR_VXSOFT;
383 switch (op & ~(POWERPC_EXCP_FP_VXSOFT | POWERPC_EXCP_FP_VXSNAN)) {
384 case POWERPC_EXCP_FP_VXISI:
385 /* Magnitude subtraction of infinities */
386 env->fpscr |= 1 << FPSCR_VXISI;
388 case POWERPC_EXCP_FP_VXIDI:
389 /* Division of infinity by infinity */
390 env->fpscr |= 1 << FPSCR_VXIDI;
392 case POWERPC_EXCP_FP_VXZDZ:
393 /* Division of zero by zero */
394 env->fpscr |= 1 << FPSCR_VXZDZ;
396 case POWERPC_EXCP_FP_VXIMZ:
397 /* Multiplication of zero by infinity */
398 env->fpscr |= 1 << FPSCR_VXIMZ;
400 case POWERPC_EXCP_FP_VXVC:
401 /* Ordered comparison of NaN */
402 env->fpscr |= 1 << FPSCR_VXVC;
403 env->fpscr &= ~(0xF << FPSCR_FPCC);
404 env->fpscr |= 0x11 << FPSCR_FPCC;
405 /* We must update the target FPR before raising the exception */
407 env->exception_index = POWERPC_EXCP_PROGRAM;
408 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
409 /* Update the floating-point enabled exception summary */
410 env->fpscr |= 1 << FPSCR_FEX;
411 /* Exception is differed */
415 case POWERPC_EXCP_FP_VXSQRT:
416 /* Square root of a negative number */
417 env->fpscr |= 1 << FPSCR_VXSQRT;
419 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
421 /* Set the result to quiet NaN */
423 env->fpscr &= ~(0xF << FPSCR_FPCC);
424 env->fpscr |= 0x11 << FPSCR_FPCC;
427 case POWERPC_EXCP_FP_VXCVI:
428 /* Invalid conversion */
429 env->fpscr |= 1 << FPSCR_VXCVI;
430 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
432 /* Set the result to quiet NaN */
434 env->fpscr &= ~(0xF << FPSCR_FPCC);
435 env->fpscr |= 0x11 << FPSCR_FPCC;
439 /* Update the floating-point invalid operation summary */
440 env->fpscr |= 1 << FPSCR_VX;
441 /* Update the floating-point exception summary */
442 env->fpscr |= 1 << FPSCR_FX;
444 /* Update the floating-point enabled exception summary */
445 env->fpscr |= 1 << FPSCR_FEX;
446 if (msr_fe0 != 0 || msr_fe1 != 0)
447 raise_exception_err(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_FP | op);
452 static always_inline uint64_t float_zero_divide_excp (uint64_t arg1, uint64_t arg2)
454 env->fpscr |= 1 << FPSCR_ZX;
455 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
456 /* Update the floating-point exception summary */
457 env->fpscr |= 1 << FPSCR_FX;
459 /* Update the floating-point enabled exception summary */
460 env->fpscr |= 1 << FPSCR_FEX;
461 if (msr_fe0 != 0 || msr_fe1 != 0) {
462 raise_exception_err(env, POWERPC_EXCP_PROGRAM,
463 POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX);
466 /* Set the result to infinity */
467 arg1 = ((arg1 ^ arg2) & 0x8000000000000000ULL);
468 arg1 |= 0x7FFULL << 52;
473 static always_inline void float_overflow_excp (void)
475 env->fpscr |= 1 << FPSCR_OX;
476 /* Update the floating-point exception summary */
477 env->fpscr |= 1 << FPSCR_FX;
479 /* XXX: should adjust the result */
480 /* Update the floating-point enabled exception summary */
481 env->fpscr |= 1 << FPSCR_FEX;
482 /* We must update the target FPR before raising the exception */
483 env->exception_index = POWERPC_EXCP_PROGRAM;
484 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
486 env->fpscr |= 1 << FPSCR_XX;
487 env->fpscr |= 1 << FPSCR_FI;
491 static always_inline void float_underflow_excp (void)
493 env->fpscr |= 1 << FPSCR_UX;
494 /* Update the floating-point exception summary */
495 env->fpscr |= 1 << FPSCR_FX;
497 /* XXX: should adjust the result */
498 /* Update the floating-point enabled exception summary */
499 env->fpscr |= 1 << FPSCR_FEX;
500 /* We must update the target FPR before raising the exception */
501 env->exception_index = POWERPC_EXCP_PROGRAM;
502 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
506 static always_inline void float_inexact_excp (void)
508 env->fpscr |= 1 << FPSCR_XX;
509 /* Update the floating-point exception summary */
510 env->fpscr |= 1 << FPSCR_FX;
512 /* Update the floating-point enabled exception summary */
513 env->fpscr |= 1 << FPSCR_FEX;
514 /* We must update the target FPR before raising the exception */
515 env->exception_index = POWERPC_EXCP_PROGRAM;
516 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
520 static always_inline void fpscr_set_rounding_mode (void)
524 /* Set rounding mode */
527 /* Best approximation (round to nearest) */
528 rnd_type = float_round_nearest_even;
531 /* Smaller magnitude (round toward zero) */
532 rnd_type = float_round_to_zero;
535 /* Round toward +infinite */
536 rnd_type = float_round_up;
540 /* Round toward -infinite */
541 rnd_type = float_round_down;
544 set_float_rounding_mode(rnd_type, &env->fp_status);
547 void helper_fpscr_setbit (uint32_t bit)
551 prev = (env->fpscr >> bit) & 1;
552 env->fpscr |= 1 << bit;
556 env->fpscr |= 1 << FPSCR_FX;
560 env->fpscr |= 1 << FPSCR_FX;
565 env->fpscr |= 1 << FPSCR_FX;
570 env->fpscr |= 1 << FPSCR_FX;
575 env->fpscr |= 1 << FPSCR_FX;
588 env->fpscr |= 1 << FPSCR_VX;
589 env->fpscr |= 1 << FPSCR_FX;
596 env->error_code = POWERPC_EXCP_FP;
598 env->error_code |= POWERPC_EXCP_FP_VXSNAN;
600 env->error_code |= POWERPC_EXCP_FP_VXISI;
602 env->error_code |= POWERPC_EXCP_FP_VXIDI;
604 env->error_code |= POWERPC_EXCP_FP_VXZDZ;
606 env->error_code |= POWERPC_EXCP_FP_VXIMZ;
608 env->error_code |= POWERPC_EXCP_FP_VXVC;
610 env->error_code |= POWERPC_EXCP_FP_VXSOFT;
612 env->error_code |= POWERPC_EXCP_FP_VXSQRT;
614 env->error_code |= POWERPC_EXCP_FP_VXCVI;
621 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
628 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
635 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX;
642 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
648 fpscr_set_rounding_mode();
653 /* Update the floating-point enabled exception summary */
654 env->fpscr |= 1 << FPSCR_FEX;
655 /* We have to update Rc1 before raising the exception */
656 env->exception_index = POWERPC_EXCP_PROGRAM;
662 void helper_store_fpscr (uint64_t arg, uint32_t mask)
665 * We use only the 32 LSB of the incoming fpr
673 new |= prev & 0x90000000;
674 for (i = 0; i < 7; i++) {
675 if (mask & (1 << i)) {
676 env->fpscr &= ~(0xF << (4 * i));
677 env->fpscr |= new & (0xF << (4 * i));
680 /* Update VX and FEX */
682 env->fpscr |= 1 << FPSCR_VX;
684 env->fpscr &= ~(1 << FPSCR_VX);
685 if ((fpscr_ex & fpscr_eex) != 0) {
686 env->fpscr |= 1 << FPSCR_FEX;
687 env->exception_index = POWERPC_EXCP_PROGRAM;
688 /* XXX: we should compute it properly */
689 env->error_code = POWERPC_EXCP_FP;
692 env->fpscr &= ~(1 << FPSCR_FEX);
693 fpscr_set_rounding_mode();
696 void helper_float_check_status (void)
698 #ifdef CONFIG_SOFTFLOAT
699 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
700 (env->error_code & POWERPC_EXCP_FP)) {
701 /* Differred floating-point exception after target FPR update */
702 if (msr_fe0 != 0 || msr_fe1 != 0)
703 raise_exception_err(env, env->exception_index, env->error_code);
704 } else if (env->fp_status.float_exception_flags & float_flag_overflow) {
705 float_overflow_excp();
706 } else if (env->fp_status.float_exception_flags & float_flag_underflow) {
707 float_underflow_excp();
708 } else if (env->fp_status.float_exception_flags & float_flag_inexact) {
709 float_inexact_excp();
712 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
713 (env->error_code & POWERPC_EXCP_FP)) {
714 /* Differred floating-point exception after target FPR update */
715 if (msr_fe0 != 0 || msr_fe1 != 0)
716 raise_exception_err(env, env->exception_index, env->error_code);
722 #ifdef CONFIG_SOFTFLOAT
723 void helper_reset_fpstatus (void)
725 env->fp_status.float_exception_flags = 0;
730 uint64_t helper_fadd (uint64_t arg1, uint64_t arg2)
732 CPU_DoubleU farg1, farg2;
736 #if USE_PRECISE_EMULATION
737 if (unlikely(float64_is_signaling_nan(farg1.d) ||
738 float64_is_signaling_nan(farg2.d))) {
740 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
741 } else if (likely(isfinite(farg1.d) || isfinite(farg2.d) ||
742 fpisneg(farg1.d) == fpisneg(farg2.d))) {
743 farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
745 /* Magnitude subtraction of infinities */
746 farg1.ll == fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
749 farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
755 uint64_t helper_fsub (uint64_t arg1, uint64_t arg2)
757 CPU_DoubleU farg1, farg2;
761 #if USE_PRECISE_EMULATION
763 if (unlikely(float64_is_signaling_nan(farg1.d) ||
764 float64_is_signaling_nan(farg2.d))) {
765 /* sNaN subtraction */
766 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
767 } else if (likely(isfinite(farg1.d) || isfinite(farg2.d) ||
768 fpisneg(farg1.d) != fpisneg(farg2.d))) {
769 farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
771 /* Magnitude subtraction of infinities */
772 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
776 farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
782 uint64_t helper_fmul (uint64_t arg1, uint64_t arg2)
784 CPU_DoubleU farg1, farg2;
788 #if USE_PRECISE_EMULATION
789 if (unlikely(float64_is_signaling_nan(farg1.d) ||
790 float64_is_signaling_nan(farg2.d))) {
791 /* sNaN multiplication */
792 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
793 } else if (unlikely((isinfinity(farg1.d) && iszero(farg2.d)) ||
794 (iszero(farg1.d) && isinfinity(farg2.d)))) {
795 /* Multiplication of zero by infinity */
796 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
798 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
802 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
808 uint64_t helper_fdiv (uint64_t arg1, uint64_t arg2)
810 CPU_DoubleU farg1, farg2;
814 #if USE_PRECISE_EMULATION
815 if (unlikely(float64_is_signaling_nan(farg1.d) ||
816 float64_is_signaling_nan(farg2.d))) {
818 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
819 } else if (unlikely(isinfinity(farg1.d) && isinfinity(farg2.d))) {
820 /* Division of infinity by infinity */
821 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIDI);
822 } else if (unlikely(iszero(farg2.d))) {
823 if (iszero(farg1.d)) {
824 /* Division of zero by zero */
825 farg1.ll fload_invalid_op_excp(POWERPC_EXCP_FP_VXZDZ);
827 /* Division by zero */
828 farg1.ll = float_zero_divide_excp(farg1.d, farg2.d);
831 farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
834 farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
840 uint64_t helper_fabs (uint64_t arg)
845 farg.d = float64_abs(farg.d);
850 uint64_t helper_fnabs (uint64_t arg)
855 farg.d = float64_abs(farg.d);
856 farg.d = float64_chs(farg.d);
861 uint64_t helper_fneg (uint64_t arg)
866 farg.d = float64_chs(farg.d);
871 uint64_t helper_fctiw (uint64_t arg)
876 if (unlikely(float64_is_signaling_nan(farg.d))) {
877 /* sNaN conversion */
878 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
879 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
880 /* qNan / infinity conversion */
881 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
883 farg.ll = float64_to_int32(farg.d, &env->fp_status);
884 #if USE_PRECISE_EMULATION
885 /* XXX: higher bits are not supposed to be significant.
886 * to make tests easier, return the same as a real PowerPC 750
888 farg.ll |= 0xFFF80000ULL << 32;
894 /* fctiwz - fctiwz. */
895 uint64_t helper_fctiwz (uint64_t arg)
900 if (unlikely(float64_is_signaling_nan(farg.d))) {
901 /* sNaN conversion */
902 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
903 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
904 /* qNan / infinity conversion */
905 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
907 farg.ll = float64_to_int32_round_to_zero(farg.d, &env->fp_status);
908 #if USE_PRECISE_EMULATION
909 /* XXX: higher bits are not supposed to be significant.
910 * to make tests easier, return the same as a real PowerPC 750
912 farg.ll |= 0xFFF80000ULL << 32;
918 #if defined(TARGET_PPC64)
920 uint64_t helper_fcfid (uint64_t arg)
923 farg.d = int64_to_float64(arg, &env->fp_status);
928 uint64_t helper_fctid (uint64_t arg)
933 if (unlikely(float64_is_signaling_nan(farg.d))) {
934 /* sNaN conversion */
935 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
936 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
937 /* qNan / infinity conversion */
938 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
940 farg.ll = float64_to_int64(farg.d, &env->fp_status);
945 /* fctidz - fctidz. */
946 uint64_t helper_fctidz (uint64_t arg)
951 if (unlikely(float64_is_signaling_nan(farg.d))) {
952 /* sNaN conversion */
953 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
954 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
955 /* qNan / infinity conversion */
956 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
958 farg.ll = float64_to_int64_round_to_zero(farg.d, &env->fp_status);
965 static always_inline uint64_t do_fri (uint64_t arg, int rounding_mode)
970 if (unlikely(float64_is_signaling_nan(farg.d))) {
972 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
973 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
974 /* qNan / infinity round */
975 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
977 set_float_rounding_mode(rounding_mode, &env->fp_status);
978 farg.ll = float64_round_to_int(farg.d, &env->fp_status);
979 /* Restore rounding mode from FPSCR */
980 fpscr_set_rounding_mode();
985 uint64_t helper_frin (uint64_t arg)
987 return do_fri(arg, float_round_nearest_even);
990 uint64_t helper_friz (uint64_t arg)
992 return do_fri(arg, float_round_to_zero);
995 uint64_t helper_frip (uint64_t arg)
997 return do_fri(arg, float_round_up);
1000 uint64_t helper_frim (uint64_t arg)
1002 return do_fri(arg, float_round_down);
1005 /* fmadd - fmadd. */
1006 uint64_t helper_fmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1008 CPU_DoubleU farg1, farg2, farg3;
1013 #if USE_PRECISE_EMULATION
1014 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1015 float64_is_signaling_nan(farg2.d) ||
1016 float64_is_signaling_nan(farg3.d))) {
1017 /* sNaN operation */
1018 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1021 /* This is the way the PowerPC specification defines it */
1022 float128 ft0_128, ft1_128;
1024 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1025 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1026 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1027 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1028 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1029 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1031 /* This is OK on x86 hosts */
1032 farg1.d = (farg1.d * farg2.d) + farg3.d;
1036 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1037 farg1.d = float64_add(farg1.d, farg3.d, &env->fp_status);
1042 /* fmsub - fmsub. */
1043 uint64_t helper_fmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1045 CPU_DoubleU farg1, farg2, farg3;
1050 #if USE_PRECISE_EMULATION
1051 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1052 float64_is_signaling_nan(farg2.d) ||
1053 float64_is_signaling_nan(farg3.d))) {
1054 /* sNaN operation */
1055 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1058 /* This is the way the PowerPC specification defines it */
1059 float128 ft0_128, ft1_128;
1061 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1062 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1063 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1064 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1065 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1066 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1068 /* This is OK on x86 hosts */
1069 farg1.d = (farg1.d * farg2.d) - farg3.d;
1073 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1074 farg1.d = float64_sub(farg1.d, farg3.d, &env->fp_status);
1079 /* fnmadd - fnmadd. */
1080 uint64_t helper_fnmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1082 CPU_DoubleU farg1, farg2, farg3;
1088 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1089 float64_is_signaling_nan(farg2.d) ||
1090 float64_is_signaling_nan(farg3.d))) {
1091 /* sNaN operation */
1092 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1094 #if USE_PRECISE_EMULATION
1096 /* This is the way the PowerPC specification defines it */
1097 float128 ft0_128, ft1_128;
1099 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1100 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1101 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1102 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1103 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1104 farg1.d= float128_to_float64(ft0_128, &env->fp_status);
1106 /* This is OK on x86 hosts */
1107 farg1.d = (farg1.d * farg2.d) + farg3.d;
1110 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1111 farg1.d = float64_add(farg1.d, farg3.d, &env->fp_status);
1113 if (likely(!isnan(farg1.d)))
1114 farg1.d = float64_chs(farg1.d);
1119 /* fnmsub - fnmsub. */
1120 uint64_t helper_fnmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1122 CPU_DoubleU farg1, farg2, farg3;
1128 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1129 float64_is_signaling_nan(farg2.d) ||
1130 float64_is_signaling_nan(farg3.d))) {
1131 /* sNaN operation */
1132 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1134 #if USE_PRECISE_EMULATION
1136 /* This is the way the PowerPC specification defines it */
1137 float128 ft0_128, ft1_128;
1139 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1140 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1141 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1142 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1143 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1144 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1146 /* This is OK on x86 hosts */
1147 farg1.d = (farg1.d * farg2.d) - farg3.d;
1150 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1151 farg1.d = float64_sub(farg1.d, farg3.d, &env->fp_status);
1153 if (likely(!isnan(farg1.d)))
1154 farg1.d = float64_chs(farg1.d);
1161 uint64_t helper_frsp (uint64_t arg)
1166 #if USE_PRECISE_EMULATION
1167 if (unlikely(float64_is_signaling_nan(farg.d))) {
1168 /* sNaN square root */
1169 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1171 fard.d = float64_to_float32(farg.d, &env->fp_status);
1174 farg.d = float64_to_float32(farg.d, &env->fp_status);
1179 /* fsqrt - fsqrt. */
1180 uint64_t helper_fsqrt (uint64_t arg)
1185 if (unlikely(float64_is_signaling_nan(farg.d))) {
1186 /* sNaN square root */
1187 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1188 } else if (unlikely(fpisneg(farg.d) && !iszero(farg.d))) {
1189 /* Square root of a negative nonzero number */
1190 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1192 farg.d = float64_sqrt(farg.d, &env->fp_status);
1198 uint64_t helper_fre (uint64_t arg)
1203 if (unlikely(float64_is_signaling_nan(farg.d))) {
1204 /* sNaN reciprocal */
1205 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1206 } else if (unlikely(iszero(farg.d))) {
1207 /* Zero reciprocal */
1208 farg.ll = float_zero_divide_excp(1.0, farg.d);
1209 } else if (likely(isnormal(farg.d))) {
1210 farg.d = float64_div(1.0, farg.d, &env->fp_status);
1212 if (farg.ll == 0x8000000000000000ULL) {
1213 farg.ll = 0xFFF0000000000000ULL;
1214 } else if (farg.ll == 0x0000000000000000ULL) {
1215 farg.ll = 0x7FF0000000000000ULL;
1216 } else if (isnan(farg.d)) {
1217 farg.ll = 0x7FF8000000000000ULL;
1218 } else if (fpisneg(farg.d)) {
1219 farg.ll = 0x8000000000000000ULL;
1221 farg.ll = 0x0000000000000000ULL;
1228 uint64_t helper_fres (uint64_t arg)
1233 if (unlikely(float64_is_signaling_nan(farg.d))) {
1234 /* sNaN reciprocal */
1235 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1236 } else if (unlikely(iszero(farg.d))) {
1237 /* Zero reciprocal */
1238 farg.ll = float_zero_divide_excp(1.0, farg.d);
1239 } else if (likely(isnormal(farg.d))) {
1240 #if USE_PRECISE_EMULATION
1241 farg.d = float64_div(1.0, farg.d, &env->fp_status);
1242 farg.d = float64_to_float32(farg.d, &env->fp_status);
1244 farg.d = float32_div(1.0, farg.d, &env->fp_status);
1247 if (farg.ll == 0x8000000000000000ULL) {
1248 farg.ll = 0xFFF0000000000000ULL;
1249 } else if (farg.ll == 0x0000000000000000ULL) {
1250 farg.ll = 0x7FF0000000000000ULL;
1251 } else if (isnan(farg.d)) {
1252 farg.ll = 0x7FF8000000000000ULL;
1253 } else if (fpisneg(farg.d)) {
1254 farg.ll = 0x8000000000000000ULL;
1256 farg.ll = 0x0000000000000000ULL;
1262 /* frsqrte - frsqrte. */
1263 uint64_t helper_frsqrte (uint64_t arg)
1268 if (unlikely(float64_is_signaling_nan(farg.d))) {
1269 /* sNaN reciprocal square root */
1270 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1271 } else if (unlikely(fpisneg(farg.d) && !iszero(farg.d))) {
1272 /* Reciprocal square root of a negative nonzero number */
1273 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1274 } else if (likely(isnormal(farg.d))) {
1275 farg.d = float64_sqrt(farg.d, &env->fp_status);
1276 farg.d = float32_div(1.0, farg.d, &env->fp_status);
1278 if (farg.ll == 0x8000000000000000ULL) {
1279 farg.ll = 0xFFF0000000000000ULL;
1280 } else if (farg.ll == 0x0000000000000000ULL) {
1281 farg.ll = 0x7FF0000000000000ULL;
1282 } else if (isnan(farg.d)) {
1283 farg.ll |= 0x000FFFFFFFFFFFFFULL;
1284 } else if (fpisneg(farg.d)) {
1285 farg.ll = 0x7FF8000000000000ULL;
1287 farg.ll = 0x0000000000000000ULL;
1294 uint64_t helper_fsel (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1296 CPU_DoubleU farg1, farg2, farg3;
1302 if (!fpisneg(farg1.d) || iszero(farg1.d))
1308 uint32_t helper_fcmpu (uint64_t arg1, uint64_t arg2)
1310 CPU_DoubleU farg1, farg2;
1315 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1316 float64_is_signaling_nan(farg2.d))) {
1317 /* sNaN comparison */
1318 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1320 if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1322 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1328 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1329 env->fpscr |= ret << FPSCR_FPRF;
1333 uint32_t helper_fcmpo (uint64_t arg1, uint64_t arg2)
1335 CPU_DoubleU farg1, farg2;
1340 if (unlikely(float64_is_nan(farg1.d) ||
1341 float64_is_nan(farg2.d))) {
1342 if (float64_is_signaling_nan(farg1.d) ||
1343 float64_is_signaling_nan(farg2.d)) {
1344 /* sNaN comparison */
1345 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN |
1346 POWERPC_EXCP_FP_VXVC);
1348 /* qNaN comparison */
1349 fload_invalid_op_excp(POWERPC_EXCP_FP_VXVC);
1352 if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1354 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1360 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1361 env->fpscr |= ret << FPSCR_FPRF;
1365 #if !defined (CONFIG_USER_ONLY)
1366 void cpu_dump_rfi (target_ulong RA, target_ulong msr);
1368 void do_store_msr (void)
1370 T0 = hreg_store_msr(env, T0, 0);
1372 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1373 raise_exception(env, T0);
1377 static always_inline void __do_rfi (target_ulong nip, target_ulong msr,
1378 target_ulong msrm, int keep_msrh)
1380 #if defined(TARGET_PPC64)
1381 if (msr & (1ULL << MSR_SF)) {
1382 nip = (uint64_t)nip;
1383 msr &= (uint64_t)msrm;
1385 nip = (uint32_t)nip;
1386 msr = (uint32_t)(msr & msrm);
1388 msr |= env->msr & ~((uint64_t)0xFFFFFFFF);
1391 nip = (uint32_t)nip;
1392 msr &= (uint32_t)msrm;
1394 /* XXX: beware: this is false if VLE is supported */
1395 env->nip = nip & ~((target_ulong)0x00000003);
1396 hreg_store_msr(env, msr, 1);
1397 #if defined (DEBUG_OP)
1398 cpu_dump_rfi(env->nip, env->msr);
1400 /* No need to raise an exception here,
1401 * as rfi is always the last insn of a TB
1403 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1408 __do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1409 ~((target_ulong)0xFFFF0000), 1);
1412 #if defined(TARGET_PPC64)
1415 __do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1416 ~((target_ulong)0xFFFF0000), 0);
1419 void do_hrfid (void)
1421 __do_rfi(env->spr[SPR_HSRR0], env->spr[SPR_HSRR1],
1422 ~((target_ulong)0xFFFF0000), 0);
1427 void helper_tw (target_ulong arg1, target_ulong arg2, uint32_t flags)
1429 if (!likely(!(((int32_t)arg1 < (int32_t)arg2 && (flags & 0x10)) ||
1430 ((int32_t)arg1 > (int32_t)arg2 && (flags & 0x08)) ||
1431 ((int32_t)arg1 == (int32_t)arg2 && (flags & 0x04)) ||
1432 ((uint32_t)arg1 < (uint32_t)arg2 && (flags & 0x02)) ||
1433 ((uint32_t)arg1 > (uint32_t)arg2 && (flags & 0x01))))) {
1434 raise_exception_err(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1438 #if defined(TARGET_PPC64)
1439 void helper_td (target_ulong arg1, target_ulong arg2, uint32_t flags)
1441 if (!likely(!(((int64_t)arg1 < (int64_t)arg2 && (flags & 0x10)) ||
1442 ((int64_t)arg1 > (int64_t)arg2 && (flags & 0x08)) ||
1443 ((int64_t)arg1 == (int64_t)arg2 && (flags & 0x04)) ||
1444 ((uint64_t)arg1 < (uint64_t)arg2 && (flags & 0x02)) ||
1445 ((uint64_t)arg1 > (uint64_t)arg2 && (flags & 0x01)))))
1446 raise_exception_err(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1450 /*****************************************************************************/
1451 /* PowerPC 601 specific instructions (POWER bridge) */
1452 void do_POWER_abso (void)
1454 if ((int32_t)T0 == INT32_MIN) {
1456 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1457 } else if ((int32_t)T0 < 0) {
1459 env->xer &= ~(1 << XER_OV);
1461 env->xer &= ~(1 << XER_OV);
1465 void do_POWER_clcs (void)
1469 /* Instruction cache line size */
1470 T0 = env->icache_line_size;
1473 /* Data cache line size */
1474 T0 = env->dcache_line_size;
1477 /* Minimum cache line size */
1478 T0 = env->icache_line_size < env->dcache_line_size ?
1479 env->icache_line_size : env->dcache_line_size;
1482 /* Maximum cache line size */
1483 T0 = env->icache_line_size > env->dcache_line_size ?
1484 env->icache_line_size : env->dcache_line_size;
1492 void do_POWER_div (void)
1496 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1498 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
1499 env->spr[SPR_MQ] = 0;
1501 tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
1502 env->spr[SPR_MQ] = tmp % T1;
1503 T0 = tmp / (int32_t)T1;
1507 void do_POWER_divo (void)
1511 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1513 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
1514 env->spr[SPR_MQ] = 0;
1515 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1517 tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
1518 env->spr[SPR_MQ] = tmp % T1;
1520 if (tmp > (int64_t)INT32_MAX || tmp < (int64_t)INT32_MIN) {
1521 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1523 env->xer &= ~(1 << XER_OV);
1529 void do_POWER_divs (void)
1531 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1533 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
1534 env->spr[SPR_MQ] = 0;
1536 env->spr[SPR_MQ] = T0 % T1;
1537 T0 = (int32_t)T0 / (int32_t)T1;
1541 void do_POWER_divso (void)
1543 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1545 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
1546 env->spr[SPR_MQ] = 0;
1547 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1549 T0 = (int32_t)T0 / (int32_t)T1;
1550 env->spr[SPR_MQ] = (int32_t)T0 % (int32_t)T1;
1551 env->xer &= ~(1 << XER_OV);
1555 void do_POWER_dozo (void)
1557 if ((int32_t)T1 > (int32_t)T0) {
1560 if (((uint32_t)(~T2) ^ (uint32_t)T1 ^ UINT32_MAX) &
1561 ((uint32_t)(~T2) ^ (uint32_t)T0) & (1UL << 31)) {
1562 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1564 env->xer &= ~(1 << XER_OV);
1568 env->xer &= ~(1 << XER_OV);
1572 void do_POWER_maskg (void)
1576 if ((uint32_t)T0 == (uint32_t)(T1 + 1)) {
1579 ret = (UINT32_MAX >> ((uint32_t)T0)) ^
1580 ((UINT32_MAX >> ((uint32_t)T1)) >> 1);
1581 if ((uint32_t)T0 > (uint32_t)T1)
1587 void do_POWER_mulo (void)
1591 tmp = (uint64_t)T0 * (uint64_t)T1;
1592 env->spr[SPR_MQ] = tmp >> 32;
1594 if (tmp >> 32 != ((uint64_t)T0 >> 16) * ((uint64_t)T1 >> 16)) {
1595 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1597 env->xer &= ~(1 << XER_OV);
1601 #if !defined (CONFIG_USER_ONLY)
1602 void do_POWER_rac (void)
1607 /* We don't have to generate many instances of this instruction,
1608 * as rac is supervisor only.
1610 /* XXX: FIX THIS: Pretend we have no BAT */
1611 nb_BATs = env->nb_BATs;
1613 if (get_physical_address(env, &ctx, T0, 0, ACCESS_INT) == 0)
1615 env->nb_BATs = nb_BATs;
1618 void do_POWER_rfsvc (void)
1620 __do_rfi(env->lr, env->ctr, 0x0000FFFF, 0);
1623 void do_store_hid0_601 (void)
1627 hid0 = env->spr[SPR_HID0];
1628 if ((T0 ^ hid0) & 0x00000008) {
1629 /* Change current endianness */
1630 env->hflags &= ~(1 << MSR_LE);
1631 env->hflags_nmsr &= ~(1 << MSR_LE);
1632 env->hflags_nmsr |= (1 << MSR_LE) & (((T0 >> 3) & 1) << MSR_LE);
1633 env->hflags |= env->hflags_nmsr;
1634 if (loglevel != 0) {
1635 fprintf(logfile, "%s: set endianness to %c => " ADDRX "\n",
1636 __func__, T0 & 0x8 ? 'l' : 'b', env->hflags);
1639 env->spr[SPR_HID0] = T0;
1643 /*****************************************************************************/
1644 /* 602 specific instructions */
1645 /* mfrom is the most crazy instruction ever seen, imho ! */
1646 /* Real implementation uses a ROM table. Do the same */
1647 #define USE_MFROM_ROM_TABLE
1648 target_ulong helper_602_mfrom (target_ulong arg)
1650 if (likely(arg < 602)) {
1651 #if defined(USE_MFROM_ROM_TABLE)
1652 #include "mfrom_table.c"
1653 return mfrom_ROM_table[T0];
1656 /* Extremly decomposed:
1658 * return 256 * log10(10 + 1.0) + 0.5
1661 d = float64_div(d, 256, &env->fp_status);
1663 d = exp10(d); // XXX: use float emulation function
1664 d = float64_add(d, 1.0, &env->fp_status);
1665 d = log10(d); // XXX: use float emulation function
1666 d = float64_mul(d, 256, &env->fp_status);
1667 d = float64_add(d, 0.5, &env->fp_status);
1668 return float64_round_to_int(d, &env->fp_status);
1675 /*****************************************************************************/
1676 /* Embedded PowerPC specific helpers */
1678 /* XXX: to be improved to check access rights when in user-mode */
1679 void do_load_dcr (void)
1683 if (unlikely(env->dcr_env == NULL)) {
1684 if (loglevel != 0) {
1685 fprintf(logfile, "No DCR environment\n");
1687 raise_exception_err(env, POWERPC_EXCP_PROGRAM,
1688 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
1689 } else if (unlikely(ppc_dcr_read(env->dcr_env, T0, &val) != 0)) {
1690 if (loglevel != 0) {
1691 fprintf(logfile, "DCR read error %d %03x\n", (int)T0, (int)T0);
1693 raise_exception_err(env, POWERPC_EXCP_PROGRAM,
1694 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
1700 void do_store_dcr (void)
1702 if (unlikely(env->dcr_env == NULL)) {
1703 if (loglevel != 0) {
1704 fprintf(logfile, "No DCR environment\n");
1706 raise_exception_err(env, POWERPC_EXCP_PROGRAM,
1707 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
1708 } else if (unlikely(ppc_dcr_write(env->dcr_env, T0, T1) != 0)) {
1709 if (loglevel != 0) {
1710 fprintf(logfile, "DCR write error %d %03x\n", (int)T0, (int)T0);
1712 raise_exception_err(env, POWERPC_EXCP_PROGRAM,
1713 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
1717 #if !defined(CONFIG_USER_ONLY)
1718 void do_40x_rfci (void)
1720 __do_rfi(env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3],
1721 ~((target_ulong)0xFFFF0000), 0);
1726 __do_rfi(env->spr[SPR_BOOKE_CSRR0], SPR_BOOKE_CSRR1,
1727 ~((target_ulong)0x3FFF0000), 0);
1732 __do_rfi(env->spr[SPR_BOOKE_DSRR0], SPR_BOOKE_DSRR1,
1733 ~((target_ulong)0x3FFF0000), 0);
1736 void do_rfmci (void)
1738 __do_rfi(env->spr[SPR_BOOKE_MCSRR0], SPR_BOOKE_MCSRR1,
1739 ~((target_ulong)0x3FFF0000), 0);
1742 void do_load_403_pb (int num)
1747 void do_store_403_pb (int num)
1749 if (likely(env->pb[num] != T0)) {
1751 /* Should be optimized */
1758 void do_440_dlmzb (void)
1764 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1765 if ((T0 & mask) == 0)
1769 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1770 if ((T1 & mask) == 0)
1778 /*****************************************************************************/
1779 /* SPE extension helpers */
1780 /* Use a table to make this quicker */
1781 static uint8_t hbrev[16] = {
1782 0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE,
1783 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF,
1786 static always_inline uint8_t byte_reverse (uint8_t val)
1788 return hbrev[val >> 4] | (hbrev[val & 0xF] << 4);
1791 static always_inline uint32_t word_reverse (uint32_t val)
1793 return byte_reverse(val >> 24) | (byte_reverse(val >> 16) << 8) |
1794 (byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24);
1797 #define MASKBITS 16 // Random value - to be fixed (implementation dependant)
1798 target_ulong helper_brinc (target_ulong arg1, target_ulong arg2)
1800 uint32_t a, b, d, mask;
1802 mask = UINT32_MAX >> (32 - MASKBITS);
1805 d = word_reverse(1 + word_reverse(a | ~b));
1806 return (arg1 & ~mask) | (d & b);
1809 uint32_t helper_cntlsw32 (uint32_t val)
1811 if (val & 0x80000000)
1817 uint32_t helper_cntlzw32 (uint32_t val)
1822 /* Single-precision floating-point conversions */
1823 static always_inline uint32_t efscfsi (uint32_t val)
1827 u.f = int32_to_float32(val, &env->spe_status);
1832 static always_inline uint32_t efscfui (uint32_t val)
1836 u.f = uint32_to_float32(val, &env->spe_status);
1841 static always_inline int32_t efsctsi (uint32_t val)
1846 /* NaN are not treated the same way IEEE 754 does */
1847 if (unlikely(isnan(u.f)))
1850 return float32_to_int32(u.f, &env->spe_status);
1853 static always_inline uint32_t efsctui (uint32_t val)
1858 /* NaN are not treated the same way IEEE 754 does */
1859 if (unlikely(isnan(u.f)))
1862 return float32_to_uint32(u.f, &env->spe_status);
1865 static always_inline uint32_t efsctsiz (uint32_t val)
1870 /* NaN are not treated the same way IEEE 754 does */
1871 if (unlikely(isnan(u.f)))
1874 return float32_to_int32_round_to_zero(u.f, &env->spe_status);
1877 static always_inline uint32_t efsctuiz (uint32_t val)
1882 /* NaN are not treated the same way IEEE 754 does */
1883 if (unlikely(isnan(u.f)))
1886 return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
1889 static always_inline uint32_t efscfsf (uint32_t val)
1894 u.f = int32_to_float32(val, &env->spe_status);
1895 tmp = int64_to_float32(1ULL << 32, &env->spe_status);
1896 u.f = float32_div(u.f, tmp, &env->spe_status);
1901 static always_inline uint32_t efscfuf (uint32_t val)
1906 u.f = uint32_to_float32(val, &env->spe_status);
1907 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1908 u.f = float32_div(u.f, tmp, &env->spe_status);
1913 static always_inline uint32_t efsctsf (uint32_t val)
1919 /* NaN are not treated the same way IEEE 754 does */
1920 if (unlikely(isnan(u.f)))
1922 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1923 u.f = float32_mul(u.f, tmp, &env->spe_status);
1925 return float32_to_int32(u.f, &env->spe_status);
1928 static always_inline uint32_t efsctuf (uint32_t val)
1934 /* NaN are not treated the same way IEEE 754 does */
1935 if (unlikely(isnan(u.f)))
1937 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
1938 u.f = float32_mul(u.f, tmp, &env->spe_status);
1940 return float32_to_uint32(u.f, &env->spe_status);
1943 #define HELPER_SPE_SINGLE_CONV(name) \
1944 uint32_t helper_e##name (uint32_t val) \
1946 return e##name(val); \
1949 HELPER_SPE_SINGLE_CONV(fscfsi);
1951 HELPER_SPE_SINGLE_CONV(fscfui);
1953 HELPER_SPE_SINGLE_CONV(fscfuf);
1955 HELPER_SPE_SINGLE_CONV(fscfsf);
1957 HELPER_SPE_SINGLE_CONV(fsctsi);
1959 HELPER_SPE_SINGLE_CONV(fsctui);
1961 HELPER_SPE_SINGLE_CONV(fsctsiz);
1963 HELPER_SPE_SINGLE_CONV(fsctuiz);
1965 HELPER_SPE_SINGLE_CONV(fsctsf);
1967 HELPER_SPE_SINGLE_CONV(fsctuf);
1969 #define HELPER_SPE_VECTOR_CONV(name) \
1970 uint64_t helper_ev##name (uint64_t val) \
1972 return ((uint64_t)e##name(val >> 32) << 32) | \
1973 (uint64_t)e##name(val); \
1976 HELPER_SPE_VECTOR_CONV(fscfsi);
1978 HELPER_SPE_VECTOR_CONV(fscfui);
1980 HELPER_SPE_VECTOR_CONV(fscfuf);
1982 HELPER_SPE_VECTOR_CONV(fscfsf);
1984 HELPER_SPE_VECTOR_CONV(fsctsi);
1986 HELPER_SPE_VECTOR_CONV(fsctui);
1988 HELPER_SPE_VECTOR_CONV(fsctsiz);
1990 HELPER_SPE_VECTOR_CONV(fsctuiz);
1992 HELPER_SPE_VECTOR_CONV(fsctsf);
1994 HELPER_SPE_VECTOR_CONV(fsctuf);
1996 /* Single-precision floating-point arithmetic */
1997 static always_inline uint32_t efsadd (uint32_t op1, uint32_t op2)
2002 u1.f = float32_add(u1.f, u2.f, &env->spe_status);
2006 static always_inline uint32_t efssub (uint32_t op1, uint32_t op2)
2011 u1.f = float32_sub(u1.f, u2.f, &env->spe_status);
2015 static always_inline uint32_t efsmul (uint32_t op1, uint32_t op2)
2020 u1.f = float32_mul(u1.f, u2.f, &env->spe_status);
2024 static always_inline uint32_t efsdiv (uint32_t op1, uint32_t op2)
2029 u1.f = float32_div(u1.f, u2.f, &env->spe_status);
2033 #define HELPER_SPE_SINGLE_ARITH(name) \
2034 uint32_t helper_e##name (uint32_t op1, uint32_t op2) \
2036 return e##name(op1, op2); \
2039 HELPER_SPE_SINGLE_ARITH(fsadd);
2041 HELPER_SPE_SINGLE_ARITH(fssub);
2043 HELPER_SPE_SINGLE_ARITH(fsmul);
2045 HELPER_SPE_SINGLE_ARITH(fsdiv);
2047 #define HELPER_SPE_VECTOR_ARITH(name) \
2048 uint64_t helper_ev##name (uint64_t op1, uint64_t op2) \
2050 return ((uint64_t)e##name(op1 >> 32, op2 >> 32) << 32) | \
2051 (uint64_t)e##name(op1, op2); \
2054 HELPER_SPE_VECTOR_ARITH(fsadd);
2056 HELPER_SPE_VECTOR_ARITH(fssub);
2058 HELPER_SPE_VECTOR_ARITH(fsmul);
2060 HELPER_SPE_VECTOR_ARITH(fsdiv);
2062 /* Single-precision floating-point comparisons */
2063 static always_inline uint32_t efststlt (uint32_t op1, uint32_t op2)
2068 return float32_lt(u1.f, u2.f, &env->spe_status) ? 4 : 0;
2071 static always_inline uint32_t efststgt (uint32_t op1, uint32_t op2)
2076 return float32_le(u1.f, u2.f, &env->spe_status) ? 0 : 4;
2079 static always_inline uint32_t efststeq (uint32_t op1, uint32_t op2)
2084 return float32_eq(u1.f, u2.f, &env->spe_status) ? 4 : 0;
2087 static always_inline uint32_t efscmplt (uint32_t op1, uint32_t op2)
2089 /* XXX: TODO: test special values (NaN, infinites, ...) */
2090 return efststlt(op1, op2);
2093 static always_inline uint32_t efscmpgt (uint32_t op1, uint32_t op2)
2095 /* XXX: TODO: test special values (NaN, infinites, ...) */
2096 return efststgt(op1, op2);
2099 static always_inline uint32_t efscmpeq (uint32_t op1, uint32_t op2)
2101 /* XXX: TODO: test special values (NaN, infinites, ...) */
2102 return efststeq(op1, op2);
2105 #define HELPER_SINGLE_SPE_CMP(name) \
2106 uint32_t helper_e##name (uint32_t op1, uint32_t op2) \
2108 return e##name(op1, op2) << 2; \
2111 HELPER_SINGLE_SPE_CMP(fststlt);
2113 HELPER_SINGLE_SPE_CMP(fststgt);
2115 HELPER_SINGLE_SPE_CMP(fststeq);
2117 HELPER_SINGLE_SPE_CMP(fscmplt);
2119 HELPER_SINGLE_SPE_CMP(fscmpgt);
2121 HELPER_SINGLE_SPE_CMP(fscmpeq);
2123 static always_inline uint32_t evcmp_merge (int t0, int t1)
2125 return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
2128 #define HELPER_VECTOR_SPE_CMP(name) \
2129 uint32_t helper_ev##name (uint64_t op1, uint64_t op2) \
2131 return evcmp_merge(e##name(op1 >> 32, op2 >> 32), e##name(op1, op2)); \
2134 HELPER_VECTOR_SPE_CMP(fststlt);
2136 HELPER_VECTOR_SPE_CMP(fststgt);
2138 HELPER_VECTOR_SPE_CMP(fststeq);
2140 HELPER_VECTOR_SPE_CMP(fscmplt);
2142 HELPER_VECTOR_SPE_CMP(fscmpgt);
2144 HELPER_VECTOR_SPE_CMP(fscmpeq);
2146 /* Double-precision floating-point conversion */
2147 uint64_t helper_efdcfsi (uint32_t val)
2151 u.d = int32_to_float64(val, &env->spe_status);
2156 uint64_t helper_efdcfsid (uint64_t val)
2160 u.d = int64_to_float64(val, &env->spe_status);
2165 uint64_t helper_efdcfui (uint32_t val)
2169 u.d = uint32_to_float64(val, &env->spe_status);
2174 uint64_t helper_efdcfuid (uint64_t val)
2178 u.d = uint64_to_float64(val, &env->spe_status);
2183 uint32_t helper_efdctsi (uint64_t val)
2188 /* NaN are not treated the same way IEEE 754 does */
2189 if (unlikely(isnan(u.d)))
2192 return float64_to_int32(u.d, &env->spe_status);
2195 uint32_t helper_efdctui (uint64_t val)
2200 /* NaN are not treated the same way IEEE 754 does */
2201 if (unlikely(isnan(u.d)))
2204 return float64_to_uint32(u.d, &env->spe_status);
2207 uint32_t helper_efdctsiz (uint64_t val)
2212 /* NaN are not treated the same way IEEE 754 does */
2213 if (unlikely(isnan(u.d)))
2216 return float64_to_int32_round_to_zero(u.d, &env->spe_status);
2219 uint64_t helper_efdctsidz (uint64_t val)
2224 /* NaN are not treated the same way IEEE 754 does */
2225 if (unlikely(isnan(u.d)))
2228 return float64_to_int64_round_to_zero(u.d, &env->spe_status);
2231 uint32_t helper_efdctuiz (uint64_t val)
2236 /* NaN are not treated the same way IEEE 754 does */
2237 if (unlikely(isnan(u.d)))
2240 return float64_to_uint32_round_to_zero(u.d, &env->spe_status);
2243 uint64_t helper_efdctuidz (uint64_t val)
2248 /* NaN are not treated the same way IEEE 754 does */
2249 if (unlikely(isnan(u.d)))
2252 return float64_to_uint64_round_to_zero(u.d, &env->spe_status);
2255 uint64_t helper_efdcfsf (uint32_t val)
2260 u.d = int32_to_float64(val, &env->spe_status);
2261 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
2262 u.d = float64_div(u.d, tmp, &env->spe_status);
2267 uint64_t helper_efdcfuf (uint32_t val)
2272 u.d = uint32_to_float64(val, &env->spe_status);
2273 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
2274 u.d = float64_div(u.d, tmp, &env->spe_status);
2279 uint32_t helper_efdctsf (uint64_t val)
2285 /* NaN are not treated the same way IEEE 754 does */
2286 if (unlikely(isnan(u.d)))
2288 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2289 u.d = float64_mul(u.d, tmp, &env->spe_status);
2291 return float64_to_int32(u.d, &env->spe_status);
2294 uint32_t helper_efdctuf (uint64_t val)
2300 /* NaN are not treated the same way IEEE 754 does */
2301 if (unlikely(isnan(u.d)))
2303 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2304 u.d = float64_mul(u.d, tmp, &env->spe_status);
2306 return float64_to_uint32(u.d, &env->spe_status);
2309 uint32_t helper_efscfd (uint64_t val)
2315 u2.f = float64_to_float32(u1.d, &env->spe_status);
2320 uint64_t helper_efdcfs (uint32_t val)
2326 u2.d = float32_to_float64(u1.f, &env->spe_status);
2331 /* Double precision fixed-point arithmetic */
2332 uint64_t helper_efdadd (uint64_t op1, uint64_t op2)
2337 u1.d = float64_add(u1.d, u2.d, &env->spe_status);
2341 uint64_t helper_efdsub (uint64_t op1, uint64_t op2)
2346 u1.d = float64_sub(u1.d, u2.d, &env->spe_status);
2350 uint64_t helper_efdmul (uint64_t op1, uint64_t op2)
2355 u1.d = float64_mul(u1.d, u2.d, &env->spe_status);
2359 uint64_t helper_efddiv (uint64_t op1, uint64_t op2)
2364 u1.d = float64_div(u1.d, u2.d, &env->spe_status);
2368 /* Double precision floating point helpers */
2369 uint32_t helper_efdtstlt (uint64_t op1, uint64_t op2)
2374 return float64_lt(u1.d, u2.d, &env->spe_status) ? 4 : 0;
2377 uint32_t helper_efdtstgt (uint64_t op1, uint64_t op2)
2382 return float64_le(u1.d, u2.d, &env->spe_status) ? 0 : 4;
2385 uint32_t helper_efdtsteq (uint64_t op1, uint64_t op2)
2390 return float64_eq(u1.d, u2.d, &env->spe_status) ? 4 : 0;
2393 uint32_t helper_efdcmplt (uint64_t op1, uint64_t op2)
2395 /* XXX: TODO: test special values (NaN, infinites, ...) */
2396 return helper_efdtstlt(op1, op2);
2399 uint32_t helper_efdcmpgt (uint64_t op1, uint64_t op2)
2401 /* XXX: TODO: test special values (NaN, infinites, ...) */
2402 return helper_efdtstgt(op1, op2);
2405 uint32_t helper_efdcmpeq (uint64_t op1, uint64_t op2)
2407 /* XXX: TODO: test special values (NaN, infinites, ...) */
2408 return helper_efdtsteq(op1, op2);
2411 /*****************************************************************************/
2412 /* Softmmu support */
2413 #if !defined (CONFIG_USER_ONLY)
2415 #define MMUSUFFIX _mmu
2418 #include "softmmu_template.h"
2421 #include "softmmu_template.h"
2424 #include "softmmu_template.h"
2427 #include "softmmu_template.h"
2429 /* try to fill the TLB and return an exception if error. If retaddr is
2430 NULL, it means that the function was called in C code (i.e. not
2431 from generated code or from helper.c) */
2432 /* XXX: fix it to restore all registers */
2433 void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
2435 TranslationBlock *tb;
2436 CPUState *saved_env;
2440 /* XXX: hack to restore env in all cases, even if not called from
2443 env = cpu_single_env;
2444 ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
2445 if (unlikely(ret != 0)) {
2446 if (likely(retaddr)) {
2447 /* now we have a real cpu fault */
2448 pc = (unsigned long)retaddr;
2449 tb = tb_find_pc(pc);
2451 /* the PC is inside the translated code. It means that we have
2452 a virtual CPU fault */
2453 cpu_restore_state(tb, env, pc, NULL);
2456 raise_exception_err(env, env->exception_index, env->error_code);
2461 /* Software driven TLBs management */
2462 /* PowerPC 602/603 software TLB load instructions helpers */
2463 static void helper_load_6xx_tlb (target_ulong new_EPN, int is_code)
2465 target_ulong RPN, CMP, EPN;
2468 RPN = env->spr[SPR_RPA];
2470 CMP = env->spr[SPR_ICMP];
2471 EPN = env->spr[SPR_IMISS];
2473 CMP = env->spr[SPR_DCMP];
2474 EPN = env->spr[SPR_DMISS];
2476 way = (env->spr[SPR_SRR1] >> 17) & 1;
2477 #if defined (DEBUG_SOFTWARE_TLB)
2478 if (loglevel != 0) {
2479 fprintf(logfile, "%s: EPN " TDX " " ADDRX " PTE0 " ADDRX
2480 " PTE1 " ADDRX " way %d\n",
2481 __func__, T0, EPN, CMP, RPN, way);
2484 /* Store this TLB */
2485 ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
2486 way, is_code, CMP, RPN);
2489 void helper_load_6xx_tlbd (target_ulong EPN)
2491 helper_load_6xx_tlb(EPN, 0);
2494 void helper_load_6xx_tlbi (target_ulong EPN)
2496 helper_load_6xx_tlb(EPN, 1);
2499 /* PowerPC 74xx software TLB load instructions helpers */
2500 static void helper_load_74xx_tlb (target_ulong new_EPN, int is_code)
2502 target_ulong RPN, CMP, EPN;
2505 RPN = env->spr[SPR_PTELO];
2506 CMP = env->spr[SPR_PTEHI];
2507 EPN = env->spr[SPR_TLBMISS] & ~0x3;
2508 way = env->spr[SPR_TLBMISS] & 0x3;
2509 #if defined (DEBUG_SOFTWARE_TLB)
2510 if (loglevel != 0) {
2511 fprintf(logfile, "%s: EPN " TDX " " ADDRX " PTE0 " ADDRX
2512 " PTE1 " ADDRX " way %d\n",
2513 __func__, T0, EPN, CMP, RPN, way);
2516 /* Store this TLB */
2517 ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
2518 way, is_code, CMP, RPN);
2521 void helper_load_74xx_tlbd (target_ulong EPN)
2523 helper_load_74xx_tlb(EPN, 0);
2526 void helper_load_74xx_tlbi (target_ulong EPN)
2528 helper_load_74xx_tlb(EPN, 1);
2531 static always_inline target_ulong booke_tlb_to_page_size (int size)
2533 return 1024 << (2 * size);
2536 static always_inline int booke_page_size_to_tlb (target_ulong page_size)
2540 switch (page_size) {
2574 #if defined (TARGET_PPC64)
2575 case 0x000100000000ULL:
2578 case 0x000400000000ULL:
2581 case 0x001000000000ULL:
2584 case 0x004000000000ULL:
2587 case 0x010000000000ULL:
2599 /* Helpers for 4xx TLB management */
2600 void do_4xx_tlbre_lo (void)
2606 tlb = &env->tlb[T0].tlbe;
2608 if (tlb->prot & PAGE_VALID)
2610 size = booke_page_size_to_tlb(tlb->size);
2611 if (size < 0 || size > 0x7)
2614 env->spr[SPR_40x_PID] = tlb->PID;
2617 void do_4xx_tlbre_hi (void)
2622 tlb = &env->tlb[T0].tlbe;
2624 if (tlb->prot & PAGE_EXEC)
2626 if (tlb->prot & PAGE_WRITE)
2630 void do_4xx_tlbwe_hi (void)
2633 target_ulong page, end;
2635 #if defined (DEBUG_SOFTWARE_TLB)
2636 if (loglevel != 0) {
2637 fprintf(logfile, "%s T0 " TDX " T1 " TDX "\n", __func__, T0, T1);
2641 tlb = &env->tlb[T0].tlbe;
2642 /* Invalidate previous TLB (if it's valid) */
2643 if (tlb->prot & PAGE_VALID) {
2644 end = tlb->EPN + tlb->size;
2645 #if defined (DEBUG_SOFTWARE_TLB)
2646 if (loglevel != 0) {
2647 fprintf(logfile, "%s: invalidate old TLB %d start " ADDRX
2648 " end " ADDRX "\n", __func__, (int)T0, tlb->EPN, end);
2651 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2652 tlb_flush_page(env, page);
2654 tlb->size = booke_tlb_to_page_size((T1 >> 7) & 0x7);
2655 /* We cannot handle TLB size < TARGET_PAGE_SIZE.
2656 * If this ever occurs, one should use the ppcemb target instead
2657 * of the ppc or ppc64 one
2659 if ((T1 & 0x40) && tlb->size < TARGET_PAGE_SIZE) {
2660 cpu_abort(env, "TLB size " TARGET_FMT_lu " < %u "
2661 "are not supported (%d)\n",
2662 tlb->size, TARGET_PAGE_SIZE, (int)((T1 >> 7) & 0x7));
2664 tlb->EPN = T1 & ~(tlb->size - 1);
2666 tlb->prot |= PAGE_VALID;
2668 tlb->prot &= ~PAGE_VALID;
2670 /* XXX: TO BE FIXED */
2671 cpu_abort(env, "Little-endian TLB entries are not supported by now\n");
2673 tlb->PID = env->spr[SPR_40x_PID]; /* PID */
2674 tlb->attr = T1 & 0xFF;
2675 #if defined (DEBUG_SOFTWARE_TLB)
2676 if (loglevel != 0) {
2677 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
2678 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
2679 (int)T0, tlb->RPN, tlb->EPN, tlb->size,
2680 tlb->prot & PAGE_READ ? 'r' : '-',
2681 tlb->prot & PAGE_WRITE ? 'w' : '-',
2682 tlb->prot & PAGE_EXEC ? 'x' : '-',
2683 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
2686 /* Invalidate new TLB (if valid) */
2687 if (tlb->prot & PAGE_VALID) {
2688 end = tlb->EPN + tlb->size;
2689 #if defined (DEBUG_SOFTWARE_TLB)
2690 if (loglevel != 0) {
2691 fprintf(logfile, "%s: invalidate TLB %d start " ADDRX
2692 " end " ADDRX "\n", __func__, (int)T0, tlb->EPN, end);
2695 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2696 tlb_flush_page(env, page);
2700 void do_4xx_tlbwe_lo (void)
2704 #if defined (DEBUG_SOFTWARE_TLB)
2705 if (loglevel != 0) {
2706 fprintf(logfile, "%s T0 " TDX " T1 " TDX "\n", __func__, T0, T1);
2710 tlb = &env->tlb[T0].tlbe;
2711 tlb->RPN = T1 & 0xFFFFFC00;
2712 tlb->prot = PAGE_READ;
2714 tlb->prot |= PAGE_EXEC;
2716 tlb->prot |= PAGE_WRITE;
2717 #if defined (DEBUG_SOFTWARE_TLB)
2718 if (loglevel != 0) {
2719 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
2720 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
2721 (int)T0, tlb->RPN, tlb->EPN, tlb->size,
2722 tlb->prot & PAGE_READ ? 'r' : '-',
2723 tlb->prot & PAGE_WRITE ? 'w' : '-',
2724 tlb->prot & PAGE_EXEC ? 'x' : '-',
2725 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
2730 /* PowerPC 440 TLB management */
2731 void do_440_tlbwe (int word)
2734 target_ulong EPN, RPN, size;
2737 #if defined (DEBUG_SOFTWARE_TLB)
2738 if (loglevel != 0) {
2739 fprintf(logfile, "%s word %d T0 " TDX " T1 " TDX "\n",
2740 __func__, word, T0, T1);
2745 tlb = &env->tlb[T0].tlbe;
2748 /* Just here to please gcc */
2750 EPN = T1 & 0xFFFFFC00;
2751 if ((tlb->prot & PAGE_VALID) && EPN != tlb->EPN)
2754 size = booke_tlb_to_page_size((T1 >> 4) & 0xF);
2755 if ((tlb->prot & PAGE_VALID) && tlb->size < size)
2759 tlb->attr |= (T1 >> 8) & 1;
2761 tlb->prot |= PAGE_VALID;
2763 if (tlb->prot & PAGE_VALID) {
2764 tlb->prot &= ~PAGE_VALID;
2768 tlb->PID = env->spr[SPR_440_MMUCR] & 0x000000FF;
2773 RPN = T1 & 0xFFFFFC0F;
2774 if ((tlb->prot & PAGE_VALID) && tlb->RPN != RPN)
2779 tlb->attr = (tlb->attr & 0x1) | (T1 & 0x0000FF00);
2780 tlb->prot = tlb->prot & PAGE_VALID;
2782 tlb->prot |= PAGE_READ << 4;
2784 tlb->prot |= PAGE_WRITE << 4;
2786 tlb->prot |= PAGE_EXEC << 4;
2788 tlb->prot |= PAGE_READ;
2790 tlb->prot |= PAGE_WRITE;
2792 tlb->prot |= PAGE_EXEC;
2797 void do_440_tlbre (int word)
2803 tlb = &env->tlb[T0].tlbe;
2806 /* Just here to please gcc */
2809 size = booke_page_size_to_tlb(tlb->size);
2810 if (size < 0 || size > 0xF)
2813 if (tlb->attr & 0x1)
2815 if (tlb->prot & PAGE_VALID)
2817 env->spr[SPR_440_MMUCR] &= ~0x000000FF;
2818 env->spr[SPR_440_MMUCR] |= tlb->PID;
2824 T0 = tlb->attr & ~0x1;
2825 if (tlb->prot & (PAGE_READ << 4))
2827 if (tlb->prot & (PAGE_WRITE << 4))
2829 if (tlb->prot & (PAGE_EXEC << 4))
2831 if (tlb->prot & PAGE_READ)
2833 if (tlb->prot & PAGE_WRITE)
2835 if (tlb->prot & PAGE_EXEC)
2840 #endif /* !CONFIG_USER_ONLY */