2 * PowerPC emulation helpers for qemu.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include "host-utils.h"
24 #include "helper_regs.h"
25 #include "op_helper.h"
28 //#define DEBUG_EXCEPTIONS
29 //#define DEBUG_SOFTWARE_TLB
31 /*****************************************************************************/
32 /* Exceptions processing helpers */
34 void helper_raise_exception_err (uint32_t exception, uint32_t error_code)
36 raise_exception_err(env, exception, error_code);
39 void helper_raise_debug (void)
41 raise_exception(env, EXCP_DEBUG);
44 /*****************************************************************************/
45 /* Registers load and stores */
46 target_ulong helper_load_cr (void)
48 return (env->crf[0] << 28) |
58 void helper_store_cr (target_ulong val, uint32_t mask)
62 for (i = 0, sh = 7; i < 8; i++, sh--) {
64 env->crf[i] = (val >> (sh * 4)) & 0xFUL;
68 #if defined(TARGET_PPC64)
69 void do_store_pri (int prio)
71 env->spr[SPR_PPR] &= ~0x001C000000000000ULL;
72 env->spr[SPR_PPR] |= ((uint64_t)prio & 0x7) << 50;
76 target_ulong ppc_load_dump_spr (int sprn)
79 fprintf(logfile, "Read SPR %d %03x => " ADDRX "\n",
80 sprn, sprn, env->spr[sprn]);
83 return env->spr[sprn];
86 void ppc_store_dump_spr (int sprn, target_ulong val)
89 fprintf(logfile, "Write SPR %d %03x => " ADDRX " <= " ADDRX "\n",
90 sprn, sprn, env->spr[sprn], val);
95 /*****************************************************************************/
96 /* Memory load and stores */
98 static always_inline target_ulong get_addr(target_ulong addr)
100 #if defined(TARGET_PPC64)
105 return (uint32_t)addr;
108 void helper_lmw (target_ulong addr, uint32_t reg)
110 #ifdef CONFIG_USER_ONLY
111 #define ldfun ldl_raw
113 int (*ldfun)(target_ulong);
115 switch (env->mmu_idx) {
117 case 0: ldfun = ldl_user;
119 case 1: ldfun = ldl_kernel;
121 case 2: ldfun = ldl_hypv;
125 for (; reg < 32; reg++, addr += 4) {
127 env->gpr[reg] = bswap32(ldfun(get_addr(addr)));
129 env->gpr[reg] = ldfun(get_addr(addr));
133 void helper_stmw (target_ulong addr, uint32_t reg)
135 #ifdef CONFIG_USER_ONLY
136 #define stfun stl_raw
138 void (*stfun)(target_ulong, int);
140 switch (env->mmu_idx) {
142 case 0: stfun = stl_user;
144 case 1: stfun = stl_kernel;
146 case 2: stfun = stl_hypv;
150 for (; reg < 32; reg++, addr += 4) {
152 stfun(get_addr(addr), bswap32((uint32_t)env->gpr[reg]));
154 stfun(get_addr(addr), (uint32_t)env->gpr[reg]);
158 void helper_lsw(target_ulong addr, uint32_t nb, uint32_t reg)
161 #ifdef CONFIG_USER_ONLY
162 #define ldfunl ldl_raw
163 #define ldfunb ldub_raw
165 int (*ldfunl)(target_ulong);
166 int (*ldfunb)(target_ulong);
168 switch (env->mmu_idx) {
176 ldfunb = ldub_kernel;
184 for (; nb > 3; nb -= 4, addr += 4) {
185 env->gpr[reg] = ldfunl(get_addr(addr));
186 reg = (reg + 1) % 32;
188 if (unlikely(nb > 0)) {
190 for (sh = 24; nb > 0; nb--, addr++, sh -= 8) {
191 env->gpr[reg] |= ldfunb(get_addr(addr)) << sh;
195 /* PPC32 specification says we must generate an exception if
196 * rA is in the range of registers to be loaded.
197 * In an other hand, IBM says this is valid, but rA won't be loaded.
198 * For now, I'll follow the spec...
200 void helper_lswx(target_ulong addr, uint32_t reg, uint32_t ra, uint32_t rb)
202 if (likely(xer_bc != 0)) {
203 if (unlikely((ra != 0 && reg < ra && (reg + xer_bc) > ra) ||
204 (reg < rb && (reg + xer_bc) > rb))) {
205 raise_exception_err(env, POWERPC_EXCP_PROGRAM,
207 POWERPC_EXCP_INVAL_LSWX);
209 helper_lsw(addr, xer_bc, reg);
214 void helper_stsw(target_ulong addr, uint32_t nb, uint32_t reg)
217 #ifdef CONFIG_USER_ONLY
218 #define stfunl stl_raw
219 #define stfunb stb_raw
221 void (*stfunl)(target_ulong, int);
222 void (*stfunb)(target_ulong, int);
224 switch (env->mmu_idx) {
241 for (; nb > 3; nb -= 4, addr += 4) {
242 stfunl(get_addr(addr), env->gpr[reg]);
243 reg = (reg + 1) % 32;
245 if (unlikely(nb > 0)) {
246 for (sh = 24; nb > 0; nb--, addr++, sh -= 8)
247 stfunb(get_addr(addr), (env->gpr[reg] >> sh) & 0xFF);
251 static void do_dcbz(target_ulong addr, int dcache_line_size)
253 target_long mask = get_addr(~(dcache_line_size - 1));
255 #ifdef CONFIG_USER_ONLY
256 #define stfun stl_raw
258 void (*stfun)(target_ulong, int);
260 switch (env->mmu_idx) {
262 case 0: stfun = stl_user;
264 case 1: stfun = stl_kernel;
266 case 2: stfun = stl_hypv;
271 for (i = 0 ; i < dcache_line_size ; i += 4) {
274 if ((env->reserve & mask) == addr)
275 env->reserve = (target_ulong)-1ULL;
278 void helper_dcbz(target_ulong addr)
280 do_dcbz(addr, env->dcache_line_size);
283 void helper_dcbz_970(target_ulong addr)
285 if (((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1)
288 do_dcbz(addr, env->dcache_line_size);
291 void helper_icbi(target_ulong addr)
295 addr = get_addr(addr & ~(env->dcache_line_size - 1));
296 /* Invalidate one cache line :
297 * PowerPC specification says this is to be treated like a load
298 * (not a fetch) by the MMU. To be sure it will be so,
299 * do the load "by hand".
301 #ifdef CONFIG_USER_ONLY
304 switch (env->mmu_idx) {
306 case 0: tmp = ldl_user(addr);
308 case 1: tmp = ldl_kernel(addr);
310 case 2: tmp = ldl_hypv(addr);
314 tb_invalidate_page_range(addr, addr + env->icache_line_size);
318 target_ulong helper_lscbx (target_ulong addr, uint32_t reg, uint32_t ra, uint32_t rb)
321 #ifdef CONFIG_USER_ONLY
322 #define ldfun ldub_raw
324 int (*ldfun)(target_ulong);
326 switch (env->mmu_idx) {
328 case 0: ldfun = ldub_user;
330 case 1: ldfun = ldub_kernel;
332 case 2: ldfun = ldub_hypv;
337 for (i = 0; i < xer_bc; i++) {
338 c = ldfun((uint32_t)addr++);
339 /* ra (if not 0) and rb are never modified */
340 if (likely(reg != rb && (ra == 0 || reg != ra))) {
341 env->gpr[reg] = (env->gpr[reg] & ~(0xFF << d)) | (c << d);
343 if (unlikely(c == xer_cmp))
345 if (likely(d != 0)) {
356 /*****************************************************************************/
357 /* Fixed point operations helpers */
358 #if defined(TARGET_PPC64)
360 /* multiply high word */
361 uint64_t helper_mulhd (uint64_t arg1, uint64_t arg2)
365 muls64(&tl, &th, arg1, arg2);
369 /* multiply high word unsigned */
370 uint64_t helper_mulhdu (uint64_t arg1, uint64_t arg2)
374 mulu64(&tl, &th, arg1, arg2);
378 uint64_t helper_mulldo (uint64_t arg1, uint64_t arg2)
383 muls64(&tl, (uint64_t *)&th, arg1, arg2);
384 /* If th != 0 && th != -1, then we had an overflow */
385 if (likely((uint64_t)(th + 1) <= 1)) {
386 env->xer &= ~(1 << XER_OV);
388 env->xer |= (1 << XER_OV) | (1 << XER_SO);
394 target_ulong helper_cntlzw (target_ulong t)
399 #if defined(TARGET_PPC64)
400 target_ulong helper_cntlzd (target_ulong t)
406 /* shift right arithmetic helper */
407 target_ulong helper_sraw (target_ulong value, target_ulong shift)
411 if (likely(!(shift & 0x20))) {
412 if (likely((uint32_t)shift != 0)) {
414 ret = (int32_t)value >> shift;
415 if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
416 env->xer &= ~(1 << XER_CA);
418 env->xer |= (1 << XER_CA);
421 ret = (int32_t)value;
422 env->xer &= ~(1 << XER_CA);
425 ret = (int32_t)value >> 31;
427 env->xer |= (1 << XER_CA);
429 env->xer &= ~(1 << XER_CA);
432 return (target_long)ret;
435 #if defined(TARGET_PPC64)
436 target_ulong helper_srad (target_ulong value, target_ulong shift)
440 if (likely(!(shift & 0x40))) {
441 if (likely((uint64_t)shift != 0)) {
443 ret = (int64_t)value >> shift;
444 if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
445 env->xer &= ~(1 << XER_CA);
447 env->xer |= (1 << XER_CA);
450 ret = (int64_t)value;
451 env->xer &= ~(1 << XER_CA);
454 ret = (int64_t)value >> 63;
456 env->xer |= (1 << XER_CA);
458 env->xer &= ~(1 << XER_CA);
465 target_ulong helper_popcntb (target_ulong val)
467 val = (val & 0x55555555) + ((val >> 1) & 0x55555555);
468 val = (val & 0x33333333) + ((val >> 2) & 0x33333333);
469 val = (val & 0x0f0f0f0f) + ((val >> 4) & 0x0f0f0f0f);
473 #if defined(TARGET_PPC64)
474 target_ulong helper_popcntb_64 (target_ulong val)
476 val = (val & 0x5555555555555555ULL) + ((val >> 1) & 0x5555555555555555ULL);
477 val = (val & 0x3333333333333333ULL) + ((val >> 2) & 0x3333333333333333ULL);
478 val = (val & 0x0f0f0f0f0f0f0f0fULL) + ((val >> 4) & 0x0f0f0f0f0f0f0f0fULL);
483 /*****************************************************************************/
484 /* Floating point operations helpers */
485 uint64_t helper_float32_to_float64(uint32_t arg)
490 d.d = float32_to_float64(f.f, &env->fp_status);
494 uint32_t helper_float64_to_float32(uint64_t arg)
499 f.f = float64_to_float32(d.d, &env->fp_status);
503 static always_inline int fpisneg (float64 d)
509 return u.ll >> 63 != 0;
512 static always_inline int isden (float64 d)
518 return ((u.ll >> 52) & 0x7FF) == 0;
521 static always_inline int iszero (float64 d)
527 return (u.ll & ~0x8000000000000000ULL) == 0;
530 static always_inline int isinfinity (float64 d)
536 return ((u.ll >> 52) & 0x7FF) == 0x7FF &&
537 (u.ll & 0x000FFFFFFFFFFFFFULL) == 0;
540 #ifdef CONFIG_SOFTFLOAT
541 static always_inline int isfinite (float64 d)
547 return (((u.ll >> 52) & 0x7FF) != 0x7FF);
550 static always_inline int isnormal (float64 d)
556 uint32_t exp = (u.ll >> 52) & 0x7FF;
557 return ((0 < exp) && (exp < 0x7FF));
561 uint32_t helper_compute_fprf (uint64_t arg, uint32_t set_fprf)
567 isneg = fpisneg(farg.d);
568 if (unlikely(float64_is_nan(farg.d))) {
569 if (float64_is_signaling_nan(farg.d)) {
570 /* Signaling NaN: flags are undefined */
576 } else if (unlikely(isinfinity(farg.d))) {
583 if (iszero(farg.d)) {
591 /* Denormalized numbers */
594 /* Normalized numbers */
605 /* We update FPSCR_FPRF */
606 env->fpscr &= ~(0x1F << FPSCR_FPRF);
607 env->fpscr |= ret << FPSCR_FPRF;
609 /* We just need fpcc to update Rc1 */
613 /* Floating-point invalid operations exception */
614 static always_inline uint64_t fload_invalid_op_excp (int op)
620 if (op & POWERPC_EXCP_FP_VXSNAN) {
621 /* Operation on signaling NaN */
622 env->fpscr |= 1 << FPSCR_VXSNAN;
624 if (op & POWERPC_EXCP_FP_VXSOFT) {
625 /* Software-defined condition */
626 env->fpscr |= 1 << FPSCR_VXSOFT;
628 switch (op & ~(POWERPC_EXCP_FP_VXSOFT | POWERPC_EXCP_FP_VXSNAN)) {
629 case POWERPC_EXCP_FP_VXISI:
630 /* Magnitude subtraction of infinities */
631 env->fpscr |= 1 << FPSCR_VXISI;
633 case POWERPC_EXCP_FP_VXIDI:
634 /* Division of infinity by infinity */
635 env->fpscr |= 1 << FPSCR_VXIDI;
637 case POWERPC_EXCP_FP_VXZDZ:
638 /* Division of zero by zero */
639 env->fpscr |= 1 << FPSCR_VXZDZ;
641 case POWERPC_EXCP_FP_VXIMZ:
642 /* Multiplication of zero by infinity */
643 env->fpscr |= 1 << FPSCR_VXIMZ;
645 case POWERPC_EXCP_FP_VXVC:
646 /* Ordered comparison of NaN */
647 env->fpscr |= 1 << FPSCR_VXVC;
648 env->fpscr &= ~(0xF << FPSCR_FPCC);
649 env->fpscr |= 0x11 << FPSCR_FPCC;
650 /* We must update the target FPR before raising the exception */
652 env->exception_index = POWERPC_EXCP_PROGRAM;
653 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
654 /* Update the floating-point enabled exception summary */
655 env->fpscr |= 1 << FPSCR_FEX;
656 /* Exception is differed */
660 case POWERPC_EXCP_FP_VXSQRT:
661 /* Square root of a negative number */
662 env->fpscr |= 1 << FPSCR_VXSQRT;
664 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
666 /* Set the result to quiet NaN */
668 env->fpscr &= ~(0xF << FPSCR_FPCC);
669 env->fpscr |= 0x11 << FPSCR_FPCC;
672 case POWERPC_EXCP_FP_VXCVI:
673 /* Invalid conversion */
674 env->fpscr |= 1 << FPSCR_VXCVI;
675 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
677 /* Set the result to quiet NaN */
679 env->fpscr &= ~(0xF << FPSCR_FPCC);
680 env->fpscr |= 0x11 << FPSCR_FPCC;
684 /* Update the floating-point invalid operation summary */
685 env->fpscr |= 1 << FPSCR_VX;
686 /* Update the floating-point exception summary */
687 env->fpscr |= 1 << FPSCR_FX;
689 /* Update the floating-point enabled exception summary */
690 env->fpscr |= 1 << FPSCR_FEX;
691 if (msr_fe0 != 0 || msr_fe1 != 0)
692 raise_exception_err(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_FP | op);
697 static always_inline uint64_t float_zero_divide_excp (uint64_t arg1, uint64_t arg2)
699 env->fpscr |= 1 << FPSCR_ZX;
700 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
701 /* Update the floating-point exception summary */
702 env->fpscr |= 1 << FPSCR_FX;
704 /* Update the floating-point enabled exception summary */
705 env->fpscr |= 1 << FPSCR_FEX;
706 if (msr_fe0 != 0 || msr_fe1 != 0) {
707 raise_exception_err(env, POWERPC_EXCP_PROGRAM,
708 POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX);
711 /* Set the result to infinity */
712 arg1 = ((arg1 ^ arg2) & 0x8000000000000000ULL);
713 arg1 |= 0x7FFULL << 52;
718 static always_inline void float_overflow_excp (void)
720 env->fpscr |= 1 << FPSCR_OX;
721 /* Update the floating-point exception summary */
722 env->fpscr |= 1 << FPSCR_FX;
724 /* XXX: should adjust the result */
725 /* Update the floating-point enabled exception summary */
726 env->fpscr |= 1 << FPSCR_FEX;
727 /* We must update the target FPR before raising the exception */
728 env->exception_index = POWERPC_EXCP_PROGRAM;
729 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
731 env->fpscr |= 1 << FPSCR_XX;
732 env->fpscr |= 1 << FPSCR_FI;
736 static always_inline void float_underflow_excp (void)
738 env->fpscr |= 1 << FPSCR_UX;
739 /* Update the floating-point exception summary */
740 env->fpscr |= 1 << FPSCR_FX;
742 /* XXX: should adjust the result */
743 /* Update the floating-point enabled exception summary */
744 env->fpscr |= 1 << FPSCR_FEX;
745 /* We must update the target FPR before raising the exception */
746 env->exception_index = POWERPC_EXCP_PROGRAM;
747 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
751 static always_inline void float_inexact_excp (void)
753 env->fpscr |= 1 << FPSCR_XX;
754 /* Update the floating-point exception summary */
755 env->fpscr |= 1 << FPSCR_FX;
757 /* Update the floating-point enabled exception summary */
758 env->fpscr |= 1 << FPSCR_FEX;
759 /* We must update the target FPR before raising the exception */
760 env->exception_index = POWERPC_EXCP_PROGRAM;
761 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
765 static always_inline void fpscr_set_rounding_mode (void)
769 /* Set rounding mode */
772 /* Best approximation (round to nearest) */
773 rnd_type = float_round_nearest_even;
776 /* Smaller magnitude (round toward zero) */
777 rnd_type = float_round_to_zero;
780 /* Round toward +infinite */
781 rnd_type = float_round_up;
785 /* Round toward -infinite */
786 rnd_type = float_round_down;
789 set_float_rounding_mode(rnd_type, &env->fp_status);
792 void helper_fpscr_setbit (uint32_t bit)
796 prev = (env->fpscr >> bit) & 1;
797 env->fpscr |= 1 << bit;
801 env->fpscr |= 1 << FPSCR_FX;
805 env->fpscr |= 1 << FPSCR_FX;
810 env->fpscr |= 1 << FPSCR_FX;
815 env->fpscr |= 1 << FPSCR_FX;
820 env->fpscr |= 1 << FPSCR_FX;
833 env->fpscr |= 1 << FPSCR_VX;
834 env->fpscr |= 1 << FPSCR_FX;
841 env->error_code = POWERPC_EXCP_FP;
843 env->error_code |= POWERPC_EXCP_FP_VXSNAN;
845 env->error_code |= POWERPC_EXCP_FP_VXISI;
847 env->error_code |= POWERPC_EXCP_FP_VXIDI;
849 env->error_code |= POWERPC_EXCP_FP_VXZDZ;
851 env->error_code |= POWERPC_EXCP_FP_VXIMZ;
853 env->error_code |= POWERPC_EXCP_FP_VXVC;
855 env->error_code |= POWERPC_EXCP_FP_VXSOFT;
857 env->error_code |= POWERPC_EXCP_FP_VXSQRT;
859 env->error_code |= POWERPC_EXCP_FP_VXCVI;
866 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
873 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
880 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX;
887 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
893 fpscr_set_rounding_mode();
898 /* Update the floating-point enabled exception summary */
899 env->fpscr |= 1 << FPSCR_FEX;
900 /* We have to update Rc1 before raising the exception */
901 env->exception_index = POWERPC_EXCP_PROGRAM;
907 void helper_store_fpscr (uint64_t arg, uint32_t mask)
910 * We use only the 32 LSB of the incoming fpr
918 new |= prev & 0x90000000;
919 for (i = 0; i < 7; i++) {
920 if (mask & (1 << i)) {
921 env->fpscr &= ~(0xF << (4 * i));
922 env->fpscr |= new & (0xF << (4 * i));
925 /* Update VX and FEX */
927 env->fpscr |= 1 << FPSCR_VX;
929 env->fpscr &= ~(1 << FPSCR_VX);
930 if ((fpscr_ex & fpscr_eex) != 0) {
931 env->fpscr |= 1 << FPSCR_FEX;
932 env->exception_index = POWERPC_EXCP_PROGRAM;
933 /* XXX: we should compute it properly */
934 env->error_code = POWERPC_EXCP_FP;
937 env->fpscr &= ~(1 << FPSCR_FEX);
938 fpscr_set_rounding_mode();
941 void helper_float_check_status (void)
943 #ifdef CONFIG_SOFTFLOAT
944 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
945 (env->error_code & POWERPC_EXCP_FP)) {
946 /* Differred floating-point exception after target FPR update */
947 if (msr_fe0 != 0 || msr_fe1 != 0)
948 raise_exception_err(env, env->exception_index, env->error_code);
949 } else if (env->fp_status.float_exception_flags & float_flag_overflow) {
950 float_overflow_excp();
951 } else if (env->fp_status.float_exception_flags & float_flag_underflow) {
952 float_underflow_excp();
953 } else if (env->fp_status.float_exception_flags & float_flag_inexact) {
954 float_inexact_excp();
957 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
958 (env->error_code & POWERPC_EXCP_FP)) {
959 /* Differred floating-point exception after target FPR update */
960 if (msr_fe0 != 0 || msr_fe1 != 0)
961 raise_exception_err(env, env->exception_index, env->error_code);
967 #ifdef CONFIG_SOFTFLOAT
968 void helper_reset_fpstatus (void)
970 env->fp_status.float_exception_flags = 0;
975 uint64_t helper_fadd (uint64_t arg1, uint64_t arg2)
977 CPU_DoubleU farg1, farg2;
981 #if USE_PRECISE_EMULATION
982 if (unlikely(float64_is_signaling_nan(farg1.d) ||
983 float64_is_signaling_nan(farg2.d))) {
985 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
986 } else if (likely(isfinite(farg1.d) || isfinite(farg2.d) ||
987 fpisneg(farg1.d) == fpisneg(farg2.d))) {
988 farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
990 /* Magnitude subtraction of infinities */
991 farg1.ll == fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
994 farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
1000 uint64_t helper_fsub (uint64_t arg1, uint64_t arg2)
1002 CPU_DoubleU farg1, farg2;
1006 #if USE_PRECISE_EMULATION
1008 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1009 float64_is_signaling_nan(farg2.d))) {
1010 /* sNaN subtraction */
1011 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1012 } else if (likely(isfinite(farg1.d) || isfinite(farg2.d) ||
1013 fpisneg(farg1.d) != fpisneg(farg2.d))) {
1014 farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
1016 /* Magnitude subtraction of infinities */
1017 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
1021 farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
1027 uint64_t helper_fmul (uint64_t arg1, uint64_t arg2)
1029 CPU_DoubleU farg1, farg2;
1033 #if USE_PRECISE_EMULATION
1034 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1035 float64_is_signaling_nan(farg2.d))) {
1036 /* sNaN multiplication */
1037 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1038 } else if (unlikely((isinfinity(farg1.d) && iszero(farg2.d)) ||
1039 (iszero(farg1.d) && isinfinity(farg2.d)))) {
1040 /* Multiplication of zero by infinity */
1041 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
1043 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1047 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1053 uint64_t helper_fdiv (uint64_t arg1, uint64_t arg2)
1055 CPU_DoubleU farg1, farg2;
1059 #if USE_PRECISE_EMULATION
1060 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1061 float64_is_signaling_nan(farg2.d))) {
1063 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1064 } else if (unlikely(isinfinity(farg1.d) && isinfinity(farg2.d))) {
1065 /* Division of infinity by infinity */
1066 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIDI);
1067 } else if (unlikely(iszero(farg2.d))) {
1068 if (iszero(farg1.d)) {
1069 /* Division of zero by zero */
1070 farg1.ll fload_invalid_op_excp(POWERPC_EXCP_FP_VXZDZ);
1072 /* Division by zero */
1073 farg1.ll = float_zero_divide_excp(farg1.d, farg2.d);
1076 farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
1079 farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
1085 uint64_t helper_fabs (uint64_t arg)
1090 farg.d = float64_abs(farg.d);
1095 uint64_t helper_fnabs (uint64_t arg)
1100 farg.d = float64_abs(farg.d);
1101 farg.d = float64_chs(farg.d);
1106 uint64_t helper_fneg (uint64_t arg)
1111 farg.d = float64_chs(farg.d);
1115 /* fctiw - fctiw. */
1116 uint64_t helper_fctiw (uint64_t arg)
1121 if (unlikely(float64_is_signaling_nan(farg.d))) {
1122 /* sNaN conversion */
1123 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1124 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
1125 /* qNan / infinity conversion */
1126 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1128 farg.ll = float64_to_int32(farg.d, &env->fp_status);
1129 #if USE_PRECISE_EMULATION
1130 /* XXX: higher bits are not supposed to be significant.
1131 * to make tests easier, return the same as a real PowerPC 750
1133 farg.ll |= 0xFFF80000ULL << 32;
1139 /* fctiwz - fctiwz. */
1140 uint64_t helper_fctiwz (uint64_t arg)
1145 if (unlikely(float64_is_signaling_nan(farg.d))) {
1146 /* sNaN conversion */
1147 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1148 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
1149 /* qNan / infinity conversion */
1150 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1152 farg.ll = float64_to_int32_round_to_zero(farg.d, &env->fp_status);
1153 #if USE_PRECISE_EMULATION
1154 /* XXX: higher bits are not supposed to be significant.
1155 * to make tests easier, return the same as a real PowerPC 750
1157 farg.ll |= 0xFFF80000ULL << 32;
1163 #if defined(TARGET_PPC64)
1164 /* fcfid - fcfid. */
1165 uint64_t helper_fcfid (uint64_t arg)
1168 farg.d = int64_to_float64(arg, &env->fp_status);
1172 /* fctid - fctid. */
1173 uint64_t helper_fctid (uint64_t arg)
1178 if (unlikely(float64_is_signaling_nan(farg.d))) {
1179 /* sNaN conversion */
1180 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1181 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
1182 /* qNan / infinity conversion */
1183 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1185 farg.ll = float64_to_int64(farg.d, &env->fp_status);
1190 /* fctidz - fctidz. */
1191 uint64_t helper_fctidz (uint64_t arg)
1196 if (unlikely(float64_is_signaling_nan(farg.d))) {
1197 /* sNaN conversion */
1198 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1199 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
1200 /* qNan / infinity conversion */
1201 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1203 farg.ll = float64_to_int64_round_to_zero(farg.d, &env->fp_status);
1210 static always_inline uint64_t do_fri (uint64_t arg, int rounding_mode)
1215 if (unlikely(float64_is_signaling_nan(farg.d))) {
1217 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1218 } else if (unlikely(float64_is_nan(farg.d) || isinfinity(farg.d))) {
1219 /* qNan / infinity round */
1220 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1222 set_float_rounding_mode(rounding_mode, &env->fp_status);
1223 farg.ll = float64_round_to_int(farg.d, &env->fp_status);
1224 /* Restore rounding mode from FPSCR */
1225 fpscr_set_rounding_mode();
1230 uint64_t helper_frin (uint64_t arg)
1232 return do_fri(arg, float_round_nearest_even);
1235 uint64_t helper_friz (uint64_t arg)
1237 return do_fri(arg, float_round_to_zero);
1240 uint64_t helper_frip (uint64_t arg)
1242 return do_fri(arg, float_round_up);
1245 uint64_t helper_frim (uint64_t arg)
1247 return do_fri(arg, float_round_down);
1250 /* fmadd - fmadd. */
1251 uint64_t helper_fmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1253 CPU_DoubleU farg1, farg2, farg3;
1258 #if USE_PRECISE_EMULATION
1259 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1260 float64_is_signaling_nan(farg2.d) ||
1261 float64_is_signaling_nan(farg3.d))) {
1262 /* sNaN operation */
1263 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1266 /* This is the way the PowerPC specification defines it */
1267 float128 ft0_128, ft1_128;
1269 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1270 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1271 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1272 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1273 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1274 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1276 /* This is OK on x86 hosts */
1277 farg1.d = (farg1.d * farg2.d) + farg3.d;
1281 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1282 farg1.d = float64_add(farg1.d, farg3.d, &env->fp_status);
1287 /* fmsub - fmsub. */
1288 uint64_t helper_fmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1290 CPU_DoubleU farg1, farg2, farg3;
1295 #if USE_PRECISE_EMULATION
1296 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1297 float64_is_signaling_nan(farg2.d) ||
1298 float64_is_signaling_nan(farg3.d))) {
1299 /* sNaN operation */
1300 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1303 /* This is the way the PowerPC specification defines it */
1304 float128 ft0_128, ft1_128;
1306 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1307 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1308 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1309 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1310 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1311 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1313 /* This is OK on x86 hosts */
1314 farg1.d = (farg1.d * farg2.d) - farg3.d;
1318 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1319 farg1.d = float64_sub(farg1.d, farg3.d, &env->fp_status);
1324 /* fnmadd - fnmadd. */
1325 uint64_t helper_fnmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1327 CPU_DoubleU farg1, farg2, farg3;
1333 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1334 float64_is_signaling_nan(farg2.d) ||
1335 float64_is_signaling_nan(farg3.d))) {
1336 /* sNaN operation */
1337 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1339 #if USE_PRECISE_EMULATION
1341 /* This is the way the PowerPC specification defines it */
1342 float128 ft0_128, ft1_128;
1344 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1345 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1346 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1347 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1348 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1349 farg1.d= float128_to_float64(ft0_128, &env->fp_status);
1351 /* This is OK on x86 hosts */
1352 farg1.d = (farg1.d * farg2.d) + farg3.d;
1355 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1356 farg1.d = float64_add(farg1.d, farg3.d, &env->fp_status);
1358 if (likely(!isnan(farg1.d)))
1359 farg1.d = float64_chs(farg1.d);
1364 /* fnmsub - fnmsub. */
1365 uint64_t helper_fnmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1367 CPU_DoubleU farg1, farg2, farg3;
1373 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1374 float64_is_signaling_nan(farg2.d) ||
1375 float64_is_signaling_nan(farg3.d))) {
1376 /* sNaN operation */
1377 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1379 #if USE_PRECISE_EMULATION
1381 /* This is the way the PowerPC specification defines it */
1382 float128 ft0_128, ft1_128;
1384 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1385 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1386 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1387 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1388 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1389 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1391 /* This is OK on x86 hosts */
1392 farg1.d = (farg1.d * farg2.d) - farg3.d;
1395 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1396 farg1.d = float64_sub(farg1.d, farg3.d, &env->fp_status);
1398 if (likely(!isnan(farg1.d)))
1399 farg1.d = float64_chs(farg1.d);
1405 uint64_t helper_frsp (uint64_t arg)
1410 #if USE_PRECISE_EMULATION
1411 if (unlikely(float64_is_signaling_nan(farg.d))) {
1412 /* sNaN square root */
1413 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1415 fard.d = float64_to_float32(farg.d, &env->fp_status);
1418 farg.d = float64_to_float32(farg.d, &env->fp_status);
1423 /* fsqrt - fsqrt. */
1424 uint64_t helper_fsqrt (uint64_t arg)
1429 if (unlikely(float64_is_signaling_nan(farg.d))) {
1430 /* sNaN square root */
1431 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1432 } else if (unlikely(fpisneg(farg.d) && !iszero(farg.d))) {
1433 /* Square root of a negative nonzero number */
1434 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1436 farg.d = float64_sqrt(farg.d, &env->fp_status);
1442 uint64_t helper_fre (uint64_t arg)
1447 if (unlikely(float64_is_signaling_nan(farg.d))) {
1448 /* sNaN reciprocal */
1449 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1450 } else if (unlikely(iszero(farg.d))) {
1451 /* Zero reciprocal */
1452 farg.ll = float_zero_divide_excp(1.0, farg.d);
1453 } else if (likely(isnormal(farg.d))) {
1454 farg.d = float64_div(1.0, farg.d, &env->fp_status);
1456 if (farg.ll == 0x8000000000000000ULL) {
1457 farg.ll = 0xFFF0000000000000ULL;
1458 } else if (farg.ll == 0x0000000000000000ULL) {
1459 farg.ll = 0x7FF0000000000000ULL;
1460 } else if (isnan(farg.d)) {
1461 farg.ll = 0x7FF8000000000000ULL;
1462 } else if (fpisneg(farg.d)) {
1463 farg.ll = 0x8000000000000000ULL;
1465 farg.ll = 0x0000000000000000ULL;
1472 uint64_t helper_fres (uint64_t arg)
1477 if (unlikely(float64_is_signaling_nan(farg.d))) {
1478 /* sNaN reciprocal */
1479 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1480 } else if (unlikely(iszero(farg.d))) {
1481 /* Zero reciprocal */
1482 farg.ll = float_zero_divide_excp(1.0, farg.d);
1483 } else if (likely(isnormal(farg.d))) {
1484 #if USE_PRECISE_EMULATION
1485 farg.d = float64_div(1.0, farg.d, &env->fp_status);
1486 farg.d = float64_to_float32(farg.d, &env->fp_status);
1488 farg.d = float32_div(1.0, farg.d, &env->fp_status);
1491 if (farg.ll == 0x8000000000000000ULL) {
1492 farg.ll = 0xFFF0000000000000ULL;
1493 } else if (farg.ll == 0x0000000000000000ULL) {
1494 farg.ll = 0x7FF0000000000000ULL;
1495 } else if (isnan(farg.d)) {
1496 farg.ll = 0x7FF8000000000000ULL;
1497 } else if (fpisneg(farg.d)) {
1498 farg.ll = 0x8000000000000000ULL;
1500 farg.ll = 0x0000000000000000ULL;
1506 /* frsqrte - frsqrte. */
1507 uint64_t helper_frsqrte (uint64_t arg)
1512 if (unlikely(float64_is_signaling_nan(farg.d))) {
1513 /* sNaN reciprocal square root */
1514 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1515 } else if (unlikely(fpisneg(farg.d) && !iszero(farg.d))) {
1516 /* Reciprocal square root of a negative nonzero number */
1517 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1518 } else if (likely(isnormal(farg.d))) {
1519 farg.d = float64_sqrt(farg.d, &env->fp_status);
1520 farg.d = float32_div(1.0, farg.d, &env->fp_status);
1522 if (farg.ll == 0x8000000000000000ULL) {
1523 farg.ll = 0xFFF0000000000000ULL;
1524 } else if (farg.ll == 0x0000000000000000ULL) {
1525 farg.ll = 0x7FF0000000000000ULL;
1526 } else if (isnan(farg.d)) {
1527 farg.ll |= 0x000FFFFFFFFFFFFFULL;
1528 } else if (fpisneg(farg.d)) {
1529 farg.ll = 0x7FF8000000000000ULL;
1531 farg.ll = 0x0000000000000000ULL;
1538 uint64_t helper_fsel (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1540 CPU_DoubleU farg1, farg2, farg3;
1546 if (!fpisneg(farg1.d) || iszero(farg1.d))
1552 uint32_t helper_fcmpu (uint64_t arg1, uint64_t arg2)
1554 CPU_DoubleU farg1, farg2;
1559 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1560 float64_is_signaling_nan(farg2.d))) {
1561 /* sNaN comparison */
1562 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1564 if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1566 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1572 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1573 env->fpscr |= ret << FPSCR_FPRF;
1577 uint32_t helper_fcmpo (uint64_t arg1, uint64_t arg2)
1579 CPU_DoubleU farg1, farg2;
1584 if (unlikely(float64_is_nan(farg1.d) ||
1585 float64_is_nan(farg2.d))) {
1586 if (float64_is_signaling_nan(farg1.d) ||
1587 float64_is_signaling_nan(farg2.d)) {
1588 /* sNaN comparison */
1589 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN |
1590 POWERPC_EXCP_FP_VXVC);
1592 /* qNaN comparison */
1593 fload_invalid_op_excp(POWERPC_EXCP_FP_VXVC);
1596 if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1598 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1604 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1605 env->fpscr |= ret << FPSCR_FPRF;
1609 #if !defined (CONFIG_USER_ONLY)
1610 void cpu_dump_rfi (target_ulong RA, target_ulong msr);
1612 void do_store_msr (void)
1614 T0 = hreg_store_msr(env, T0, 0);
1616 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1617 raise_exception(env, T0);
1621 static always_inline void do_rfi (target_ulong nip, target_ulong msr,
1622 target_ulong msrm, int keep_msrh)
1624 #if defined(TARGET_PPC64)
1625 if (msr & (1ULL << MSR_SF)) {
1626 nip = (uint64_t)nip;
1627 msr &= (uint64_t)msrm;
1629 nip = (uint32_t)nip;
1630 msr = (uint32_t)(msr & msrm);
1632 msr |= env->msr & ~((uint64_t)0xFFFFFFFF);
1635 nip = (uint32_t)nip;
1636 msr &= (uint32_t)msrm;
1638 /* XXX: beware: this is false if VLE is supported */
1639 env->nip = nip & ~((target_ulong)0x00000003);
1640 hreg_store_msr(env, msr, 1);
1641 #if defined (DEBUG_OP)
1642 cpu_dump_rfi(env->nip, env->msr);
1644 /* No need to raise an exception here,
1645 * as rfi is always the last insn of a TB
1647 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1650 void helper_rfi (void)
1652 do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1653 ~((target_ulong)0xFFFF0000), 1);
1656 #if defined(TARGET_PPC64)
1657 void helper_rfid (void)
1659 do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1660 ~((target_ulong)0xFFFF0000), 0);
1663 void helper_hrfid (void)
1665 do_rfi(env->spr[SPR_HSRR0], env->spr[SPR_HSRR1],
1666 ~((target_ulong)0xFFFF0000), 0);
1671 void helper_tw (target_ulong arg1, target_ulong arg2, uint32_t flags)
1673 if (!likely(!(((int32_t)arg1 < (int32_t)arg2 && (flags & 0x10)) ||
1674 ((int32_t)arg1 > (int32_t)arg2 && (flags & 0x08)) ||
1675 ((int32_t)arg1 == (int32_t)arg2 && (flags & 0x04)) ||
1676 ((uint32_t)arg1 < (uint32_t)arg2 && (flags & 0x02)) ||
1677 ((uint32_t)arg1 > (uint32_t)arg2 && (flags & 0x01))))) {
1678 raise_exception_err(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1682 #if defined(TARGET_PPC64)
1683 void helper_td (target_ulong arg1, target_ulong arg2, uint32_t flags)
1685 if (!likely(!(((int64_t)arg1 < (int64_t)arg2 && (flags & 0x10)) ||
1686 ((int64_t)arg1 > (int64_t)arg2 && (flags & 0x08)) ||
1687 ((int64_t)arg1 == (int64_t)arg2 && (flags & 0x04)) ||
1688 ((uint64_t)arg1 < (uint64_t)arg2 && (flags & 0x02)) ||
1689 ((uint64_t)arg1 > (uint64_t)arg2 && (flags & 0x01)))))
1690 raise_exception_err(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1694 /*****************************************************************************/
1695 /* PowerPC 601 specific instructions (POWER bridge) */
1696 void do_POWER_abso (void)
1698 if ((int32_t)T0 == INT32_MIN) {
1700 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1701 } else if ((int32_t)T0 < 0) {
1703 env->xer &= ~(1 << XER_OV);
1705 env->xer &= ~(1 << XER_OV);
1709 void do_POWER_clcs (void)
1713 /* Instruction cache line size */
1714 T0 = env->icache_line_size;
1717 /* Data cache line size */
1718 T0 = env->dcache_line_size;
1721 /* Minimum cache line size */
1722 T0 = env->icache_line_size < env->dcache_line_size ?
1723 env->icache_line_size : env->dcache_line_size;
1726 /* Maximum cache line size */
1727 T0 = env->icache_line_size > env->dcache_line_size ?
1728 env->icache_line_size : env->dcache_line_size;
1736 void do_POWER_div (void)
1740 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1742 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
1743 env->spr[SPR_MQ] = 0;
1745 tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
1746 env->spr[SPR_MQ] = tmp % T1;
1747 T0 = tmp / (int32_t)T1;
1751 void do_POWER_divo (void)
1755 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1757 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
1758 env->spr[SPR_MQ] = 0;
1759 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1761 tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
1762 env->spr[SPR_MQ] = tmp % T1;
1764 if (tmp > (int64_t)INT32_MAX || tmp < (int64_t)INT32_MIN) {
1765 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1767 env->xer &= ~(1 << XER_OV);
1773 void do_POWER_divs (void)
1775 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1777 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
1778 env->spr[SPR_MQ] = 0;
1780 env->spr[SPR_MQ] = T0 % T1;
1781 T0 = (int32_t)T0 / (int32_t)T1;
1785 void do_POWER_divso (void)
1787 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1789 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
1790 env->spr[SPR_MQ] = 0;
1791 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1793 T0 = (int32_t)T0 / (int32_t)T1;
1794 env->spr[SPR_MQ] = (int32_t)T0 % (int32_t)T1;
1795 env->xer &= ~(1 << XER_OV);
1799 void do_POWER_dozo (void)
1801 if ((int32_t)T1 > (int32_t)T0) {
1804 if (((uint32_t)(~T2) ^ (uint32_t)T1 ^ UINT32_MAX) &
1805 ((uint32_t)(~T2) ^ (uint32_t)T0) & (1UL << 31)) {
1806 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1808 env->xer &= ~(1 << XER_OV);
1812 env->xer &= ~(1 << XER_OV);
1816 void do_POWER_maskg (void)
1820 if ((uint32_t)T0 == (uint32_t)(T1 + 1)) {
1823 ret = (UINT32_MAX >> ((uint32_t)T0)) ^
1824 ((UINT32_MAX >> ((uint32_t)T1)) >> 1);
1825 if ((uint32_t)T0 > (uint32_t)T1)
1831 void do_POWER_mulo (void)
1835 tmp = (uint64_t)T0 * (uint64_t)T1;
1836 env->spr[SPR_MQ] = tmp >> 32;
1838 if (tmp >> 32 != ((uint64_t)T0 >> 16) * ((uint64_t)T1 >> 16)) {
1839 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1841 env->xer &= ~(1 << XER_OV);
1845 #if !defined (CONFIG_USER_ONLY)
1846 void do_POWER_rac (void)
1851 /* We don't have to generate many instances of this instruction,
1852 * as rac is supervisor only.
1854 /* XXX: FIX THIS: Pretend we have no BAT */
1855 nb_BATs = env->nb_BATs;
1857 if (get_physical_address(env, &ctx, T0, 0, ACCESS_INT) == 0)
1859 env->nb_BATs = nb_BATs;
1862 void helper_rfsvc (void)
1864 do_rfi(env->lr, env->ctr, 0x0000FFFF, 0);
1867 void do_store_hid0_601 (void)
1871 hid0 = env->spr[SPR_HID0];
1872 if ((T0 ^ hid0) & 0x00000008) {
1873 /* Change current endianness */
1874 env->hflags &= ~(1 << MSR_LE);
1875 env->hflags_nmsr &= ~(1 << MSR_LE);
1876 env->hflags_nmsr |= (1 << MSR_LE) & (((T0 >> 3) & 1) << MSR_LE);
1877 env->hflags |= env->hflags_nmsr;
1878 if (loglevel != 0) {
1879 fprintf(logfile, "%s: set endianness to %c => " ADDRX "\n",
1880 __func__, T0 & 0x8 ? 'l' : 'b', env->hflags);
1883 env->spr[SPR_HID0] = T0;
1887 /*****************************************************************************/
1888 /* 602 specific instructions */
1889 /* mfrom is the most crazy instruction ever seen, imho ! */
1890 /* Real implementation uses a ROM table. Do the same */
1891 #define USE_MFROM_ROM_TABLE
1892 target_ulong helper_602_mfrom (target_ulong arg)
1894 if (likely(arg < 602)) {
1895 #if defined(USE_MFROM_ROM_TABLE)
1896 #include "mfrom_table.c"
1897 return mfrom_ROM_table[T0];
1900 /* Extremly decomposed:
1902 * return 256 * log10(10 + 1.0) + 0.5
1905 d = float64_div(d, 256, &env->fp_status);
1907 d = exp10(d); // XXX: use float emulation function
1908 d = float64_add(d, 1.0, &env->fp_status);
1909 d = log10(d); // XXX: use float emulation function
1910 d = float64_mul(d, 256, &env->fp_status);
1911 d = float64_add(d, 0.5, &env->fp_status);
1912 return float64_round_to_int(d, &env->fp_status);
1919 /*****************************************************************************/
1920 /* Embedded PowerPC specific helpers */
1922 /* XXX: to be improved to check access rights when in user-mode */
1923 void do_load_dcr (void)
1927 if (unlikely(env->dcr_env == NULL)) {
1928 if (loglevel != 0) {
1929 fprintf(logfile, "No DCR environment\n");
1931 raise_exception_err(env, POWERPC_EXCP_PROGRAM,
1932 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
1933 } else if (unlikely(ppc_dcr_read(env->dcr_env, T0, &val) != 0)) {
1934 if (loglevel != 0) {
1935 fprintf(logfile, "DCR read error %d %03x\n", (int)T0, (int)T0);
1937 raise_exception_err(env, POWERPC_EXCP_PROGRAM,
1938 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
1944 void do_store_dcr (void)
1946 if (unlikely(env->dcr_env == NULL)) {
1947 if (loglevel != 0) {
1948 fprintf(logfile, "No DCR environment\n");
1950 raise_exception_err(env, POWERPC_EXCP_PROGRAM,
1951 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
1952 } else if (unlikely(ppc_dcr_write(env->dcr_env, T0, T1) != 0)) {
1953 if (loglevel != 0) {
1954 fprintf(logfile, "DCR write error %d %03x\n", (int)T0, (int)T0);
1956 raise_exception_err(env, POWERPC_EXCP_PROGRAM,
1957 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
1961 #if !defined(CONFIG_USER_ONLY)
1962 void helper_40x_rfci (void)
1964 do_rfi(env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3],
1965 ~((target_ulong)0xFFFF0000), 0);
1968 void helper_rfci (void)
1970 do_rfi(env->spr[SPR_BOOKE_CSRR0], SPR_BOOKE_CSRR1,
1971 ~((target_ulong)0x3FFF0000), 0);
1974 void helper_rfdi (void)
1976 do_rfi(env->spr[SPR_BOOKE_DSRR0], SPR_BOOKE_DSRR1,
1977 ~((target_ulong)0x3FFF0000), 0);
1980 void helper_rfmci (void)
1982 do_rfi(env->spr[SPR_BOOKE_MCSRR0], SPR_BOOKE_MCSRR1,
1983 ~((target_ulong)0x3FFF0000), 0);
1986 void do_load_403_pb (int num)
1991 void do_store_403_pb (int num)
1993 if (likely(env->pb[num] != T0)) {
1995 /* Should be optimized */
2002 void do_440_dlmzb (void)
2008 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
2009 if ((T0 & mask) == 0)
2013 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
2014 if ((T1 & mask) == 0)
2022 /*****************************************************************************/
2023 /* SPE extension helpers */
2024 /* Use a table to make this quicker */
2025 static uint8_t hbrev[16] = {
2026 0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE,
2027 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF,
2030 static always_inline uint8_t byte_reverse (uint8_t val)
2032 return hbrev[val >> 4] | (hbrev[val & 0xF] << 4);
2035 static always_inline uint32_t word_reverse (uint32_t val)
2037 return byte_reverse(val >> 24) | (byte_reverse(val >> 16) << 8) |
2038 (byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24);
2041 #define MASKBITS 16 // Random value - to be fixed (implementation dependant)
2042 target_ulong helper_brinc (target_ulong arg1, target_ulong arg2)
2044 uint32_t a, b, d, mask;
2046 mask = UINT32_MAX >> (32 - MASKBITS);
2049 d = word_reverse(1 + word_reverse(a | ~b));
2050 return (arg1 & ~mask) | (d & b);
2053 uint32_t helper_cntlsw32 (uint32_t val)
2055 if (val & 0x80000000)
2061 uint32_t helper_cntlzw32 (uint32_t val)
2066 /* Single-precision floating-point conversions */
2067 static always_inline uint32_t efscfsi (uint32_t val)
2071 u.f = int32_to_float32(val, &env->spe_status);
2076 static always_inline uint32_t efscfui (uint32_t val)
2080 u.f = uint32_to_float32(val, &env->spe_status);
2085 static always_inline int32_t efsctsi (uint32_t val)
2090 /* NaN are not treated the same way IEEE 754 does */
2091 if (unlikely(isnan(u.f)))
2094 return float32_to_int32(u.f, &env->spe_status);
2097 static always_inline uint32_t efsctui (uint32_t val)
2102 /* NaN are not treated the same way IEEE 754 does */
2103 if (unlikely(isnan(u.f)))
2106 return float32_to_uint32(u.f, &env->spe_status);
2109 static always_inline uint32_t efsctsiz (uint32_t val)
2114 /* NaN are not treated the same way IEEE 754 does */
2115 if (unlikely(isnan(u.f)))
2118 return float32_to_int32_round_to_zero(u.f, &env->spe_status);
2121 static always_inline uint32_t efsctuiz (uint32_t val)
2126 /* NaN are not treated the same way IEEE 754 does */
2127 if (unlikely(isnan(u.f)))
2130 return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
2133 static always_inline uint32_t efscfsf (uint32_t val)
2138 u.f = int32_to_float32(val, &env->spe_status);
2139 tmp = int64_to_float32(1ULL << 32, &env->spe_status);
2140 u.f = float32_div(u.f, tmp, &env->spe_status);
2145 static always_inline uint32_t efscfuf (uint32_t val)
2150 u.f = uint32_to_float32(val, &env->spe_status);
2151 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2152 u.f = float32_div(u.f, tmp, &env->spe_status);
2157 static always_inline uint32_t efsctsf (uint32_t val)
2163 /* NaN are not treated the same way IEEE 754 does */
2164 if (unlikely(isnan(u.f)))
2166 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2167 u.f = float32_mul(u.f, tmp, &env->spe_status);
2169 return float32_to_int32(u.f, &env->spe_status);
2172 static always_inline uint32_t efsctuf (uint32_t val)
2178 /* NaN are not treated the same way IEEE 754 does */
2179 if (unlikely(isnan(u.f)))
2181 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2182 u.f = float32_mul(u.f, tmp, &env->spe_status);
2184 return float32_to_uint32(u.f, &env->spe_status);
2187 #define HELPER_SPE_SINGLE_CONV(name) \
2188 uint32_t helper_e##name (uint32_t val) \
2190 return e##name(val); \
2193 HELPER_SPE_SINGLE_CONV(fscfsi);
2195 HELPER_SPE_SINGLE_CONV(fscfui);
2197 HELPER_SPE_SINGLE_CONV(fscfuf);
2199 HELPER_SPE_SINGLE_CONV(fscfsf);
2201 HELPER_SPE_SINGLE_CONV(fsctsi);
2203 HELPER_SPE_SINGLE_CONV(fsctui);
2205 HELPER_SPE_SINGLE_CONV(fsctsiz);
2207 HELPER_SPE_SINGLE_CONV(fsctuiz);
2209 HELPER_SPE_SINGLE_CONV(fsctsf);
2211 HELPER_SPE_SINGLE_CONV(fsctuf);
2213 #define HELPER_SPE_VECTOR_CONV(name) \
2214 uint64_t helper_ev##name (uint64_t val) \
2216 return ((uint64_t)e##name(val >> 32) << 32) | \
2217 (uint64_t)e##name(val); \
2220 HELPER_SPE_VECTOR_CONV(fscfsi);
2222 HELPER_SPE_VECTOR_CONV(fscfui);
2224 HELPER_SPE_VECTOR_CONV(fscfuf);
2226 HELPER_SPE_VECTOR_CONV(fscfsf);
2228 HELPER_SPE_VECTOR_CONV(fsctsi);
2230 HELPER_SPE_VECTOR_CONV(fsctui);
2232 HELPER_SPE_VECTOR_CONV(fsctsiz);
2234 HELPER_SPE_VECTOR_CONV(fsctuiz);
2236 HELPER_SPE_VECTOR_CONV(fsctsf);
2238 HELPER_SPE_VECTOR_CONV(fsctuf);
2240 /* Single-precision floating-point arithmetic */
2241 static always_inline uint32_t efsadd (uint32_t op1, uint32_t op2)
2246 u1.f = float32_add(u1.f, u2.f, &env->spe_status);
2250 static always_inline uint32_t efssub (uint32_t op1, uint32_t op2)
2255 u1.f = float32_sub(u1.f, u2.f, &env->spe_status);
2259 static always_inline uint32_t efsmul (uint32_t op1, uint32_t op2)
2264 u1.f = float32_mul(u1.f, u2.f, &env->spe_status);
2268 static always_inline uint32_t efsdiv (uint32_t op1, uint32_t op2)
2273 u1.f = float32_div(u1.f, u2.f, &env->spe_status);
2277 #define HELPER_SPE_SINGLE_ARITH(name) \
2278 uint32_t helper_e##name (uint32_t op1, uint32_t op2) \
2280 return e##name(op1, op2); \
2283 HELPER_SPE_SINGLE_ARITH(fsadd);
2285 HELPER_SPE_SINGLE_ARITH(fssub);
2287 HELPER_SPE_SINGLE_ARITH(fsmul);
2289 HELPER_SPE_SINGLE_ARITH(fsdiv);
2291 #define HELPER_SPE_VECTOR_ARITH(name) \
2292 uint64_t helper_ev##name (uint64_t op1, uint64_t op2) \
2294 return ((uint64_t)e##name(op1 >> 32, op2 >> 32) << 32) | \
2295 (uint64_t)e##name(op1, op2); \
2298 HELPER_SPE_VECTOR_ARITH(fsadd);
2300 HELPER_SPE_VECTOR_ARITH(fssub);
2302 HELPER_SPE_VECTOR_ARITH(fsmul);
2304 HELPER_SPE_VECTOR_ARITH(fsdiv);
2306 /* Single-precision floating-point comparisons */
2307 static always_inline uint32_t efststlt (uint32_t op1, uint32_t op2)
2312 return float32_lt(u1.f, u2.f, &env->spe_status) ? 4 : 0;
2315 static always_inline uint32_t efststgt (uint32_t op1, uint32_t op2)
2320 return float32_le(u1.f, u2.f, &env->spe_status) ? 0 : 4;
2323 static always_inline uint32_t efststeq (uint32_t op1, uint32_t op2)
2328 return float32_eq(u1.f, u2.f, &env->spe_status) ? 4 : 0;
2331 static always_inline uint32_t efscmplt (uint32_t op1, uint32_t op2)
2333 /* XXX: TODO: test special values (NaN, infinites, ...) */
2334 return efststlt(op1, op2);
2337 static always_inline uint32_t efscmpgt (uint32_t op1, uint32_t op2)
2339 /* XXX: TODO: test special values (NaN, infinites, ...) */
2340 return efststgt(op1, op2);
2343 static always_inline uint32_t efscmpeq (uint32_t op1, uint32_t op2)
2345 /* XXX: TODO: test special values (NaN, infinites, ...) */
2346 return efststeq(op1, op2);
2349 #define HELPER_SINGLE_SPE_CMP(name) \
2350 uint32_t helper_e##name (uint32_t op1, uint32_t op2) \
2352 return e##name(op1, op2) << 2; \
2355 HELPER_SINGLE_SPE_CMP(fststlt);
2357 HELPER_SINGLE_SPE_CMP(fststgt);
2359 HELPER_SINGLE_SPE_CMP(fststeq);
2361 HELPER_SINGLE_SPE_CMP(fscmplt);
2363 HELPER_SINGLE_SPE_CMP(fscmpgt);
2365 HELPER_SINGLE_SPE_CMP(fscmpeq);
2367 static always_inline uint32_t evcmp_merge (int t0, int t1)
2369 return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
2372 #define HELPER_VECTOR_SPE_CMP(name) \
2373 uint32_t helper_ev##name (uint64_t op1, uint64_t op2) \
2375 return evcmp_merge(e##name(op1 >> 32, op2 >> 32), e##name(op1, op2)); \
2378 HELPER_VECTOR_SPE_CMP(fststlt);
2380 HELPER_VECTOR_SPE_CMP(fststgt);
2382 HELPER_VECTOR_SPE_CMP(fststeq);
2384 HELPER_VECTOR_SPE_CMP(fscmplt);
2386 HELPER_VECTOR_SPE_CMP(fscmpgt);
2388 HELPER_VECTOR_SPE_CMP(fscmpeq);
2390 /* Double-precision floating-point conversion */
2391 uint64_t helper_efdcfsi (uint32_t val)
2395 u.d = int32_to_float64(val, &env->spe_status);
2400 uint64_t helper_efdcfsid (uint64_t val)
2404 u.d = int64_to_float64(val, &env->spe_status);
2409 uint64_t helper_efdcfui (uint32_t val)
2413 u.d = uint32_to_float64(val, &env->spe_status);
2418 uint64_t helper_efdcfuid (uint64_t val)
2422 u.d = uint64_to_float64(val, &env->spe_status);
2427 uint32_t helper_efdctsi (uint64_t val)
2432 /* NaN are not treated the same way IEEE 754 does */
2433 if (unlikely(isnan(u.d)))
2436 return float64_to_int32(u.d, &env->spe_status);
2439 uint32_t helper_efdctui (uint64_t val)
2444 /* NaN are not treated the same way IEEE 754 does */
2445 if (unlikely(isnan(u.d)))
2448 return float64_to_uint32(u.d, &env->spe_status);
2451 uint32_t helper_efdctsiz (uint64_t val)
2456 /* NaN are not treated the same way IEEE 754 does */
2457 if (unlikely(isnan(u.d)))
2460 return float64_to_int32_round_to_zero(u.d, &env->spe_status);
2463 uint64_t helper_efdctsidz (uint64_t val)
2468 /* NaN are not treated the same way IEEE 754 does */
2469 if (unlikely(isnan(u.d)))
2472 return float64_to_int64_round_to_zero(u.d, &env->spe_status);
2475 uint32_t helper_efdctuiz (uint64_t val)
2480 /* NaN are not treated the same way IEEE 754 does */
2481 if (unlikely(isnan(u.d)))
2484 return float64_to_uint32_round_to_zero(u.d, &env->spe_status);
2487 uint64_t helper_efdctuidz (uint64_t val)
2492 /* NaN are not treated the same way IEEE 754 does */
2493 if (unlikely(isnan(u.d)))
2496 return float64_to_uint64_round_to_zero(u.d, &env->spe_status);
2499 uint64_t helper_efdcfsf (uint32_t val)
2504 u.d = int32_to_float64(val, &env->spe_status);
2505 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
2506 u.d = float64_div(u.d, tmp, &env->spe_status);
2511 uint64_t helper_efdcfuf (uint32_t val)
2516 u.d = uint32_to_float64(val, &env->spe_status);
2517 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
2518 u.d = float64_div(u.d, tmp, &env->spe_status);
2523 uint32_t helper_efdctsf (uint64_t val)
2529 /* NaN are not treated the same way IEEE 754 does */
2530 if (unlikely(isnan(u.d)))
2532 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2533 u.d = float64_mul(u.d, tmp, &env->spe_status);
2535 return float64_to_int32(u.d, &env->spe_status);
2538 uint32_t helper_efdctuf (uint64_t val)
2544 /* NaN are not treated the same way IEEE 754 does */
2545 if (unlikely(isnan(u.d)))
2547 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2548 u.d = float64_mul(u.d, tmp, &env->spe_status);
2550 return float64_to_uint32(u.d, &env->spe_status);
2553 uint32_t helper_efscfd (uint64_t val)
2559 u2.f = float64_to_float32(u1.d, &env->spe_status);
2564 uint64_t helper_efdcfs (uint32_t val)
2570 u2.d = float32_to_float64(u1.f, &env->spe_status);
2575 /* Double precision fixed-point arithmetic */
2576 uint64_t helper_efdadd (uint64_t op1, uint64_t op2)
2581 u1.d = float64_add(u1.d, u2.d, &env->spe_status);
2585 uint64_t helper_efdsub (uint64_t op1, uint64_t op2)
2590 u1.d = float64_sub(u1.d, u2.d, &env->spe_status);
2594 uint64_t helper_efdmul (uint64_t op1, uint64_t op2)
2599 u1.d = float64_mul(u1.d, u2.d, &env->spe_status);
2603 uint64_t helper_efddiv (uint64_t op1, uint64_t op2)
2608 u1.d = float64_div(u1.d, u2.d, &env->spe_status);
2612 /* Double precision floating point helpers */
2613 uint32_t helper_efdtstlt (uint64_t op1, uint64_t op2)
2618 return float64_lt(u1.d, u2.d, &env->spe_status) ? 4 : 0;
2621 uint32_t helper_efdtstgt (uint64_t op1, uint64_t op2)
2626 return float64_le(u1.d, u2.d, &env->spe_status) ? 0 : 4;
2629 uint32_t helper_efdtsteq (uint64_t op1, uint64_t op2)
2634 return float64_eq(u1.d, u2.d, &env->spe_status) ? 4 : 0;
2637 uint32_t helper_efdcmplt (uint64_t op1, uint64_t op2)
2639 /* XXX: TODO: test special values (NaN, infinites, ...) */
2640 return helper_efdtstlt(op1, op2);
2643 uint32_t helper_efdcmpgt (uint64_t op1, uint64_t op2)
2645 /* XXX: TODO: test special values (NaN, infinites, ...) */
2646 return helper_efdtstgt(op1, op2);
2649 uint32_t helper_efdcmpeq (uint64_t op1, uint64_t op2)
2651 /* XXX: TODO: test special values (NaN, infinites, ...) */
2652 return helper_efdtsteq(op1, op2);
2655 /*****************************************************************************/
2656 /* Softmmu support */
2657 #if !defined (CONFIG_USER_ONLY)
2659 #define MMUSUFFIX _mmu
2662 #include "softmmu_template.h"
2665 #include "softmmu_template.h"
2668 #include "softmmu_template.h"
2671 #include "softmmu_template.h"
2673 /* try to fill the TLB and return an exception if error. If retaddr is
2674 NULL, it means that the function was called in C code (i.e. not
2675 from generated code or from helper.c) */
2676 /* XXX: fix it to restore all registers */
2677 void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
2679 TranslationBlock *tb;
2680 CPUState *saved_env;
2684 /* XXX: hack to restore env in all cases, even if not called from
2687 env = cpu_single_env;
2688 ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
2689 if (unlikely(ret != 0)) {
2690 if (likely(retaddr)) {
2691 /* now we have a real cpu fault */
2692 pc = (unsigned long)retaddr;
2693 tb = tb_find_pc(pc);
2695 /* the PC is inside the translated code. It means that we have
2696 a virtual CPU fault */
2697 cpu_restore_state(tb, env, pc, NULL);
2700 raise_exception_err(env, env->exception_index, env->error_code);
2705 /* Software driven TLBs management */
2706 /* PowerPC 602/603 software TLB load instructions helpers */
2707 static void helper_load_6xx_tlb (target_ulong new_EPN, int is_code)
2709 target_ulong RPN, CMP, EPN;
2712 RPN = env->spr[SPR_RPA];
2714 CMP = env->spr[SPR_ICMP];
2715 EPN = env->spr[SPR_IMISS];
2717 CMP = env->spr[SPR_DCMP];
2718 EPN = env->spr[SPR_DMISS];
2720 way = (env->spr[SPR_SRR1] >> 17) & 1;
2721 #if defined (DEBUG_SOFTWARE_TLB)
2722 if (loglevel != 0) {
2723 fprintf(logfile, "%s: EPN " TDX " " ADDRX " PTE0 " ADDRX
2724 " PTE1 " ADDRX " way %d\n",
2725 __func__, T0, EPN, CMP, RPN, way);
2728 /* Store this TLB */
2729 ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
2730 way, is_code, CMP, RPN);
2733 void helper_load_6xx_tlbd (target_ulong EPN)
2735 helper_load_6xx_tlb(EPN, 0);
2738 void helper_load_6xx_tlbi (target_ulong EPN)
2740 helper_load_6xx_tlb(EPN, 1);
2743 /* PowerPC 74xx software TLB load instructions helpers */
2744 static void helper_load_74xx_tlb (target_ulong new_EPN, int is_code)
2746 target_ulong RPN, CMP, EPN;
2749 RPN = env->spr[SPR_PTELO];
2750 CMP = env->spr[SPR_PTEHI];
2751 EPN = env->spr[SPR_TLBMISS] & ~0x3;
2752 way = env->spr[SPR_TLBMISS] & 0x3;
2753 #if defined (DEBUG_SOFTWARE_TLB)
2754 if (loglevel != 0) {
2755 fprintf(logfile, "%s: EPN " TDX " " ADDRX " PTE0 " ADDRX
2756 " PTE1 " ADDRX " way %d\n",
2757 __func__, T0, EPN, CMP, RPN, way);
2760 /* Store this TLB */
2761 ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
2762 way, is_code, CMP, RPN);
2765 void helper_load_74xx_tlbd (target_ulong EPN)
2767 helper_load_74xx_tlb(EPN, 0);
2770 void helper_load_74xx_tlbi (target_ulong EPN)
2772 helper_load_74xx_tlb(EPN, 1);
2775 static always_inline target_ulong booke_tlb_to_page_size (int size)
2777 return 1024 << (2 * size);
2780 static always_inline int booke_page_size_to_tlb (target_ulong page_size)
2784 switch (page_size) {
2818 #if defined (TARGET_PPC64)
2819 case 0x000100000000ULL:
2822 case 0x000400000000ULL:
2825 case 0x001000000000ULL:
2828 case 0x004000000000ULL:
2831 case 0x010000000000ULL:
2843 /* Helpers for 4xx TLB management */
2844 void do_4xx_tlbre_lo (void)
2850 tlb = &env->tlb[T0].tlbe;
2852 if (tlb->prot & PAGE_VALID)
2854 size = booke_page_size_to_tlb(tlb->size);
2855 if (size < 0 || size > 0x7)
2858 env->spr[SPR_40x_PID] = tlb->PID;
2861 void do_4xx_tlbre_hi (void)
2866 tlb = &env->tlb[T0].tlbe;
2868 if (tlb->prot & PAGE_EXEC)
2870 if (tlb->prot & PAGE_WRITE)
2874 void do_4xx_tlbwe_hi (void)
2877 target_ulong page, end;
2879 #if defined (DEBUG_SOFTWARE_TLB)
2880 if (loglevel != 0) {
2881 fprintf(logfile, "%s T0 " TDX " T1 " TDX "\n", __func__, T0, T1);
2885 tlb = &env->tlb[T0].tlbe;
2886 /* Invalidate previous TLB (if it's valid) */
2887 if (tlb->prot & PAGE_VALID) {
2888 end = tlb->EPN + tlb->size;
2889 #if defined (DEBUG_SOFTWARE_TLB)
2890 if (loglevel != 0) {
2891 fprintf(logfile, "%s: invalidate old TLB %d start " ADDRX
2892 " end " ADDRX "\n", __func__, (int)T0, tlb->EPN, end);
2895 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2896 tlb_flush_page(env, page);
2898 tlb->size = booke_tlb_to_page_size((T1 >> 7) & 0x7);
2899 /* We cannot handle TLB size < TARGET_PAGE_SIZE.
2900 * If this ever occurs, one should use the ppcemb target instead
2901 * of the ppc or ppc64 one
2903 if ((T1 & 0x40) && tlb->size < TARGET_PAGE_SIZE) {
2904 cpu_abort(env, "TLB size " TARGET_FMT_lu " < %u "
2905 "are not supported (%d)\n",
2906 tlb->size, TARGET_PAGE_SIZE, (int)((T1 >> 7) & 0x7));
2908 tlb->EPN = T1 & ~(tlb->size - 1);
2910 tlb->prot |= PAGE_VALID;
2912 tlb->prot &= ~PAGE_VALID;
2914 /* XXX: TO BE FIXED */
2915 cpu_abort(env, "Little-endian TLB entries are not supported by now\n");
2917 tlb->PID = env->spr[SPR_40x_PID]; /* PID */
2918 tlb->attr = T1 & 0xFF;
2919 #if defined (DEBUG_SOFTWARE_TLB)
2920 if (loglevel != 0) {
2921 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
2922 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
2923 (int)T0, tlb->RPN, tlb->EPN, tlb->size,
2924 tlb->prot & PAGE_READ ? 'r' : '-',
2925 tlb->prot & PAGE_WRITE ? 'w' : '-',
2926 tlb->prot & PAGE_EXEC ? 'x' : '-',
2927 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
2930 /* Invalidate new TLB (if valid) */
2931 if (tlb->prot & PAGE_VALID) {
2932 end = tlb->EPN + tlb->size;
2933 #if defined (DEBUG_SOFTWARE_TLB)
2934 if (loglevel != 0) {
2935 fprintf(logfile, "%s: invalidate TLB %d start " ADDRX
2936 " end " ADDRX "\n", __func__, (int)T0, tlb->EPN, end);
2939 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2940 tlb_flush_page(env, page);
2944 void do_4xx_tlbwe_lo (void)
2948 #if defined (DEBUG_SOFTWARE_TLB)
2949 if (loglevel != 0) {
2950 fprintf(logfile, "%s T0 " TDX " T1 " TDX "\n", __func__, T0, T1);
2954 tlb = &env->tlb[T0].tlbe;
2955 tlb->RPN = T1 & 0xFFFFFC00;
2956 tlb->prot = PAGE_READ;
2958 tlb->prot |= PAGE_EXEC;
2960 tlb->prot |= PAGE_WRITE;
2961 #if defined (DEBUG_SOFTWARE_TLB)
2962 if (loglevel != 0) {
2963 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
2964 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
2965 (int)T0, tlb->RPN, tlb->EPN, tlb->size,
2966 tlb->prot & PAGE_READ ? 'r' : '-',
2967 tlb->prot & PAGE_WRITE ? 'w' : '-',
2968 tlb->prot & PAGE_EXEC ? 'x' : '-',
2969 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
2974 /* PowerPC 440 TLB management */
2975 void do_440_tlbwe (int word)
2978 target_ulong EPN, RPN, size;
2981 #if defined (DEBUG_SOFTWARE_TLB)
2982 if (loglevel != 0) {
2983 fprintf(logfile, "%s word %d T0 " TDX " T1 " TDX "\n",
2984 __func__, word, T0, T1);
2989 tlb = &env->tlb[T0].tlbe;
2992 /* Just here to please gcc */
2994 EPN = T1 & 0xFFFFFC00;
2995 if ((tlb->prot & PAGE_VALID) && EPN != tlb->EPN)
2998 size = booke_tlb_to_page_size((T1 >> 4) & 0xF);
2999 if ((tlb->prot & PAGE_VALID) && tlb->size < size)
3003 tlb->attr |= (T1 >> 8) & 1;
3005 tlb->prot |= PAGE_VALID;
3007 if (tlb->prot & PAGE_VALID) {
3008 tlb->prot &= ~PAGE_VALID;
3012 tlb->PID = env->spr[SPR_440_MMUCR] & 0x000000FF;
3017 RPN = T1 & 0xFFFFFC0F;
3018 if ((tlb->prot & PAGE_VALID) && tlb->RPN != RPN)
3023 tlb->attr = (tlb->attr & 0x1) | (T1 & 0x0000FF00);
3024 tlb->prot = tlb->prot & PAGE_VALID;
3026 tlb->prot |= PAGE_READ << 4;
3028 tlb->prot |= PAGE_WRITE << 4;
3030 tlb->prot |= PAGE_EXEC << 4;
3032 tlb->prot |= PAGE_READ;
3034 tlb->prot |= PAGE_WRITE;
3036 tlb->prot |= PAGE_EXEC;
3041 void do_440_tlbre (int word)
3047 tlb = &env->tlb[T0].tlbe;
3050 /* Just here to please gcc */
3053 size = booke_page_size_to_tlb(tlb->size);
3054 if (size < 0 || size > 0xF)
3057 if (tlb->attr & 0x1)
3059 if (tlb->prot & PAGE_VALID)
3061 env->spr[SPR_440_MMUCR] &= ~0x000000FF;
3062 env->spr[SPR_440_MMUCR] |= tlb->PID;
3068 T0 = tlb->attr & ~0x1;
3069 if (tlb->prot & (PAGE_READ << 4))
3071 if (tlb->prot & (PAGE_WRITE << 4))
3073 if (tlb->prot & (PAGE_EXEC << 4))
3075 if (tlb->prot & PAGE_READ)
3077 if (tlb->prot & PAGE_WRITE)
3079 if (tlb->prot & PAGE_EXEC)
3084 #endif /* !CONFIG_USER_ONLY */