2 * PowerPC emulation micro-operations helpers for qemu.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 /* Multiple word / string load and store */
22 static inline target_ulong glue(ld32r, MEMSUFFIX) (target_ulong EA)
24 uint32_t tmp = glue(ldl, MEMSUFFIX)(EA);
25 return ((tmp & 0xFF000000UL) >> 24) | ((tmp & 0x00FF0000UL) >> 8) |
26 ((tmp & 0x0000FF00UL) << 8) | ((tmp & 0x000000FFUL) << 24);
29 static inline void glue(st32r, MEMSUFFIX) (target_ulong EA, target_ulong data)
32 ((data & 0xFF000000UL) >> 24) | ((data & 0x00FF0000UL) >> 8) |
33 ((data & 0x0000FF00UL) << 8) | ((data & 0x000000FFUL) << 24);
34 glue(stl, MEMSUFFIX)(EA, tmp);
37 void glue(do_lmw, MEMSUFFIX) (int dst)
39 for (; dst < 32; dst++, T0 += 4) {
40 env->gpr[dst] = glue(ldl, MEMSUFFIX)((uint32_t)T0);
44 #if defined(TARGET_PPC64)
45 void glue(do_lmw_64, MEMSUFFIX) (int dst)
47 for (; dst < 32; dst++, T0 += 4) {
48 env->gpr[dst] = glue(ldl, MEMSUFFIX)((uint64_t)T0);
53 void glue(do_stmw, MEMSUFFIX) (int src)
55 for (; src < 32; src++, T0 += 4) {
56 glue(stl, MEMSUFFIX)((uint32_t)T0, env->gpr[src]);
60 #if defined(TARGET_PPC64)
61 void glue(do_stmw_64, MEMSUFFIX) (int src)
63 for (; src < 32; src++, T0 += 4) {
64 glue(stl, MEMSUFFIX)((uint64_t)T0, env->gpr[src]);
69 void glue(do_lmw_le, MEMSUFFIX) (int dst)
71 for (; dst < 32; dst++, T0 += 4) {
72 env->gpr[dst] = glue(ld32r, MEMSUFFIX)((uint32_t)T0);
76 #if defined(TARGET_PPC64)
77 void glue(do_lmw_le_64, MEMSUFFIX) (int dst)
79 for (; dst < 32; dst++, T0 += 4) {
80 env->gpr[dst] = glue(ld32r, MEMSUFFIX)((uint64_t)T0);
85 void glue(do_stmw_le, MEMSUFFIX) (int src)
87 for (; src < 32; src++, T0 += 4) {
88 glue(st32r, MEMSUFFIX)((uint32_t)T0, env->gpr[src]);
92 #if defined(TARGET_PPC64)
93 void glue(do_stmw_le_64, MEMSUFFIX) (int src)
95 for (; src < 32; src++, T0 += 4) {
96 glue(st32r, MEMSUFFIX)((uint64_t)T0, env->gpr[src]);
101 void glue(do_lsw, MEMSUFFIX) (int dst)
106 for (; T1 > 3; T1 -= 4, T0 += 4) {
107 env->gpr[dst++] = glue(ldl, MEMSUFFIX)((uint32_t)T0);
108 if (unlikely(dst == 32))
111 if (unlikely(T1 != 0)) {
113 for (sh = 24; T1 > 0; T1--, T0++, sh -= 8) {
114 tmp |= glue(ldub, MEMSUFFIX)((uint32_t)T0) << sh;
120 #if defined(TARGET_PPC64)
121 void glue(do_lsw_64, MEMSUFFIX) (int dst)
126 for (; T1 > 3; T1 -= 4, T0 += 4) {
127 env->gpr[dst++] = glue(ldl, MEMSUFFIX)((uint64_t)T0);
128 if (unlikely(dst == 32))
131 if (unlikely(T1 != 0)) {
133 for (sh = 24; T1 > 0; T1--, T0++, sh -= 8) {
134 tmp |= glue(ldub, MEMSUFFIX)((uint64_t)T0) << sh;
141 void glue(do_stsw, MEMSUFFIX) (int src)
145 for (; T1 > 3; T1 -= 4, T0 += 4) {
146 glue(stl, MEMSUFFIX)((uint32_t)T0, env->gpr[src++]);
147 if (unlikely(src == 32))
150 if (unlikely(T1 != 0)) {
151 for (sh = 24; T1 > 0; T1--, T0++, sh -= 8)
152 glue(stb, MEMSUFFIX)((uint32_t)T0, (env->gpr[src] >> sh) & 0xFF);
156 #if defined(TARGET_PPC64)
157 void glue(do_stsw_64, MEMSUFFIX) (int src)
161 for (; T1 > 3; T1 -= 4, T0 += 4) {
162 glue(stl, MEMSUFFIX)((uint64_t)T0, env->gpr[src++]);
163 if (unlikely(src == 32))
166 if (unlikely(T1 != 0)) {
167 for (sh = 24; T1 > 0; T1--, T0++, sh -= 8)
168 glue(stb, MEMSUFFIX)((uint64_t)T0, (env->gpr[src] >> sh) & 0xFF);
173 void glue(do_lsw_le, MEMSUFFIX) (int dst)
178 for (; T1 > 3; T1 -= 4, T0 += 4) {
179 env->gpr[dst++] = glue(ld32r, MEMSUFFIX)((uint32_t)T0);
180 if (unlikely(dst == 32))
183 if (unlikely(T1 != 0)) {
185 for (sh = 0; T1 > 0; T1--, T0++, sh += 8) {
186 tmp |= glue(ldub, MEMSUFFIX)((uint32_t)T0) << sh;
192 #if defined(TARGET_PPC64)
193 void glue(do_lsw_le_64, MEMSUFFIX) (int dst)
198 for (; T1 > 3; T1 -= 4, T0 += 4) {
199 env->gpr[dst++] = glue(ld32r, MEMSUFFIX)((uint64_t)T0);
200 if (unlikely(dst == 32))
203 if (unlikely(T1 != 0)) {
205 for (sh = 0; T1 > 0; T1--, T0++, sh += 8) {
206 tmp |= glue(ldub, MEMSUFFIX)((uint64_t)T0) << sh;
213 void glue(do_stsw_le, MEMSUFFIX) (int src)
217 for (; T1 > 3; T1 -= 4, T0 += 4) {
218 glue(st32r, MEMSUFFIX)((uint32_t)T0, env->gpr[src++]);
219 if (unlikely(src == 32))
222 if (unlikely(T1 != 0)) {
223 for (sh = 0; T1 > 0; T1--, T0++, sh += 8)
224 glue(stb, MEMSUFFIX)((uint32_t)T0, (env->gpr[src] >> sh) & 0xFF);
228 #if defined(TARGET_PPC64)
229 void glue(do_stsw_le_64, MEMSUFFIX) (int src)
233 for (; T1 > 3; T1 -= 4, T0 += 4) {
234 glue(st32r, MEMSUFFIX)((uint64_t)T0, env->gpr[src++]);
235 if (unlikely(src == 32))
238 if (unlikely(T1 != 0)) {
239 for (sh = 0; T1 > 0; T1--, T0++, sh += 8)
240 glue(stb, MEMSUFFIX)((uint64_t)T0, (env->gpr[src] >> sh) & 0xFF);
245 /* Instruction cache invalidation helper */
246 void glue(do_icbi, MEMSUFFIX) (void)
249 /* Invalidate one cache line :
250 * PowerPC specification says this is to be treated like a load
251 * (not a fetch) by the MMU. To be sure it will be so,
252 * do the load "by hand".
254 tmp = glue(ldl, MEMSUFFIX)((uint32_t)T0);
255 T0 &= ~(env->icache_line_size - 1);
256 tb_invalidate_page_range((uint32_t)T0,
257 (uint32_t)(T0 + env->icache_line_size));
260 #if defined(TARGET_PPC64)
261 void glue(do_icbi_64, MEMSUFFIX) (void)
264 /* Invalidate one cache line :
265 * PowerPC specification says this is to be treated like a load
266 * (not a fetch) by the MMU. To be sure it will be so,
267 * do the load "by hand".
269 tmp = glue(ldq, MEMSUFFIX)((uint64_t)T0);
270 T0 &= ~(env->icache_line_size - 1);
271 tb_invalidate_page_range((uint64_t)T0,
272 (uint64_t)(T0 + env->icache_line_size));
276 void glue(do_dcbz, MEMSUFFIX) (void)
278 int dcache_line_size = env->dcache_line_size;
280 /* XXX: should be 970 specific (?) */
281 if (((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1)
282 dcache_line_size = 32;
283 glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x00), 0);
284 glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x04), 0);
285 glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x08), 0);
286 glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x0C), 0);
287 glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x10), 0);
288 glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x14), 0);
289 glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x18), 0);
290 glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x1C), 0);
291 if (dcache_line_size >= 64) {
292 glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x20UL), 0);
293 glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x24UL), 0);
294 glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x28UL), 0);
295 glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x2CUL), 0);
296 glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x30UL), 0);
297 glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x34UL), 0);
298 glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x38UL), 0);
299 glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x3CUL), 0);
300 if (dcache_line_size >= 128) {
301 glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x40UL), 0);
302 glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x44UL), 0);
303 glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x48UL), 0);
304 glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x4CUL), 0);
305 glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x50UL), 0);
306 glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x54UL), 0);
307 glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x58UL), 0);
308 glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x5CUL), 0);
309 glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x60UL), 0);
310 glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x64UL), 0);
311 glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x68UL), 0);
312 glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x6CUL), 0);
313 glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x70UL), 0);
314 glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x74UL), 0);
315 glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x78UL), 0);
316 glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x7CUL), 0);
321 #if defined(TARGET_PPC64)
322 void glue(do_dcbz_64, MEMSUFFIX) (void)
324 int dcache_line_size = env->dcache_line_size;
326 /* XXX: should be 970 specific (?) */
327 if (((env->spr[SPR_970_HID5] >> 6) & 0x3) == 0x2)
328 dcache_line_size = 32;
329 glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x00), 0);
330 glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x04), 0);
331 glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x08), 0);
332 glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x0C), 0);
333 glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x10), 0);
334 glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x14), 0);
335 glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x18), 0);
336 glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x1C), 0);
337 if (dcache_line_size >= 64) {
338 glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x20UL), 0);
339 glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x24UL), 0);
340 glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x28UL), 0);
341 glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x2CUL), 0);
342 glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x30UL), 0);
343 glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x34UL), 0);
344 glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x38UL), 0);
345 glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x3CUL), 0);
346 if (dcache_line_size >= 128) {
347 glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x40UL), 0);
348 glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x44UL), 0);
349 glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x48UL), 0);
350 glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x4CUL), 0);
351 glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x50UL), 0);
352 glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x54UL), 0);
353 glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x58UL), 0);
354 glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x5CUL), 0);
355 glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x60UL), 0);
356 glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x64UL), 0);
357 glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x68UL), 0);
358 glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x6CUL), 0);
359 glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x70UL), 0);
360 glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x74UL), 0);
361 glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x78UL), 0);
362 glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x7CUL), 0);
368 /* PowerPC 601 specific instructions (POWER bridge) */
370 void glue(do_POWER_lscbx, MEMSUFFIX) (int dest, int ra, int rb)
376 for (i = 0; i < T1; i++) {
377 c = glue(ldub, MEMSUFFIX)((uint32_t)T0++);
378 /* ra (if not 0) and rb are never modified */
379 if (likely(reg != rb && (ra == 0 || reg != ra))) {
380 env->gpr[reg] = (env->gpr[reg] & ~(0xFF << d)) | (c << d);
382 if (unlikely(c == T2))
384 if (likely(d != 0)) {
395 /* XXX: TAGs are not managed */
396 void glue(do_POWER2_lfq, MEMSUFFIX) (void)
398 FT0 = glue(ldfq, MEMSUFFIX)((uint32_t)T0);
399 FT1 = glue(ldfq, MEMSUFFIX)((uint32_t)(T0 + 4));
402 static inline double glue(ldfqr, MEMSUFFIX) (target_ulong EA)
409 u.d = glue(ldfq, MEMSUFFIX)(EA);
410 u.u = ((u.u & 0xFF00000000000000ULL) >> 56) |
411 ((u.u & 0x00FF000000000000ULL) >> 40) |
412 ((u.u & 0x0000FF0000000000ULL) >> 24) |
413 ((u.u & 0x000000FF00000000ULL) >> 8) |
414 ((u.u & 0x00000000FF000000ULL) << 8) |
415 ((u.u & 0x0000000000FF0000ULL) << 24) |
416 ((u.u & 0x000000000000FF00ULL) << 40) |
417 ((u.u & 0x00000000000000FFULL) << 56);
422 void glue(do_POWER2_lfq_le, MEMSUFFIX) (void)
424 FT0 = glue(ldfqr, MEMSUFFIX)((uint32_t)(T0 + 4));
425 FT1 = glue(ldfqr, MEMSUFFIX)((uint32_t)T0);
428 void glue(do_POWER2_stfq, MEMSUFFIX) (void)
430 glue(stfq, MEMSUFFIX)((uint32_t)T0, FT0);
431 glue(stfq, MEMSUFFIX)((uint32_t)(T0 + 4), FT1);
434 static inline void glue(stfqr, MEMSUFFIX) (target_ulong EA, double d)
442 u.u = ((u.u & 0xFF00000000000000ULL) >> 56) |
443 ((u.u & 0x00FF000000000000ULL) >> 40) |
444 ((u.u & 0x0000FF0000000000ULL) >> 24) |
445 ((u.u & 0x000000FF00000000ULL) >> 8) |
446 ((u.u & 0x00000000FF000000ULL) << 8) |
447 ((u.u & 0x0000000000FF0000ULL) << 24) |
448 ((u.u & 0x000000000000FF00ULL) << 40) |
449 ((u.u & 0x00000000000000FFULL) << 56);
450 glue(stfq, MEMSUFFIX)(EA, u.d);
453 void glue(do_POWER2_stfq_le, MEMSUFFIX) (void)
455 glue(stfqr, MEMSUFFIX)((uint32_t)(T0 + 4), FT0);
456 glue(stfqr, MEMSUFFIX)((uint32_t)T0, FT1);