2 * PowerPC emulation for qemu: main translation routines.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 #include "qemu-common.h"
33 #define CPU_SINGLE_STEP 0x1
34 #define CPU_BRANCH_STEP 0x2
35 #define GDBSTUB_SINGLE_STEP 0x4
37 /* Include definitions for instructions classes and implementations flags */
38 //#define DO_SINGLE_STEP
39 //#define PPC_DEBUG_DISAS
40 //#define DEBUG_MEMORY_ACCESSES
41 //#define DO_PPC_STATISTICS
42 //#define OPTIMIZE_FPRF_UPDATE
44 /*****************************************************************************/
45 /* Code translation helpers */
47 static TCGv cpu_env, cpu_T[3];
49 #include "gen-icount.h"
51 void ppc_translate_init(void)
53 static int done_init = 0;
56 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
57 #if TARGET_LONG_BITS > HOST_LONG_BITS
58 cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
59 TCG_AREG0, offsetof(CPUState, t0), "T0");
60 cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
61 TCG_AREG0, offsetof(CPUState, t1), "T1");
62 cpu_T[2] = tcg_global_mem_new(TCG_TYPE_TL,
63 TCG_AREG0, offsetof(CPUState, t2), "T2");
65 cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
66 cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
67 cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2");
70 /* register helpers */
72 #define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
78 #if defined(OPTIMIZE_FPRF_UPDATE)
79 static uint16_t *gen_fprf_buf[OPC_BUF_SIZE];
80 static uint16_t **gen_fprf_ptr;
83 #define GEN8(func, NAME) \
84 static GenOpFunc *NAME ## _table [8] = { \
85 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
86 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
88 static always_inline void func (int n) \
90 NAME ## _table[n](); \
93 #define GEN16(func, NAME) \
94 static GenOpFunc *NAME ## _table [16] = { \
95 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
96 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
97 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
98 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
100 static always_inline void func (int n) \
102 NAME ## _table[n](); \
105 #define GEN32(func, NAME) \
106 static GenOpFunc *NAME ## _table [32] = { \
107 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
108 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
109 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
110 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
111 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
112 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
113 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
114 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
116 static always_inline void func (int n) \
118 NAME ## _table[n](); \
121 /* Condition register moves */
122 GEN8(gen_op_load_crf_T0, gen_op_load_crf_T0_crf);
123 GEN8(gen_op_load_crf_T1, gen_op_load_crf_T1_crf);
124 GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf);
126 GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf);
129 /* General purpose registers moves */
130 GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);
131 GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);
132 GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);
134 GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
135 GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
137 GEN32(gen_op_store_T2_gpr, gen_op_store_T2_gpr_gpr);
140 /* floating point registers moves */
141 GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr);
142 GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr);
143 GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fpr);
144 GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fpr);
145 GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fpr);
147 GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fpr);
150 /* internal defines */
151 typedef struct DisasContext {
152 struct TranslationBlock *tb;
156 /* Routine used to access memory */
158 /* Translation flags */
159 #if !defined(CONFIG_USER_ONLY)
162 #if defined(TARGET_PPC64)
168 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
169 int singlestep_enabled;
170 int dcache_line_size;
173 struct opc_handler_t {
176 /* instruction type */
179 void (*handler)(DisasContext *ctx);
180 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
181 const unsigned char *oname;
183 #if defined(DO_PPC_STATISTICS)
188 static always_inline void gen_set_Rc0 (DisasContext *ctx)
190 #if defined(TARGET_PPC64)
199 static always_inline void gen_reset_fpstatus (void)
201 #ifdef CONFIG_SOFTFLOAT
202 gen_op_reset_fpstatus();
206 static always_inline void gen_compute_fprf (int set_fprf, int set_rc)
209 /* This case might be optimized later */
210 #if defined(OPTIMIZE_FPRF_UPDATE)
211 *gen_fprf_ptr++ = gen_opc_ptr;
213 gen_op_compute_fprf(1);
214 if (unlikely(set_rc))
215 gen_op_store_T0_crf(1);
216 gen_op_float_check_status();
217 } else if (unlikely(set_rc)) {
218 /* We always need to compute fpcc */
219 gen_op_compute_fprf(0);
220 gen_op_store_T0_crf(1);
222 gen_op_float_check_status();
226 static always_inline void gen_optimize_fprf (void)
228 #if defined(OPTIMIZE_FPRF_UPDATE)
231 for (ptr = gen_fprf_buf; ptr != (gen_fprf_ptr - 1); ptr++)
232 *ptr = INDEX_op_nop1;
233 gen_fprf_ptr = gen_fprf_buf;
237 static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
239 #if defined(TARGET_PPC64)
241 gen_op_update_nip_64(nip >> 32, nip);
244 gen_op_update_nip(nip);
247 #define GEN_EXCP(ctx, excp, error) \
249 if ((ctx)->exception == POWERPC_EXCP_NONE) { \
250 gen_update_nip(ctx, (ctx)->nip); \
252 gen_op_raise_exception_err((excp), (error)); \
253 ctx->exception = (excp); \
256 #define GEN_EXCP_INVAL(ctx) \
257 GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
258 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL)
260 #define GEN_EXCP_PRIVOPC(ctx) \
261 GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
262 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC)
264 #define GEN_EXCP_PRIVREG(ctx) \
265 GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
266 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG)
268 #define GEN_EXCP_NO_FP(ctx) \
269 GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0)
271 #define GEN_EXCP_NO_AP(ctx) \
272 GEN_EXCP(ctx, POWERPC_EXCP_APU, 0)
274 #define GEN_EXCP_NO_VR(ctx) \
275 GEN_EXCP(ctx, POWERPC_EXCP_VPU, 0)
277 /* Stop translation */
278 static always_inline void GEN_STOP (DisasContext *ctx)
280 gen_update_nip(ctx, ctx->nip);
281 ctx->exception = POWERPC_EXCP_STOP;
284 /* No need to update nip here, as execution flow will change */
285 static always_inline void GEN_SYNC (DisasContext *ctx)
287 ctx->exception = POWERPC_EXCP_SYNC;
290 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
291 static void gen_##name (DisasContext *ctx); \
292 GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
293 static void gen_##name (DisasContext *ctx)
295 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
296 static void gen_##name (DisasContext *ctx); \
297 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
298 static void gen_##name (DisasContext *ctx)
300 typedef struct opcode_t {
301 unsigned char opc1, opc2, opc3;
302 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
303 unsigned char pad[5];
305 unsigned char pad[1];
307 opc_handler_t handler;
308 const unsigned char *oname;
311 /*****************************************************************************/
312 /*** Instruction decoding ***/
313 #define EXTRACT_HELPER(name, shift, nb) \
314 static always_inline uint32_t name (uint32_t opcode) \
316 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
319 #define EXTRACT_SHELPER(name, shift, nb) \
320 static always_inline int32_t name (uint32_t opcode) \
322 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
326 EXTRACT_HELPER(opc1, 26, 6);
328 EXTRACT_HELPER(opc2, 1, 5);
330 EXTRACT_HELPER(opc3, 6, 5);
331 /* Update Cr0 flags */
332 EXTRACT_HELPER(Rc, 0, 1);
334 EXTRACT_HELPER(rD, 21, 5);
336 EXTRACT_HELPER(rS, 21, 5);
338 EXTRACT_HELPER(rA, 16, 5);
340 EXTRACT_HELPER(rB, 11, 5);
342 EXTRACT_HELPER(rC, 6, 5);
344 EXTRACT_HELPER(crfD, 23, 3);
345 EXTRACT_HELPER(crfS, 18, 3);
346 EXTRACT_HELPER(crbD, 21, 5);
347 EXTRACT_HELPER(crbA, 16, 5);
348 EXTRACT_HELPER(crbB, 11, 5);
350 EXTRACT_HELPER(_SPR, 11, 10);
351 static always_inline uint32_t SPR (uint32_t opcode)
353 uint32_t sprn = _SPR(opcode);
355 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
357 /*** Get constants ***/
358 EXTRACT_HELPER(IMM, 12, 8);
359 /* 16 bits signed immediate value */
360 EXTRACT_SHELPER(SIMM, 0, 16);
361 /* 16 bits unsigned immediate value */
362 EXTRACT_HELPER(UIMM, 0, 16);
364 EXTRACT_HELPER(NB, 11, 5);
366 EXTRACT_HELPER(SH, 11, 5);
368 EXTRACT_HELPER(MB, 6, 5);
370 EXTRACT_HELPER(ME, 1, 5);
372 EXTRACT_HELPER(TO, 21, 5);
374 EXTRACT_HELPER(CRM, 12, 8);
375 EXTRACT_HELPER(FM, 17, 8);
376 EXTRACT_HELPER(SR, 16, 4);
377 EXTRACT_HELPER(FPIMM, 12, 4);
379 /*** Jump target decoding ***/
381 EXTRACT_SHELPER(d, 0, 16);
382 /* Immediate address */
383 static always_inline target_ulong LI (uint32_t opcode)
385 return (opcode >> 0) & 0x03FFFFFC;
388 static always_inline uint32_t BD (uint32_t opcode)
390 return (opcode >> 0) & 0xFFFC;
393 EXTRACT_HELPER(BO, 21, 5);
394 EXTRACT_HELPER(BI, 16, 5);
395 /* Absolute/relative address */
396 EXTRACT_HELPER(AA, 1, 1);
398 EXTRACT_HELPER(LK, 0, 1);
400 /* Create a mask between <start> and <end> bits */
401 static always_inline target_ulong MASK (uint32_t start, uint32_t end)
405 #if defined(TARGET_PPC64)
406 if (likely(start == 0)) {
407 ret = UINT64_MAX << (63 - end);
408 } else if (likely(end == 63)) {
409 ret = UINT64_MAX >> start;
412 if (likely(start == 0)) {
413 ret = UINT32_MAX << (31 - end);
414 } else if (likely(end == 31)) {
415 ret = UINT32_MAX >> start;
419 ret = (((target_ulong)(-1ULL)) >> (start)) ^
420 (((target_ulong)(-1ULL) >> (end)) >> 1);
421 if (unlikely(start > end))
428 /*****************************************************************************/
429 /* PowerPC Instructions types definitions */
431 PPC_NONE = 0x0000000000000000ULL,
432 /* PowerPC base instructions set */
433 PPC_INSNS_BASE = 0x0000000000000001ULL,
434 /* integer operations instructions */
435 #define PPC_INTEGER PPC_INSNS_BASE
436 /* flow control instructions */
437 #define PPC_FLOW PPC_INSNS_BASE
438 /* virtual memory instructions */
439 #define PPC_MEM PPC_INSNS_BASE
440 /* ld/st with reservation instructions */
441 #define PPC_RES PPC_INSNS_BASE
442 /* spr/msr access instructions */
443 #define PPC_MISC PPC_INSNS_BASE
444 /* Deprecated instruction sets */
445 /* Original POWER instruction set */
446 PPC_POWER = 0x0000000000000002ULL,
447 /* POWER2 instruction set extension */
448 PPC_POWER2 = 0x0000000000000004ULL,
449 /* Power RTC support */
450 PPC_POWER_RTC = 0x0000000000000008ULL,
451 /* Power-to-PowerPC bridge (601) */
452 PPC_POWER_BR = 0x0000000000000010ULL,
453 /* 64 bits PowerPC instruction set */
454 PPC_64B = 0x0000000000000020ULL,
455 /* New 64 bits extensions (PowerPC 2.0x) */
456 PPC_64BX = 0x0000000000000040ULL,
457 /* 64 bits hypervisor extensions */
458 PPC_64H = 0x0000000000000080ULL,
459 /* New wait instruction (PowerPC 2.0x) */
460 PPC_WAIT = 0x0000000000000100ULL,
461 /* Time base mftb instruction */
462 PPC_MFTB = 0x0000000000000200ULL,
464 /* Fixed-point unit extensions */
465 /* PowerPC 602 specific */
466 PPC_602_SPEC = 0x0000000000000400ULL,
467 /* isel instruction */
468 PPC_ISEL = 0x0000000000000800ULL,
469 /* popcntb instruction */
470 PPC_POPCNTB = 0x0000000000001000ULL,
471 /* string load / store */
472 PPC_STRING = 0x0000000000002000ULL,
474 /* Floating-point unit extensions */
475 /* Optional floating point instructions */
476 PPC_FLOAT = 0x0000000000010000ULL,
477 /* New floating-point extensions (PowerPC 2.0x) */
478 PPC_FLOAT_EXT = 0x0000000000020000ULL,
479 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
480 PPC_FLOAT_FRES = 0x0000000000080000ULL,
481 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
482 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
483 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
484 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
486 /* Vector/SIMD extensions */
487 /* Altivec support */
488 PPC_ALTIVEC = 0x0000000001000000ULL,
489 /* PowerPC 2.03 SPE extension */
490 PPC_SPE = 0x0000000002000000ULL,
491 /* PowerPC 2.03 SPE floating-point extension */
492 PPC_SPEFPU = 0x0000000004000000ULL,
494 /* Optional memory control instructions */
495 PPC_MEM_TLBIA = 0x0000000010000000ULL,
496 PPC_MEM_TLBIE = 0x0000000020000000ULL,
497 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
498 /* sync instruction */
499 PPC_MEM_SYNC = 0x0000000080000000ULL,
500 /* eieio instruction */
501 PPC_MEM_EIEIO = 0x0000000100000000ULL,
503 /* Cache control instructions */
504 PPC_CACHE = 0x0000000200000000ULL,
505 /* icbi instruction */
506 PPC_CACHE_ICBI = 0x0000000400000000ULL,
507 /* dcbz instruction with fixed cache line size */
508 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
509 /* dcbz instruction with tunable cache line size */
510 PPC_CACHE_DCBZT = 0x0000001000000000ULL,
511 /* dcba instruction */
512 PPC_CACHE_DCBA = 0x0000002000000000ULL,
513 /* Freescale cache locking instructions */
514 PPC_CACHE_LOCK = 0x0000004000000000ULL,
516 /* MMU related extensions */
517 /* external control instructions */
518 PPC_EXTERN = 0x0000010000000000ULL,
519 /* segment register access instructions */
520 PPC_SEGMENT = 0x0000020000000000ULL,
521 /* PowerPC 6xx TLB management instructions */
522 PPC_6xx_TLB = 0x0000040000000000ULL,
523 /* PowerPC 74xx TLB management instructions */
524 PPC_74xx_TLB = 0x0000080000000000ULL,
525 /* PowerPC 40x TLB management instructions */
526 PPC_40x_TLB = 0x0000100000000000ULL,
527 /* segment register access instructions for PowerPC 64 "bridge" */
528 PPC_SEGMENT_64B = 0x0000200000000000ULL,
530 PPC_SLBI = 0x0000400000000000ULL,
532 /* Embedded PowerPC dedicated instructions */
533 PPC_WRTEE = 0x0001000000000000ULL,
534 /* PowerPC 40x exception model */
535 PPC_40x_EXCP = 0x0002000000000000ULL,
536 /* PowerPC 405 Mac instructions */
537 PPC_405_MAC = 0x0004000000000000ULL,
538 /* PowerPC 440 specific instructions */
539 PPC_440_SPEC = 0x0008000000000000ULL,
540 /* BookE (embedded) PowerPC specification */
541 PPC_BOOKE = 0x0010000000000000ULL,
542 /* mfapidi instruction */
543 PPC_MFAPIDI = 0x0020000000000000ULL,
544 /* tlbiva instruction */
545 PPC_TLBIVA = 0x0040000000000000ULL,
546 /* tlbivax instruction */
547 PPC_TLBIVAX = 0x0080000000000000ULL,
548 /* PowerPC 4xx dedicated instructions */
549 PPC_4xx_COMMON = 0x0100000000000000ULL,
550 /* PowerPC 40x ibct instructions */
551 PPC_40x_ICBT = 0x0200000000000000ULL,
552 /* rfmci is not implemented in all BookE PowerPC */
553 PPC_RFMCI = 0x0400000000000000ULL,
554 /* rfdi instruction */
555 PPC_RFDI = 0x0800000000000000ULL,
557 PPC_DCR = 0x1000000000000000ULL,
558 /* DCR extended accesse */
559 PPC_DCRX = 0x2000000000000000ULL,
560 /* user-mode DCR access, implemented in PowerPC 460 */
561 PPC_DCRUX = 0x4000000000000000ULL,
564 /*****************************************************************************/
565 /* PowerPC instructions table */
566 #if HOST_LONG_BITS == 64
571 #if defined(__APPLE__)
572 #define OPCODES_SECTION \
573 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
575 #define OPCODES_SECTION \
576 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
579 #if defined(DO_PPC_STATISTICS)
580 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
581 OPCODES_SECTION opcode_t opc_##name = { \
589 .handler = &gen_##name, \
590 .oname = stringify(name), \
592 .oname = stringify(name), \
594 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
595 OPCODES_SECTION opcode_t opc_##name = { \
603 .handler = &gen_##name, \
609 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
610 OPCODES_SECTION opcode_t opc_##name = { \
618 .handler = &gen_##name, \
620 .oname = stringify(name), \
622 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
623 OPCODES_SECTION opcode_t opc_##name = { \
631 .handler = &gen_##name, \
637 #define GEN_OPCODE_MARK(name) \
638 OPCODES_SECTION opcode_t opc_##name = { \
644 .inval = 0x00000000, \
648 .oname = stringify(name), \
651 /* Start opcode list */
652 GEN_OPCODE_MARK(start);
654 /* Invalid instruction */
655 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
660 static opc_handler_t invalid_handler = {
663 .handler = gen_invalid,
666 /*** Integer arithmetic ***/
667 #define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval, type) \
668 GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
670 gen_op_load_gpr_T0(rA(ctx->opcode)); \
671 gen_op_load_gpr_T1(rB(ctx->opcode)); \
673 gen_op_store_T0_gpr(rD(ctx->opcode)); \
674 if (unlikely(Rc(ctx->opcode) != 0)) \
678 #define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval, type) \
679 GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
681 gen_op_load_gpr_T0(rA(ctx->opcode)); \
682 gen_op_load_gpr_T1(rB(ctx->opcode)); \
684 gen_op_store_T0_gpr(rD(ctx->opcode)); \
685 if (unlikely(Rc(ctx->opcode) != 0)) \
689 #define __GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
690 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
692 gen_op_load_gpr_T0(rA(ctx->opcode)); \
694 gen_op_store_T0_gpr(rD(ctx->opcode)); \
695 if (unlikely(Rc(ctx->opcode) != 0)) \
698 #define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3, type) \
699 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
701 gen_op_load_gpr_T0(rA(ctx->opcode)); \
703 gen_op_store_T0_gpr(rD(ctx->opcode)); \
704 if (unlikely(Rc(ctx->opcode) != 0)) \
708 /* Two operands arithmetic functions */
709 #define GEN_INT_ARITH2(name, opc1, opc2, opc3, type) \
710 __GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000, type) \
711 __GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
713 /* Two operands arithmetic functions with no overflow allowed */
714 #define GEN_INT_ARITHN(name, opc1, opc2, opc3, type) \
715 __GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400, type)
717 /* One operand arithmetic functions */
718 #define GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
719 __GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
720 __GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10, type)
722 #if defined(TARGET_PPC64)
723 #define __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, inval, type) \
724 GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
726 gen_op_load_gpr_T0(rA(ctx->opcode)); \
727 gen_op_load_gpr_T1(rB(ctx->opcode)); \
729 gen_op_##name##_64(); \
732 gen_op_store_T0_gpr(rD(ctx->opcode)); \
733 if (unlikely(Rc(ctx->opcode) != 0)) \
737 #define __GEN_INT_ARITH2_O_64(name, opc1, opc2, opc3, inval, type) \
738 GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
740 gen_op_load_gpr_T0(rA(ctx->opcode)); \
741 gen_op_load_gpr_T1(rB(ctx->opcode)); \
743 gen_op_##name##_64(); \
746 gen_op_store_T0_gpr(rD(ctx->opcode)); \
747 if (unlikely(Rc(ctx->opcode) != 0)) \
751 #define __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
752 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
754 gen_op_load_gpr_T0(rA(ctx->opcode)); \
756 gen_op_##name##_64(); \
759 gen_op_store_T0_gpr(rD(ctx->opcode)); \
760 if (unlikely(Rc(ctx->opcode) != 0)) \
763 #define __GEN_INT_ARITH1_O_64(name, opc1, opc2, opc3, type) \
764 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
766 gen_op_load_gpr_T0(rA(ctx->opcode)); \
768 gen_op_##name##_64(); \
771 gen_op_store_T0_gpr(rD(ctx->opcode)); \
772 if (unlikely(Rc(ctx->opcode) != 0)) \
776 /* Two operands arithmetic functions */
777 #define GEN_INT_ARITH2_64(name, opc1, opc2, opc3, type) \
778 __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000000, type) \
779 __GEN_INT_ARITH2_O_64(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
781 /* Two operands arithmetic functions with no overflow allowed */
782 #define GEN_INT_ARITHN_64(name, opc1, opc2, opc3, type) \
783 __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000400, type)
785 /* One operand arithmetic functions */
786 #define GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
787 __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
788 __GEN_INT_ARITH1_O_64(name##o, opc1, opc2, opc3 | 0x10, type)
790 #define GEN_INT_ARITH2_64 GEN_INT_ARITH2
791 #define GEN_INT_ARITHN_64 GEN_INT_ARITHN
792 #define GEN_INT_ARITH1_64 GEN_INT_ARITH1
795 /* add add. addo addo. */
796 static always_inline void gen_op_addo (void)
802 #if defined(TARGET_PPC64)
803 #define gen_op_add_64 gen_op_add
804 static always_inline void gen_op_addo_64 (void)
808 gen_op_check_addo_64();
811 GEN_INT_ARITH2_64 (add, 0x1F, 0x0A, 0x08, PPC_INTEGER);
812 /* addc addc. addco addco. */
813 static always_inline void gen_op_addc (void)
819 static always_inline void gen_op_addco (void)
826 #if defined(TARGET_PPC64)
827 static always_inline void gen_op_addc_64 (void)
831 gen_op_check_addc_64();
833 static always_inline void gen_op_addco_64 (void)
837 gen_op_check_addc_64();
838 gen_op_check_addo_64();
841 GEN_INT_ARITH2_64 (addc, 0x1F, 0x0A, 0x00, PPC_INTEGER);
842 /* adde adde. addeo addeo. */
843 static always_inline void gen_op_addeo (void)
849 #if defined(TARGET_PPC64)
850 static always_inline void gen_op_addeo_64 (void)
854 gen_op_check_addo_64();
857 GEN_INT_ARITH2_64 (adde, 0x1F, 0x0A, 0x04, PPC_INTEGER);
858 /* addme addme. addmeo addmeo. */
859 static always_inline void gen_op_addme (void)
864 #if defined(TARGET_PPC64)
865 static always_inline void gen_op_addme_64 (void)
871 GEN_INT_ARITH1_64 (addme, 0x1F, 0x0A, 0x07, PPC_INTEGER);
872 /* addze addze. addzeo addzeo. */
873 static always_inline void gen_op_addze (void)
879 static always_inline void gen_op_addzeo (void)
886 #if defined(TARGET_PPC64)
887 static always_inline void gen_op_addze_64 (void)
891 gen_op_check_addc_64();
893 static always_inline void gen_op_addzeo_64 (void)
897 gen_op_check_addc_64();
898 gen_op_check_addo_64();
901 GEN_INT_ARITH1_64 (addze, 0x1F, 0x0A, 0x06, PPC_INTEGER);
902 /* divw divw. divwo divwo. */
903 GEN_INT_ARITH2 (divw, 0x1F, 0x0B, 0x0F, PPC_INTEGER);
904 /* divwu divwu. divwuo divwuo. */
905 GEN_INT_ARITH2 (divwu, 0x1F, 0x0B, 0x0E, PPC_INTEGER);
907 GEN_INT_ARITHN (mulhw, 0x1F, 0x0B, 0x02, PPC_INTEGER);
909 GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00, PPC_INTEGER);
910 /* mullw mullw. mullwo mullwo. */
911 GEN_INT_ARITH2 (mullw, 0x1F, 0x0B, 0x07, PPC_INTEGER);
912 /* neg neg. nego nego. */
913 GEN_INT_ARITH1_64 (neg, 0x1F, 0x08, 0x03, PPC_INTEGER);
914 /* subf subf. subfo subfo. */
915 static always_inline void gen_op_subfo (void)
917 gen_op_moven_T2_T0();
921 #if defined(TARGET_PPC64)
922 #define gen_op_subf_64 gen_op_subf
923 static always_inline void gen_op_subfo_64 (void)
925 gen_op_moven_T2_T0();
927 gen_op_check_addo_64();
930 GEN_INT_ARITH2_64 (subf, 0x1F, 0x08, 0x01, PPC_INTEGER);
931 /* subfc subfc. subfco subfco. */
932 static always_inline void gen_op_subfc (void)
935 gen_op_check_subfc();
937 static always_inline void gen_op_subfco (void)
939 gen_op_moven_T2_T0();
941 gen_op_check_subfc();
944 #if defined(TARGET_PPC64)
945 static always_inline void gen_op_subfc_64 (void)
948 gen_op_check_subfc_64();
950 static always_inline void gen_op_subfco_64 (void)
952 gen_op_moven_T2_T0();
954 gen_op_check_subfc_64();
955 gen_op_check_addo_64();
958 GEN_INT_ARITH2_64 (subfc, 0x1F, 0x08, 0x00, PPC_INTEGER);
959 /* subfe subfe. subfeo subfeo. */
960 static always_inline void gen_op_subfeo (void)
962 gen_op_moven_T2_T0();
966 #if defined(TARGET_PPC64)
967 #define gen_op_subfe_64 gen_op_subfe
968 static always_inline void gen_op_subfeo_64 (void)
970 gen_op_moven_T2_T0();
972 gen_op_check_addo_64();
975 GEN_INT_ARITH2_64 (subfe, 0x1F, 0x08, 0x04, PPC_INTEGER);
976 /* subfme subfme. subfmeo subfmeo. */
977 GEN_INT_ARITH1_64 (subfme, 0x1F, 0x08, 0x07, PPC_INTEGER);
978 /* subfze subfze. subfzeo subfzeo. */
979 GEN_INT_ARITH1_64 (subfze, 0x1F, 0x08, 0x06, PPC_INTEGER);
981 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
983 target_long simm = SIMM(ctx->opcode);
985 if (rA(ctx->opcode) == 0) {
987 tcg_gen_movi_tl(cpu_T[0], simm);
989 gen_op_load_gpr_T0(rA(ctx->opcode));
990 if (likely(simm != 0))
993 gen_op_store_T0_gpr(rD(ctx->opcode));
996 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
998 target_long simm = SIMM(ctx->opcode);
1000 gen_op_load_gpr_T0(rA(ctx->opcode));
1001 if (likely(simm != 0)) {
1002 gen_op_move_T2_T0();
1004 #if defined(TARGET_PPC64)
1006 gen_op_check_addc_64();
1009 gen_op_check_addc();
1011 gen_op_clear_xer_ca();
1013 gen_op_store_T0_gpr(rD(ctx->opcode));
1016 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1018 target_long simm = SIMM(ctx->opcode);
1020 gen_op_load_gpr_T0(rA(ctx->opcode));
1021 if (likely(simm != 0)) {
1022 gen_op_move_T2_T0();
1024 #if defined(TARGET_PPC64)
1026 gen_op_check_addc_64();
1029 gen_op_check_addc();
1031 gen_op_clear_xer_ca();
1033 gen_op_store_T0_gpr(rD(ctx->opcode));
1037 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1039 target_long simm = SIMM(ctx->opcode);
1041 if (rA(ctx->opcode) == 0) {
1043 tcg_gen_movi_tl(cpu_T[0], simm << 16);
1045 gen_op_load_gpr_T0(rA(ctx->opcode));
1046 if (likely(simm != 0))
1047 gen_op_addi(simm << 16);
1049 gen_op_store_T0_gpr(rD(ctx->opcode));
1052 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1054 gen_op_load_gpr_T0(rA(ctx->opcode));
1055 gen_op_mulli(SIMM(ctx->opcode));
1056 gen_op_store_T0_gpr(rD(ctx->opcode));
1059 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1061 gen_op_load_gpr_T0(rA(ctx->opcode));
1062 #if defined(TARGET_PPC64)
1064 gen_op_subfic_64(SIMM(ctx->opcode));
1067 gen_op_subfic(SIMM(ctx->opcode));
1068 gen_op_store_T0_gpr(rD(ctx->opcode));
1071 #if defined(TARGET_PPC64)
1073 GEN_INT_ARITHN (mulhd, 0x1F, 0x09, 0x02, PPC_64B);
1074 /* mulhdu mulhdu. */
1075 GEN_INT_ARITHN (mulhdu, 0x1F, 0x09, 0x00, PPC_64B);
1076 /* mulld mulld. mulldo mulldo. */
1077 GEN_INT_ARITH2 (mulld, 0x1F, 0x09, 0x07, PPC_64B);
1078 /* divd divd. divdo divdo. */
1079 GEN_INT_ARITH2 (divd, 0x1F, 0x09, 0x0F, PPC_64B);
1080 /* divdu divdu. divduo divduo. */
1081 GEN_INT_ARITH2 (divdu, 0x1F, 0x09, 0x0E, PPC_64B);
1084 /*** Integer comparison ***/
1085 #if defined(TARGET_PPC64)
1086 #define GEN_CMP(name, opc, type) \
1087 GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \
1089 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1090 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1091 if (ctx->sf_mode && (ctx->opcode & 0x00200000)) \
1092 gen_op_##name##_64(); \
1095 gen_op_store_T0_crf(crfD(ctx->opcode)); \
1098 #define GEN_CMP(name, opc, type) \
1099 GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \
1101 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1102 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1104 gen_op_store_T0_crf(crfD(ctx->opcode)); \
1109 GEN_CMP(cmp, 0x00, PPC_INTEGER);
1111 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
1113 gen_op_load_gpr_T0(rA(ctx->opcode));
1114 #if defined(TARGET_PPC64)
1115 if (ctx->sf_mode && (ctx->opcode & 0x00200000))
1116 gen_op_cmpi_64(SIMM(ctx->opcode));
1119 gen_op_cmpi(SIMM(ctx->opcode));
1120 gen_op_store_T0_crf(crfD(ctx->opcode));
1123 GEN_CMP(cmpl, 0x01, PPC_INTEGER);
1125 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
1127 gen_op_load_gpr_T0(rA(ctx->opcode));
1128 #if defined(TARGET_PPC64)
1129 if (ctx->sf_mode && (ctx->opcode & 0x00200000))
1130 gen_op_cmpli_64(UIMM(ctx->opcode));
1133 gen_op_cmpli(UIMM(ctx->opcode));
1134 gen_op_store_T0_crf(crfD(ctx->opcode));
1137 /* isel (PowerPC 2.03 specification) */
1138 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
1140 uint32_t bi = rC(ctx->opcode);
1143 if (rA(ctx->opcode) == 0) {
1144 tcg_gen_movi_tl(cpu_T[0], 0);
1146 gen_op_load_gpr_T1(rA(ctx->opcode));
1148 gen_op_load_gpr_T2(rB(ctx->opcode));
1149 mask = 1 << (3 - (bi & 0x03));
1150 gen_op_load_crf_T0(bi >> 2);
1151 gen_op_test_true(mask);
1153 gen_op_store_T0_gpr(rD(ctx->opcode));
1156 /*** Integer logical ***/
1157 #define __GEN_LOGICAL2(name, opc2, opc3, type) \
1158 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, type) \
1160 gen_op_load_gpr_T0(rS(ctx->opcode)); \
1161 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1163 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1164 if (unlikely(Rc(ctx->opcode) != 0)) \
1167 #define GEN_LOGICAL2(name, opc, type) \
1168 __GEN_LOGICAL2(name, 0x1C, opc, type)
1170 #define GEN_LOGICAL1(name, opc, type) \
1171 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
1173 gen_op_load_gpr_T0(rS(ctx->opcode)); \
1175 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1176 if (unlikely(Rc(ctx->opcode) != 0)) \
1181 GEN_LOGICAL2(and, 0x00, PPC_INTEGER);
1183 GEN_LOGICAL2(andc, 0x01, PPC_INTEGER);
1185 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1187 gen_op_load_gpr_T0(rS(ctx->opcode));
1188 gen_op_andi_T0(UIMM(ctx->opcode));
1189 gen_op_store_T0_gpr(rA(ctx->opcode));
1193 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1195 gen_op_load_gpr_T0(rS(ctx->opcode));
1196 gen_op_andi_T0(UIMM(ctx->opcode) << 16);
1197 gen_op_store_T0_gpr(rA(ctx->opcode));
1202 GEN_LOGICAL1(cntlzw, 0x00, PPC_INTEGER);
1204 GEN_LOGICAL2(eqv, 0x08, PPC_INTEGER);
1205 /* extsb & extsb. */
1206 GEN_LOGICAL1(extsb, 0x1D, PPC_INTEGER);
1207 /* extsh & extsh. */
1208 GEN_LOGICAL1(extsh, 0x1C, PPC_INTEGER);
1210 GEN_LOGICAL2(nand, 0x0E, PPC_INTEGER);
1212 GEN_LOGICAL2(nor, 0x03, PPC_INTEGER);
1215 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1219 rs = rS(ctx->opcode);
1220 ra = rA(ctx->opcode);
1221 rb = rB(ctx->opcode);
1222 /* Optimisation for mr. ri case */
1223 if (rs != ra || rs != rb) {
1224 gen_op_load_gpr_T0(rs);
1226 gen_op_load_gpr_T1(rb);
1229 gen_op_store_T0_gpr(ra);
1230 if (unlikely(Rc(ctx->opcode) != 0))
1232 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1233 gen_op_load_gpr_T0(rs);
1235 #if defined(TARGET_PPC64)
1239 /* Set process priority to low */
1240 gen_op_store_pri(2);
1243 /* Set process priority to medium-low */
1244 gen_op_store_pri(3);
1247 /* Set process priority to normal */
1248 gen_op_store_pri(4);
1250 #if !defined(CONFIG_USER_ONLY)
1252 if (ctx->supervisor > 0) {
1253 /* Set process priority to very low */
1254 gen_op_store_pri(1);
1258 if (ctx->supervisor > 0) {
1259 /* Set process priority to medium-hight */
1260 gen_op_store_pri(5);
1264 if (ctx->supervisor > 0) {
1265 /* Set process priority to high */
1266 gen_op_store_pri(6);
1270 if (ctx->supervisor > 1) {
1271 /* Set process priority to very high */
1272 gen_op_store_pri(7);
1285 GEN_LOGICAL2(orc, 0x0C, PPC_INTEGER);
1287 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1289 gen_op_load_gpr_T0(rS(ctx->opcode));
1290 /* Optimisation for "set to zero" case */
1291 if (rS(ctx->opcode) != rB(ctx->opcode)) {
1292 gen_op_load_gpr_T1(rB(ctx->opcode));
1297 gen_op_store_T0_gpr(rA(ctx->opcode));
1298 if (unlikely(Rc(ctx->opcode) != 0))
1302 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1304 target_ulong uimm = UIMM(ctx->opcode);
1306 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1308 /* XXX: should handle special NOPs for POWER series */
1311 gen_op_load_gpr_T0(rS(ctx->opcode));
1312 if (likely(uimm != 0))
1314 gen_op_store_T0_gpr(rA(ctx->opcode));
1317 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1319 target_ulong uimm = UIMM(ctx->opcode);
1321 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1325 gen_op_load_gpr_T0(rS(ctx->opcode));
1326 if (likely(uimm != 0))
1327 gen_op_ori(uimm << 16);
1328 gen_op_store_T0_gpr(rA(ctx->opcode));
1331 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1333 target_ulong uimm = UIMM(ctx->opcode);
1335 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1339 gen_op_load_gpr_T0(rS(ctx->opcode));
1340 if (likely(uimm != 0))
1342 gen_op_store_T0_gpr(rA(ctx->opcode));
1346 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1348 target_ulong uimm = UIMM(ctx->opcode);
1350 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1354 gen_op_load_gpr_T0(rS(ctx->opcode));
1355 if (likely(uimm != 0))
1356 gen_op_xori(uimm << 16);
1357 gen_op_store_T0_gpr(rA(ctx->opcode));
1360 /* popcntb : PowerPC 2.03 specification */
1361 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
1363 gen_op_load_gpr_T0(rS(ctx->opcode));
1364 #if defined(TARGET_PPC64)
1366 gen_op_popcntb_64();
1370 gen_op_store_T0_gpr(rA(ctx->opcode));
1373 #if defined(TARGET_PPC64)
1374 /* extsw & extsw. */
1375 GEN_LOGICAL1(extsw, 0x1E, PPC_64B);
1377 GEN_LOGICAL1(cntlzd, 0x01, PPC_64B);
1380 /*** Integer rotate ***/
1381 /* rlwimi & rlwimi. */
1382 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1385 uint32_t mb, me, sh;
1387 mb = MB(ctx->opcode);
1388 me = ME(ctx->opcode);
1389 sh = SH(ctx->opcode);
1390 if (likely(sh == 0)) {
1391 if (likely(mb == 0 && me == 31)) {
1392 gen_op_load_gpr_T0(rS(ctx->opcode));
1394 } else if (likely(mb == 31 && me == 0)) {
1395 gen_op_load_gpr_T0(rA(ctx->opcode));
1398 gen_op_load_gpr_T0(rS(ctx->opcode));
1399 gen_op_load_gpr_T1(rA(ctx->opcode));
1402 gen_op_load_gpr_T0(rS(ctx->opcode));
1403 gen_op_load_gpr_T1(rA(ctx->opcode));
1404 gen_op_rotli32_T0(SH(ctx->opcode));
1406 #if defined(TARGET_PPC64)
1410 mask = MASK(mb, me);
1411 gen_op_andi_T0(mask);
1412 gen_op_andi_T1(~mask);
1415 gen_op_store_T0_gpr(rA(ctx->opcode));
1416 if (unlikely(Rc(ctx->opcode) != 0))
1419 /* rlwinm & rlwinm. */
1420 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1422 uint32_t mb, me, sh;
1424 sh = SH(ctx->opcode);
1425 mb = MB(ctx->opcode);
1426 me = ME(ctx->opcode);
1427 gen_op_load_gpr_T0(rS(ctx->opcode));
1428 if (likely(sh == 0)) {
1431 if (likely(mb == 0)) {
1432 if (likely(me == 31)) {
1433 gen_op_rotli32_T0(sh);
1435 } else if (likely(me == (31 - sh))) {
1439 } else if (likely(me == 31)) {
1440 if (likely(sh == (32 - mb))) {
1445 gen_op_rotli32_T0(sh);
1447 #if defined(TARGET_PPC64)
1451 gen_op_andi_T0(MASK(mb, me));
1453 gen_op_store_T0_gpr(rA(ctx->opcode));
1454 if (unlikely(Rc(ctx->opcode) != 0))
1457 /* rlwnm & rlwnm. */
1458 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1462 mb = MB(ctx->opcode);
1463 me = ME(ctx->opcode);
1464 gen_op_load_gpr_T0(rS(ctx->opcode));
1465 gen_op_load_gpr_T1(rB(ctx->opcode));
1466 gen_op_rotl32_T0_T1();
1467 if (unlikely(mb != 0 || me != 31)) {
1468 #if defined(TARGET_PPC64)
1472 gen_op_andi_T0(MASK(mb, me));
1474 gen_op_store_T0_gpr(rA(ctx->opcode));
1475 if (unlikely(Rc(ctx->opcode) != 0))
1479 #if defined(TARGET_PPC64)
1480 #define GEN_PPC64_R2(name, opc1, opc2) \
1481 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1483 gen_##name(ctx, 0); \
1485 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1488 gen_##name(ctx, 1); \
1490 #define GEN_PPC64_R4(name, opc1, opc2) \
1491 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1493 gen_##name(ctx, 0, 0); \
1495 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1498 gen_##name(ctx, 0, 1); \
1500 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1503 gen_##name(ctx, 1, 0); \
1505 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1508 gen_##name(ctx, 1, 1); \
1511 static always_inline void gen_andi_T0_64 (DisasContext *ctx, uint64_t mask)
1514 gen_op_andi_T0_64(mask >> 32, mask & 0xFFFFFFFF);
1516 gen_op_andi_T0(mask);
1519 static always_inline void gen_andi_T1_64 (DisasContext *ctx, uint64_t mask)
1522 gen_op_andi_T1_64(mask >> 32, mask & 0xFFFFFFFF);
1524 gen_op_andi_T1(mask);
1527 static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1528 uint32_t me, uint32_t sh)
1530 gen_op_load_gpr_T0(rS(ctx->opcode));
1531 if (likely(sh == 0)) {
1534 if (likely(mb == 0)) {
1535 if (likely(me == 63)) {
1536 gen_op_rotli64_T0(sh);
1538 } else if (likely(me == (63 - sh))) {
1542 } else if (likely(me == 63)) {
1543 if (likely(sh == (64 - mb))) {
1544 gen_op_srli_T0_64(mb);
1548 gen_op_rotli64_T0(sh);
1550 gen_andi_T0_64(ctx, MASK(mb, me));
1552 gen_op_store_T0_gpr(rA(ctx->opcode));
1553 if (unlikely(Rc(ctx->opcode) != 0))
1556 /* rldicl - rldicl. */
1557 static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
1561 sh = SH(ctx->opcode) | (shn << 5);
1562 mb = MB(ctx->opcode) | (mbn << 5);
1563 gen_rldinm(ctx, mb, 63, sh);
1565 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1566 /* rldicr - rldicr. */
1567 static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
1571 sh = SH(ctx->opcode) | (shn << 5);
1572 me = MB(ctx->opcode) | (men << 5);
1573 gen_rldinm(ctx, 0, me, sh);
1575 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1576 /* rldic - rldic. */
1577 static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
1581 sh = SH(ctx->opcode) | (shn << 5);
1582 mb = MB(ctx->opcode) | (mbn << 5);
1583 gen_rldinm(ctx, mb, 63 - sh, sh);
1585 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1587 static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1590 gen_op_load_gpr_T0(rS(ctx->opcode));
1591 gen_op_load_gpr_T1(rB(ctx->opcode));
1592 gen_op_rotl64_T0_T1();
1593 if (unlikely(mb != 0 || me != 63)) {
1594 gen_andi_T0_64(ctx, MASK(mb, me));
1596 gen_op_store_T0_gpr(rA(ctx->opcode));
1597 if (unlikely(Rc(ctx->opcode) != 0))
1601 /* rldcl - rldcl. */
1602 static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
1606 mb = MB(ctx->opcode) | (mbn << 5);
1607 gen_rldnm(ctx, mb, 63);
1609 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1610 /* rldcr - rldcr. */
1611 static always_inline void gen_rldcr (DisasContext *ctx, int men)
1615 me = MB(ctx->opcode) | (men << 5);
1616 gen_rldnm(ctx, 0, me);
1618 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1619 /* rldimi - rldimi. */
1620 static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
1623 uint32_t sh, mb, me;
1625 sh = SH(ctx->opcode) | (shn << 5);
1626 mb = MB(ctx->opcode) | (mbn << 5);
1628 if (likely(sh == 0)) {
1629 if (likely(mb == 0)) {
1630 gen_op_load_gpr_T0(rS(ctx->opcode));
1633 gen_op_load_gpr_T0(rS(ctx->opcode));
1634 gen_op_load_gpr_T1(rA(ctx->opcode));
1637 gen_op_load_gpr_T0(rS(ctx->opcode));
1638 gen_op_load_gpr_T1(rA(ctx->opcode));
1639 gen_op_rotli64_T0(sh);
1641 mask = MASK(mb, me);
1642 gen_andi_T0_64(ctx, mask);
1643 gen_andi_T1_64(ctx, ~mask);
1646 gen_op_store_T0_gpr(rA(ctx->opcode));
1647 if (unlikely(Rc(ctx->opcode) != 0))
1650 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1653 /*** Integer shift ***/
1655 __GEN_LOGICAL2(slw, 0x18, 0x00, PPC_INTEGER);
1657 __GEN_LOGICAL2(sraw, 0x18, 0x18, PPC_INTEGER);
1658 /* srawi & srawi. */
1659 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1662 gen_op_load_gpr_T0(rS(ctx->opcode));
1663 if (SH(ctx->opcode) != 0) {
1664 gen_op_move_T1_T0();
1665 mb = 32 - SH(ctx->opcode);
1667 #if defined(TARGET_PPC64)
1671 gen_op_srawi(SH(ctx->opcode), MASK(mb, me));
1673 gen_op_store_T0_gpr(rA(ctx->opcode));
1674 if (unlikely(Rc(ctx->opcode) != 0))
1678 __GEN_LOGICAL2(srw, 0x18, 0x10, PPC_INTEGER);
1680 #if defined(TARGET_PPC64)
1682 __GEN_LOGICAL2(sld, 0x1B, 0x00, PPC_64B);
1684 __GEN_LOGICAL2(srad, 0x1A, 0x18, PPC_64B);
1685 /* sradi & sradi. */
1686 static always_inline void gen_sradi (DisasContext *ctx, int n)
1691 gen_op_load_gpr_T0(rS(ctx->opcode));
1692 sh = SH(ctx->opcode) + (n << 5);
1694 gen_op_move_T1_T0();
1695 mb = 64 - SH(ctx->opcode);
1697 mask = MASK(mb, me);
1698 gen_op_sradi(sh, mask >> 32, mask);
1700 gen_op_store_T0_gpr(rA(ctx->opcode));
1701 if (unlikely(Rc(ctx->opcode) != 0))
1704 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
1708 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
1713 __GEN_LOGICAL2(srd, 0x1B, 0x10, PPC_64B);
1716 /*** Floating-Point arithmetic ***/
1717 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
1718 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
1720 if (unlikely(!ctx->fpu_enabled)) { \
1721 GEN_EXCP_NO_FP(ctx); \
1724 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1725 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
1726 gen_op_load_fpr_FT2(rB(ctx->opcode)); \
1727 gen_reset_fpstatus(); \
1732 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1733 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
1736 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
1737 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
1738 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
1740 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1741 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
1743 if (unlikely(!ctx->fpu_enabled)) { \
1744 GEN_EXCP_NO_FP(ctx); \
1747 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1748 gen_op_load_fpr_FT1(rB(ctx->opcode)); \
1749 gen_reset_fpstatus(); \
1754 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1755 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
1757 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
1758 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1759 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
1761 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1762 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
1764 if (unlikely(!ctx->fpu_enabled)) { \
1765 GEN_EXCP_NO_FP(ctx); \
1768 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1769 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
1770 gen_reset_fpstatus(); \
1775 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1776 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
1778 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
1779 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1780 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
1782 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
1783 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
1785 if (unlikely(!ctx->fpu_enabled)) { \
1786 GEN_EXCP_NO_FP(ctx); \
1789 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
1790 gen_reset_fpstatus(); \
1792 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1793 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
1796 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
1797 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
1799 if (unlikely(!ctx->fpu_enabled)) { \
1800 GEN_EXCP_NO_FP(ctx); \
1803 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
1804 gen_reset_fpstatus(); \
1806 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1807 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
1811 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
1813 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
1815 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
1818 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
1821 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
1824 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
1827 static always_inline void gen_op_frsqrtes (void)
1832 GEN_FLOAT_BS(rsqrtes, 0x3B, 0x1A, 1, PPC_FLOAT_FRSQRTES);
1835 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
1837 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
1840 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
1842 if (unlikely(!ctx->fpu_enabled)) {
1843 GEN_EXCP_NO_FP(ctx);
1846 gen_op_load_fpr_FT0(rB(ctx->opcode));
1847 gen_reset_fpstatus();
1849 gen_op_store_FT0_fpr(rD(ctx->opcode));
1850 gen_compute_fprf(1, Rc(ctx->opcode) != 0);
1853 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
1855 if (unlikely(!ctx->fpu_enabled)) {
1856 GEN_EXCP_NO_FP(ctx);
1859 gen_op_load_fpr_FT0(rB(ctx->opcode));
1860 gen_reset_fpstatus();
1863 gen_op_store_FT0_fpr(rD(ctx->opcode));
1864 gen_compute_fprf(1, Rc(ctx->opcode) != 0);
1867 /*** Floating-Point multiply-and-add ***/
1868 /* fmadd - fmadds */
1869 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
1870 /* fmsub - fmsubs */
1871 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
1872 /* fnmadd - fnmadds */
1873 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
1874 /* fnmsub - fnmsubs */
1875 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
1877 /*** Floating-Point round & convert ***/
1879 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
1881 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
1883 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
1884 #if defined(TARGET_PPC64)
1886 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
1888 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
1890 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
1894 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
1896 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
1898 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
1900 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
1902 /*** Floating-Point compare ***/
1904 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
1906 if (unlikely(!ctx->fpu_enabled)) {
1907 GEN_EXCP_NO_FP(ctx);
1910 gen_op_load_fpr_FT0(rA(ctx->opcode));
1911 gen_op_load_fpr_FT1(rB(ctx->opcode));
1912 gen_reset_fpstatus();
1914 gen_op_store_T0_crf(crfD(ctx->opcode));
1915 gen_op_float_check_status();
1919 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
1921 if (unlikely(!ctx->fpu_enabled)) {
1922 GEN_EXCP_NO_FP(ctx);
1925 gen_op_load_fpr_FT0(rA(ctx->opcode));
1926 gen_op_load_fpr_FT1(rB(ctx->opcode));
1927 gen_reset_fpstatus();
1929 gen_op_store_T0_crf(crfD(ctx->opcode));
1930 gen_op_float_check_status();
1933 /*** Floating-point move ***/
1935 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
1936 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
1939 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
1940 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
1942 if (unlikely(!ctx->fpu_enabled)) {
1943 GEN_EXCP_NO_FP(ctx);
1946 gen_op_load_fpr_FT0(rB(ctx->opcode));
1947 gen_op_store_FT0_fpr(rD(ctx->opcode));
1948 gen_compute_fprf(0, Rc(ctx->opcode) != 0);
1952 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
1953 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
1955 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
1956 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
1958 /*** Floating-Point status & ctrl register ***/
1960 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
1964 if (unlikely(!ctx->fpu_enabled)) {
1965 GEN_EXCP_NO_FP(ctx);
1968 gen_optimize_fprf();
1969 bfa = 4 * (7 - crfS(ctx->opcode));
1970 gen_op_load_fpscr_T0(bfa);
1971 gen_op_store_T0_crf(crfD(ctx->opcode));
1972 gen_op_fpscr_resetbit(~(0xF << bfa));
1976 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
1978 if (unlikely(!ctx->fpu_enabled)) {
1979 GEN_EXCP_NO_FP(ctx);
1982 gen_optimize_fprf();
1983 gen_reset_fpstatus();
1984 gen_op_load_fpscr_FT0();
1985 gen_op_store_FT0_fpr(rD(ctx->opcode));
1986 gen_compute_fprf(0, Rc(ctx->opcode) != 0);
1990 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
1994 if (unlikely(!ctx->fpu_enabled)) {
1995 GEN_EXCP_NO_FP(ctx);
1998 crb = 32 - (crbD(ctx->opcode) >> 2);
1999 gen_optimize_fprf();
2000 gen_reset_fpstatus();
2001 if (likely(crb != 30 && crb != 29))
2002 gen_op_fpscr_resetbit(~(1 << crb));
2003 if (unlikely(Rc(ctx->opcode) != 0)) {
2010 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
2014 if (unlikely(!ctx->fpu_enabled)) {
2015 GEN_EXCP_NO_FP(ctx);
2018 crb = 32 - (crbD(ctx->opcode) >> 2);
2019 gen_optimize_fprf();
2020 gen_reset_fpstatus();
2021 /* XXX: we pretend we can only do IEEE floating-point computations */
2022 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI))
2023 gen_op_fpscr_setbit(crb);
2024 if (unlikely(Rc(ctx->opcode) != 0)) {
2028 /* We can raise a differed exception */
2029 gen_op_float_check_status();
2033 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2035 if (unlikely(!ctx->fpu_enabled)) {
2036 GEN_EXCP_NO_FP(ctx);
2039 gen_optimize_fprf();
2040 gen_op_load_fpr_FT0(rB(ctx->opcode));
2041 gen_reset_fpstatus();
2042 gen_op_store_fpscr(FM(ctx->opcode));
2043 if (unlikely(Rc(ctx->opcode) != 0)) {
2047 /* We can raise a differed exception */
2048 gen_op_float_check_status();
2052 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2056 if (unlikely(!ctx->fpu_enabled)) {
2057 GEN_EXCP_NO_FP(ctx);
2060 bf = crbD(ctx->opcode) >> 2;
2062 gen_optimize_fprf();
2063 gen_op_set_FT0(FPIMM(ctx->opcode) << (4 * sh));
2064 gen_reset_fpstatus();
2065 gen_op_store_fpscr(1 << sh);
2066 if (unlikely(Rc(ctx->opcode) != 0)) {
2070 /* We can raise a differed exception */
2071 gen_op_float_check_status();
2074 /*** Addressing modes ***/
2075 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2076 static always_inline void gen_addr_imm_index (DisasContext *ctx,
2079 target_long simm = SIMM(ctx->opcode);
2082 if (rA(ctx->opcode) == 0) {
2083 tcg_gen_movi_tl(cpu_T[0], simm);
2085 gen_op_load_gpr_T0(rA(ctx->opcode));
2086 if (likely(simm != 0))
2089 #ifdef DEBUG_MEMORY_ACCESSES
2090 gen_op_print_mem_EA();
2094 static always_inline void gen_addr_reg_index (DisasContext *ctx)
2096 if (rA(ctx->opcode) == 0) {
2097 gen_op_load_gpr_T0(rB(ctx->opcode));
2099 gen_op_load_gpr_T0(rA(ctx->opcode));
2100 gen_op_load_gpr_T1(rB(ctx->opcode));
2103 #ifdef DEBUG_MEMORY_ACCESSES
2104 gen_op_print_mem_EA();
2108 static always_inline void gen_addr_register (DisasContext *ctx)
2110 if (rA(ctx->opcode) == 0) {
2113 gen_op_load_gpr_T0(rA(ctx->opcode));
2115 #ifdef DEBUG_MEMORY_ACCESSES
2116 gen_op_print_mem_EA();
2120 #if defined(TARGET_PPC64)
2121 #define _GEN_MEM_FUNCS(name, mode) \
2122 &gen_op_##name##_##mode, \
2123 &gen_op_##name##_le_##mode, \
2124 &gen_op_##name##_64_##mode, \
2125 &gen_op_##name##_le_64_##mode
2127 #define _GEN_MEM_FUNCS(name, mode) \
2128 &gen_op_##name##_##mode, \
2129 &gen_op_##name##_le_##mode
2131 #if defined(CONFIG_USER_ONLY)
2132 #if defined(TARGET_PPC64)
2133 #define NB_MEM_FUNCS 4
2135 #define NB_MEM_FUNCS 2
2137 #define GEN_MEM_FUNCS(name) \
2138 _GEN_MEM_FUNCS(name, raw)
2140 #if defined(TARGET_PPC64)
2141 #define NB_MEM_FUNCS 12
2143 #define NB_MEM_FUNCS 6
2145 #define GEN_MEM_FUNCS(name) \
2146 _GEN_MEM_FUNCS(name, user), \
2147 _GEN_MEM_FUNCS(name, kernel), \
2148 _GEN_MEM_FUNCS(name, hypv)
2151 /*** Integer load ***/
2152 #define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
2153 /* Byte access routine are endian safe */
2154 #define gen_op_lbz_le_raw gen_op_lbz_raw
2155 #define gen_op_lbz_le_user gen_op_lbz_user
2156 #define gen_op_lbz_le_kernel gen_op_lbz_kernel
2157 #define gen_op_lbz_le_hypv gen_op_lbz_hypv
2158 #define gen_op_lbz_le_64_raw gen_op_lbz_64_raw
2159 #define gen_op_lbz_le_64_user gen_op_lbz_64_user
2160 #define gen_op_lbz_le_64_kernel gen_op_lbz_64_kernel
2161 #define gen_op_lbz_le_64_hypv gen_op_lbz_64_hypv
2162 #define gen_op_stb_le_raw gen_op_stb_raw
2163 #define gen_op_stb_le_user gen_op_stb_user
2164 #define gen_op_stb_le_kernel gen_op_stb_kernel
2165 #define gen_op_stb_le_hypv gen_op_stb_hypv
2166 #define gen_op_stb_le_64_raw gen_op_stb_64_raw
2167 #define gen_op_stb_le_64_user gen_op_stb_64_user
2168 #define gen_op_stb_le_64_kernel gen_op_stb_64_kernel
2169 #define gen_op_stb_le_64_hypv gen_op_stb_64_hypv
2170 #define OP_LD_TABLE(width) \
2171 static GenOpFunc *gen_op_l##width[NB_MEM_FUNCS] = { \
2172 GEN_MEM_FUNCS(l##width), \
2174 #define OP_ST_TABLE(width) \
2175 static GenOpFunc *gen_op_st##width[NB_MEM_FUNCS] = { \
2176 GEN_MEM_FUNCS(st##width), \
2179 #define GEN_LD(width, opc, type) \
2180 GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
2182 gen_addr_imm_index(ctx, 0); \
2183 op_ldst(l##width); \
2184 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2187 #define GEN_LDU(width, opc, type) \
2188 GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2190 if (unlikely(rA(ctx->opcode) == 0 || \
2191 rA(ctx->opcode) == rD(ctx->opcode))) { \
2192 GEN_EXCP_INVAL(ctx); \
2195 if (type == PPC_64B) \
2196 gen_addr_imm_index(ctx, 0x03); \
2198 gen_addr_imm_index(ctx, 0); \
2199 op_ldst(l##width); \
2200 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2201 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2204 #define GEN_LDUX(width, opc2, opc3, type) \
2205 GEN_HANDLER(l##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2207 if (unlikely(rA(ctx->opcode) == 0 || \
2208 rA(ctx->opcode) == rD(ctx->opcode))) { \
2209 GEN_EXCP_INVAL(ctx); \
2212 gen_addr_reg_index(ctx); \
2213 op_ldst(l##width); \
2214 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2215 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2218 #define GEN_LDX(width, opc2, opc3, type) \
2219 GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
2221 gen_addr_reg_index(ctx); \
2222 op_ldst(l##width); \
2223 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2226 #define GEN_LDS(width, op, type) \
2227 OP_LD_TABLE(width); \
2228 GEN_LD(width, op | 0x20, type); \
2229 GEN_LDU(width, op | 0x21, type); \
2230 GEN_LDUX(width, 0x17, op | 0x01, type); \
2231 GEN_LDX(width, 0x17, op | 0x00, type)
2233 /* lbz lbzu lbzux lbzx */
2234 GEN_LDS(bz, 0x02, PPC_INTEGER);
2235 /* lha lhau lhaux lhax */
2236 GEN_LDS(ha, 0x0A, PPC_INTEGER);
2237 /* lhz lhzu lhzux lhzx */
2238 GEN_LDS(hz, 0x08, PPC_INTEGER);
2239 /* lwz lwzu lwzux lwzx */
2240 GEN_LDS(wz, 0x00, PPC_INTEGER);
2241 #if defined(TARGET_PPC64)
2245 GEN_LDUX(wa, 0x15, 0x0B, PPC_64B);
2247 GEN_LDX(wa, 0x15, 0x0A, PPC_64B);
2249 GEN_LDUX(d, 0x15, 0x01, PPC_64B);
2251 GEN_LDX(d, 0x15, 0x00, PPC_64B);
2252 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2254 if (Rc(ctx->opcode)) {
2255 if (unlikely(rA(ctx->opcode) == 0 ||
2256 rA(ctx->opcode) == rD(ctx->opcode))) {
2257 GEN_EXCP_INVAL(ctx);
2261 gen_addr_imm_index(ctx, 0x03);
2262 if (ctx->opcode & 0x02) {
2263 /* lwa (lwau is undefined) */
2269 gen_op_store_T1_gpr(rD(ctx->opcode));
2270 if (Rc(ctx->opcode))
2271 gen_op_store_T0_gpr(rA(ctx->opcode));
2274 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2276 #if defined(CONFIG_USER_ONLY)
2277 GEN_EXCP_PRIVOPC(ctx);
2281 /* Restore CPU state */
2282 if (unlikely(ctx->supervisor == 0)) {
2283 GEN_EXCP_PRIVOPC(ctx);
2286 ra = rA(ctx->opcode);
2287 rd = rD(ctx->opcode);
2288 if (unlikely((rd & 1) || rd == ra)) {
2289 GEN_EXCP_INVAL(ctx);
2292 if (unlikely(ctx->mem_idx & 1)) {
2293 /* Little-endian mode is not handled */
2294 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2297 gen_addr_imm_index(ctx, 0x0F);
2299 gen_op_store_T1_gpr(rd);
2302 gen_op_store_T1_gpr(rd + 1);
2307 /*** Integer store ***/
2308 #define GEN_ST(width, opc, type) \
2309 GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
2311 gen_addr_imm_index(ctx, 0); \
2312 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2313 op_ldst(st##width); \
2316 #define GEN_STU(width, opc, type) \
2317 GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2319 if (unlikely(rA(ctx->opcode) == 0)) { \
2320 GEN_EXCP_INVAL(ctx); \
2323 if (type == PPC_64B) \
2324 gen_addr_imm_index(ctx, 0x03); \
2326 gen_addr_imm_index(ctx, 0); \
2327 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2328 op_ldst(st##width); \
2329 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2332 #define GEN_STUX(width, opc2, opc3, type) \
2333 GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2335 if (unlikely(rA(ctx->opcode) == 0)) { \
2336 GEN_EXCP_INVAL(ctx); \
2339 gen_addr_reg_index(ctx); \
2340 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2341 op_ldst(st##width); \
2342 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2345 #define GEN_STX(width, opc2, opc3, type) \
2346 GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
2348 gen_addr_reg_index(ctx); \
2349 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2350 op_ldst(st##width); \
2353 #define GEN_STS(width, op, type) \
2354 OP_ST_TABLE(width); \
2355 GEN_ST(width, op | 0x20, type); \
2356 GEN_STU(width, op | 0x21, type); \
2357 GEN_STUX(width, 0x17, op | 0x01, type); \
2358 GEN_STX(width, 0x17, op | 0x00, type)
2360 /* stb stbu stbux stbx */
2361 GEN_STS(b, 0x06, PPC_INTEGER);
2362 /* sth sthu sthux sthx */
2363 GEN_STS(h, 0x0C, PPC_INTEGER);
2364 /* stw stwu stwux stwx */
2365 GEN_STS(w, 0x04, PPC_INTEGER);
2366 #if defined(TARGET_PPC64)
2368 GEN_STUX(d, 0x15, 0x05, PPC_64B);
2369 GEN_STX(d, 0x15, 0x04, PPC_64B);
2370 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
2374 rs = rS(ctx->opcode);
2375 if ((ctx->opcode & 0x3) == 0x2) {
2376 #if defined(CONFIG_USER_ONLY)
2377 GEN_EXCP_PRIVOPC(ctx);
2380 if (unlikely(ctx->supervisor == 0)) {
2381 GEN_EXCP_PRIVOPC(ctx);
2384 if (unlikely(rs & 1)) {
2385 GEN_EXCP_INVAL(ctx);
2388 if (unlikely(ctx->mem_idx & 1)) {
2389 /* Little-endian mode is not handled */
2390 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2393 gen_addr_imm_index(ctx, 0x03);
2394 gen_op_load_gpr_T1(rs);
2397 gen_op_load_gpr_T1(rs + 1);
2402 if (Rc(ctx->opcode)) {
2403 if (unlikely(rA(ctx->opcode) == 0)) {
2404 GEN_EXCP_INVAL(ctx);
2408 gen_addr_imm_index(ctx, 0x03);
2409 gen_op_load_gpr_T1(rs);
2411 if (Rc(ctx->opcode))
2412 gen_op_store_T0_gpr(rA(ctx->opcode));
2416 /*** Integer load and store with byte reverse ***/
2419 GEN_LDX(hbr, 0x16, 0x18, PPC_INTEGER);
2422 GEN_LDX(wbr, 0x16, 0x10, PPC_INTEGER);
2425 GEN_STX(hbr, 0x16, 0x1C, PPC_INTEGER);
2428 GEN_STX(wbr, 0x16, 0x14, PPC_INTEGER);
2430 /*** Integer load and store multiple ***/
2431 #define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
2432 static GenOpFunc1 *gen_op_lmw[NB_MEM_FUNCS] = {
2435 static GenOpFunc1 *gen_op_stmw[NB_MEM_FUNCS] = {
2436 GEN_MEM_FUNCS(stmw),
2440 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
2442 /* NIP cannot be restored if the memory exception comes from an helper */
2443 gen_update_nip(ctx, ctx->nip - 4);
2444 gen_addr_imm_index(ctx, 0);
2445 op_ldstm(lmw, rD(ctx->opcode));
2449 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
2451 /* NIP cannot be restored if the memory exception comes from an helper */
2452 gen_update_nip(ctx, ctx->nip - 4);
2453 gen_addr_imm_index(ctx, 0);
2454 op_ldstm(stmw, rS(ctx->opcode));
2457 /*** Integer load and store strings ***/
2458 #define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
2459 #define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
2460 /* string load & stores are by definition endian-safe */
2461 #define gen_op_lswi_le_raw gen_op_lswi_raw
2462 #define gen_op_lswi_le_user gen_op_lswi_user
2463 #define gen_op_lswi_le_kernel gen_op_lswi_kernel
2464 #define gen_op_lswi_le_hypv gen_op_lswi_hypv
2465 #define gen_op_lswi_le_64_raw gen_op_lswi_raw
2466 #define gen_op_lswi_le_64_user gen_op_lswi_user
2467 #define gen_op_lswi_le_64_kernel gen_op_lswi_kernel
2468 #define gen_op_lswi_le_64_hypv gen_op_lswi_hypv
2469 static GenOpFunc1 *gen_op_lswi[NB_MEM_FUNCS] = {
2470 GEN_MEM_FUNCS(lswi),
2472 #define gen_op_lswx_le_raw gen_op_lswx_raw
2473 #define gen_op_lswx_le_user gen_op_lswx_user
2474 #define gen_op_lswx_le_kernel gen_op_lswx_kernel
2475 #define gen_op_lswx_le_hypv gen_op_lswx_hypv
2476 #define gen_op_lswx_le_64_raw gen_op_lswx_raw
2477 #define gen_op_lswx_le_64_user gen_op_lswx_user
2478 #define gen_op_lswx_le_64_kernel gen_op_lswx_kernel
2479 #define gen_op_lswx_le_64_hypv gen_op_lswx_hypv
2480 static GenOpFunc3 *gen_op_lswx[NB_MEM_FUNCS] = {
2481 GEN_MEM_FUNCS(lswx),
2483 #define gen_op_stsw_le_raw gen_op_stsw_raw
2484 #define gen_op_stsw_le_user gen_op_stsw_user
2485 #define gen_op_stsw_le_kernel gen_op_stsw_kernel
2486 #define gen_op_stsw_le_hypv gen_op_stsw_hypv
2487 #define gen_op_stsw_le_64_raw gen_op_stsw_raw
2488 #define gen_op_stsw_le_64_user gen_op_stsw_user
2489 #define gen_op_stsw_le_64_kernel gen_op_stsw_kernel
2490 #define gen_op_stsw_le_64_hypv gen_op_stsw_hypv
2491 static GenOpFunc1 *gen_op_stsw[NB_MEM_FUNCS] = {
2492 GEN_MEM_FUNCS(stsw),
2496 /* PowerPC32 specification says we must generate an exception if
2497 * rA is in the range of registers to be loaded.
2498 * In an other hand, IBM says this is valid, but rA won't be loaded.
2499 * For now, I'll follow the spec...
2501 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
2503 int nb = NB(ctx->opcode);
2504 int start = rD(ctx->opcode);
2505 int ra = rA(ctx->opcode);
2511 if (unlikely(((start + nr) > 32 &&
2512 start <= ra && (start + nr - 32) > ra) ||
2513 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
2514 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
2515 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_LSWX);
2518 /* NIP cannot be restored if the memory exception comes from an helper */
2519 gen_update_nip(ctx, ctx->nip - 4);
2520 gen_addr_register(ctx);
2522 op_ldsts(lswi, start);
2526 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
2528 int ra = rA(ctx->opcode);
2529 int rb = rB(ctx->opcode);
2531 /* NIP cannot be restored if the memory exception comes from an helper */
2532 gen_update_nip(ctx, ctx->nip - 4);
2533 gen_addr_reg_index(ctx);
2537 gen_op_load_xer_bc();
2538 op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
2542 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
2544 int nb = NB(ctx->opcode);
2546 /* NIP cannot be restored if the memory exception comes from an helper */
2547 gen_update_nip(ctx, ctx->nip - 4);
2548 gen_addr_register(ctx);
2552 op_ldsts(stsw, rS(ctx->opcode));
2556 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
2558 /* NIP cannot be restored if the memory exception comes from an helper */
2559 gen_update_nip(ctx, ctx->nip - 4);
2560 gen_addr_reg_index(ctx);
2561 gen_op_load_xer_bc();
2562 op_ldsts(stsw, rS(ctx->opcode));
2565 /*** Memory synchronisation ***/
2567 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
2572 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
2577 #define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
2578 #define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
2579 static GenOpFunc *gen_op_lwarx[NB_MEM_FUNCS] = {
2580 GEN_MEM_FUNCS(lwarx),
2582 static GenOpFunc *gen_op_stwcx[NB_MEM_FUNCS] = {
2583 GEN_MEM_FUNCS(stwcx),
2587 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
2589 /* NIP cannot be restored if the memory exception comes from an helper */
2590 gen_update_nip(ctx, ctx->nip - 4);
2591 gen_addr_reg_index(ctx);
2593 gen_op_store_T1_gpr(rD(ctx->opcode));
2597 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
2599 /* NIP cannot be restored if the memory exception comes from an helper */
2600 gen_update_nip(ctx, ctx->nip - 4);
2601 gen_addr_reg_index(ctx);
2602 gen_op_load_gpr_T1(rS(ctx->opcode));
2606 #if defined(TARGET_PPC64)
2607 #define op_ldarx() (*gen_op_ldarx[ctx->mem_idx])()
2608 #define op_stdcx() (*gen_op_stdcx[ctx->mem_idx])()
2609 static GenOpFunc *gen_op_ldarx[NB_MEM_FUNCS] = {
2610 GEN_MEM_FUNCS(ldarx),
2612 static GenOpFunc *gen_op_stdcx[NB_MEM_FUNCS] = {
2613 GEN_MEM_FUNCS(stdcx),
2617 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
2619 /* NIP cannot be restored if the memory exception comes from an helper */
2620 gen_update_nip(ctx, ctx->nip - 4);
2621 gen_addr_reg_index(ctx);
2623 gen_op_store_T1_gpr(rD(ctx->opcode));
2627 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
2629 /* NIP cannot be restored if the memory exception comes from an helper */
2630 gen_update_nip(ctx, ctx->nip - 4);
2631 gen_addr_reg_index(ctx);
2632 gen_op_load_gpr_T1(rS(ctx->opcode));
2635 #endif /* defined(TARGET_PPC64) */
2638 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
2643 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
2645 /* Stop translation, as the CPU is supposed to sleep from now */
2647 GEN_EXCP(ctx, EXCP_HLT, 1);
2650 /*** Floating-point load ***/
2651 #define GEN_LDF(width, opc, type) \
2652 GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
2654 if (unlikely(!ctx->fpu_enabled)) { \
2655 GEN_EXCP_NO_FP(ctx); \
2658 gen_addr_imm_index(ctx, 0); \
2659 op_ldst(l##width); \
2660 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
2663 #define GEN_LDUF(width, opc, type) \
2664 GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2666 if (unlikely(!ctx->fpu_enabled)) { \
2667 GEN_EXCP_NO_FP(ctx); \
2670 if (unlikely(rA(ctx->opcode) == 0)) { \
2671 GEN_EXCP_INVAL(ctx); \
2674 gen_addr_imm_index(ctx, 0); \
2675 op_ldst(l##width); \
2676 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
2677 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2680 #define GEN_LDUXF(width, opc, type) \
2681 GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
2683 if (unlikely(!ctx->fpu_enabled)) { \
2684 GEN_EXCP_NO_FP(ctx); \
2687 if (unlikely(rA(ctx->opcode) == 0)) { \
2688 GEN_EXCP_INVAL(ctx); \
2691 gen_addr_reg_index(ctx); \
2692 op_ldst(l##width); \
2693 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
2694 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2697 #define GEN_LDXF(width, opc2, opc3, type) \
2698 GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
2700 if (unlikely(!ctx->fpu_enabled)) { \
2701 GEN_EXCP_NO_FP(ctx); \
2704 gen_addr_reg_index(ctx); \
2705 op_ldst(l##width); \
2706 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
2709 #define GEN_LDFS(width, op, type) \
2710 OP_LD_TABLE(width); \
2711 GEN_LDF(width, op | 0x20, type); \
2712 GEN_LDUF(width, op | 0x21, type); \
2713 GEN_LDUXF(width, op | 0x01, type); \
2714 GEN_LDXF(width, 0x17, op | 0x00, type)
2716 /* lfd lfdu lfdux lfdx */
2717 GEN_LDFS(fd, 0x12, PPC_FLOAT);
2718 /* lfs lfsu lfsux lfsx */
2719 GEN_LDFS(fs, 0x10, PPC_FLOAT);
2721 /*** Floating-point store ***/
2722 #define GEN_STF(width, opc, type) \
2723 GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
2725 if (unlikely(!ctx->fpu_enabled)) { \
2726 GEN_EXCP_NO_FP(ctx); \
2729 gen_addr_imm_index(ctx, 0); \
2730 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
2731 op_ldst(st##width); \
2734 #define GEN_STUF(width, opc, type) \
2735 GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2737 if (unlikely(!ctx->fpu_enabled)) { \
2738 GEN_EXCP_NO_FP(ctx); \
2741 if (unlikely(rA(ctx->opcode) == 0)) { \
2742 GEN_EXCP_INVAL(ctx); \
2745 gen_addr_imm_index(ctx, 0); \
2746 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
2747 op_ldst(st##width); \
2748 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2751 #define GEN_STUXF(width, opc, type) \
2752 GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
2754 if (unlikely(!ctx->fpu_enabled)) { \
2755 GEN_EXCP_NO_FP(ctx); \
2758 if (unlikely(rA(ctx->opcode) == 0)) { \
2759 GEN_EXCP_INVAL(ctx); \
2762 gen_addr_reg_index(ctx); \
2763 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
2764 op_ldst(st##width); \
2765 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2768 #define GEN_STXF(width, opc2, opc3, type) \
2769 GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
2771 if (unlikely(!ctx->fpu_enabled)) { \
2772 GEN_EXCP_NO_FP(ctx); \
2775 gen_addr_reg_index(ctx); \
2776 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
2777 op_ldst(st##width); \
2780 #define GEN_STFS(width, op, type) \
2781 OP_ST_TABLE(width); \
2782 GEN_STF(width, op | 0x20, type); \
2783 GEN_STUF(width, op | 0x21, type); \
2784 GEN_STUXF(width, op | 0x01, type); \
2785 GEN_STXF(width, 0x17, op | 0x00, type)
2787 /* stfd stfdu stfdux stfdx */
2788 GEN_STFS(fd, 0x16, PPC_FLOAT);
2789 /* stfs stfsu stfsux stfsx */
2790 GEN_STFS(fs, 0x14, PPC_FLOAT);
2795 GEN_STXF(fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
2798 static always_inline void gen_goto_tb (DisasContext *ctx, int n,
2801 TranslationBlock *tb;
2803 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
2804 likely(!ctx->singlestep_enabled)) {
2806 tcg_gen_movi_tl(cpu_T[1], dest);
2807 #if defined(TARGET_PPC64)
2813 tcg_gen_exit_tb((long)tb + n);
2815 tcg_gen_movi_tl(cpu_T[1], dest);
2816 #if defined(TARGET_PPC64)
2822 if (unlikely(ctx->singlestep_enabled)) {
2823 if ((ctx->singlestep_enabled &
2824 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
2825 ctx->exception == POWERPC_EXCP_BRANCH) {
2826 target_ulong tmp = ctx->nip;
2828 GEN_EXCP(ctx, POWERPC_EXCP_TRACE, 0);
2831 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
2832 gen_update_nip(ctx, dest);
2840 static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
2842 #if defined(TARGET_PPC64)
2843 if (ctx->sf_mode != 0 && (nip >> 32))
2844 gen_op_setlr_64(ctx->nip >> 32, ctx->nip);
2847 gen_op_setlr(ctx->nip);
2851 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
2853 target_ulong li, target;
2855 ctx->exception = POWERPC_EXCP_BRANCH;
2856 /* sign extend LI */
2857 #if defined(TARGET_PPC64)
2859 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
2862 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
2863 if (likely(AA(ctx->opcode) == 0))
2864 target = ctx->nip + li - 4;
2867 #if defined(TARGET_PPC64)
2869 target = (uint32_t)target;
2871 if (LK(ctx->opcode))
2872 gen_setlr(ctx, ctx->nip);
2873 gen_goto_tb(ctx, 0, target);
2880 static always_inline void gen_bcond (DisasContext *ctx, int type)
2882 target_ulong target = 0;
2884 uint32_t bo = BO(ctx->opcode);
2885 uint32_t bi = BI(ctx->opcode);
2888 ctx->exception = POWERPC_EXCP_BRANCH;
2889 if ((bo & 0x4) == 0)
2893 li = (target_long)((int16_t)(BD(ctx->opcode)));
2894 if (likely(AA(ctx->opcode) == 0)) {
2895 target = ctx->nip + li - 4;
2899 #if defined(TARGET_PPC64)
2901 target = (uint32_t)target;
2905 gen_op_movl_T1_ctr();
2909 gen_op_movl_T1_lr();
2912 if (LK(ctx->opcode))
2913 gen_setlr(ctx, ctx->nip);
2915 /* No CR condition */
2918 #if defined(TARGET_PPC64)
2920 gen_op_test_ctr_64();
2926 #if defined(TARGET_PPC64)
2928 gen_op_test_ctrz_64();
2936 if (type == BCOND_IM) {
2937 gen_goto_tb(ctx, 0, target);
2940 #if defined(TARGET_PPC64)
2951 mask = 1 << (3 - (bi & 0x03));
2952 gen_op_load_crf_T0(bi >> 2);
2956 #if defined(TARGET_PPC64)
2958 gen_op_test_ctr_true_64(mask);
2961 gen_op_test_ctr_true(mask);
2964 #if defined(TARGET_PPC64)
2966 gen_op_test_ctrz_true_64(mask);
2969 gen_op_test_ctrz_true(mask);
2974 gen_op_test_true(mask);
2980 #if defined(TARGET_PPC64)
2982 gen_op_test_ctr_false_64(mask);
2985 gen_op_test_ctr_false(mask);
2988 #if defined(TARGET_PPC64)
2990 gen_op_test_ctrz_false_64(mask);
2993 gen_op_test_ctrz_false(mask);
2998 gen_op_test_false(mask);
3003 if (type == BCOND_IM) {
3004 int l1 = gen_new_label();
3006 gen_goto_tb(ctx, 0, target);
3008 gen_goto_tb(ctx, 1, ctx->nip);
3010 #if defined(TARGET_PPC64)
3012 gen_op_btest_T1_64(ctx->nip >> 32, ctx->nip);
3015 gen_op_btest_T1(ctx->nip);
3017 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3018 gen_update_nip(ctx, ctx->nip);
3025 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3027 gen_bcond(ctx, BCOND_IM);
3030 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3032 gen_bcond(ctx, BCOND_CTR);
3035 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3037 gen_bcond(ctx, BCOND_LR);
3040 /*** Condition register logical ***/
3041 #define GEN_CRLOGIC(op, opc) \
3042 GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
3046 gen_op_load_crf_T0(crbA(ctx->opcode) >> 2); \
3047 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3049 gen_op_srli_T0(sh); \
3051 gen_op_sli_T0(-sh); \
3052 gen_op_load_crf_T1(crbB(ctx->opcode) >> 2); \
3053 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3055 gen_op_srli_T1(sh); \
3057 gen_op_sli_T1(-sh); \
3059 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3060 gen_op_andi_T0(bitmask); \
3061 gen_op_load_crf_T1(crbD(ctx->opcode) >> 2); \
3062 gen_op_andi_T1(~bitmask); \
3064 gen_op_store_T0_crf(crbD(ctx->opcode) >> 2); \
3068 GEN_CRLOGIC(and, 0x08);
3070 GEN_CRLOGIC(andc, 0x04);
3072 GEN_CRLOGIC(eqv, 0x09);
3074 GEN_CRLOGIC(nand, 0x07);
3076 GEN_CRLOGIC(nor, 0x01);
3078 GEN_CRLOGIC(or, 0x0E);
3080 GEN_CRLOGIC(orc, 0x0D);
3082 GEN_CRLOGIC(xor, 0x06);
3084 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3086 gen_op_load_crf_T0(crfS(ctx->opcode));
3087 gen_op_store_T0_crf(crfD(ctx->opcode));
3090 /*** System linkage ***/
3091 /* rfi (supervisor only) */
3092 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
3094 #if defined(CONFIG_USER_ONLY)
3095 GEN_EXCP_PRIVOPC(ctx);
3097 /* Restore CPU state */
3098 if (unlikely(!ctx->supervisor)) {
3099 GEN_EXCP_PRIVOPC(ctx);
3107 #if defined(TARGET_PPC64)
3108 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
3110 #if defined(CONFIG_USER_ONLY)
3111 GEN_EXCP_PRIVOPC(ctx);
3113 /* Restore CPU state */
3114 if (unlikely(!ctx->supervisor)) {
3115 GEN_EXCP_PRIVOPC(ctx);
3123 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
3125 #if defined(CONFIG_USER_ONLY)
3126 GEN_EXCP_PRIVOPC(ctx);
3128 /* Restore CPU state */
3129 if (unlikely(ctx->supervisor <= 1)) {
3130 GEN_EXCP_PRIVOPC(ctx);
3140 #if defined(CONFIG_USER_ONLY)
3141 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3143 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3145 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
3149 lev = (ctx->opcode >> 5) & 0x7F;
3150 GEN_EXCP(ctx, POWERPC_SYSCALL, lev);
3155 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
3157 gen_op_load_gpr_T0(rA(ctx->opcode));
3158 gen_op_load_gpr_T1(rB(ctx->opcode));
3159 /* Update the nip since this might generate a trap exception */
3160 gen_update_nip(ctx, ctx->nip);
3161 gen_op_tw(TO(ctx->opcode));
3165 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3167 gen_op_load_gpr_T0(rA(ctx->opcode));
3168 tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
3169 /* Update the nip since this might generate a trap exception */
3170 gen_update_nip(ctx, ctx->nip);
3171 gen_op_tw(TO(ctx->opcode));
3174 #if defined(TARGET_PPC64)
3176 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3178 gen_op_load_gpr_T0(rA(ctx->opcode));
3179 gen_op_load_gpr_T1(rB(ctx->opcode));
3180 /* Update the nip since this might generate a trap exception */
3181 gen_update_nip(ctx, ctx->nip);
3182 gen_op_td(TO(ctx->opcode));
3186 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3188 gen_op_load_gpr_T0(rA(ctx->opcode));
3189 tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
3190 /* Update the nip since this might generate a trap exception */
3191 gen_update_nip(ctx, ctx->nip);
3192 gen_op_td(TO(ctx->opcode));
3196 /*** Processor control ***/
3198 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3200 gen_op_load_xer_cr();
3201 gen_op_store_T0_crf(crfD(ctx->opcode));
3202 gen_op_clear_xer_ov();
3203 gen_op_clear_xer_ca();
3207 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
3211 if (likely(ctx->opcode & 0x00100000)) {
3212 crm = CRM(ctx->opcode);
3213 if (likely((crm ^ (crm - 1)) == 0)) {
3215 gen_op_load_cro(7 - crn);
3220 gen_op_store_T0_gpr(rD(ctx->opcode));
3224 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3226 #if defined(CONFIG_USER_ONLY)
3227 GEN_EXCP_PRIVREG(ctx);
3229 if (unlikely(!ctx->supervisor)) {
3230 GEN_EXCP_PRIVREG(ctx);
3234 gen_op_store_T0_gpr(rD(ctx->opcode));
3239 #define SPR_NOACCESS ((void *)(-1UL))
3241 static void spr_noaccess (void *opaque, int sprn)
3243 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3244 printf("ERROR: try to access SPR %d !\n", sprn);
3246 #define SPR_NOACCESS (&spr_noaccess)
3250 static always_inline void gen_op_mfspr (DisasContext *ctx)
3252 void (*read_cb)(void *opaque, int sprn);
3253 uint32_t sprn = SPR(ctx->opcode);
3255 #if !defined(CONFIG_USER_ONLY)
3256 if (ctx->supervisor == 2)
3257 read_cb = ctx->spr_cb[sprn].hea_read;
3258 else if (ctx->supervisor)
3259 read_cb = ctx->spr_cb[sprn].oea_read;
3262 read_cb = ctx->spr_cb[sprn].uea_read;
3263 if (likely(read_cb != NULL)) {
3264 if (likely(read_cb != SPR_NOACCESS)) {
3265 (*read_cb)(ctx, sprn);
3266 gen_op_store_T0_gpr(rD(ctx->opcode));
3268 /* Privilege exception */
3269 /* This is a hack to avoid warnings when running Linux:
3270 * this OS breaks the PowerPC virtualisation model,
3271 * allowing userland application to read the PVR
3273 if (sprn != SPR_PVR) {
3274 if (loglevel != 0) {
3275 fprintf(logfile, "Trying to read privileged spr %d %03x at "
3276 ADDRX "\n", sprn, sprn, ctx->nip);
3278 printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3279 sprn, sprn, ctx->nip);
3281 GEN_EXCP_PRIVREG(ctx);
3285 if (loglevel != 0) {
3286 fprintf(logfile, "Trying to read invalid spr %d %03x at "
3287 ADDRX "\n", sprn, sprn, ctx->nip);
3289 printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3290 sprn, sprn, ctx->nip);
3291 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3292 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
3296 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
3302 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3308 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
3312 gen_op_load_gpr_T0(rS(ctx->opcode));
3313 crm = CRM(ctx->opcode);
3314 if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
3316 gen_op_srli_T0(crn * 4);
3317 gen_op_andi_T0(0xF);
3318 gen_op_store_cro(7 - crn);
3320 gen_op_store_cr(crm);
3325 #if defined(TARGET_PPC64)
3326 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
3328 #if defined(CONFIG_USER_ONLY)
3329 GEN_EXCP_PRIVREG(ctx);
3331 if (unlikely(!ctx->supervisor)) {
3332 GEN_EXCP_PRIVREG(ctx);
3335 gen_op_load_gpr_T0(rS(ctx->opcode));
3336 if (ctx->opcode & 0x00010000) {
3337 /* Special form that does not need any synchronisation */
3338 gen_op_update_riee();
3340 /* XXX: we need to update nip before the store
3341 * if we enter power saving mode, we will exit the loop
3342 * directly from ppc_store_msr
3344 gen_update_nip(ctx, ctx->nip);
3346 /* Must stop the translation as machine state (may have) changed */
3347 /* Note that mtmsr is not always defined as context-synchronizing */
3348 ctx->exception = POWERPC_EXCP_STOP;
3354 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3356 #if defined(CONFIG_USER_ONLY)
3357 GEN_EXCP_PRIVREG(ctx);
3359 if (unlikely(!ctx->supervisor)) {
3360 GEN_EXCP_PRIVREG(ctx);
3363 gen_op_load_gpr_T0(rS(ctx->opcode));
3364 if (ctx->opcode & 0x00010000) {
3365 /* Special form that does not need any synchronisation */
3366 gen_op_update_riee();
3368 /* XXX: we need to update nip before the store
3369 * if we enter power saving mode, we will exit the loop
3370 * directly from ppc_store_msr
3372 gen_update_nip(ctx, ctx->nip);
3373 #if defined(TARGET_PPC64)
3375 gen_op_store_msr_32();
3379 /* Must stop the translation as machine state (may have) changed */
3380 /* Note that mtmsrd is not always defined as context-synchronizing */
3381 ctx->exception = POWERPC_EXCP_STOP;
3387 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
3389 void (*write_cb)(void *opaque, int sprn);
3390 uint32_t sprn = SPR(ctx->opcode);
3392 #if !defined(CONFIG_USER_ONLY)
3393 if (ctx->supervisor == 2)
3394 write_cb = ctx->spr_cb[sprn].hea_write;
3395 else if (ctx->supervisor)
3396 write_cb = ctx->spr_cb[sprn].oea_write;
3399 write_cb = ctx->spr_cb[sprn].uea_write;
3400 if (likely(write_cb != NULL)) {
3401 if (likely(write_cb != SPR_NOACCESS)) {
3402 gen_op_load_gpr_T0(rS(ctx->opcode));
3403 (*write_cb)(ctx, sprn);
3405 /* Privilege exception */
3406 if (loglevel != 0) {
3407 fprintf(logfile, "Trying to write privileged spr %d %03x at "
3408 ADDRX "\n", sprn, sprn, ctx->nip);
3410 printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
3411 sprn, sprn, ctx->nip);
3412 GEN_EXCP_PRIVREG(ctx);
3416 if (loglevel != 0) {
3417 fprintf(logfile, "Trying to write invalid spr %d %03x at "
3418 ADDRX "\n", sprn, sprn, ctx->nip);
3420 printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
3421 sprn, sprn, ctx->nip);
3422 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3423 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
3427 /*** Cache management ***/
3429 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
3431 /* XXX: specification says this is treated as a load by the MMU */
3432 gen_addr_reg_index(ctx);
3436 /* dcbi (Supervisor only) */
3437 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
3439 #if defined(CONFIG_USER_ONLY)
3440 GEN_EXCP_PRIVOPC(ctx);
3442 if (unlikely(!ctx->supervisor)) {
3443 GEN_EXCP_PRIVOPC(ctx);
3446 gen_addr_reg_index(ctx);
3447 /* XXX: specification says this should be treated as a store by the MMU */
3454 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
3456 /* XXX: specification say this is treated as a load by the MMU */
3457 gen_addr_reg_index(ctx);
3462 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
3464 /* interpreted as no-op */
3465 /* XXX: specification say this is treated as a load by the MMU
3466 * but does not generate any exception
3471 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
3473 /* interpreted as no-op */
3474 /* XXX: specification say this is treated as a load by the MMU
3475 * but does not generate any exception
3480 #define op_dcbz(n) (*gen_op_dcbz[n][ctx->mem_idx])()
3481 static GenOpFunc *gen_op_dcbz[4][NB_MEM_FUNCS] = {
3482 /* 32 bytes cache line size */
3484 #define gen_op_dcbz_l32_le_raw gen_op_dcbz_l32_raw
3485 #define gen_op_dcbz_l32_le_user gen_op_dcbz_l32_user
3486 #define gen_op_dcbz_l32_le_kernel gen_op_dcbz_l32_kernel
3487 #define gen_op_dcbz_l32_le_hypv gen_op_dcbz_l32_hypv
3488 #define gen_op_dcbz_l32_le_64_raw gen_op_dcbz_l32_64_raw
3489 #define gen_op_dcbz_l32_le_64_user gen_op_dcbz_l32_64_user
3490 #define gen_op_dcbz_l32_le_64_kernel gen_op_dcbz_l32_64_kernel
3491 #define gen_op_dcbz_l32_le_64_hypv gen_op_dcbz_l32_64_hypv
3492 GEN_MEM_FUNCS(dcbz_l32),
3494 /* 64 bytes cache line size */
3496 #define gen_op_dcbz_l64_le_raw gen_op_dcbz_l64_raw
3497 #define gen_op_dcbz_l64_le_user gen_op_dcbz_l64_user
3498 #define gen_op_dcbz_l64_le_kernel gen_op_dcbz_l64_kernel
3499 #define gen_op_dcbz_l64_le_hypv gen_op_dcbz_l64_hypv
3500 #define gen_op_dcbz_l64_le_64_raw gen_op_dcbz_l64_64_raw
3501 #define gen_op_dcbz_l64_le_64_user gen_op_dcbz_l64_64_user
3502 #define gen_op_dcbz_l64_le_64_kernel gen_op_dcbz_l64_64_kernel
3503 #define gen_op_dcbz_l64_le_64_hypv gen_op_dcbz_l64_64_hypv
3504 GEN_MEM_FUNCS(dcbz_l64),
3506 /* 128 bytes cache line size */
3508 #define gen_op_dcbz_l128_le_raw gen_op_dcbz_l128_raw
3509 #define gen_op_dcbz_l128_le_user gen_op_dcbz_l128_user
3510 #define gen_op_dcbz_l128_le_kernel gen_op_dcbz_l128_kernel
3511 #define gen_op_dcbz_l128_le_hypv gen_op_dcbz_l128_hypv
3512 #define gen_op_dcbz_l128_le_64_raw gen_op_dcbz_l128_64_raw
3513 #define gen_op_dcbz_l128_le_64_user gen_op_dcbz_l128_64_user
3514 #define gen_op_dcbz_l128_le_64_kernel gen_op_dcbz_l128_64_kernel
3515 #define gen_op_dcbz_l128_le_64_hypv gen_op_dcbz_l128_64_hypv
3516 GEN_MEM_FUNCS(dcbz_l128),
3518 /* tunable cache line size */
3520 #define gen_op_dcbz_le_raw gen_op_dcbz_raw
3521 #define gen_op_dcbz_le_user gen_op_dcbz_user
3522 #define gen_op_dcbz_le_kernel gen_op_dcbz_kernel
3523 #define gen_op_dcbz_le_hypv gen_op_dcbz_hypv
3524 #define gen_op_dcbz_le_64_raw gen_op_dcbz_64_raw
3525 #define gen_op_dcbz_le_64_user gen_op_dcbz_64_user
3526 #define gen_op_dcbz_le_64_kernel gen_op_dcbz_64_kernel
3527 #define gen_op_dcbz_le_64_hypv gen_op_dcbz_64_hypv
3528 GEN_MEM_FUNCS(dcbz),
3532 static always_inline void handler_dcbz (DisasContext *ctx,
3533 int dcache_line_size)
3537 switch (dcache_line_size) {
3554 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
3556 gen_addr_reg_index(ctx);
3557 handler_dcbz(ctx, ctx->dcache_line_size);
3558 gen_op_check_reservation();
3561 GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
3563 gen_addr_reg_index(ctx);
3564 if (ctx->opcode & 0x00200000)
3565 handler_dcbz(ctx, ctx->dcache_line_size);
3567 handler_dcbz(ctx, -1);
3568 gen_op_check_reservation();
3572 #define op_icbi() (*gen_op_icbi[ctx->mem_idx])()
3573 #define gen_op_icbi_le_raw gen_op_icbi_raw
3574 #define gen_op_icbi_le_user gen_op_icbi_user
3575 #define gen_op_icbi_le_kernel gen_op_icbi_kernel
3576 #define gen_op_icbi_le_hypv gen_op_icbi_hypv
3577 #define gen_op_icbi_le_64_raw gen_op_icbi_64_raw
3578 #define gen_op_icbi_le_64_user gen_op_icbi_64_user
3579 #define gen_op_icbi_le_64_kernel gen_op_icbi_64_kernel
3580 #define gen_op_icbi_le_64_hypv gen_op_icbi_64_hypv
3581 static GenOpFunc *gen_op_icbi[NB_MEM_FUNCS] = {
3582 GEN_MEM_FUNCS(icbi),
3585 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
3587 /* NIP cannot be restored if the memory exception comes from an helper */
3588 gen_update_nip(ctx, ctx->nip - 4);
3589 gen_addr_reg_index(ctx);
3595 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
3597 /* interpreted as no-op */
3598 /* XXX: specification say this is treated as a store by the MMU
3599 * but does not generate any exception
3603 /*** Segment register manipulation ***/
3604 /* Supervisor only: */
3606 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
3608 #if defined(CONFIG_USER_ONLY)
3609 GEN_EXCP_PRIVREG(ctx);
3611 if (unlikely(!ctx->supervisor)) {
3612 GEN_EXCP_PRIVREG(ctx);
3615 gen_op_set_T1(SR(ctx->opcode));
3617 gen_op_store_T0_gpr(rD(ctx->opcode));
3622 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
3624 #if defined(CONFIG_USER_ONLY)
3625 GEN_EXCP_PRIVREG(ctx);
3627 if (unlikely(!ctx->supervisor)) {
3628 GEN_EXCP_PRIVREG(ctx);
3631 gen_op_load_gpr_T1(rB(ctx->opcode));
3634 gen_op_store_T0_gpr(rD(ctx->opcode));
3639 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
3641 #if defined(CONFIG_USER_ONLY)
3642 GEN_EXCP_PRIVREG(ctx);
3644 if (unlikely(!ctx->supervisor)) {
3645 GEN_EXCP_PRIVREG(ctx);
3648 gen_op_load_gpr_T0(rS(ctx->opcode));
3649 gen_op_set_T1(SR(ctx->opcode));
3655 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
3657 #if defined(CONFIG_USER_ONLY)
3658 GEN_EXCP_PRIVREG(ctx);
3660 if (unlikely(!ctx->supervisor)) {
3661 GEN_EXCP_PRIVREG(ctx);
3664 gen_op_load_gpr_T0(rS(ctx->opcode));
3665 gen_op_load_gpr_T1(rB(ctx->opcode));
3671 #if defined(TARGET_PPC64)
3672 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
3674 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
3676 #if defined(CONFIG_USER_ONLY)
3677 GEN_EXCP_PRIVREG(ctx);
3679 if (unlikely(!ctx->supervisor)) {
3680 GEN_EXCP_PRIVREG(ctx);
3683 gen_op_set_T1(SR(ctx->opcode));
3685 gen_op_store_T0_gpr(rD(ctx->opcode));
3690 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
3693 #if defined(CONFIG_USER_ONLY)
3694 GEN_EXCP_PRIVREG(ctx);
3696 if (unlikely(!ctx->supervisor)) {
3697 GEN_EXCP_PRIVREG(ctx);
3700 gen_op_load_gpr_T1(rB(ctx->opcode));
3703 gen_op_store_T0_gpr(rD(ctx->opcode));
3708 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
3710 #if defined(CONFIG_USER_ONLY)
3711 GEN_EXCP_PRIVREG(ctx);
3713 if (unlikely(!ctx->supervisor)) {
3714 GEN_EXCP_PRIVREG(ctx);
3717 gen_op_load_gpr_T0(rS(ctx->opcode));
3718 gen_op_set_T1(SR(ctx->opcode));
3724 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
3727 #if defined(CONFIG_USER_ONLY)
3728 GEN_EXCP_PRIVREG(ctx);
3730 if (unlikely(!ctx->supervisor)) {
3731 GEN_EXCP_PRIVREG(ctx);
3734 gen_op_load_gpr_T0(rS(ctx->opcode));
3735 gen_op_load_gpr_T1(rB(ctx->opcode));
3740 #endif /* defined(TARGET_PPC64) */
3742 /*** Lookaside buffer management ***/
3743 /* Optional & supervisor only: */
3745 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
3747 #if defined(CONFIG_USER_ONLY)
3748 GEN_EXCP_PRIVOPC(ctx);
3750 if (unlikely(!ctx->supervisor)) {
3751 GEN_EXCP_PRIVOPC(ctx);
3759 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
3761 #if defined(CONFIG_USER_ONLY)
3762 GEN_EXCP_PRIVOPC(ctx);
3764 if (unlikely(!ctx->supervisor)) {
3765 GEN_EXCP_PRIVOPC(ctx);
3768 gen_op_load_gpr_T0(rB(ctx->opcode));
3769 #if defined(TARGET_PPC64)
3779 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
3781 #if defined(CONFIG_USER_ONLY)
3782 GEN_EXCP_PRIVOPC(ctx);
3784 if (unlikely(!ctx->supervisor)) {
3785 GEN_EXCP_PRIVOPC(ctx);
3788 /* This has no effect: it should ensure that all previous
3789 * tlbie have completed
3795 #if defined(TARGET_PPC64)
3797 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
3799 #if defined(CONFIG_USER_ONLY)
3800 GEN_EXCP_PRIVOPC(ctx);
3802 if (unlikely(!ctx->supervisor)) {
3803 GEN_EXCP_PRIVOPC(ctx);
3811 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
3813 #if defined(CONFIG_USER_ONLY)
3814 GEN_EXCP_PRIVOPC(ctx);
3816 if (unlikely(!ctx->supervisor)) {
3817 GEN_EXCP_PRIVOPC(ctx);
3820 gen_op_load_gpr_T0(rB(ctx->opcode));
3826 /*** External control ***/
3828 #define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
3829 #define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
3830 static GenOpFunc *gen_op_eciwx[NB_MEM_FUNCS] = {
3831 GEN_MEM_FUNCS(eciwx),
3833 static GenOpFunc *gen_op_ecowx[NB_MEM_FUNCS] = {
3834 GEN_MEM_FUNCS(ecowx),
3838 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
3840 /* Should check EAR[E] & alignment ! */
3841 gen_addr_reg_index(ctx);
3843 gen_op_store_T0_gpr(rD(ctx->opcode));
3847 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
3849 /* Should check EAR[E] & alignment ! */
3850 gen_addr_reg_index(ctx);
3851 gen_op_load_gpr_T1(rS(ctx->opcode));
3855 /* PowerPC 601 specific instructions */
3857 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
3859 gen_op_load_gpr_T0(rA(ctx->opcode));
3861 gen_op_store_T0_gpr(rD(ctx->opcode));
3862 if (unlikely(Rc(ctx->opcode) != 0))
3867 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
3869 gen_op_load_gpr_T0(rA(ctx->opcode));
3870 gen_op_POWER_abso();
3871 gen_op_store_T0_gpr(rD(ctx->opcode));
3872 if (unlikely(Rc(ctx->opcode) != 0))
3877 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
3879 gen_op_load_gpr_T0(rA(ctx->opcode));
3880 gen_op_POWER_clcs();
3881 /* Rc=1 sets CR0 to an undefined state */
3882 gen_op_store_T0_gpr(rD(ctx->opcode));
3886 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
3888 gen_op_load_gpr_T0(rA(ctx->opcode));
3889 gen_op_load_gpr_T1(rB(ctx->opcode));
3891 gen_op_store_T0_gpr(rD(ctx->opcode));
3892 if (unlikely(Rc(ctx->opcode) != 0))
3897 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
3899 gen_op_load_gpr_T0(rA(ctx->opcode));
3900 gen_op_load_gpr_T1(rB(ctx->opcode));
3901 gen_op_POWER_divo();
3902 gen_op_store_T0_gpr(rD(ctx->opcode));
3903 if (unlikely(Rc(ctx->opcode) != 0))
3908 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
3910 gen_op_load_gpr_T0(rA(ctx->opcode));
3911 gen_op_load_gpr_T1(rB(ctx->opcode));
3912 gen_op_POWER_divs();
3913 gen_op_store_T0_gpr(rD(ctx->opcode));
3914 if (unlikely(Rc(ctx->opcode) != 0))
3918 /* divso - divso. */
3919 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
3921 gen_op_load_gpr_T0(rA(ctx->opcode));
3922 gen_op_load_gpr_T1(rB(ctx->opcode));
3923 gen_op_POWER_divso();
3924 gen_op_store_T0_gpr(rD(ctx->opcode));
3925 if (unlikely(Rc(ctx->opcode) != 0))
3930 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
3932 gen_op_load_gpr_T0(rA(ctx->opcode));
3933 gen_op_load_gpr_T1(rB(ctx->opcode));
3935 gen_op_store_T0_gpr(rD(ctx->opcode));
3936 if (unlikely(Rc(ctx->opcode) != 0))
3941 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
3943 gen_op_load_gpr_T0(rA(ctx->opcode));
3944 gen_op_load_gpr_T1(rB(ctx->opcode));
3945 gen_op_POWER_dozo();
3946 gen_op_store_T0_gpr(rD(ctx->opcode));
3947 if (unlikely(Rc(ctx->opcode) != 0))
3952 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
3954 gen_op_load_gpr_T0(rA(ctx->opcode));
3955 gen_op_set_T1(SIMM(ctx->opcode));
3957 gen_op_store_T0_gpr(rD(ctx->opcode));
3960 /* As lscbx load from memory byte after byte, it's always endian safe.
3961 * Original POWER is 32 bits only, define 64 bits ops as 32 bits ones
3963 #define op_POWER_lscbx(start, ra, rb) \
3964 (*gen_op_POWER_lscbx[ctx->mem_idx])(start, ra, rb)
3965 #define gen_op_POWER_lscbx_64_raw gen_op_POWER_lscbx_raw
3966 #define gen_op_POWER_lscbx_64_user gen_op_POWER_lscbx_user
3967 #define gen_op_POWER_lscbx_64_kernel gen_op_POWER_lscbx_kernel
3968 #define gen_op_POWER_lscbx_64_hypv gen_op_POWER_lscbx_hypv
3969 #define gen_op_POWER_lscbx_le_raw gen_op_POWER_lscbx_raw
3970 #define gen_op_POWER_lscbx_le_user gen_op_POWER_lscbx_user
3971 #define gen_op_POWER_lscbx_le_kernel gen_op_POWER_lscbx_kernel
3972 #define gen_op_POWER_lscbx_le_hypv gen_op_POWER_lscbx_hypv
3973 #define gen_op_POWER_lscbx_le_64_raw gen_op_POWER_lscbx_raw
3974 #define gen_op_POWER_lscbx_le_64_user gen_op_POWER_lscbx_user
3975 #define gen_op_POWER_lscbx_le_64_kernel gen_op_POWER_lscbx_kernel
3976 #define gen_op_POWER_lscbx_le_64_hypv gen_op_POWER_lscbx_hypv
3977 static GenOpFunc3 *gen_op_POWER_lscbx[NB_MEM_FUNCS] = {
3978 GEN_MEM_FUNCS(POWER_lscbx),
3981 /* lscbx - lscbx. */
3982 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
3984 int ra = rA(ctx->opcode);
3985 int rb = rB(ctx->opcode);
3987 gen_addr_reg_index(ctx);
3991 /* NIP cannot be restored if the memory exception comes from an helper */
3992 gen_update_nip(ctx, ctx->nip - 4);
3993 gen_op_load_xer_bc();
3994 gen_op_load_xer_cmp();
3995 op_POWER_lscbx(rD(ctx->opcode), ra, rb);
3996 gen_op_store_xer_bc();
3997 if (unlikely(Rc(ctx->opcode) != 0))
4001 /* maskg - maskg. */
4002 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4004 gen_op_load_gpr_T0(rS(ctx->opcode));
4005 gen_op_load_gpr_T1(rB(ctx->opcode));
4006 gen_op_POWER_maskg();
4007 gen_op_store_T0_gpr(rA(ctx->opcode));
4008 if (unlikely(Rc(ctx->opcode) != 0))
4012 /* maskir - maskir. */
4013 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4015 gen_op_load_gpr_T0(rA(ctx->opcode));
4016 gen_op_load_gpr_T1(rS(ctx->opcode));
4017 gen_op_load_gpr_T2(rB(ctx->opcode));
4018 gen_op_POWER_maskir();
4019 gen_op_store_T0_gpr(rA(ctx->opcode));
4020 if (unlikely(Rc(ctx->opcode) != 0))
4025 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4027 gen_op_load_gpr_T0(rA(ctx->opcode));
4028 gen_op_load_gpr_T1(rB(ctx->opcode));
4030 gen_op_store_T0_gpr(rD(ctx->opcode));
4031 if (unlikely(Rc(ctx->opcode) != 0))
4036 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4038 gen_op_load_gpr_T0(rA(ctx->opcode));
4039 gen_op_load_gpr_T1(rB(ctx->opcode));
4040 gen_op_POWER_mulo();
4041 gen_op_store_T0_gpr(rD(ctx->opcode));
4042 if (unlikely(Rc(ctx->opcode) != 0))
4047 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4049 gen_op_load_gpr_T0(rA(ctx->opcode));
4050 gen_op_POWER_nabs();
4051 gen_op_store_T0_gpr(rD(ctx->opcode));
4052 if (unlikely(Rc(ctx->opcode) != 0))
4056 /* nabso - nabso. */
4057 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4059 gen_op_load_gpr_T0(rA(ctx->opcode));
4060 gen_op_POWER_nabso();
4061 gen_op_store_T0_gpr(rD(ctx->opcode));
4062 if (unlikely(Rc(ctx->opcode) != 0))
4067 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4071 mb = MB(ctx->opcode);
4072 me = ME(ctx->opcode);
4073 gen_op_load_gpr_T0(rS(ctx->opcode));
4074 gen_op_load_gpr_T1(rA(ctx->opcode));
4075 gen_op_load_gpr_T2(rB(ctx->opcode));
4076 gen_op_POWER_rlmi(MASK(mb, me), ~MASK(mb, me));
4077 gen_op_store_T0_gpr(rA(ctx->opcode));
4078 if (unlikely(Rc(ctx->opcode) != 0))
4083 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4085 gen_op_load_gpr_T0(rS(ctx->opcode));
4086 gen_op_load_gpr_T1(rA(ctx->opcode));
4087 gen_op_load_gpr_T2(rB(ctx->opcode));
4088 gen_op_POWER_rrib();
4089 gen_op_store_T0_gpr(rA(ctx->opcode));
4090 if (unlikely(Rc(ctx->opcode) != 0))
4095 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4097 gen_op_load_gpr_T0(rS(ctx->opcode));
4098 gen_op_load_gpr_T1(rB(ctx->opcode));
4100 gen_op_store_T0_gpr(rA(ctx->opcode));
4101 if (unlikely(Rc(ctx->opcode) != 0))
4106 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4108 gen_op_load_gpr_T0(rS(ctx->opcode));
4109 gen_op_load_gpr_T1(rB(ctx->opcode));
4110 gen_op_POWER_sleq();
4111 gen_op_store_T0_gpr(rA(ctx->opcode));
4112 if (unlikely(Rc(ctx->opcode) != 0))
4117 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4119 gen_op_load_gpr_T0(rS(ctx->opcode));
4120 gen_op_set_T1(SH(ctx->opcode));
4122 gen_op_store_T0_gpr(rA(ctx->opcode));
4123 if (unlikely(Rc(ctx->opcode) != 0))
4127 /* slliq - slliq. */
4128 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4130 gen_op_load_gpr_T0(rS(ctx->opcode));
4131 gen_op_set_T1(SH(ctx->opcode));
4132 gen_op_POWER_sleq();
4133 gen_op_store_T0_gpr(rA(ctx->opcode));
4134 if (unlikely(Rc(ctx->opcode) != 0))
4139 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4141 gen_op_load_gpr_T0(rS(ctx->opcode));
4142 gen_op_load_gpr_T1(rB(ctx->opcode));
4143 gen_op_POWER_sllq();
4144 gen_op_store_T0_gpr(rA(ctx->opcode));
4145 if (unlikely(Rc(ctx->opcode) != 0))
4150 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4152 gen_op_load_gpr_T0(rS(ctx->opcode));
4153 gen_op_load_gpr_T1(rB(ctx->opcode));
4155 gen_op_store_T0_gpr(rA(ctx->opcode));
4156 if (unlikely(Rc(ctx->opcode) != 0))
4160 /* sraiq - sraiq. */
4161 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4163 gen_op_load_gpr_T0(rS(ctx->opcode));
4164 gen_op_set_T1(SH(ctx->opcode));
4165 gen_op_POWER_sraq();
4166 gen_op_store_T0_gpr(rA(ctx->opcode));
4167 if (unlikely(Rc(ctx->opcode) != 0))
4172 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4174 gen_op_load_gpr_T0(rS(ctx->opcode));
4175 gen_op_load_gpr_T1(rB(ctx->opcode));
4176 gen_op_POWER_sraq();
4177 gen_op_store_T0_gpr(rA(ctx->opcode));
4178 if (unlikely(Rc(ctx->opcode) != 0))
4183 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4185 gen_op_load_gpr_T0(rS(ctx->opcode));
4186 gen_op_load_gpr_T1(rB(ctx->opcode));
4188 gen_op_store_T0_gpr(rA(ctx->opcode));
4189 if (unlikely(Rc(ctx->opcode) != 0))
4194 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4196 gen_op_load_gpr_T0(rS(ctx->opcode));
4197 gen_op_load_gpr_T1(rB(ctx->opcode));
4198 gen_op_POWER_srea();
4199 gen_op_store_T0_gpr(rA(ctx->opcode));
4200 if (unlikely(Rc(ctx->opcode) != 0))
4205 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
4207 gen_op_load_gpr_T0(rS(ctx->opcode));
4208 gen_op_load_gpr_T1(rB(ctx->opcode));
4209 gen_op_POWER_sreq();
4210 gen_op_store_T0_gpr(rA(ctx->opcode));
4211 if (unlikely(Rc(ctx->opcode) != 0))
4216 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
4218 gen_op_load_gpr_T0(rS(ctx->opcode));
4219 gen_op_set_T1(SH(ctx->opcode));
4221 gen_op_store_T0_gpr(rA(ctx->opcode));
4222 if (unlikely(Rc(ctx->opcode) != 0))
4227 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
4229 gen_op_load_gpr_T0(rS(ctx->opcode));
4230 gen_op_load_gpr_T1(rB(ctx->opcode));
4231 gen_op_set_T1(SH(ctx->opcode));
4232 gen_op_POWER_srlq();
4233 gen_op_store_T0_gpr(rA(ctx->opcode));
4234 if (unlikely(Rc(ctx->opcode) != 0))
4239 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
4241 gen_op_load_gpr_T0(rS(ctx->opcode));
4242 gen_op_load_gpr_T1(rB(ctx->opcode));
4243 gen_op_POWER_srlq();
4244 gen_op_store_T0_gpr(rA(ctx->opcode));
4245 if (unlikely(Rc(ctx->opcode) != 0))
4250 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
4252 gen_op_load_gpr_T0(rS(ctx->opcode));
4253 gen_op_load_gpr_T1(rB(ctx->opcode));
4255 gen_op_store_T0_gpr(rA(ctx->opcode));
4256 if (unlikely(Rc(ctx->opcode) != 0))
4260 /* PowerPC 602 specific instructions */
4262 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
4265 GEN_EXCP_INVAL(ctx);
4269 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
4272 GEN_EXCP_INVAL(ctx);
4276 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
4278 #if defined(CONFIG_USER_ONLY)
4279 GEN_EXCP_PRIVOPC(ctx);
4281 if (unlikely(!ctx->supervisor)) {
4282 GEN_EXCP_PRIVOPC(ctx);
4285 gen_op_load_gpr_T0(rA(ctx->opcode));
4287 gen_op_store_T0_gpr(rD(ctx->opcode));
4291 /* 602 - 603 - G2 TLB management */
4293 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
4295 #if defined(CONFIG_USER_ONLY)
4296 GEN_EXCP_PRIVOPC(ctx);
4298 if (unlikely(!ctx->supervisor)) {
4299 GEN_EXCP_PRIVOPC(ctx);
4302 gen_op_load_gpr_T0(rB(ctx->opcode));
4308 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
4310 #if defined(CONFIG_USER_ONLY)
4311 GEN_EXCP_PRIVOPC(ctx);
4313 if (unlikely(!ctx->supervisor)) {
4314 GEN_EXCP_PRIVOPC(ctx);
4317 gen_op_load_gpr_T0(rB(ctx->opcode));
4322 /* 74xx TLB management */
4324 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
4326 #if defined(CONFIG_USER_ONLY)
4327 GEN_EXCP_PRIVOPC(ctx);
4329 if (unlikely(!ctx->supervisor)) {
4330 GEN_EXCP_PRIVOPC(ctx);
4333 gen_op_load_gpr_T0(rB(ctx->opcode));
4334 gen_op_74xx_tlbld();
4339 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
4341 #if defined(CONFIG_USER_ONLY)
4342 GEN_EXCP_PRIVOPC(ctx);
4344 if (unlikely(!ctx->supervisor)) {
4345 GEN_EXCP_PRIVOPC(ctx);
4348 gen_op_load_gpr_T0(rB(ctx->opcode));
4349 gen_op_74xx_tlbli();
4353 /* POWER instructions not in PowerPC 601 */
4355 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
4357 /* Cache line flush: implemented as no-op */
4361 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
4363 /* Cache line invalidate: privileged and treated as no-op */
4364 #if defined(CONFIG_USER_ONLY)
4365 GEN_EXCP_PRIVOPC(ctx);
4367 if (unlikely(!ctx->supervisor)) {
4368 GEN_EXCP_PRIVOPC(ctx);
4375 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
4377 /* Data cache line store: treated as no-op */
4380 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
4382 #if defined(CONFIG_USER_ONLY)
4383 GEN_EXCP_PRIVOPC(ctx);
4385 if (unlikely(!ctx->supervisor)) {
4386 GEN_EXCP_PRIVOPC(ctx);
4389 int ra = rA(ctx->opcode);
4390 int rd = rD(ctx->opcode);
4392 gen_addr_reg_index(ctx);
4393 gen_op_POWER_mfsri();
4394 gen_op_store_T0_gpr(rd);
4395 if (ra != 0 && ra != rd)
4396 gen_op_store_T1_gpr(ra);
4400 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
4402 #if defined(CONFIG_USER_ONLY)
4403 GEN_EXCP_PRIVOPC(ctx);
4405 if (unlikely(!ctx->supervisor)) {
4406 GEN_EXCP_PRIVOPC(ctx);
4409 gen_addr_reg_index(ctx);
4411 gen_op_store_T0_gpr(rD(ctx->opcode));
4415 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
4417 #if defined(CONFIG_USER_ONLY)
4418 GEN_EXCP_PRIVOPC(ctx);
4420 if (unlikely(!ctx->supervisor)) {
4421 GEN_EXCP_PRIVOPC(ctx);
4424 gen_op_POWER_rfsvc();
4429 /* svc is not implemented for now */
4431 /* POWER2 specific instructions */
4432 /* Quad manipulation (load/store two floats at a time) */
4433 /* Original POWER2 is 32 bits only, define 64 bits ops as 32 bits ones */
4434 #define op_POWER2_lfq() (*gen_op_POWER2_lfq[ctx->mem_idx])()
4435 #define op_POWER2_stfq() (*gen_op_POWER2_stfq[ctx->mem_idx])()
4436 #define gen_op_POWER2_lfq_64_raw gen_op_POWER2_lfq_raw
4437 #define gen_op_POWER2_lfq_64_user gen_op_POWER2_lfq_user
4438 #define gen_op_POWER2_lfq_64_kernel gen_op_POWER2_lfq_kernel
4439 #define gen_op_POWER2_lfq_64_hypv gen_op_POWER2_lfq_hypv
4440 #define gen_op_POWER2_lfq_le_64_raw gen_op_POWER2_lfq_le_raw
4441 #define gen_op_POWER2_lfq_le_64_user gen_op_POWER2_lfq_le_user
4442 #define gen_op_POWER2_lfq_le_64_kernel gen_op_POWER2_lfq_le_kernel
4443 #define gen_op_POWER2_lfq_le_64_hypv gen_op_POWER2_lfq_le_hypv
4444 #define gen_op_POWER2_stfq_64_raw gen_op_POWER2_stfq_raw
4445 #define gen_op_POWER2_stfq_64_user gen_op_POWER2_stfq_user
4446 #define gen_op_POWER2_stfq_64_kernel gen_op_POWER2_stfq_kernel
4447 #define gen_op_POWER2_stfq_64_hypv gen_op_POWER2_stfq_hypv
4448 #define gen_op_POWER2_stfq_le_64_raw gen_op_POWER2_stfq_le_raw
4449 #define gen_op_POWER2_stfq_le_64_user gen_op_POWER2_stfq_le_user
4450 #define gen_op_POWER2_stfq_le_64_kernel gen_op_POWER2_stfq_le_kernel
4451 #define gen_op_POWER2_stfq_le_64_hypv gen_op_POWER2_stfq_le_hypv
4452 static GenOpFunc *gen_op_POWER2_lfq[NB_MEM_FUNCS] = {
4453 GEN_MEM_FUNCS(POWER2_lfq),
4455 static GenOpFunc *gen_op_POWER2_stfq[NB_MEM_FUNCS] = {
4456 GEN_MEM_FUNCS(POWER2_stfq),
4460 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4462 /* NIP cannot be restored if the memory exception comes from an helper */
4463 gen_update_nip(ctx, ctx->nip - 4);
4464 gen_addr_imm_index(ctx, 0);
4466 gen_op_store_FT0_fpr(rD(ctx->opcode));
4467 gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4471 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4473 int ra = rA(ctx->opcode);
4475 /* NIP cannot be restored if the memory exception comes from an helper */
4476 gen_update_nip(ctx, ctx->nip - 4);
4477 gen_addr_imm_index(ctx, 0);
4479 gen_op_store_FT0_fpr(rD(ctx->opcode));
4480 gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4482 gen_op_store_T0_gpr(ra);
4486 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
4488 int ra = rA(ctx->opcode);
4490 /* NIP cannot be restored if the memory exception comes from an helper */
4491 gen_update_nip(ctx, ctx->nip - 4);
4492 gen_addr_reg_index(ctx);
4494 gen_op_store_FT0_fpr(rD(ctx->opcode));
4495 gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4497 gen_op_store_T0_gpr(ra);
4501 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
4503 /* NIP cannot be restored if the memory exception comes from an helper */
4504 gen_update_nip(ctx, ctx->nip - 4);
4505 gen_addr_reg_index(ctx);
4507 gen_op_store_FT0_fpr(rD(ctx->opcode));
4508 gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4512 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4514 /* NIP cannot be restored if the memory exception comes from an helper */
4515 gen_update_nip(ctx, ctx->nip - 4);
4516 gen_addr_imm_index(ctx, 0);
4517 gen_op_load_fpr_FT0(rS(ctx->opcode));
4518 gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
4523 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4525 int ra = rA(ctx->opcode);
4527 /* NIP cannot be restored if the memory exception comes from an helper */
4528 gen_update_nip(ctx, ctx->nip - 4);
4529 gen_addr_imm_index(ctx, 0);
4530 gen_op_load_fpr_FT0(rS(ctx->opcode));
4531 gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
4534 gen_op_store_T0_gpr(ra);
4538 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
4540 int ra = rA(ctx->opcode);
4542 /* NIP cannot be restored if the memory exception comes from an helper */
4543 gen_update_nip(ctx, ctx->nip - 4);
4544 gen_addr_reg_index(ctx);
4545 gen_op_load_fpr_FT0(rS(ctx->opcode));
4546 gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
4549 gen_op_store_T0_gpr(ra);
4553 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
4555 /* NIP cannot be restored if the memory exception comes from an helper */
4556 gen_update_nip(ctx, ctx->nip - 4);
4557 gen_addr_reg_index(ctx);
4558 gen_op_load_fpr_FT0(rS(ctx->opcode));
4559 gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
4563 /* BookE specific instructions */
4564 /* XXX: not implemented on 440 ? */
4565 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)
4568 GEN_EXCP_INVAL(ctx);
4571 /* XXX: not implemented on 440 ? */
4572 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
4574 #if defined(CONFIG_USER_ONLY)
4575 GEN_EXCP_PRIVOPC(ctx);
4577 if (unlikely(!ctx->supervisor)) {
4578 GEN_EXCP_PRIVOPC(ctx);
4581 gen_addr_reg_index(ctx);
4582 /* Use the same micro-ops as for tlbie */
4583 #if defined(TARGET_PPC64)
4592 /* All 405 MAC instructions are translated here */
4593 static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
4595 int ra, int rb, int rt, int Rc)
4597 gen_op_load_gpr_T0(ra);
4598 gen_op_load_gpr_T1(rb);
4599 switch (opc3 & 0x0D) {
4601 /* macchw - macchw. - macchwo - macchwo. */
4602 /* macchws - macchws. - macchwso - macchwso. */
4603 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
4604 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
4605 /* mulchw - mulchw. */
4606 gen_op_405_mulchw();
4609 /* macchwu - macchwu. - macchwuo - macchwuo. */
4610 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
4611 /* mulchwu - mulchwu. */
4612 gen_op_405_mulchwu();
4615 /* machhw - machhw. - machhwo - machhwo. */
4616 /* machhws - machhws. - machhwso - machhwso. */
4617 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
4618 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
4619 /* mulhhw - mulhhw. */
4620 gen_op_405_mulhhw();
4623 /* machhwu - machhwu. - machhwuo - machhwuo. */
4624 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
4625 /* mulhhwu - mulhhwu. */
4626 gen_op_405_mulhhwu();
4629 /* maclhw - maclhw. - maclhwo - maclhwo. */
4630 /* maclhws - maclhws. - maclhwso - maclhwso. */
4631 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
4632 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
4633 /* mullhw - mullhw. */
4634 gen_op_405_mullhw();
4637 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
4638 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
4639 /* mullhwu - mullhwu. */
4640 gen_op_405_mullhwu();
4644 /* nmultiply-and-accumulate (0x0E) */
4648 /* (n)multiply-and-accumulate (0x0C - 0x0E) */
4649 gen_op_load_gpr_T2(rt);
4650 gen_op_move_T1_T0();
4651 gen_op_405_add_T0_T2();
4654 /* Check overflow */
4656 gen_op_check_addo();
4658 gen_op_405_check_ovu();
4663 gen_op_405_check_sat();
4665 gen_op_405_check_satu();
4667 gen_op_store_T0_gpr(rt);
4668 if (unlikely(Rc) != 0) {
4674 #define GEN_MAC_HANDLER(name, opc2, opc3) \
4675 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
4677 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
4678 rD(ctx->opcode), Rc(ctx->opcode)); \
4681 /* macchw - macchw. */
4682 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
4683 /* macchwo - macchwo. */
4684 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
4685 /* macchws - macchws. */
4686 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
4687 /* macchwso - macchwso. */
4688 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
4689 /* macchwsu - macchwsu. */
4690 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
4691 /* macchwsuo - macchwsuo. */
4692 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
4693 /* macchwu - macchwu. */
4694 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
4695 /* macchwuo - macchwuo. */
4696 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
4697 /* machhw - machhw. */
4698 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
4699 /* machhwo - machhwo. */
4700 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
4701 /* machhws - machhws. */
4702 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
4703 /* machhwso - machhwso. */
4704 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
4705 /* machhwsu - machhwsu. */
4706 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
4707 /* machhwsuo - machhwsuo. */
4708 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
4709 /* machhwu - machhwu. */
4710 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
4711 /* machhwuo - machhwuo. */
4712 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
4713 /* maclhw - maclhw. */
4714 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
4715 /* maclhwo - maclhwo. */
4716 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
4717 /* maclhws - maclhws. */
4718 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
4719 /* maclhwso - maclhwso. */
4720 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
4721 /* maclhwu - maclhwu. */
4722 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
4723 /* maclhwuo - maclhwuo. */
4724 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
4725 /* maclhwsu - maclhwsu. */
4726 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
4727 /* maclhwsuo - maclhwsuo. */
4728 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
4729 /* nmacchw - nmacchw. */
4730 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
4731 /* nmacchwo - nmacchwo. */
4732 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
4733 /* nmacchws - nmacchws. */
4734 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
4735 /* nmacchwso - nmacchwso. */
4736 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
4737 /* nmachhw - nmachhw. */
4738 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
4739 /* nmachhwo - nmachhwo. */
4740 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
4741 /* nmachhws - nmachhws. */
4742 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
4743 /* nmachhwso - nmachhwso. */
4744 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
4745 /* nmaclhw - nmaclhw. */
4746 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
4747 /* nmaclhwo - nmaclhwo. */
4748 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
4749 /* nmaclhws - nmaclhws. */
4750 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
4751 /* nmaclhwso - nmaclhwso. */
4752 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
4754 /* mulchw - mulchw. */
4755 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
4756 /* mulchwu - mulchwu. */
4757 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
4758 /* mulhhw - mulhhw. */
4759 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
4760 /* mulhhwu - mulhhwu. */
4761 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
4762 /* mullhw - mullhw. */
4763 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
4764 /* mullhwu - mullhwu. */
4765 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
4768 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
4770 #if defined(CONFIG_USER_ONLY)
4771 GEN_EXCP_PRIVREG(ctx);
4773 uint32_t dcrn = SPR(ctx->opcode);
4775 if (unlikely(!ctx->supervisor)) {
4776 GEN_EXCP_PRIVREG(ctx);
4779 gen_op_set_T0(dcrn);
4781 gen_op_store_T0_gpr(rD(ctx->opcode));
4786 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
4788 #if defined(CONFIG_USER_ONLY)
4789 GEN_EXCP_PRIVREG(ctx);
4791 uint32_t dcrn = SPR(ctx->opcode);
4793 if (unlikely(!ctx->supervisor)) {
4794 GEN_EXCP_PRIVREG(ctx);
4797 gen_op_set_T0(dcrn);
4798 gen_op_load_gpr_T1(rS(ctx->opcode));
4804 /* XXX: not implemented on 440 ? */
4805 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
4807 #if defined(CONFIG_USER_ONLY)
4808 GEN_EXCP_PRIVREG(ctx);
4810 if (unlikely(!ctx->supervisor)) {
4811 GEN_EXCP_PRIVREG(ctx);
4814 gen_op_load_gpr_T0(rA(ctx->opcode));
4816 gen_op_store_T0_gpr(rD(ctx->opcode));
4817 /* Note: Rc update flag set leads to undefined state of Rc0 */
4822 /* XXX: not implemented on 440 ? */
4823 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
4825 #if defined(CONFIG_USER_ONLY)
4826 GEN_EXCP_PRIVREG(ctx);
4828 if (unlikely(!ctx->supervisor)) {
4829 GEN_EXCP_PRIVREG(ctx);
4832 gen_op_load_gpr_T0(rA(ctx->opcode));
4833 gen_op_load_gpr_T1(rS(ctx->opcode));
4835 /* Note: Rc update flag set leads to undefined state of Rc0 */
4839 /* mfdcrux (PPC 460) : user-mode access to DCR */
4840 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
4842 gen_op_load_gpr_T0(rA(ctx->opcode));
4844 gen_op_store_T0_gpr(rD(ctx->opcode));
4845 /* Note: Rc update flag set leads to undefined state of Rc0 */
4848 /* mtdcrux (PPC 460) : user-mode access to DCR */
4849 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
4851 gen_op_load_gpr_T0(rA(ctx->opcode));
4852 gen_op_load_gpr_T1(rS(ctx->opcode));
4854 /* Note: Rc update flag set leads to undefined state of Rc0 */
4858 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
4860 #if defined(CONFIG_USER_ONLY)
4861 GEN_EXCP_PRIVOPC(ctx);
4863 if (unlikely(!ctx->supervisor)) {
4864 GEN_EXCP_PRIVOPC(ctx);
4867 /* interpreted as no-op */
4872 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
4874 #if defined(CONFIG_USER_ONLY)
4875 GEN_EXCP_PRIVOPC(ctx);
4877 if (unlikely(!ctx->supervisor)) {
4878 GEN_EXCP_PRIVOPC(ctx);
4881 gen_addr_reg_index(ctx);
4883 gen_op_store_T0_gpr(rD(ctx->opcode));
4888 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
4890 /* interpreted as no-op */
4891 /* XXX: specification say this is treated as a load by the MMU
4892 * but does not generate any exception
4897 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
4899 #if defined(CONFIG_USER_ONLY)
4900 GEN_EXCP_PRIVOPC(ctx);
4902 if (unlikely(!ctx->supervisor)) {
4903 GEN_EXCP_PRIVOPC(ctx);
4906 /* interpreted as no-op */
4911 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
4913 #if defined(CONFIG_USER_ONLY)
4914 GEN_EXCP_PRIVOPC(ctx);
4916 if (unlikely(!ctx->supervisor)) {
4917 GEN_EXCP_PRIVOPC(ctx);
4920 /* interpreted as no-op */
4924 /* rfci (supervisor only) */
4925 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
4927 #if defined(CONFIG_USER_ONLY)
4928 GEN_EXCP_PRIVOPC(ctx);
4930 if (unlikely(!ctx->supervisor)) {
4931 GEN_EXCP_PRIVOPC(ctx);
4934 /* Restore CPU state */
4940 GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
4942 #if defined(CONFIG_USER_ONLY)
4943 GEN_EXCP_PRIVOPC(ctx);
4945 if (unlikely(!ctx->supervisor)) {
4946 GEN_EXCP_PRIVOPC(ctx);
4949 /* Restore CPU state */
4955 /* BookE specific */
4956 /* XXX: not implemented on 440 ? */
4957 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)
4959 #if defined(CONFIG_USER_ONLY)
4960 GEN_EXCP_PRIVOPC(ctx);
4962 if (unlikely(!ctx->supervisor)) {
4963 GEN_EXCP_PRIVOPC(ctx);
4966 /* Restore CPU state */
4972 /* XXX: not implemented on 440 ? */
4973 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
4975 #if defined(CONFIG_USER_ONLY)
4976 GEN_EXCP_PRIVOPC(ctx);
4978 if (unlikely(!ctx->supervisor)) {
4979 GEN_EXCP_PRIVOPC(ctx);
4982 /* Restore CPU state */
4988 /* TLB management - PowerPC 405 implementation */
4990 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
4992 #if defined(CONFIG_USER_ONLY)
4993 GEN_EXCP_PRIVOPC(ctx);
4995 if (unlikely(!ctx->supervisor)) {
4996 GEN_EXCP_PRIVOPC(ctx);
4999 switch (rB(ctx->opcode)) {
5001 gen_op_load_gpr_T0(rA(ctx->opcode));
5002 gen_op_4xx_tlbre_hi();
5003 gen_op_store_T0_gpr(rD(ctx->opcode));
5006 gen_op_load_gpr_T0(rA(ctx->opcode));
5007 gen_op_4xx_tlbre_lo();
5008 gen_op_store_T0_gpr(rD(ctx->opcode));
5011 GEN_EXCP_INVAL(ctx);
5017 /* tlbsx - tlbsx. */
5018 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
5020 #if defined(CONFIG_USER_ONLY)
5021 GEN_EXCP_PRIVOPC(ctx);
5023 if (unlikely(!ctx->supervisor)) {
5024 GEN_EXCP_PRIVOPC(ctx);
5027 gen_addr_reg_index(ctx);
5029 if (Rc(ctx->opcode))
5030 gen_op_4xx_tlbsx_check();
5031 gen_op_store_T0_gpr(rD(ctx->opcode));
5036 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
5038 #if defined(CONFIG_USER_ONLY)
5039 GEN_EXCP_PRIVOPC(ctx);
5041 if (unlikely(!ctx->supervisor)) {
5042 GEN_EXCP_PRIVOPC(ctx);
5045 switch (rB(ctx->opcode)) {
5047 gen_op_load_gpr_T0(rA(ctx->opcode));
5048 gen_op_load_gpr_T1(rS(ctx->opcode));
5049 gen_op_4xx_tlbwe_hi();
5052 gen_op_load_gpr_T0(rA(ctx->opcode));
5053 gen_op_load_gpr_T1(rS(ctx->opcode));
5054 gen_op_4xx_tlbwe_lo();
5057 GEN_EXCP_INVAL(ctx);
5063 /* TLB management - PowerPC 440 implementation */
5065 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5067 #if defined(CONFIG_USER_ONLY)
5068 GEN_EXCP_PRIVOPC(ctx);
5070 if (unlikely(!ctx->supervisor)) {
5071 GEN_EXCP_PRIVOPC(ctx);
5074 switch (rB(ctx->opcode)) {
5078 gen_op_load_gpr_T0(rA(ctx->opcode));
5079 gen_op_440_tlbre(rB(ctx->opcode));
5080 gen_op_store_T0_gpr(rD(ctx->opcode));
5083 GEN_EXCP_INVAL(ctx);
5089 /* tlbsx - tlbsx. */
5090 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5092 #if defined(CONFIG_USER_ONLY)
5093 GEN_EXCP_PRIVOPC(ctx);
5095 if (unlikely(!ctx->supervisor)) {
5096 GEN_EXCP_PRIVOPC(ctx);
5099 gen_addr_reg_index(ctx);
5101 if (Rc(ctx->opcode))
5102 gen_op_4xx_tlbsx_check();
5103 gen_op_store_T0_gpr(rD(ctx->opcode));
5108 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5110 #if defined(CONFIG_USER_ONLY)
5111 GEN_EXCP_PRIVOPC(ctx);
5113 if (unlikely(!ctx->supervisor)) {
5114 GEN_EXCP_PRIVOPC(ctx);
5117 switch (rB(ctx->opcode)) {
5121 gen_op_load_gpr_T0(rA(ctx->opcode));
5122 gen_op_load_gpr_T1(rS(ctx->opcode));
5123 gen_op_440_tlbwe(rB(ctx->opcode));
5126 GEN_EXCP_INVAL(ctx);
5133 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
5135 #if defined(CONFIG_USER_ONLY)
5136 GEN_EXCP_PRIVOPC(ctx);
5138 if (unlikely(!ctx->supervisor)) {
5139 GEN_EXCP_PRIVOPC(ctx);
5142 gen_op_load_gpr_T0(rD(ctx->opcode));
5144 /* Stop translation to have a chance to raise an exception
5145 * if we just set msr_ee to 1
5152 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
5154 #if defined(CONFIG_USER_ONLY)
5155 GEN_EXCP_PRIVOPC(ctx);
5157 if (unlikely(!ctx->supervisor)) {
5158 GEN_EXCP_PRIVOPC(ctx);
5161 gen_op_set_T0(ctx->opcode & 0x00010000);
5163 /* Stop translation to have a chance to raise an exception
5164 * if we just set msr_ee to 1
5170 /* PowerPC 440 specific instructions */
5172 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
5174 gen_op_load_gpr_T0(rS(ctx->opcode));
5175 gen_op_load_gpr_T1(rB(ctx->opcode));
5177 gen_op_store_T0_gpr(rA(ctx->opcode));
5178 gen_op_store_xer_bc();
5179 if (Rc(ctx->opcode)) {
5180 gen_op_440_dlmzb_update_Rc();
5181 gen_op_store_T0_crf(0);
5185 /* mbar replaces eieio on 440 */
5186 GEN_HANDLER(mbar, 0x1F, 0x16, 0x13, 0x001FF801, PPC_BOOKE)
5188 /* interpreted as no-op */
5191 /* msync replaces sync on 440 */
5192 GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
5194 /* interpreted as no-op */
5198 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
5200 /* interpreted as no-op */
5201 /* XXX: specification say this is treated as a load by the MMU
5202 * but does not generate any exception
5206 /*** Altivec vector extension ***/
5207 /* Altivec registers moves */
5208 GEN32(gen_op_load_avr_A0, gen_op_load_avr_A0_avr);
5209 GEN32(gen_op_load_avr_A1, gen_op_load_avr_A1_avr);
5210 GEN32(gen_op_load_avr_A2, gen_op_load_avr_A2_avr);
5212 GEN32(gen_op_store_A0_avr, gen_op_store_A0_avr_avr);
5213 GEN32(gen_op_store_A1_avr, gen_op_store_A1_avr_avr);
5215 GEN32(gen_op_store_A2_avr, gen_op_store_A2_avr_avr);
5218 #define op_vr_ldst(name) (*gen_op_##name[ctx->mem_idx])()
5219 #define OP_VR_LD_TABLE(name) \
5220 static GenOpFunc *gen_op_vr_l##name[NB_MEM_FUNCS] = { \
5221 GEN_MEM_FUNCS(vr_l##name), \
5223 #define OP_VR_ST_TABLE(name) \
5224 static GenOpFunc *gen_op_vr_st##name[NB_MEM_FUNCS] = { \
5225 GEN_MEM_FUNCS(vr_st##name), \
5228 #define GEN_VR_LDX(name, opc2, opc3) \
5229 GEN_HANDLER(l##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5231 if (unlikely(!ctx->altivec_enabled)) { \
5232 GEN_EXCP_NO_VR(ctx); \
5235 gen_addr_reg_index(ctx); \
5236 op_vr_ldst(vr_l##name); \
5237 gen_op_store_A0_avr(rD(ctx->opcode)); \
5240 #define GEN_VR_STX(name, opc2, opc3) \
5241 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5243 if (unlikely(!ctx->altivec_enabled)) { \
5244 GEN_EXCP_NO_VR(ctx); \
5247 gen_addr_reg_index(ctx); \
5248 gen_op_load_avr_A0(rS(ctx->opcode)); \
5249 op_vr_ldst(vr_st##name); \
5253 GEN_VR_LDX(vx, 0x07, 0x03);
5254 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
5255 #define gen_op_vr_lvxl gen_op_vr_lvx
5256 GEN_VR_LDX(vxl, 0x07, 0x0B);
5259 GEN_VR_STX(vx, 0x07, 0x07);
5260 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
5261 #define gen_op_vr_stvxl gen_op_vr_stvx
5262 GEN_VR_STX(vxl, 0x07, 0x0F);
5264 /*** SPE extension ***/
5265 /* Register moves */
5266 #if !defined(TARGET_PPC64)
5268 GEN32(gen_op_load_gpr64_T0, gen_op_load_gpr64_T0_gpr);
5269 GEN32(gen_op_load_gpr64_T1, gen_op_load_gpr64_T1_gpr);
5271 GEN32(gen_op_load_gpr64_T2, gen_op_load_gpr64_T2_gpr);
5274 GEN32(gen_op_store_T0_gpr64, gen_op_store_T0_gpr64_gpr);
5275 GEN32(gen_op_store_T1_gpr64, gen_op_store_T1_gpr64_gpr);
5277 GEN32(gen_op_store_T2_gpr64, gen_op_store_T2_gpr64_gpr);
5280 #else /* !defined(TARGET_PPC64) */
5282 /* No specific load/store functions: GPRs are already 64 bits */
5283 #define gen_op_load_gpr64_T0 gen_op_load_gpr_T0
5284 #define gen_op_load_gpr64_T1 gen_op_load_gpr_T1
5286 #define gen_op_load_gpr64_T2 gen_op_load_gpr_T2
5289 #define gen_op_store_T0_gpr64 gen_op_store_T0_gpr
5290 #define gen_op_store_T1_gpr64 gen_op_store_T1_gpr
5292 #define gen_op_store_T2_gpr64 gen_op_store_T2_gpr
5295 #endif /* !defined(TARGET_PPC64) */
5297 #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
5298 GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
5300 if (Rc(ctx->opcode)) \
5306 /* Handler for undefined SPE opcodes */
5307 static always_inline void gen_speundef (DisasContext *ctx)
5309 GEN_EXCP_INVAL(ctx);
5312 /* SPE load and stores */
5313 static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, int sh)
5315 target_long simm = rB(ctx->opcode);
5317 if (rA(ctx->opcode) == 0) {
5318 tcg_gen_movi_tl(cpu_T[0], simm << sh);
5320 gen_op_load_gpr_T0(rA(ctx->opcode));
5321 if (likely(simm != 0))
5322 gen_op_addi(simm << sh);
5326 #define op_spe_ldst(name) (*gen_op_##name[ctx->mem_idx])()
5327 #define OP_SPE_LD_TABLE(name) \
5328 static GenOpFunc *gen_op_spe_l##name[NB_MEM_FUNCS] = { \
5329 GEN_MEM_FUNCS(spe_l##name), \
5331 #define OP_SPE_ST_TABLE(name) \
5332 static GenOpFunc *gen_op_spe_st##name[NB_MEM_FUNCS] = { \
5333 GEN_MEM_FUNCS(spe_st##name), \
5336 #define GEN_SPE_LD(name, sh) \
5337 static always_inline void gen_evl##name (DisasContext *ctx) \
5339 if (unlikely(!ctx->spe_enabled)) { \
5340 GEN_EXCP_NO_AP(ctx); \
5343 gen_addr_spe_imm_index(ctx, sh); \
5344 op_spe_ldst(spe_l##name); \
5345 gen_op_store_T1_gpr64(rD(ctx->opcode)); \
5348 #define GEN_SPE_LDX(name) \
5349 static always_inline void gen_evl##name##x (DisasContext *ctx) \
5351 if (unlikely(!ctx->spe_enabled)) { \
5352 GEN_EXCP_NO_AP(ctx); \
5355 gen_addr_reg_index(ctx); \
5356 op_spe_ldst(spe_l##name); \
5357 gen_op_store_T1_gpr64(rD(ctx->opcode)); \
5360 #define GEN_SPEOP_LD(name, sh) \
5361 OP_SPE_LD_TABLE(name); \
5362 GEN_SPE_LD(name, sh); \
5365 #define GEN_SPE_ST(name, sh) \
5366 static always_inline void gen_evst##name (DisasContext *ctx) \
5368 if (unlikely(!ctx->spe_enabled)) { \
5369 GEN_EXCP_NO_AP(ctx); \
5372 gen_addr_spe_imm_index(ctx, sh); \
5373 gen_op_load_gpr64_T1(rS(ctx->opcode)); \
5374 op_spe_ldst(spe_st##name); \
5377 #define GEN_SPE_STX(name) \
5378 static always_inline void gen_evst##name##x (DisasContext *ctx) \
5380 if (unlikely(!ctx->spe_enabled)) { \
5381 GEN_EXCP_NO_AP(ctx); \
5384 gen_addr_reg_index(ctx); \
5385 gen_op_load_gpr64_T1(rS(ctx->opcode)); \
5386 op_spe_ldst(spe_st##name); \
5389 #define GEN_SPEOP_ST(name, sh) \
5390 OP_SPE_ST_TABLE(name); \
5391 GEN_SPE_ST(name, sh); \
5394 #define GEN_SPEOP_LDST(name, sh) \
5395 GEN_SPEOP_LD(name, sh); \
5396 GEN_SPEOP_ST(name, sh)
5398 /* SPE arithmetic and logic */
5399 #define GEN_SPEOP_ARITH2(name) \
5400 static always_inline void gen_##name (DisasContext *ctx) \
5402 if (unlikely(!ctx->spe_enabled)) { \
5403 GEN_EXCP_NO_AP(ctx); \
5406 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
5407 gen_op_load_gpr64_T1(rB(ctx->opcode)); \
5409 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
5412 #define GEN_SPEOP_ARITH1(name) \
5413 static always_inline void gen_##name (DisasContext *ctx) \
5415 if (unlikely(!ctx->spe_enabled)) { \
5416 GEN_EXCP_NO_AP(ctx); \
5419 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
5421 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
5424 #define GEN_SPEOP_COMP(name) \
5425 static always_inline void gen_##name (DisasContext *ctx) \
5427 if (unlikely(!ctx->spe_enabled)) { \
5428 GEN_EXCP_NO_AP(ctx); \
5431 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
5432 gen_op_load_gpr64_T1(rB(ctx->opcode)); \
5434 gen_op_store_T0_crf(crfD(ctx->opcode)); \
5438 GEN_SPEOP_ARITH2(evand);
5439 GEN_SPEOP_ARITH2(evandc);
5440 GEN_SPEOP_ARITH2(evxor);
5441 GEN_SPEOP_ARITH2(evor);
5442 GEN_SPEOP_ARITH2(evnor);
5443 GEN_SPEOP_ARITH2(eveqv);
5444 GEN_SPEOP_ARITH2(evorc);
5445 GEN_SPEOP_ARITH2(evnand);
5446 GEN_SPEOP_ARITH2(evsrwu);
5447 GEN_SPEOP_ARITH2(evsrws);
5448 GEN_SPEOP_ARITH2(evslw);
5449 GEN_SPEOP_ARITH2(evrlw);
5450 GEN_SPEOP_ARITH2(evmergehi);
5451 GEN_SPEOP_ARITH2(evmergelo);
5452 GEN_SPEOP_ARITH2(evmergehilo);
5453 GEN_SPEOP_ARITH2(evmergelohi);
5456 GEN_SPEOP_ARITH2(evaddw);
5457 GEN_SPEOP_ARITH2(evsubfw);
5458 GEN_SPEOP_ARITH1(evabs);
5459 GEN_SPEOP_ARITH1(evneg);
5460 GEN_SPEOP_ARITH1(evextsb);
5461 GEN_SPEOP_ARITH1(evextsh);
5462 GEN_SPEOP_ARITH1(evrndw);
5463 GEN_SPEOP_ARITH1(evcntlzw);
5464 GEN_SPEOP_ARITH1(evcntlsw);
5465 static always_inline void gen_brinc (DisasContext *ctx)
5467 /* Note: brinc is usable even if SPE is disabled */
5468 gen_op_load_gpr_T0(rA(ctx->opcode));
5469 gen_op_load_gpr_T1(rB(ctx->opcode));
5471 gen_op_store_T0_gpr(rD(ctx->opcode));
5474 #define GEN_SPEOP_ARITH_IMM2(name) \
5475 static always_inline void gen_##name##i (DisasContext *ctx) \
5477 if (unlikely(!ctx->spe_enabled)) { \
5478 GEN_EXCP_NO_AP(ctx); \
5481 gen_op_load_gpr64_T0(rB(ctx->opcode)); \
5482 gen_op_splatwi_T1_64(rA(ctx->opcode)); \
5484 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
5487 #define GEN_SPEOP_LOGIC_IMM2(name) \
5488 static always_inline void gen_##name##i (DisasContext *ctx) \
5490 if (unlikely(!ctx->spe_enabled)) { \
5491 GEN_EXCP_NO_AP(ctx); \
5494 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
5495 gen_op_splatwi_T1_64(rB(ctx->opcode)); \
5497 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
5500 GEN_SPEOP_ARITH_IMM2(evaddw);
5501 #define gen_evaddiw gen_evaddwi
5502 GEN_SPEOP_ARITH_IMM2(evsubfw);
5503 #define gen_evsubifw gen_evsubfwi
5504 GEN_SPEOP_LOGIC_IMM2(evslw);
5505 GEN_SPEOP_LOGIC_IMM2(evsrwu);
5506 #define gen_evsrwis gen_evsrwsi
5507 GEN_SPEOP_LOGIC_IMM2(evsrws);
5508 #define gen_evsrwiu gen_evsrwui
5509 GEN_SPEOP_LOGIC_IMM2(evrlw);
5511 static always_inline void gen_evsplati (DisasContext *ctx)
5513 int32_t imm = (int32_t)(rA(ctx->opcode) << 27) >> 27;
5515 gen_op_splatwi_T0_64(imm);
5516 gen_op_store_T0_gpr64(rD(ctx->opcode));
5519 static always_inline void gen_evsplatfi (DisasContext *ctx)
5521 uint32_t imm = rA(ctx->opcode) << 27;
5523 gen_op_splatwi_T0_64(imm);
5524 gen_op_store_T0_gpr64(rD(ctx->opcode));
5528 GEN_SPEOP_COMP(evcmpgtu);
5529 GEN_SPEOP_COMP(evcmpgts);
5530 GEN_SPEOP_COMP(evcmpltu);
5531 GEN_SPEOP_COMP(evcmplts);
5532 GEN_SPEOP_COMP(evcmpeq);
5534 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
5535 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
5536 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
5537 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
5538 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
5539 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
5540 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
5541 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
5542 GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
5543 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
5544 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
5545 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
5546 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
5547 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
5548 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
5549 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
5550 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
5551 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
5552 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
5553 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
5554 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
5555 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
5556 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
5557 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
5558 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
5560 static always_inline void gen_evsel (DisasContext *ctx)
5562 if (unlikely(!ctx->spe_enabled)) {
5563 GEN_EXCP_NO_AP(ctx);
5566 gen_op_load_crf_T0(ctx->opcode & 0x7);
5567 gen_op_load_gpr64_T0(rA(ctx->opcode));
5568 gen_op_load_gpr64_T1(rB(ctx->opcode));
5570 gen_op_store_T0_gpr64(rD(ctx->opcode));
5573 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
5577 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
5581 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
5585 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
5590 /* Load and stores */
5591 #if defined(TARGET_PPC64)
5592 /* In that case, we already have 64 bits load & stores
5593 * so, spe_ldd is equivalent to ld and spe_std is equivalent to std
5595 #define gen_op_spe_ldd_raw gen_op_ld_raw
5596 #define gen_op_spe_ldd_user gen_op_ld_user
5597 #define gen_op_spe_ldd_kernel gen_op_ld_kernel
5598 #define gen_op_spe_ldd_hypv gen_op_ld_hypv
5599 #define gen_op_spe_ldd_64_raw gen_op_ld_64_raw
5600 #define gen_op_spe_ldd_64_user gen_op_ld_64_user
5601 #define gen_op_spe_ldd_64_kernel gen_op_ld_64_kernel
5602 #define gen_op_spe_ldd_64_hypv gen_op_ld_64_hypv
5603 #define gen_op_spe_ldd_le_raw gen_op_ld_le_raw
5604 #define gen_op_spe_ldd_le_user gen_op_ld_le_user
5605 #define gen_op_spe_ldd_le_kernel gen_op_ld_le_kernel
5606 #define gen_op_spe_ldd_le_hypv gen_op_ld_le_hypv
5607 #define gen_op_spe_ldd_le_64_raw gen_op_ld_le_64_raw
5608 #define gen_op_spe_ldd_le_64_user gen_op_ld_le_64_user
5609 #define gen_op_spe_ldd_le_64_kernel gen_op_ld_le_64_kernel
5610 #define gen_op_spe_ldd_le_64_hypv gen_op_ld_le_64_hypv
5611 #define gen_op_spe_stdd_raw gen_op_std_raw
5612 #define gen_op_spe_stdd_user gen_op_std_user
5613 #define gen_op_spe_stdd_kernel gen_op_std_kernel
5614 #define gen_op_spe_stdd_hypv gen_op_std_hypv
5615 #define gen_op_spe_stdd_64_raw gen_op_std_64_raw
5616 #define gen_op_spe_stdd_64_user gen_op_std_64_user
5617 #define gen_op_spe_stdd_64_kernel gen_op_std_64_kernel
5618 #define gen_op_spe_stdd_64_hypv gen_op_std_64_hypv
5619 #define gen_op_spe_stdd_le_raw gen_op_std_le_raw
5620 #define gen_op_spe_stdd_le_user gen_op_std_le_user
5621 #define gen_op_spe_stdd_le_kernel gen_op_std_le_kernel
5622 #define gen_op_spe_stdd_le_hypv gen_op_std_le_hypv
5623 #define gen_op_spe_stdd_le_64_raw gen_op_std_le_64_raw
5624 #define gen_op_spe_stdd_le_64_user gen_op_std_le_64_user
5625 #define gen_op_spe_stdd_le_64_kernel gen_op_std_le_64_kernel
5626 #define gen_op_spe_stdd_le_64_hypv gen_op_std_le_64_hypv
5627 #endif /* defined(TARGET_PPC64) */
5628 GEN_SPEOP_LDST(dd, 3);
5629 GEN_SPEOP_LDST(dw, 3);
5630 GEN_SPEOP_LDST(dh, 3);
5631 GEN_SPEOP_LDST(whe, 2);
5632 GEN_SPEOP_LD(whou, 2);
5633 GEN_SPEOP_LD(whos, 2);
5634 GEN_SPEOP_ST(who, 2);
5636 #if defined(TARGET_PPC64)
5637 /* In that case, spe_stwwo is equivalent to stw */
5638 #define gen_op_spe_stwwo_raw gen_op_stw_raw
5639 #define gen_op_spe_stwwo_user gen_op_stw_user
5640 #define gen_op_spe_stwwo_kernel gen_op_stw_kernel
5641 #define gen_op_spe_stwwo_hypv gen_op_stw_hypv
5642 #define gen_op_spe_stwwo_le_raw gen_op_stw_le_raw
5643 #define gen_op_spe_stwwo_le_user gen_op_stw_le_user
5644 #define gen_op_spe_stwwo_le_kernel gen_op_stw_le_kernel
5645 #define gen_op_spe_stwwo_le_hypv gen_op_stw_le_hypv
5646 #define gen_op_spe_stwwo_64_raw gen_op_stw_64_raw
5647 #define gen_op_spe_stwwo_64_user gen_op_stw_64_user
5648 #define gen_op_spe_stwwo_64_kernel gen_op_stw_64_kernel
5649 #define gen_op_spe_stwwo_64_hypv gen_op_stw_64_hypv
5650 #define gen_op_spe_stwwo_le_64_raw gen_op_stw_le_64_raw
5651 #define gen_op_spe_stwwo_le_64_user gen_op_stw_le_64_user
5652 #define gen_op_spe_stwwo_le_64_kernel gen_op_stw_le_64_kernel
5653 #define gen_op_spe_stwwo_le_64_hypv gen_op_stw_le_64_hypv
5655 #define _GEN_OP_SPE_STWWE(suffix) \
5656 static always_inline void gen_op_spe_stwwe_##suffix (void) \
5658 gen_op_srli32_T1_64(); \
5659 gen_op_spe_stwwo_##suffix(); \
5661 #define _GEN_OP_SPE_STWWE_LE(suffix) \
5662 static always_inline void gen_op_spe_stwwe_le_##suffix (void) \
5664 gen_op_srli32_T1_64(); \
5665 gen_op_spe_stwwo_le_##suffix(); \
5667 #if defined(TARGET_PPC64)
5668 #define GEN_OP_SPE_STWWE(suffix) \
5669 _GEN_OP_SPE_STWWE(suffix); \
5670 _GEN_OP_SPE_STWWE_LE(suffix); \
5671 static always_inline void gen_op_spe_stwwe_64_##suffix (void) \
5673 gen_op_srli32_T1_64(); \
5674 gen_op_spe_stwwo_64_##suffix(); \
5676 static always_inline void gen_op_spe_stwwe_le_64_##suffix (void) \
5678 gen_op_srli32_T1_64(); \
5679 gen_op_spe_stwwo_le_64_##suffix(); \
5682 #define GEN_OP_SPE_STWWE(suffix) \
5683 _GEN_OP_SPE_STWWE(suffix); \
5684 _GEN_OP_SPE_STWWE_LE(suffix)
5686 #if defined(CONFIG_USER_ONLY)
5687 GEN_OP_SPE_STWWE(raw);
5688 #else /* defined(CONFIG_USER_ONLY) */
5689 GEN_OP_SPE_STWWE(user);
5690 GEN_OP_SPE_STWWE(kernel);
5691 GEN_OP_SPE_STWWE(hypv);
5692 #endif /* defined(CONFIG_USER_ONLY) */
5693 GEN_SPEOP_ST(wwe, 2);
5694 GEN_SPEOP_ST(wwo, 2);
5696 #define GEN_SPE_LDSPLAT(name, op, suffix) \
5697 static always_inline void gen_op_spe_l##name##_##suffix (void) \
5699 gen_op_##op##_##suffix(); \
5700 gen_op_splatw_T1_64(); \
5703 #define GEN_OP_SPE_LHE(suffix) \
5704 static always_inline void gen_op_spe_lhe_##suffix (void) \
5706 gen_op_spe_lh_##suffix(); \
5707 gen_op_sli16_T1_64(); \
5710 #define GEN_OP_SPE_LHX(suffix) \
5711 static always_inline void gen_op_spe_lhx_##suffix (void) \
5713 gen_op_spe_lh_##suffix(); \
5714 gen_op_extsh_T1_64(); \
5717 #if defined(CONFIG_USER_ONLY)
5718 GEN_OP_SPE_LHE(raw);
5719 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, raw);
5720 GEN_OP_SPE_LHE(le_raw);
5721 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_raw);
5722 GEN_SPE_LDSPLAT(hhousplat, spe_lh, raw);
5723 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_raw);
5724 GEN_OP_SPE_LHX(raw);
5725 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, raw);
5726 GEN_OP_SPE_LHX(le_raw);
5727 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_raw);
5728 #if defined(TARGET_PPC64)
5729 GEN_OP_SPE_LHE(64_raw);
5730 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_raw);
5731 GEN_OP_SPE_LHE(le_64_raw);
5732 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_raw);
5733 GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_raw);
5734 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_raw);
5735 GEN_OP_SPE_LHX(64_raw);
5736 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_raw);
5737 GEN_OP_SPE_LHX(le_64_raw);
5738 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_raw);
5741 GEN_OP_SPE_LHE(user);
5742 GEN_OP_SPE_LHE(kernel);
5743 GEN_OP_SPE_LHE(hypv);
5744 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, user);
5745 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, kernel);
5746 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, hypv);
5747 GEN_OP_SPE_LHE(le_user);
5748 GEN_OP_SPE_LHE(le_kernel);
5749 GEN_OP_SPE_LHE(le_hypv);
5750 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_user);
5751 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_kernel);
5752 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_hypv);
5753 GEN_SPE_LDSPLAT(hhousplat, spe_lh, user);
5754 GEN_SPE_LDSPLAT(hhousplat, spe_lh, kernel);
5755 GEN_SPE_LDSPLAT(hhousplat, spe_lh, hypv);
5756 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_user);
5757 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_kernel);
5758 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_hypv);
5759 GEN_OP_SPE_LHX(user);
5760 GEN_OP_SPE_LHX(kernel);
5761 GEN_OP_SPE_LHX(hypv);
5762 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, user);
5763 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, kernel);
5764 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, hypv);
5765 GEN_OP_SPE_LHX(le_user);
5766 GEN_OP_SPE_LHX(le_kernel);
5767 GEN_OP_SPE_LHX(le_hypv);
5768 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_user);
5769 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_kernel);
5770 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_hypv);
5771 #if defined(TARGET_PPC64)
5772 GEN_OP_SPE_LHE(64_user);
5773 GEN_OP_SPE_LHE(64_kernel);
5774 GEN_OP_SPE_LHE(64_hypv);
5775 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_user);
5776 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_kernel);
5777 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_hypv);
5778 GEN_OP_SPE_LHE(le_64_user);
5779 GEN_OP_SPE_LHE(le_64_kernel);
5780 GEN_OP_SPE_LHE(le_64_hypv);
5781 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_user);
5782 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_kernel);
5783 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_hypv);
5784 GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_user);
5785 GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_kernel);
5786 GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_hypv);
5787 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_user);
5788 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_kernel);
5789 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_hypv);
5790 GEN_OP_SPE_LHX(64_user);
5791 GEN_OP_SPE_LHX(64_kernel);
5792 GEN_OP_SPE_LHX(64_hypv);
5793 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_user);
5794 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_kernel);
5795 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_hypv);
5796 GEN_OP_SPE_LHX(le_64_user);
5797 GEN_OP_SPE_LHX(le_64_kernel);
5798 GEN_OP_SPE_LHX(le_64_hypv);
5799 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_user);
5800 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_kernel);
5801 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_hypv);
5804 GEN_SPEOP_LD(hhesplat, 1);
5805 GEN_SPEOP_LD(hhousplat, 1);
5806 GEN_SPEOP_LD(hhossplat, 1);
5807 GEN_SPEOP_LD(wwsplat, 2);
5808 GEN_SPEOP_LD(whsplat, 2);
5810 GEN_SPE(evlddx, evldd, 0x00, 0x0C, 0x00000000, PPC_SPE); //
5811 GEN_SPE(evldwx, evldw, 0x01, 0x0C, 0x00000000, PPC_SPE); //
5812 GEN_SPE(evldhx, evldh, 0x02, 0x0C, 0x00000000, PPC_SPE); //
5813 GEN_SPE(evlhhesplatx, evlhhesplat, 0x04, 0x0C, 0x00000000, PPC_SPE); //
5814 GEN_SPE(evlhhousplatx, evlhhousplat, 0x06, 0x0C, 0x00000000, PPC_SPE); //
5815 GEN_SPE(evlhhossplatx, evlhhossplat, 0x07, 0x0C, 0x00000000, PPC_SPE); //
5816 GEN_SPE(evlwhex, evlwhe, 0x08, 0x0C, 0x00000000, PPC_SPE); //
5817 GEN_SPE(evlwhoux, evlwhou, 0x0A, 0x0C, 0x00000000, PPC_SPE); //
5818 GEN_SPE(evlwhosx, evlwhos, 0x0B, 0x0C, 0x00000000, PPC_SPE); //
5819 GEN_SPE(evlwwsplatx, evlwwsplat, 0x0C, 0x0C, 0x00000000, PPC_SPE); //
5820 GEN_SPE(evlwhsplatx, evlwhsplat, 0x0E, 0x0C, 0x00000000, PPC_SPE); //
5821 GEN_SPE(evstddx, evstdd, 0x10, 0x0C, 0x00000000, PPC_SPE); //
5822 GEN_SPE(evstdwx, evstdw, 0x11, 0x0C, 0x00000000, PPC_SPE); //
5823 GEN_SPE(evstdhx, evstdh, 0x12, 0x0C, 0x00000000, PPC_SPE); //
5824 GEN_SPE(evstwhex, evstwhe, 0x18, 0x0C, 0x00000000, PPC_SPE); //
5825 GEN_SPE(evstwhox, evstwho, 0x1A, 0x0C, 0x00000000, PPC_SPE); //
5826 GEN_SPE(evstwwex, evstwwe, 0x1C, 0x0C, 0x00000000, PPC_SPE); //
5827 GEN_SPE(evstwwox, evstwwo, 0x1E, 0x0C, 0x00000000, PPC_SPE); //
5829 /* Multiply and add - TODO */
5831 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
5832 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
5833 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
5834 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
5835 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
5836 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
5837 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
5838 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
5839 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
5840 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
5841 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
5842 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
5844 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
5845 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
5846 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
5847 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
5848 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
5849 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
5850 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
5851 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
5852 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
5853 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
5854 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
5855 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
5856 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
5857 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
5859 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
5860 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
5861 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
5862 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
5863 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
5864 GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
5866 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
5867 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
5868 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
5869 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
5870 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
5871 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
5872 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
5873 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
5874 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
5875 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
5876 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
5877 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
5879 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
5880 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
5881 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
5882 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
5883 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
5885 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
5886 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
5887 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
5888 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
5889 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
5890 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
5891 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
5892 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
5893 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
5894 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
5895 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
5896 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
5898 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
5899 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
5900 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
5901 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
5902 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
5905 /*** SPE floating-point extension ***/
5906 #define GEN_SPEFPUOP_CONV(name) \
5907 static always_inline void gen_##name (DisasContext *ctx) \
5909 gen_op_load_gpr64_T0(rB(ctx->opcode)); \
5911 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
5914 /* Single precision floating-point vectors operations */
5916 GEN_SPEOP_ARITH2(evfsadd);
5917 GEN_SPEOP_ARITH2(evfssub);
5918 GEN_SPEOP_ARITH2(evfsmul);
5919 GEN_SPEOP_ARITH2(evfsdiv);
5920 GEN_SPEOP_ARITH1(evfsabs);
5921 GEN_SPEOP_ARITH1(evfsnabs);
5922 GEN_SPEOP_ARITH1(evfsneg);
5924 GEN_SPEFPUOP_CONV(evfscfui);
5925 GEN_SPEFPUOP_CONV(evfscfsi);
5926 GEN_SPEFPUOP_CONV(evfscfuf);
5927 GEN_SPEFPUOP_CONV(evfscfsf);
5928 GEN_SPEFPUOP_CONV(evfsctui);
5929 GEN_SPEFPUOP_CONV(evfsctsi);
5930 GEN_SPEFPUOP_CONV(evfsctuf);
5931 GEN_SPEFPUOP_CONV(evfsctsf);
5932 GEN_SPEFPUOP_CONV(evfsctuiz);
5933 GEN_SPEFPUOP_CONV(evfsctsiz);
5935 GEN_SPEOP_COMP(evfscmpgt);
5936 GEN_SPEOP_COMP(evfscmplt);
5937 GEN_SPEOP_COMP(evfscmpeq);
5938 GEN_SPEOP_COMP(evfststgt);
5939 GEN_SPEOP_COMP(evfststlt);
5940 GEN_SPEOP_COMP(evfststeq);
5942 /* Opcodes definitions */
5943 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
5944 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPEFPU); //
5945 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPEFPU); //
5946 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPEFPU); //
5947 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPEFPU); //
5948 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPEFPU); //
5949 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPEFPU); //
5950 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPEFPU); //
5951 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPEFPU); //
5952 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPEFPU); //
5953 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPEFPU); //
5954 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPEFPU); //
5955 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPEFPU); //
5956 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPEFPU); //
5958 /* Single precision floating-point operations */
5960 GEN_SPEOP_ARITH2(efsadd);
5961 GEN_SPEOP_ARITH2(efssub);
5962 GEN_SPEOP_ARITH2(efsmul);
5963 GEN_SPEOP_ARITH2(efsdiv);
5964 GEN_SPEOP_ARITH1(efsabs);
5965 GEN_SPEOP_ARITH1(efsnabs);
5966 GEN_SPEOP_ARITH1(efsneg);
5968 GEN_SPEFPUOP_CONV(efscfui);
5969 GEN_SPEFPUOP_CONV(efscfsi);
5970 GEN_SPEFPUOP_CONV(efscfuf);
5971 GEN_SPEFPUOP_CONV(efscfsf);
5972 GEN_SPEFPUOP_CONV(efsctui);
5973 GEN_SPEFPUOP_CONV(efsctsi);
5974 GEN_SPEFPUOP_CONV(efsctuf);
5975 GEN_SPEFPUOP_CONV(efsctsf);
5976 GEN_SPEFPUOP_CONV(efsctuiz);
5977 GEN_SPEFPUOP_CONV(efsctsiz);
5978 GEN_SPEFPUOP_CONV(efscfd);
5980 GEN_SPEOP_COMP(efscmpgt);
5981 GEN_SPEOP_COMP(efscmplt);
5982 GEN_SPEOP_COMP(efscmpeq);
5983 GEN_SPEOP_COMP(efststgt);
5984 GEN_SPEOP_COMP(efststlt);
5985 GEN_SPEOP_COMP(efststeq);
5987 /* Opcodes definitions */
5988 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPEFPU); //
5989 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU); //
5990 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU); //
5991 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPEFPU); //
5992 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPEFPU); //
5993 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPEFPU); //
5994 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPEFPU); //
5995 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPEFPU); //
5996 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPEFPU); //
5997 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPEFPU); //
5998 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU); //
5999 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPEFPU); //
6000 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPEFPU); //
6001 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPEFPU); //
6003 /* Double precision floating-point operations */
6005 GEN_SPEOP_ARITH2(efdadd);
6006 GEN_SPEOP_ARITH2(efdsub);
6007 GEN_SPEOP_ARITH2(efdmul);
6008 GEN_SPEOP_ARITH2(efddiv);
6009 GEN_SPEOP_ARITH1(efdabs);
6010 GEN_SPEOP_ARITH1(efdnabs);
6011 GEN_SPEOP_ARITH1(efdneg);
6014 GEN_SPEFPUOP_CONV(efdcfui);
6015 GEN_SPEFPUOP_CONV(efdcfsi);
6016 GEN_SPEFPUOP_CONV(efdcfuf);
6017 GEN_SPEFPUOP_CONV(efdcfsf);
6018 GEN_SPEFPUOP_CONV(efdctui);
6019 GEN_SPEFPUOP_CONV(efdctsi);
6020 GEN_SPEFPUOP_CONV(efdctuf);
6021 GEN_SPEFPUOP_CONV(efdctsf);
6022 GEN_SPEFPUOP_CONV(efdctuiz);
6023 GEN_SPEFPUOP_CONV(efdctsiz);
6024 GEN_SPEFPUOP_CONV(efdcfs);
6025 GEN_SPEFPUOP_CONV(efdcfuid);
6026 GEN_SPEFPUOP_CONV(efdcfsid);
6027 GEN_SPEFPUOP_CONV(efdctuidz);
6028 GEN_SPEFPUOP_CONV(efdctsidz);
6030 GEN_SPEOP_COMP(efdcmpgt);
6031 GEN_SPEOP_COMP(efdcmplt);
6032 GEN_SPEOP_COMP(efdcmpeq);
6033 GEN_SPEOP_COMP(efdtstgt);
6034 GEN_SPEOP_COMP(efdtstlt);
6035 GEN_SPEOP_COMP(efdtsteq);
6037 /* Opcodes definitions */
6038 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPEFPU); //
6039 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPEFPU); //
6040 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPEFPU); //
6041 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPEFPU); //
6042 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPEFPU); //
6043 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPEFPU); //
6044 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPEFPU); //
6045 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPEFPU); //
6046 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPEFPU); //
6047 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPEFPU); //
6048 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPEFPU); //
6049 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPEFPU); //
6050 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPEFPU); //
6051 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU); //
6052 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU); //
6053 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU); //
6055 /* End opcode list */
6056 GEN_OPCODE_MARK(end);
6058 #include "translate_init.c"
6059 #include "helper_regs.h"
6061 /*****************************************************************************/
6062 /* Misc PowerPC helpers */
6063 void cpu_dump_state (CPUState *env, FILE *f,
6064 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
6072 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
6073 env->nip, env->lr, env->ctr, hreg_load_xer(env));
6074 cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n",
6075 env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx);
6076 #if !defined(NO_TIMER_DUMP)
6077 cpu_fprintf(f, "TB %08x %08x "
6078 #if !defined(CONFIG_USER_ONLY)
6082 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
6083 #if !defined(CONFIG_USER_ONLY)
6084 , cpu_ppc_load_decr(env)
6088 for (i = 0; i < 32; i++) {
6089 if ((i & (RGPL - 1)) == 0)
6090 cpu_fprintf(f, "GPR%02d", i);
6091 cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
6092 if ((i & (RGPL - 1)) == (RGPL - 1))
6093 cpu_fprintf(f, "\n");
6095 cpu_fprintf(f, "CR ");
6096 for (i = 0; i < 8; i++)
6097 cpu_fprintf(f, "%01x", env->crf[i]);
6098 cpu_fprintf(f, " [");
6099 for (i = 0; i < 8; i++) {
6101 if (env->crf[i] & 0x08)
6103 else if (env->crf[i] & 0x04)
6105 else if (env->crf[i] & 0x02)
6107 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
6109 cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve);
6110 for (i = 0; i < 32; i++) {
6111 if ((i & (RFPL - 1)) == 0)
6112 cpu_fprintf(f, "FPR%02d", i);
6113 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
6114 if ((i & (RFPL - 1)) == (RFPL - 1))
6115 cpu_fprintf(f, "\n");
6117 #if !defined(CONFIG_USER_ONLY)
6118 cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n",
6119 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
6126 void cpu_dump_statistics (CPUState *env, FILE*f,
6127 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
6130 #if defined(DO_PPC_STATISTICS)
6131 opc_handler_t **t1, **t2, **t3, *handler;
6135 for (op1 = 0; op1 < 64; op1++) {
6137 if (is_indirect_opcode(handler)) {
6138 t2 = ind_table(handler);
6139 for (op2 = 0; op2 < 32; op2++) {
6141 if (is_indirect_opcode(handler)) {
6142 t3 = ind_table(handler);
6143 for (op3 = 0; op3 < 32; op3++) {
6145 if (handler->count == 0)
6147 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
6149 op1, op2, op3, op1, (op3 << 5) | op2,
6151 handler->count, handler->count);
6154 if (handler->count == 0)
6156 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
6158 op1, op2, op1, op2, handler->oname,
6159 handler->count, handler->count);
6163 if (handler->count == 0)
6165 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
6166 op1, op1, handler->oname,
6167 handler->count, handler->count);
6173 /*****************************************************************************/
6174 static always_inline void gen_intermediate_code_internal (CPUState *env,
6175 TranslationBlock *tb,
6178 DisasContext ctx, *ctxp = &ctx;
6179 opc_handler_t **table, *handler;
6180 target_ulong pc_start;
6181 uint16_t *gen_opc_end;
6182 int supervisor, little_endian;
6188 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
6189 #if defined(OPTIMIZE_FPRF_UPDATE)
6190 gen_fprf_ptr = gen_fprf_buf;
6194 ctx.exception = POWERPC_EXCP_NONE;
6195 ctx.spr_cb = env->spr_cb;
6196 supervisor = env->mmu_idx;
6197 #if !defined(CONFIG_USER_ONLY)
6198 ctx.supervisor = supervisor;
6200 little_endian = env->hflags & (1 << MSR_LE) ? 1 : 0;
6201 #if defined(TARGET_PPC64)
6202 ctx.sf_mode = msr_sf;
6203 ctx.mem_idx = (supervisor << 2) | (msr_sf << 1) | little_endian;
6205 ctx.mem_idx = (supervisor << 1) | little_endian;
6207 ctx.dcache_line_size = env->dcache_line_size;
6208 ctx.fpu_enabled = msr_fp;
6209 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
6210 ctx.spe_enabled = msr_spe;
6212 ctx.spe_enabled = 0;
6213 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
6214 ctx.altivec_enabled = msr_vr;
6216 ctx.altivec_enabled = 0;
6217 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
6218 ctx.singlestep_enabled = CPU_SINGLE_STEP;
6220 ctx.singlestep_enabled = 0;
6221 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
6222 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
6223 if (unlikely(env->singlestep_enabled))
6224 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
6225 #if defined (DO_SINGLE_STEP) && 0
6226 /* Single step trace mode */
6230 max_insns = tb->cflags & CF_COUNT_MASK;
6232 max_insns = CF_COUNT_MASK;
6235 /* Set env in case of segfault during code fetch */
6236 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
6237 if (unlikely(env->nb_breakpoints > 0)) {
6238 for (j = 0; j < env->nb_breakpoints; j++) {
6239 if (env->breakpoints[j] == ctx.nip) {
6240 gen_update_nip(&ctx, ctx.nip);
6246 if (unlikely(search_pc)) {
6247 j = gen_opc_ptr - gen_opc_buf;
6251 gen_opc_instr_start[lj++] = 0;
6252 gen_opc_pc[lj] = ctx.nip;
6253 gen_opc_instr_start[lj] = 1;
6254 gen_opc_icount[lj] = num_insns;
6257 #if defined PPC_DEBUG_DISAS
6258 if (loglevel & CPU_LOG_TB_IN_ASM) {
6259 fprintf(logfile, "----------------\n");
6260 fprintf(logfile, "nip=" ADDRX " super=%d ir=%d\n",
6261 ctx.nip, supervisor, (int)msr_ir);
6264 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
6266 if (unlikely(little_endian)) {
6267 ctx.opcode = bswap32(ldl_code(ctx.nip));
6269 ctx.opcode = ldl_code(ctx.nip);
6271 #if defined PPC_DEBUG_DISAS
6272 if (loglevel & CPU_LOG_TB_IN_ASM) {
6273 fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n",
6274 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
6275 opc3(ctx.opcode), little_endian ? "little" : "big");
6279 table = env->opcodes;
6281 handler = table[opc1(ctx.opcode)];
6282 if (is_indirect_opcode(handler)) {
6283 table = ind_table(handler);
6284 handler = table[opc2(ctx.opcode)];
6285 if (is_indirect_opcode(handler)) {
6286 table = ind_table(handler);
6287 handler = table[opc3(ctx.opcode)];
6290 /* Is opcode *REALLY* valid ? */
6291 if (unlikely(handler->handler == &gen_invalid)) {
6292 if (loglevel != 0) {
6293 fprintf(logfile, "invalid/unsupported opcode: "
6294 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
6295 opc1(ctx.opcode), opc2(ctx.opcode),
6296 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
6298 printf("invalid/unsupported opcode: "
6299 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
6300 opc1(ctx.opcode), opc2(ctx.opcode),
6301 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
6304 if (unlikely((ctx.opcode & handler->inval) != 0)) {
6305 if (loglevel != 0) {
6306 fprintf(logfile, "invalid bits: %08x for opcode: "
6307 "%02x - %02x - %02x (%08x) " ADDRX "\n",
6308 ctx.opcode & handler->inval, opc1(ctx.opcode),
6309 opc2(ctx.opcode), opc3(ctx.opcode),
6310 ctx.opcode, ctx.nip - 4);
6312 printf("invalid bits: %08x for opcode: "
6313 "%02x - %02x - %02x (%08x) " ADDRX "\n",
6314 ctx.opcode & handler->inval, opc1(ctx.opcode),
6315 opc2(ctx.opcode), opc3(ctx.opcode),
6316 ctx.opcode, ctx.nip - 4);
6318 GEN_EXCP_INVAL(ctxp);
6322 (*(handler->handler))(&ctx);
6323 #if defined(DO_PPC_STATISTICS)
6326 /* Check trace mode exceptions */
6327 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
6328 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
6329 ctx.exception != POWERPC_SYSCALL &&
6330 ctx.exception != POWERPC_EXCP_TRAP &&
6331 ctx.exception != POWERPC_EXCP_BRANCH)) {
6332 GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0);
6333 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
6334 (env->singlestep_enabled) ||
6335 num_insns >= max_insns)) {
6336 /* if we reach a page boundary or are single stepping, stop
6341 #if defined (DO_SINGLE_STEP)
6345 if (tb->cflags & CF_LAST_IO)
6347 if (ctx.exception == POWERPC_EXCP_NONE) {
6348 gen_goto_tb(&ctx, 0, ctx.nip);
6349 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
6350 if (unlikely(env->singlestep_enabled)) {
6351 gen_update_nip(&ctx, ctx.nip);
6354 /* Generate the return instruction */
6357 gen_icount_end(tb, num_insns);
6358 *gen_opc_ptr = INDEX_op_end;
6359 if (unlikely(search_pc)) {
6360 j = gen_opc_ptr - gen_opc_buf;
6363 gen_opc_instr_start[lj++] = 0;
6365 tb->size = ctx.nip - pc_start;
6366 tb->icount = num_insns;
6368 #if defined(DEBUG_DISAS)
6369 if (loglevel & CPU_LOG_TB_CPU) {
6370 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
6371 cpu_dump_state(env, logfile, fprintf, 0);
6373 if (loglevel & CPU_LOG_TB_IN_ASM) {
6375 flags = env->bfd_mach;
6376 flags |= little_endian << 16;
6377 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
6378 target_disas(logfile, pc_start, ctx.nip - pc_start, flags);
6379 fprintf(logfile, "\n");
6384 void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
6386 gen_intermediate_code_internal(env, tb, 0);
6389 void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
6391 gen_intermediate_code_internal(env, tb, 1);
6394 void gen_pc_load(CPUState *env, TranslationBlock *tb,
6395 unsigned long searched_pc, int pc_pos, void *puc)
6398 /* for PPC, we need to look at the micro operation to get the
6400 env->nip = gen_opc_pc[pc_pos];
6401 c = gen_opc_buf[pc_pos];
6403 #if defined(CONFIG_USER_ONLY)
6405 case INDEX_op_ ## op ## _raw
6408 case INDEX_op_ ## op ## _user:\
6409 case INDEX_op_ ## op ## _kernel:\
6410 case INDEX_op_ ## op ## _hypv
6417 type = ACCESS_FLOAT;
6433 env->access_type = type;