2 * PowerPC emulation for qemu: main translation routines.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30 /* Include definitions for instructions classes and implementations flags */
31 //#define DO_SINGLE_STEP
32 //#define PPC_DEBUG_DISAS
33 //#define DEBUG_MEMORY_ACCESSES
34 //#define DO_PPC_STATISTICS
36 /*****************************************************************************/
37 /* Code translation helpers */
38 #if defined(USE_DIRECT_JUMP)
41 #define TBPARAM(x) (long)(x)
45 #define DEF(s, n, copy_size) INDEX_op_ ## s,
51 static uint16_t *gen_opc_ptr;
52 static uint32_t *gen_opparam_ptr;
56 static always_inline void gen_set_T0 (target_ulong val)
58 #if defined(TARGET_PPC64)
60 gen_op_set_T0_64(val >> 32, val);
66 static always_inline void gen_set_T1 (target_ulong val)
68 #if defined(TARGET_PPC64)
70 gen_op_set_T1_64(val >> 32, val);
76 #define GEN8(func, NAME) \
77 static GenOpFunc *NAME ## _table [8] = { \
78 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
79 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
81 static always_inline void func (int n) \
83 NAME ## _table[n](); \
86 #define GEN16(func, NAME) \
87 static GenOpFunc *NAME ## _table [16] = { \
88 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
89 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
90 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
91 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
93 static always_inline void func (int n) \
95 NAME ## _table[n](); \
98 #define GEN32(func, NAME) \
99 static GenOpFunc *NAME ## _table [32] = { \
100 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
101 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
102 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
103 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
104 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
105 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
106 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
107 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
109 static always_inline void func (int n) \
111 NAME ## _table[n](); \
114 /* Condition register moves */
115 GEN8(gen_op_load_crf_T0, gen_op_load_crf_T0_crf);
116 GEN8(gen_op_load_crf_T1, gen_op_load_crf_T1_crf);
117 GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf);
118 GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf);
120 /* Floating point condition and status register moves */
121 GEN8(gen_op_load_fpscr_T0, gen_op_load_fpscr_T0_fpscr);
122 GEN8(gen_op_store_T0_fpscr, gen_op_store_T0_fpscr_fpscr);
123 GEN8(gen_op_clear_fpscr, gen_op_clear_fpscr_fpscr);
124 static always_inline void gen_op_store_T0_fpscri (int n, uint8_t param)
126 gen_op_set_T0(param);
127 gen_op_store_T0_fpscr(n);
130 /* General purpose registers moves */
131 GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);
132 GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);
133 GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);
135 GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
136 GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
138 GEN32(gen_op_store_T2_gpr, gen_op_store_T2_gpr_gpr);
141 /* floating point registers moves */
142 GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr);
143 GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr);
144 GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fpr);
145 GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fpr);
146 GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fpr);
148 GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fpr);
151 /* internal defines */
152 typedef struct DisasContext {
153 struct TranslationBlock *tb;
157 /* Routine used to access memory */
159 /* Translation flags */
160 #if !defined(CONFIG_USER_ONLY)
163 #if defined(TARGET_PPC64)
168 #if defined(TARGET_PPCEMB)
171 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
172 int singlestep_enabled;
173 int dcache_line_size;
176 struct opc_handler_t {
179 /* instruction type */
182 void (*handler)(DisasContext *ctx);
183 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
184 const unsigned char *oname;
186 #if defined(DO_PPC_STATISTICS)
191 static always_inline void gen_set_Rc0 (DisasContext *ctx)
193 #if defined(TARGET_PPC64)
202 static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
204 #if defined(TARGET_PPC64)
206 gen_op_update_nip_64(nip >> 32, nip);
209 gen_op_update_nip(nip);
212 #define GEN_EXCP(ctx, excp, error) \
214 if ((ctx)->exception == POWERPC_EXCP_NONE) { \
215 gen_update_nip(ctx, (ctx)->nip); \
217 gen_op_raise_exception_err((excp), (error)); \
218 ctx->exception = (excp); \
221 #define GEN_EXCP_INVAL(ctx) \
222 GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
223 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL)
225 #define GEN_EXCP_PRIVOPC(ctx) \
226 GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
227 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC)
229 #define GEN_EXCP_PRIVREG(ctx) \
230 GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
231 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG)
233 #define GEN_EXCP_NO_FP(ctx) \
234 GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0)
236 #define GEN_EXCP_NO_AP(ctx) \
237 GEN_EXCP(ctx, POWERPC_EXCP_APU, 0)
239 #define GEN_EXCP_NO_VR(ctx) \
240 GEN_EXCP(ctx, POWERPC_EXCP_VPU, 0)
242 /* Stop translation */
243 static always_inline void GEN_STOP (DisasContext *ctx)
245 gen_update_nip(ctx, ctx->nip);
246 ctx->exception = POWERPC_EXCP_STOP;
249 /* No need to update nip here, as execution flow will change */
250 static always_inline void GEN_SYNC (DisasContext *ctx)
252 ctx->exception = POWERPC_EXCP_SYNC;
255 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
256 static void gen_##name (DisasContext *ctx); \
257 GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
258 static void gen_##name (DisasContext *ctx)
260 typedef struct opcode_t {
261 unsigned char opc1, opc2, opc3;
262 #if HOST_LONG_BITS == 64 /* Explicitely align to 64 bits */
263 unsigned char pad[5];
265 unsigned char pad[1];
267 opc_handler_t handler;
268 const unsigned char *oname;
271 /*****************************************************************************/
272 /*** Instruction decoding ***/
273 #define EXTRACT_HELPER(name, shift, nb) \
274 static always_inline uint32_t name (uint32_t opcode) \
276 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
279 #define EXTRACT_SHELPER(name, shift, nb) \
280 static always_inline int32_t name (uint32_t opcode) \
282 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
286 EXTRACT_HELPER(opc1, 26, 6);
288 EXTRACT_HELPER(opc2, 1, 5);
290 EXTRACT_HELPER(opc3, 6, 5);
291 /* Update Cr0 flags */
292 EXTRACT_HELPER(Rc, 0, 1);
294 EXTRACT_HELPER(rD, 21, 5);
296 EXTRACT_HELPER(rS, 21, 5);
298 EXTRACT_HELPER(rA, 16, 5);
300 EXTRACT_HELPER(rB, 11, 5);
302 EXTRACT_HELPER(rC, 6, 5);
304 EXTRACT_HELPER(crfD, 23, 3);
305 EXTRACT_HELPER(crfS, 18, 3);
306 EXTRACT_HELPER(crbD, 21, 5);
307 EXTRACT_HELPER(crbA, 16, 5);
308 EXTRACT_HELPER(crbB, 11, 5);
310 EXTRACT_HELPER(_SPR, 11, 10);
311 static always_inline uint32_t SPR (uint32_t opcode)
313 uint32_t sprn = _SPR(opcode);
315 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
317 /*** Get constants ***/
318 EXTRACT_HELPER(IMM, 12, 8);
319 /* 16 bits signed immediate value */
320 EXTRACT_SHELPER(SIMM, 0, 16);
321 /* 16 bits unsigned immediate value */
322 EXTRACT_HELPER(UIMM, 0, 16);
324 EXTRACT_HELPER(NB, 11, 5);
326 EXTRACT_HELPER(SH, 11, 5);
328 EXTRACT_HELPER(MB, 6, 5);
330 EXTRACT_HELPER(ME, 1, 5);
332 EXTRACT_HELPER(TO, 21, 5);
334 EXTRACT_HELPER(CRM, 12, 8);
335 EXTRACT_HELPER(FM, 17, 8);
336 EXTRACT_HELPER(SR, 16, 4);
337 EXTRACT_HELPER(FPIMM, 20, 4);
339 /*** Jump target decoding ***/
341 EXTRACT_SHELPER(d, 0, 16);
342 /* Immediate address */
343 static always_inline target_ulong LI (uint32_t opcode)
345 return (opcode >> 0) & 0x03FFFFFC;
348 static always_inline uint32_t BD (uint32_t opcode)
350 return (opcode >> 0) & 0xFFFC;
353 EXTRACT_HELPER(BO, 21, 5);
354 EXTRACT_HELPER(BI, 16, 5);
355 /* Absolute/relative address */
356 EXTRACT_HELPER(AA, 1, 1);
358 EXTRACT_HELPER(LK, 0, 1);
360 /* Create a mask between <start> and <end> bits */
361 static always_inline target_ulong MASK (uint32_t start, uint32_t end)
365 #if defined(TARGET_PPC64)
366 if (likely(start == 0)) {
367 ret = (uint64_t)(-1ULL) << (63 - end);
368 } else if (likely(end == 63)) {
369 ret = (uint64_t)(-1ULL) >> start;
372 if (likely(start == 0)) {
373 ret = (uint32_t)(-1ULL) << (31 - end);
374 } else if (likely(end == 31)) {
375 ret = (uint32_t)(-1ULL) >> start;
379 ret = (((target_ulong)(-1ULL)) >> (start)) ^
380 (((target_ulong)(-1ULL) >> (end)) >> 1);
381 if (unlikely(start > end))
388 /*****************************************************************************/
389 /* PowerPC Instructions types definitions */
391 PPC_NONE = 0x0000000000000000ULL,
392 /* PowerPC base instructions set */
393 PPC_INSNS_BASE = 0x0000000000000001ULL,
394 /* integer operations instructions */
395 #define PPC_INTEGER PPC_INSNS_BASE
396 /* flow control instructions */
397 #define PPC_FLOW PPC_INSNS_BASE
398 /* virtual memory instructions */
399 #define PPC_MEM PPC_INSNS_BASE
400 /* ld/st with reservation instructions */
401 #define PPC_RES PPC_INSNS_BASE
402 /* cache control instructions */
403 #define PPC_CACHE PPC_INSNS_BASE
404 /* spr/msr access instructions */
405 #define PPC_MISC PPC_INSNS_BASE
406 /* Optional floating point instructions */
407 PPC_FLOAT = 0x0000000000000002ULL,
408 PPC_FLOAT_FSQRT = 0x0000000000000004ULL,
409 PPC_FLOAT_FRES = 0x0000000000000008ULL,
410 PPC_FLOAT_FRSQRTE = 0x0000000000000010ULL,
411 PPC_FLOAT_FSEL = 0x0000000000000020ULL,
412 PPC_FLOAT_STFIWX = 0x0000000000000040ULL,
413 /* external control instructions */
414 PPC_EXTERN = 0x0000000000000080ULL,
415 /* segment register access instructions */
416 PPC_SEGMENT = 0x0000000000000100ULL,
417 /* Optional cache control instruction */
418 PPC_CACHE_DCBA = 0x0000000000000200ULL,
419 /* Optional memory control instructions */
420 PPC_MEM_TLBIA = 0x0000000000000400ULL,
421 PPC_MEM_TLBIE = 0x0000000000000800ULL,
422 PPC_MEM_TLBSYNC = 0x0000000000001000ULL,
424 PPC_MEM_SYNC = 0x0000000000002000ULL,
425 /* PowerPC 6xx TLB management instructions */
426 PPC_6xx_TLB = 0x0000000000004000ULL,
427 /* Altivec support */
428 PPC_ALTIVEC = 0x0000000000008000ULL,
429 /* Time base mftb instruction */
430 PPC_MFTB = 0x0000000000010000ULL,
431 /* Embedded PowerPC dedicated instructions */
432 PPC_EMB_COMMON = 0x0000000000020000ULL,
433 /* PowerPC 40x exception model */
434 PPC_40x_EXCP = 0x0000000000040000ULL,
435 /* PowerPC 40x TLB management instructions */
436 PPC_40x_TLB = 0x0000000000080000ULL,
437 /* PowerPC 405 Mac instructions */
438 PPC_405_MAC = 0x0000000000100000ULL,
439 /* PowerPC 440 specific instructions */
440 PPC_440_SPEC = 0x0000000000200000ULL,
441 /* Power-to-PowerPC bridge (601) */
442 PPC_POWER_BR = 0x0000000000400000ULL,
443 /* PowerPC 602 specific */
444 PPC_602_SPEC = 0x0000000000800000ULL,
445 /* Deprecated instructions */
446 /* Original POWER instruction set */
447 PPC_POWER = 0x0000000001000000ULL,
448 /* POWER2 instruction set extension */
449 PPC_POWER2 = 0x0000000002000000ULL,
450 /* Power RTC support */
451 PPC_POWER_RTC = 0x0000000004000000ULL,
452 /* 64 bits PowerPC instruction set */
453 PPC_64B = 0x0000000008000000ULL,
454 /* 64 bits hypervisor extensions */
455 PPC_64H = 0x0000000010000000ULL,
456 /* segment register access instructions for PowerPC 64 "bridge" */
457 PPC_SEGMENT_64B = 0x0000000020000000ULL,
458 /* BookE (embedded) PowerPC specification */
459 PPC_BOOKE = 0x0000000040000000ULL,
461 PPC_MEM_EIEIO = 0x0000000080000000ULL,
462 /* e500 vector instructions */
463 PPC_E500_VECTOR = 0x0000000100000000ULL,
464 /* PowerPC 4xx dedicated instructions */
465 PPC_4xx_COMMON = 0x0000000200000000ULL,
466 /* PowerPC 2.03 specification extensions */
467 PPC_203 = 0x0000000400000000ULL,
468 /* PowerPC 2.03 SPE extension */
469 PPC_SPE = 0x0000000800000000ULL,
470 /* PowerPC 2.03 SPE floating-point extension */
471 PPC_SPEFPU = 0x0000001000000000ULL,
473 PPC_SLBI = 0x0000002000000000ULL,
474 /* PowerPC 40x ibct instructions */
475 PPC_40x_ICBT = 0x0000004000000000ULL,
476 /* PowerPC 74xx TLB management instructions */
477 PPC_74xx_TLB = 0x0000008000000000ULL,
478 /* More BookE (embedded) instructions... */
479 PPC_BOOKE_EXT = 0x0000010000000000ULL,
480 /* rfmci is not implemented in all BookE PowerPC */
481 PPC_RFMCI = 0x0000020000000000ULL,
482 /* user-mode DCR access, implemented in PowerPC 460 */
483 PPC_DCRUX = 0x0000040000000000ULL,
484 /* New floating-point extensions (PowerPC 2.0x) */
485 PPC_FLOAT_EXT = 0x0000080000000000ULL,
486 /* New wait instruction (PowerPC 2.0x) */
487 PPC_WAIT = 0x0000100000000000ULL,
488 /* New 64 bits extensions (PowerPC 2.0x) */
489 PPC_64BX = 0x0000200000000000ULL,
490 /* dcbz instruction with fixed cache line size */
491 PPC_CACHE_DCBZ = 0x0000400000000000ULL,
492 /* dcbz instruction with tunable cache line size */
493 PPC_CACHE_DCBZT = 0x0000800000000000ULL,
496 /*****************************************************************************/
497 /* PowerPC instructions table */
498 #if HOST_LONG_BITS == 64
503 #if defined(__APPLE__)
504 #define OPCODES_SECTION \
505 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
507 #define OPCODES_SECTION \
508 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
511 #if defined(DO_PPC_STATISTICS)
512 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
513 OPCODES_SECTION opcode_t opc_##name = { \
521 .handler = &gen_##name, \
522 .oname = stringify(name), \
524 .oname = stringify(name), \
527 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
528 OPCODES_SECTION opcode_t opc_##name = { \
536 .handler = &gen_##name, \
538 .oname = stringify(name), \
542 #define GEN_OPCODE_MARK(name) \
543 OPCODES_SECTION opcode_t opc_##name = { \
549 .inval = 0x00000000, \
553 .oname = stringify(name), \
556 /* Start opcode list */
557 GEN_OPCODE_MARK(start);
559 /* Invalid instruction */
560 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
565 static opc_handler_t invalid_handler = {
568 .handler = gen_invalid,
571 /*** Integer arithmetic ***/
572 #define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval, type) \
573 GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
575 gen_op_load_gpr_T0(rA(ctx->opcode)); \
576 gen_op_load_gpr_T1(rB(ctx->opcode)); \
578 gen_op_store_T0_gpr(rD(ctx->opcode)); \
579 if (unlikely(Rc(ctx->opcode) != 0)) \
583 #define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval, type) \
584 GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
586 gen_op_load_gpr_T0(rA(ctx->opcode)); \
587 gen_op_load_gpr_T1(rB(ctx->opcode)); \
589 gen_op_store_T0_gpr(rD(ctx->opcode)); \
590 if (unlikely(Rc(ctx->opcode) != 0)) \
594 #define __GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
595 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
597 gen_op_load_gpr_T0(rA(ctx->opcode)); \
599 gen_op_store_T0_gpr(rD(ctx->opcode)); \
600 if (unlikely(Rc(ctx->opcode) != 0)) \
603 #define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3, type) \
604 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
606 gen_op_load_gpr_T0(rA(ctx->opcode)); \
608 gen_op_store_T0_gpr(rD(ctx->opcode)); \
609 if (unlikely(Rc(ctx->opcode) != 0)) \
613 /* Two operands arithmetic functions */
614 #define GEN_INT_ARITH2(name, opc1, opc2, opc3, type) \
615 __GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000, type) \
616 __GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
618 /* Two operands arithmetic functions with no overflow allowed */
619 #define GEN_INT_ARITHN(name, opc1, opc2, opc3, type) \
620 __GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400, type)
622 /* One operand arithmetic functions */
623 #define GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
624 __GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
625 __GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10, type)
627 #if defined(TARGET_PPC64)
628 #define __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, inval, type) \
629 GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
631 gen_op_load_gpr_T0(rA(ctx->opcode)); \
632 gen_op_load_gpr_T1(rB(ctx->opcode)); \
634 gen_op_##name##_64(); \
637 gen_op_store_T0_gpr(rD(ctx->opcode)); \
638 if (unlikely(Rc(ctx->opcode) != 0)) \
642 #define __GEN_INT_ARITH2_O_64(name, opc1, opc2, opc3, inval, type) \
643 GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
645 gen_op_load_gpr_T0(rA(ctx->opcode)); \
646 gen_op_load_gpr_T1(rB(ctx->opcode)); \
648 gen_op_##name##_64(); \
651 gen_op_store_T0_gpr(rD(ctx->opcode)); \
652 if (unlikely(Rc(ctx->opcode) != 0)) \
656 #define __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
657 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
659 gen_op_load_gpr_T0(rA(ctx->opcode)); \
661 gen_op_##name##_64(); \
664 gen_op_store_T0_gpr(rD(ctx->opcode)); \
665 if (unlikely(Rc(ctx->opcode) != 0)) \
668 #define __GEN_INT_ARITH1_O_64(name, opc1, opc2, opc3, type) \
669 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
671 gen_op_load_gpr_T0(rA(ctx->opcode)); \
673 gen_op_##name##_64(); \
676 gen_op_store_T0_gpr(rD(ctx->opcode)); \
677 if (unlikely(Rc(ctx->opcode) != 0)) \
681 /* Two operands arithmetic functions */
682 #define GEN_INT_ARITH2_64(name, opc1, opc2, opc3, type) \
683 __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000000, type) \
684 __GEN_INT_ARITH2_O_64(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
686 /* Two operands arithmetic functions with no overflow allowed */
687 #define GEN_INT_ARITHN_64(name, opc1, opc2, opc3, type) \
688 __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000400, type)
690 /* One operand arithmetic functions */
691 #define GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
692 __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
693 __GEN_INT_ARITH1_O_64(name##o, opc1, opc2, opc3 | 0x10, type)
695 #define GEN_INT_ARITH2_64 GEN_INT_ARITH2
696 #define GEN_INT_ARITHN_64 GEN_INT_ARITHN
697 #define GEN_INT_ARITH1_64 GEN_INT_ARITH1
700 /* add add. addo addo. */
701 static always_inline void gen_op_addo (void)
707 #if defined(TARGET_PPC64)
708 #define gen_op_add_64 gen_op_add
709 static always_inline void gen_op_addo_64 (void)
713 gen_op_check_addo_64();
716 GEN_INT_ARITH2_64 (add, 0x1F, 0x0A, 0x08, PPC_INTEGER);
717 /* addc addc. addco addco. */
718 static always_inline void gen_op_addc (void)
724 static always_inline void gen_op_addco (void)
731 #if defined(TARGET_PPC64)
732 static always_inline void gen_op_addc_64 (void)
736 gen_op_check_addc_64();
738 static always_inline void gen_op_addco_64 (void)
742 gen_op_check_addc_64();
743 gen_op_check_addo_64();
746 GEN_INT_ARITH2_64 (addc, 0x1F, 0x0A, 0x00, PPC_INTEGER);
747 /* adde adde. addeo addeo. */
748 static always_inline void gen_op_addeo (void)
754 #if defined(TARGET_PPC64)
755 static always_inline void gen_op_addeo_64 (void)
759 gen_op_check_addo_64();
762 GEN_INT_ARITH2_64 (adde, 0x1F, 0x0A, 0x04, PPC_INTEGER);
763 /* addme addme. addmeo addmeo. */
764 static always_inline void gen_op_addme (void)
769 #if defined(TARGET_PPC64)
770 static always_inline void gen_op_addme_64 (void)
776 GEN_INT_ARITH1_64 (addme, 0x1F, 0x0A, 0x07, PPC_INTEGER);
777 /* addze addze. addzeo addzeo. */
778 static always_inline void gen_op_addze (void)
784 static always_inline void gen_op_addzeo (void)
791 #if defined(TARGET_PPC64)
792 static always_inline void gen_op_addze_64 (void)
796 gen_op_check_addc_64();
798 static always_inline void gen_op_addzeo_64 (void)
802 gen_op_check_addc_64();
803 gen_op_check_addo_64();
806 GEN_INT_ARITH1_64 (addze, 0x1F, 0x0A, 0x06, PPC_INTEGER);
807 /* divw divw. divwo divwo. */
808 GEN_INT_ARITH2 (divw, 0x1F, 0x0B, 0x0F, PPC_INTEGER);
809 /* divwu divwu. divwuo divwuo. */
810 GEN_INT_ARITH2 (divwu, 0x1F, 0x0B, 0x0E, PPC_INTEGER);
812 GEN_INT_ARITHN (mulhw, 0x1F, 0x0B, 0x02, PPC_INTEGER);
814 GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00, PPC_INTEGER);
815 /* mullw mullw. mullwo mullwo. */
816 GEN_INT_ARITH2 (mullw, 0x1F, 0x0B, 0x07, PPC_INTEGER);
817 /* neg neg. nego nego. */
818 GEN_INT_ARITH1_64 (neg, 0x1F, 0x08, 0x03, PPC_INTEGER);
819 /* subf subf. subfo subfo. */
820 static always_inline void gen_op_subfo (void)
824 gen_op_check_subfo();
826 #if defined(TARGET_PPC64)
827 #define gen_op_subf_64 gen_op_subf
828 static always_inline void gen_op_subfo_64 (void)
832 gen_op_check_subfo_64();
835 GEN_INT_ARITH2_64 (subf, 0x1F, 0x08, 0x01, PPC_INTEGER);
836 /* subfc subfc. subfco subfco. */
837 static always_inline void gen_op_subfc (void)
840 gen_op_check_subfc();
842 static always_inline void gen_op_subfco (void)
846 gen_op_check_subfc();
847 gen_op_check_subfo();
849 #if defined(TARGET_PPC64)
850 static always_inline void gen_op_subfc_64 (void)
853 gen_op_check_subfc_64();
855 static always_inline void gen_op_subfco_64 (void)
859 gen_op_check_subfc_64();
860 gen_op_check_subfo_64();
863 GEN_INT_ARITH2_64 (subfc, 0x1F, 0x08, 0x00, PPC_INTEGER);
864 /* subfe subfe. subfeo subfeo. */
865 static always_inline void gen_op_subfeo (void)
869 gen_op_check_subfo();
871 #if defined(TARGET_PPC64)
872 #define gen_op_subfe_64 gen_op_subfe
873 static always_inline void gen_op_subfeo_64 (void)
877 gen_op_check_subfo_64();
880 GEN_INT_ARITH2_64 (subfe, 0x1F, 0x08, 0x04, PPC_INTEGER);
881 /* subfme subfme. subfmeo subfmeo. */
882 GEN_INT_ARITH1_64 (subfme, 0x1F, 0x08, 0x07, PPC_INTEGER);
883 /* subfze subfze. subfzeo subfzeo. */
884 GEN_INT_ARITH1_64 (subfze, 0x1F, 0x08, 0x06, PPC_INTEGER);
886 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
888 target_long simm = SIMM(ctx->opcode);
890 if (rA(ctx->opcode) == 0) {
894 gen_op_load_gpr_T0(rA(ctx->opcode));
895 if (likely(simm != 0))
898 gen_op_store_T0_gpr(rD(ctx->opcode));
901 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
903 target_long simm = SIMM(ctx->opcode);
905 gen_op_load_gpr_T0(rA(ctx->opcode));
906 if (likely(simm != 0)) {
909 #if defined(TARGET_PPC64)
911 gen_op_check_addc_64();
916 gen_op_clear_xer_ca();
918 gen_op_store_T0_gpr(rD(ctx->opcode));
921 GEN_HANDLER(addic_, 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
923 target_long simm = SIMM(ctx->opcode);
925 gen_op_load_gpr_T0(rA(ctx->opcode));
926 if (likely(simm != 0)) {
929 #if defined(TARGET_PPC64)
931 gen_op_check_addc_64();
936 gen_op_clear_xer_ca();
938 gen_op_store_T0_gpr(rD(ctx->opcode));
942 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
944 target_long simm = SIMM(ctx->opcode);
946 if (rA(ctx->opcode) == 0) {
948 gen_set_T0(simm << 16);
950 gen_op_load_gpr_T0(rA(ctx->opcode));
951 if (likely(simm != 0))
952 gen_op_addi(simm << 16);
954 gen_op_store_T0_gpr(rD(ctx->opcode));
957 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
959 gen_op_load_gpr_T0(rA(ctx->opcode));
960 gen_op_mulli(SIMM(ctx->opcode));
961 gen_op_store_T0_gpr(rD(ctx->opcode));
964 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
966 gen_op_load_gpr_T0(rA(ctx->opcode));
967 #if defined(TARGET_PPC64)
969 gen_op_subfic_64(SIMM(ctx->opcode));
972 gen_op_subfic(SIMM(ctx->opcode));
973 gen_op_store_T0_gpr(rD(ctx->opcode));
976 #if defined(TARGET_PPC64)
978 GEN_INT_ARITHN (mulhd, 0x1F, 0x09, 0x02, PPC_64B);
980 GEN_INT_ARITHN (mulhdu, 0x1F, 0x09, 0x00, PPC_64B);
981 /* mulld mulld. mulldo mulldo. */
982 GEN_INT_ARITH2 (mulld, 0x1F, 0x09, 0x07, PPC_64B);
983 /* divd divd. divdo divdo. */
984 GEN_INT_ARITH2 (divd, 0x1F, 0x09, 0x0F, PPC_64B);
985 /* divdu divdu. divduo divduo. */
986 GEN_INT_ARITH2 (divdu, 0x1F, 0x09, 0x0E, PPC_64B);
989 /*** Integer comparison ***/
990 #if defined(TARGET_PPC64)
991 #define GEN_CMP(name, opc, type) \
992 GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \
994 gen_op_load_gpr_T0(rA(ctx->opcode)); \
995 gen_op_load_gpr_T1(rB(ctx->opcode)); \
996 if (ctx->sf_mode && (ctx->opcode & 0x00200000)) \
997 gen_op_##name##_64(); \
1000 gen_op_store_T0_crf(crfD(ctx->opcode)); \
1003 #define GEN_CMP(name, opc, type) \
1004 GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \
1006 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1007 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1009 gen_op_store_T0_crf(crfD(ctx->opcode)); \
1014 GEN_CMP(cmp, 0x00, PPC_INTEGER);
1016 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
1018 gen_op_load_gpr_T0(rA(ctx->opcode));
1019 #if defined(TARGET_PPC64)
1020 if (ctx->sf_mode && (ctx->opcode & 0x00200000))
1021 gen_op_cmpi_64(SIMM(ctx->opcode));
1024 gen_op_cmpi(SIMM(ctx->opcode));
1025 gen_op_store_T0_crf(crfD(ctx->opcode));
1028 GEN_CMP(cmpl, 0x01, PPC_INTEGER);
1030 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
1032 gen_op_load_gpr_T0(rA(ctx->opcode));
1033 #if defined(TARGET_PPC64)
1034 if (ctx->sf_mode && (ctx->opcode & 0x00200000))
1035 gen_op_cmpli_64(UIMM(ctx->opcode));
1038 gen_op_cmpli(UIMM(ctx->opcode));
1039 gen_op_store_T0_crf(crfD(ctx->opcode));
1042 /* isel (PowerPC 2.03 specification) */
1043 GEN_HANDLER(isel, 0x1F, 0x0F, 0x00, 0x00000001, PPC_203)
1045 uint32_t bi = rC(ctx->opcode);
1048 if (rA(ctx->opcode) == 0) {
1051 gen_op_load_gpr_T1(rA(ctx->opcode));
1053 gen_op_load_gpr_T2(rB(ctx->opcode));
1054 mask = 1 << (3 - (bi & 0x03));
1055 gen_op_load_crf_T0(bi >> 2);
1056 gen_op_test_true(mask);
1058 gen_op_store_T0_gpr(rD(ctx->opcode));
1061 /*** Integer logical ***/
1062 #define __GEN_LOGICAL2(name, opc2, opc3, type) \
1063 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, type) \
1065 gen_op_load_gpr_T0(rS(ctx->opcode)); \
1066 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1068 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1069 if (unlikely(Rc(ctx->opcode) != 0)) \
1072 #define GEN_LOGICAL2(name, opc, type) \
1073 __GEN_LOGICAL2(name, 0x1C, opc, type)
1075 #define GEN_LOGICAL1(name, opc, type) \
1076 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
1078 gen_op_load_gpr_T0(rS(ctx->opcode)); \
1080 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1081 if (unlikely(Rc(ctx->opcode) != 0)) \
1086 GEN_LOGICAL2(and, 0x00, PPC_INTEGER);
1088 GEN_LOGICAL2(andc, 0x01, PPC_INTEGER);
1090 GEN_HANDLER(andi_, 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1092 gen_op_load_gpr_T0(rS(ctx->opcode));
1093 gen_op_andi_T0(UIMM(ctx->opcode));
1094 gen_op_store_T0_gpr(rA(ctx->opcode));
1098 GEN_HANDLER(andis_, 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1100 gen_op_load_gpr_T0(rS(ctx->opcode));
1101 gen_op_andi_T0(UIMM(ctx->opcode) << 16);
1102 gen_op_store_T0_gpr(rA(ctx->opcode));
1107 GEN_LOGICAL1(cntlzw, 0x00, PPC_INTEGER);
1109 GEN_LOGICAL2(eqv, 0x08, PPC_INTEGER);
1110 /* extsb & extsb. */
1111 GEN_LOGICAL1(extsb, 0x1D, PPC_INTEGER);
1112 /* extsh & extsh. */
1113 GEN_LOGICAL1(extsh, 0x1C, PPC_INTEGER);
1115 GEN_LOGICAL2(nand, 0x0E, PPC_INTEGER);
1117 GEN_LOGICAL2(nor, 0x03, PPC_INTEGER);
1120 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1124 rs = rS(ctx->opcode);
1125 ra = rA(ctx->opcode);
1126 rb = rB(ctx->opcode);
1127 /* Optimisation for mr. ri case */
1128 if (rs != ra || rs != rb) {
1129 gen_op_load_gpr_T0(rs);
1131 gen_op_load_gpr_T1(rb);
1134 gen_op_store_T0_gpr(ra);
1135 if (unlikely(Rc(ctx->opcode) != 0))
1137 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1138 gen_op_load_gpr_T0(rs);
1140 #if defined(TARGET_PPC64)
1144 /* Set process priority to low */
1145 gen_op_store_pri(2);
1148 /* Set process priority to medium-low */
1149 gen_op_store_pri(3);
1152 /* Set process priority to normal */
1153 gen_op_store_pri(4);
1155 #if !defined(CONFIG_USER_ONLY)
1157 if (ctx->supervisor > 0) {
1158 /* Set process priority to very low */
1159 gen_op_store_pri(1);
1163 if (ctx->supervisor > 0) {
1164 /* Set process priority to medium-hight */
1165 gen_op_store_pri(5);
1169 if (ctx->supervisor > 0) {
1170 /* Set process priority to high */
1171 gen_op_store_pri(6);
1174 #if defined(TARGET_PPC64H)
1176 if (ctx->supervisor > 1) {
1177 /* Set process priority to very high */
1178 gen_op_store_pri(7);
1192 GEN_LOGICAL2(orc, 0x0C, PPC_INTEGER);
1194 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1196 gen_op_load_gpr_T0(rS(ctx->opcode));
1197 /* Optimisation for "set to zero" case */
1198 if (rS(ctx->opcode) != rB(ctx->opcode)) {
1199 gen_op_load_gpr_T1(rB(ctx->opcode));
1204 gen_op_store_T0_gpr(rA(ctx->opcode));
1205 if (unlikely(Rc(ctx->opcode) != 0))
1209 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1211 target_ulong uimm = UIMM(ctx->opcode);
1213 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1215 /* XXX: should handle special NOPs for POWER series */
1218 gen_op_load_gpr_T0(rS(ctx->opcode));
1219 if (likely(uimm != 0))
1221 gen_op_store_T0_gpr(rA(ctx->opcode));
1224 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1226 target_ulong uimm = UIMM(ctx->opcode);
1228 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1232 gen_op_load_gpr_T0(rS(ctx->opcode));
1233 if (likely(uimm != 0))
1234 gen_op_ori(uimm << 16);
1235 gen_op_store_T0_gpr(rA(ctx->opcode));
1238 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1240 target_ulong uimm = UIMM(ctx->opcode);
1242 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1246 gen_op_load_gpr_T0(rS(ctx->opcode));
1247 if (likely(uimm != 0))
1249 gen_op_store_T0_gpr(rA(ctx->opcode));
1253 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1255 target_ulong uimm = UIMM(ctx->opcode);
1257 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1261 gen_op_load_gpr_T0(rS(ctx->opcode));
1262 if (likely(uimm != 0))
1263 gen_op_xori(uimm << 16);
1264 gen_op_store_T0_gpr(rA(ctx->opcode));
1267 /* popcntb : PowerPC 2.03 specification */
1268 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_203)
1270 gen_op_load_gpr_T0(rS(ctx->opcode));
1271 #if defined(TARGET_PPC64)
1273 gen_op_popcntb_64();
1277 gen_op_store_T0_gpr(rA(ctx->opcode));
1280 #if defined(TARGET_PPC64)
1281 /* extsw & extsw. */
1282 GEN_LOGICAL1(extsw, 0x1E, PPC_64B);
1284 GEN_LOGICAL1(cntlzd, 0x01, PPC_64B);
1287 /*** Integer rotate ***/
1288 /* rlwimi & rlwimi. */
1289 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1292 uint32_t mb, me, sh;
1294 mb = MB(ctx->opcode);
1295 me = ME(ctx->opcode);
1296 sh = SH(ctx->opcode);
1297 if (likely(sh == 0)) {
1298 if (likely(mb == 0 && me == 31)) {
1299 gen_op_load_gpr_T0(rS(ctx->opcode));
1301 } else if (likely(mb == 31 && me == 0)) {
1302 gen_op_load_gpr_T0(rA(ctx->opcode));
1305 gen_op_load_gpr_T0(rS(ctx->opcode));
1306 gen_op_load_gpr_T1(rA(ctx->opcode));
1309 gen_op_load_gpr_T0(rS(ctx->opcode));
1310 gen_op_load_gpr_T1(rA(ctx->opcode));
1311 gen_op_rotli32_T0(SH(ctx->opcode));
1313 #if defined(TARGET_PPC64)
1317 mask = MASK(mb, me);
1318 gen_op_andi_T0(mask);
1319 gen_op_andi_T1(~mask);
1322 gen_op_store_T0_gpr(rA(ctx->opcode));
1323 if (unlikely(Rc(ctx->opcode) != 0))
1326 /* rlwinm & rlwinm. */
1327 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1329 uint32_t mb, me, sh;
1331 sh = SH(ctx->opcode);
1332 mb = MB(ctx->opcode);
1333 me = ME(ctx->opcode);
1334 gen_op_load_gpr_T0(rS(ctx->opcode));
1335 if (likely(sh == 0)) {
1338 if (likely(mb == 0)) {
1339 if (likely(me == 31)) {
1340 gen_op_rotli32_T0(sh);
1342 } else if (likely(me == (31 - sh))) {
1346 } else if (likely(me == 31)) {
1347 if (likely(sh == (32 - mb))) {
1352 gen_op_rotli32_T0(sh);
1354 #if defined(TARGET_PPC64)
1358 gen_op_andi_T0(MASK(mb, me));
1360 gen_op_store_T0_gpr(rA(ctx->opcode));
1361 if (unlikely(Rc(ctx->opcode) != 0))
1364 /* rlwnm & rlwnm. */
1365 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1369 mb = MB(ctx->opcode);
1370 me = ME(ctx->opcode);
1371 gen_op_load_gpr_T0(rS(ctx->opcode));
1372 gen_op_load_gpr_T1(rB(ctx->opcode));
1373 gen_op_rotl32_T0_T1();
1374 if (unlikely(mb != 0 || me != 31)) {
1375 #if defined(TARGET_PPC64)
1379 gen_op_andi_T0(MASK(mb, me));
1381 gen_op_store_T0_gpr(rA(ctx->opcode));
1382 if (unlikely(Rc(ctx->opcode) != 0))
1386 #if defined(TARGET_PPC64)
1387 #define GEN_PPC64_R2(name, opc1, opc2) \
1388 GEN_HANDLER(name##0, opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1390 gen_##name(ctx, 0); \
1392 GEN_HANDLER(name##1, opc1, opc2 | 0x10, 0xFF, 0x00000000, PPC_64B) \
1394 gen_##name(ctx, 1); \
1396 #define GEN_PPC64_R4(name, opc1, opc2) \
1397 GEN_HANDLER(name##0, opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1399 gen_##name(ctx, 0, 0); \
1401 GEN_HANDLER(name##1, opc1, opc2 | 0x01, 0xFF, 0x00000000, PPC_64B) \
1403 gen_##name(ctx, 0, 1); \
1405 GEN_HANDLER(name##2, opc1, opc2 | 0x10, 0xFF, 0x00000000, PPC_64B) \
1407 gen_##name(ctx, 1, 0); \
1409 GEN_HANDLER(name##3, opc1, opc2 | 0x11, 0xFF, 0x00000000, PPC_64B) \
1411 gen_##name(ctx, 1, 1); \
1414 static always_inline void gen_andi_T0_64 (DisasContext *ctx, uint64_t mask)
1417 gen_op_andi_T0_64(mask >> 32, mask & 0xFFFFFFFF);
1419 gen_op_andi_T0(mask);
1422 static always_inline void gen_andi_T1_64 (DisasContext *ctx, uint64_t mask)
1425 gen_op_andi_T1_64(mask >> 32, mask & 0xFFFFFFFF);
1427 gen_op_andi_T1(mask);
1430 static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1431 uint32_t me, uint32_t sh)
1433 gen_op_load_gpr_T0(rS(ctx->opcode));
1434 if (likely(sh == 0)) {
1437 if (likely(mb == 0)) {
1438 if (likely(me == 63)) {
1439 gen_op_rotli64_T0(sh);
1441 } else if (likely(me == (63 - sh))) {
1445 } else if (likely(me == 63)) {
1446 if (likely(sh == (64 - mb))) {
1447 gen_op_srli_T0_64(mb);
1451 gen_op_rotli64_T0(sh);
1453 gen_andi_T0_64(ctx, MASK(mb, me));
1455 gen_op_store_T0_gpr(rA(ctx->opcode));
1456 if (unlikely(Rc(ctx->opcode) != 0))
1459 /* rldicl - rldicl. */
1460 static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
1464 sh = SH(ctx->opcode) | (shn << 5);
1465 mb = MB(ctx->opcode) | (mbn << 5);
1466 gen_rldinm(ctx, mb, 63, sh);
1468 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1469 /* rldicr - rldicr. */
1470 static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
1474 sh = SH(ctx->opcode) | (shn << 5);
1475 me = MB(ctx->opcode) | (men << 5);
1476 gen_rldinm(ctx, 0, me, sh);
1478 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1479 /* rldic - rldic. */
1480 static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
1484 sh = SH(ctx->opcode) | (shn << 5);
1485 mb = MB(ctx->opcode) | (mbn << 5);
1486 gen_rldinm(ctx, mb, 63 - sh, sh);
1488 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1490 static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1493 gen_op_load_gpr_T0(rS(ctx->opcode));
1494 gen_op_load_gpr_T1(rB(ctx->opcode));
1495 gen_op_rotl64_T0_T1();
1496 if (unlikely(mb != 0 || me != 63)) {
1497 gen_andi_T0_64(ctx, MASK(mb, me));
1499 gen_op_store_T0_gpr(rA(ctx->opcode));
1500 if (unlikely(Rc(ctx->opcode) != 0))
1504 /* rldcl - rldcl. */
1505 static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
1509 mb = MB(ctx->opcode) | (mbn << 5);
1510 gen_rldnm(ctx, mb, 63);
1512 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1513 /* rldcr - rldcr. */
1514 static always_inline void gen_rldcr (DisasContext *ctx, int men)
1518 me = MB(ctx->opcode) | (men << 5);
1519 gen_rldnm(ctx, 0, me);
1521 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1522 /* rldimi - rldimi. */
1523 static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
1528 sh = SH(ctx->opcode) | (shn << 5);
1529 mb = MB(ctx->opcode) | (mbn << 5);
1530 if (likely(sh == 0)) {
1531 if (likely(mb == 0)) {
1532 gen_op_load_gpr_T0(rS(ctx->opcode));
1534 } else if (likely(mb == 63)) {
1535 gen_op_load_gpr_T0(rA(ctx->opcode));
1538 gen_op_load_gpr_T0(rS(ctx->opcode));
1539 gen_op_load_gpr_T1(rA(ctx->opcode));
1542 gen_op_load_gpr_T0(rS(ctx->opcode));
1543 gen_op_load_gpr_T1(rA(ctx->opcode));
1544 gen_op_rotli64_T0(sh);
1546 mask = MASK(mb, 63 - sh);
1547 gen_andi_T0_64(ctx, mask);
1548 gen_andi_T1_64(ctx, ~mask);
1551 gen_op_store_T0_gpr(rA(ctx->opcode));
1552 if (unlikely(Rc(ctx->opcode) != 0))
1555 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1558 /*** Integer shift ***/
1560 __GEN_LOGICAL2(slw, 0x18, 0x00, PPC_INTEGER);
1562 __GEN_LOGICAL2(sraw, 0x18, 0x18, PPC_INTEGER);
1563 /* srawi & srawi. */
1564 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1567 gen_op_load_gpr_T0(rS(ctx->opcode));
1568 if (SH(ctx->opcode) != 0) {
1569 gen_op_move_T1_T0();
1570 mb = 32 - SH(ctx->opcode);
1572 #if defined(TARGET_PPC64)
1576 gen_op_srawi(SH(ctx->opcode), MASK(mb, me));
1578 gen_op_store_T0_gpr(rA(ctx->opcode));
1579 if (unlikely(Rc(ctx->opcode) != 0))
1583 __GEN_LOGICAL2(srw, 0x18, 0x10, PPC_INTEGER);
1585 #if defined(TARGET_PPC64)
1587 __GEN_LOGICAL2(sld, 0x1B, 0x00, PPC_64B);
1589 __GEN_LOGICAL2(srad, 0x1A, 0x18, PPC_64B);
1590 /* sradi & sradi. */
1591 static always_inline void gen_sradi (DisasContext *ctx, int n)
1596 gen_op_load_gpr_T0(rS(ctx->opcode));
1597 sh = SH(ctx->opcode) + (n << 5);
1599 gen_op_move_T1_T0();
1600 mb = 64 - SH(ctx->opcode);
1602 mask = MASK(mb, me);
1603 gen_op_sradi(sh, mask >> 32, mask);
1605 gen_op_store_T0_gpr(rA(ctx->opcode));
1606 if (unlikely(Rc(ctx->opcode) != 0))
1609 GEN_HANDLER(sradi0, 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
1613 GEN_HANDLER(sradi1, 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
1618 __GEN_LOGICAL2(srd, 0x1B, 0x10, PPC_64B);
1621 /*** Floating-Point arithmetic ***/
1622 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, type) \
1623 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
1625 if (unlikely(!ctx->fpu_enabled)) { \
1626 GEN_EXCP_NO_FP(ctx); \
1629 gen_op_reset_scrfx(); \
1630 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1631 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
1632 gen_op_load_fpr_FT2(rB(ctx->opcode)); \
1637 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1638 if (unlikely(Rc(ctx->opcode) != 0)) \
1642 #define GEN_FLOAT_ACB(name, op2, type) \
1643 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, type); \
1644 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, type);
1646 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat) \
1647 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \
1649 if (unlikely(!ctx->fpu_enabled)) { \
1650 GEN_EXCP_NO_FP(ctx); \
1653 gen_op_reset_scrfx(); \
1654 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1655 gen_op_load_fpr_FT1(rB(ctx->opcode)); \
1660 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1661 if (unlikely(Rc(ctx->opcode) != 0)) \
1664 #define GEN_FLOAT_AB(name, op2, inval) \
1665 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0); \
1666 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1);
1668 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat) \
1669 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \
1671 if (unlikely(!ctx->fpu_enabled)) { \
1672 GEN_EXCP_NO_FP(ctx); \
1675 gen_op_reset_scrfx(); \
1676 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1677 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
1682 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1683 if (unlikely(Rc(ctx->opcode) != 0)) \
1686 #define GEN_FLOAT_AC(name, op2, inval) \
1687 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0); \
1688 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1);
1690 #define GEN_FLOAT_B(name, op2, op3, type) \
1691 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
1693 if (unlikely(!ctx->fpu_enabled)) { \
1694 GEN_EXCP_NO_FP(ctx); \
1697 gen_op_reset_scrfx(); \
1698 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
1700 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1701 if (unlikely(Rc(ctx->opcode) != 0)) \
1705 #define GEN_FLOAT_BS(name, op1, op2, type) \
1706 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
1708 if (unlikely(!ctx->fpu_enabled)) { \
1709 GEN_EXCP_NO_FP(ctx); \
1712 gen_op_reset_scrfx(); \
1713 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
1715 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1716 if (unlikely(Rc(ctx->opcode) != 0)) \
1721 GEN_FLOAT_AB(add, 0x15, 0x000007C0);
1723 GEN_FLOAT_AB(div, 0x12, 0x000007C0);
1725 GEN_FLOAT_AC(mul, 0x19, 0x0000F800);
1728 GEN_FLOAT_BS(re, 0x3F, 0x18, PPC_FLOAT_EXT);
1731 GEN_FLOAT_BS(res, 0x3B, 0x18, PPC_FLOAT_FRES);
1734 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, PPC_FLOAT_FRSQRTE);
1737 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, PPC_FLOAT_FSEL);
1739 GEN_FLOAT_AB(sub, 0x14, 0x000007C0);
1742 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
1744 if (unlikely(!ctx->fpu_enabled)) {
1745 GEN_EXCP_NO_FP(ctx);
1748 gen_op_reset_scrfx();
1749 gen_op_load_fpr_FT0(rB(ctx->opcode));
1751 gen_op_store_FT0_fpr(rD(ctx->opcode));
1752 if (unlikely(Rc(ctx->opcode) != 0))
1756 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
1758 if (unlikely(!ctx->fpu_enabled)) {
1759 GEN_EXCP_NO_FP(ctx);
1762 gen_op_reset_scrfx();
1763 gen_op_load_fpr_FT0(rB(ctx->opcode));
1766 gen_op_store_FT0_fpr(rD(ctx->opcode));
1767 if (unlikely(Rc(ctx->opcode) != 0))
1771 /*** Floating-Point multiply-and-add ***/
1772 /* fmadd - fmadds */
1773 GEN_FLOAT_ACB(madd, 0x1D, PPC_FLOAT);
1774 /* fmsub - fmsubs */
1775 GEN_FLOAT_ACB(msub, 0x1C, PPC_FLOAT);
1776 /* fnmadd - fnmadds */
1777 GEN_FLOAT_ACB(nmadd, 0x1F, PPC_FLOAT);
1778 /* fnmsub - fnmsubs */
1779 GEN_FLOAT_ACB(nmsub, 0x1E, PPC_FLOAT);
1781 /*** Floating-Point round & convert ***/
1783 GEN_FLOAT_B(ctiw, 0x0E, 0x00, PPC_FLOAT);
1785 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, PPC_FLOAT);
1787 GEN_FLOAT_B(rsp, 0x0C, 0x00, PPC_FLOAT);
1788 #if defined(TARGET_PPC64)
1790 GEN_FLOAT_B(cfid, 0x0E, 0x1A, PPC_64B);
1792 GEN_FLOAT_B(ctid, 0x0E, 0x19, PPC_64B);
1794 GEN_FLOAT_B(ctidz, 0x0F, 0x19, PPC_64B);
1798 GEN_FLOAT_B(rin, 0x08, 0x0C, PPC_FLOAT_EXT);
1800 GEN_FLOAT_B(riz, 0x08, 0x0D, PPC_FLOAT_EXT);
1802 GEN_FLOAT_B(rip, 0x08, 0x0E, PPC_FLOAT_EXT);
1804 GEN_FLOAT_B(rim, 0x08, 0x0F, PPC_FLOAT_EXT);
1806 /*** Floating-Point compare ***/
1808 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
1810 if (unlikely(!ctx->fpu_enabled)) {
1811 GEN_EXCP_NO_FP(ctx);
1814 gen_op_reset_scrfx();
1815 gen_op_load_fpr_FT0(rA(ctx->opcode));
1816 gen_op_load_fpr_FT1(rB(ctx->opcode));
1818 gen_op_store_T0_crf(crfD(ctx->opcode));
1822 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
1824 if (unlikely(!ctx->fpu_enabled)) {
1825 GEN_EXCP_NO_FP(ctx);
1828 gen_op_reset_scrfx();
1829 gen_op_load_fpr_FT0(rA(ctx->opcode));
1830 gen_op_load_fpr_FT1(rB(ctx->opcode));
1832 gen_op_store_T0_crf(crfD(ctx->opcode));
1835 /*** Floating-point move ***/
1837 GEN_FLOAT_B(abs, 0x08, 0x08, PPC_FLOAT);
1840 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
1842 if (unlikely(!ctx->fpu_enabled)) {
1843 GEN_EXCP_NO_FP(ctx);
1846 gen_op_reset_scrfx();
1847 gen_op_load_fpr_FT0(rB(ctx->opcode));
1848 gen_op_store_FT0_fpr(rD(ctx->opcode));
1849 if (unlikely(Rc(ctx->opcode) != 0))
1854 GEN_FLOAT_B(nabs, 0x08, 0x04, PPC_FLOAT);
1856 GEN_FLOAT_B(neg, 0x08, 0x01, PPC_FLOAT);
1858 /*** Floating-Point status & ctrl register ***/
1860 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
1862 if (unlikely(!ctx->fpu_enabled)) {
1863 GEN_EXCP_NO_FP(ctx);
1866 gen_op_load_fpscr_T0(crfS(ctx->opcode));
1867 gen_op_store_T0_crf(crfD(ctx->opcode));
1868 gen_op_clear_fpscr(crfS(ctx->opcode));
1872 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
1874 if (unlikely(!ctx->fpu_enabled)) {
1875 GEN_EXCP_NO_FP(ctx);
1878 gen_op_load_fpscr();
1879 gen_op_store_FT0_fpr(rD(ctx->opcode));
1880 if (unlikely(Rc(ctx->opcode) != 0))
1885 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
1889 if (unlikely(!ctx->fpu_enabled)) {
1890 GEN_EXCP_NO_FP(ctx);
1893 crb = crbD(ctx->opcode) >> 2;
1894 gen_op_load_fpscr_T0(crb);
1895 gen_op_andi_T0(~(1 << (crbD(ctx->opcode) & 0x03)));
1896 gen_op_store_T0_fpscr(crb);
1897 if (unlikely(Rc(ctx->opcode) != 0))
1902 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
1906 if (unlikely(!ctx->fpu_enabled)) {
1907 GEN_EXCP_NO_FP(ctx);
1910 crb = crbD(ctx->opcode) >> 2;
1911 gen_op_load_fpscr_T0(crb);
1912 gen_op_ori(1 << (crbD(ctx->opcode) & 0x03));
1913 gen_op_store_T0_fpscr(crb);
1914 if (unlikely(Rc(ctx->opcode) != 0))
1919 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
1921 if (unlikely(!ctx->fpu_enabled)) {
1922 GEN_EXCP_NO_FP(ctx);
1925 gen_op_load_fpr_FT0(rB(ctx->opcode));
1926 gen_op_store_fpscr(FM(ctx->opcode));
1927 if (unlikely(Rc(ctx->opcode) != 0))
1932 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
1934 if (unlikely(!ctx->fpu_enabled)) {
1935 GEN_EXCP_NO_FP(ctx);
1938 gen_op_store_T0_fpscri(crbD(ctx->opcode) >> 2, FPIMM(ctx->opcode));
1939 if (unlikely(Rc(ctx->opcode) != 0))
1943 /*** Addressing modes ***/
1944 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
1945 static always_inline void gen_addr_imm_index (DisasContext *ctx,
1948 target_long simm = SIMM(ctx->opcode);
1951 if (rA(ctx->opcode) == 0) {
1954 gen_op_load_gpr_T0(rA(ctx->opcode));
1955 if (likely(simm != 0))
1958 #ifdef DEBUG_MEMORY_ACCESSES
1959 gen_op_print_mem_EA();
1963 static always_inline void gen_addr_reg_index (DisasContext *ctx)
1965 if (rA(ctx->opcode) == 0) {
1966 gen_op_load_gpr_T0(rB(ctx->opcode));
1968 gen_op_load_gpr_T0(rA(ctx->opcode));
1969 gen_op_load_gpr_T1(rB(ctx->opcode));
1972 #ifdef DEBUG_MEMORY_ACCESSES
1973 gen_op_print_mem_EA();
1977 static always_inline void gen_addr_register (DisasContext *ctx)
1979 if (rA(ctx->opcode) == 0) {
1982 gen_op_load_gpr_T0(rA(ctx->opcode));
1984 #ifdef DEBUG_MEMORY_ACCESSES
1985 gen_op_print_mem_EA();
1989 /*** Integer load ***/
1990 #define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
1991 #if defined(CONFIG_USER_ONLY)
1992 #if defined(TARGET_PPC64)
1993 /* User mode only - 64 bits */
1994 #define OP_LD_TABLE(width) \
1995 static GenOpFunc *gen_op_l##width[] = { \
1996 &gen_op_l##width##_raw, \
1997 &gen_op_l##width##_le_raw, \
1998 &gen_op_l##width##_64_raw, \
1999 &gen_op_l##width##_le_64_raw, \
2001 #define OP_ST_TABLE(width) \
2002 static GenOpFunc *gen_op_st##width[] = { \
2003 &gen_op_st##width##_raw, \
2004 &gen_op_st##width##_le_raw, \
2005 &gen_op_st##width##_64_raw, \
2006 &gen_op_st##width##_le_64_raw, \
2008 /* Byte access routine are endian safe */
2009 #define gen_op_stb_le_64_raw gen_op_stb_64_raw
2010 #define gen_op_lbz_le_64_raw gen_op_lbz_64_raw
2012 /* User mode only - 32 bits */
2013 #define OP_LD_TABLE(width) \
2014 static GenOpFunc *gen_op_l##width[] = { \
2015 &gen_op_l##width##_raw, \
2016 &gen_op_l##width##_le_raw, \
2018 #define OP_ST_TABLE(width) \
2019 static GenOpFunc *gen_op_st##width[] = { \
2020 &gen_op_st##width##_raw, \
2021 &gen_op_st##width##_le_raw, \
2024 /* Byte access routine are endian safe */
2025 #define gen_op_stb_le_raw gen_op_stb_raw
2026 #define gen_op_lbz_le_raw gen_op_lbz_raw
2028 #if defined(TARGET_PPC64)
2029 #if defined(TARGET_PPC64H)
2030 /* Full system - 64 bits with hypervisor mode */
2031 #define OP_LD_TABLE(width) \
2032 static GenOpFunc *gen_op_l##width[] = { \
2033 &gen_op_l##width##_user, \
2034 &gen_op_l##width##_le_user, \
2035 &gen_op_l##width##_64_user, \
2036 &gen_op_l##width##_le_64_user, \
2037 &gen_op_l##width##_kernel, \
2038 &gen_op_l##width##_le_kernel, \
2039 &gen_op_l##width##_64_kernel, \
2040 &gen_op_l##width##_le_64_kernel, \
2041 &gen_op_l##width##_hypv, \
2042 &gen_op_l##width##_le_hypv, \
2043 &gen_op_l##width##_64_hypv, \
2044 &gen_op_l##width##_le_64_hypv, \
2046 #define OP_ST_TABLE(width) \
2047 static GenOpFunc *gen_op_st##width[] = { \
2048 &gen_op_st##width##_user, \
2049 &gen_op_st##width##_le_user, \
2050 &gen_op_st##width##_64_user, \
2051 &gen_op_st##width##_le_64_user, \
2052 &gen_op_st##width##_kernel, \
2053 &gen_op_st##width##_le_kernel, \
2054 &gen_op_st##width##_64_kernel, \
2055 &gen_op_st##width##_le_64_kernel, \
2056 &gen_op_st##width##_hypv, \
2057 &gen_op_st##width##_le_hypv, \
2058 &gen_op_st##width##_64_hypv, \
2059 &gen_op_st##width##_le_64_hypv, \
2061 /* Byte access routine are endian safe */
2062 #define gen_op_stb_le_hypv gen_op_stb_64_hypv
2063 #define gen_op_lbz_le_hypv gen_op_lbz_64_hypv
2064 #define gen_op_stb_le_64_hypv gen_op_stb_64_hypv
2065 #define gen_op_lbz_le_64_hypv gen_op_lbz_64_hypv
2067 /* Full system - 64 bits */
2068 #define OP_LD_TABLE(width) \
2069 static GenOpFunc *gen_op_l##width[] = { \
2070 &gen_op_l##width##_user, \
2071 &gen_op_l##width##_le_user, \
2072 &gen_op_l##width##_64_user, \
2073 &gen_op_l##width##_le_64_user, \
2074 &gen_op_l##width##_kernel, \
2075 &gen_op_l##width##_le_kernel, \
2076 &gen_op_l##width##_64_kernel, \
2077 &gen_op_l##width##_le_64_kernel, \
2079 #define OP_ST_TABLE(width) \
2080 static GenOpFunc *gen_op_st##width[] = { \
2081 &gen_op_st##width##_user, \
2082 &gen_op_st##width##_le_user, \
2083 &gen_op_st##width##_64_user, \
2084 &gen_op_st##width##_le_64_user, \
2085 &gen_op_st##width##_kernel, \
2086 &gen_op_st##width##_le_kernel, \
2087 &gen_op_st##width##_64_kernel, \
2088 &gen_op_st##width##_le_64_kernel, \
2091 /* Byte access routine are endian safe */
2092 #define gen_op_stb_le_64_user gen_op_stb_64_user
2093 #define gen_op_lbz_le_64_user gen_op_lbz_64_user
2094 #define gen_op_stb_le_64_kernel gen_op_stb_64_kernel
2095 #define gen_op_lbz_le_64_kernel gen_op_lbz_64_kernel
2097 /* Full system - 32 bits */
2098 #define OP_LD_TABLE(width) \
2099 static GenOpFunc *gen_op_l##width[] = { \
2100 &gen_op_l##width##_user, \
2101 &gen_op_l##width##_le_user, \
2102 &gen_op_l##width##_kernel, \
2103 &gen_op_l##width##_le_kernel, \
2105 #define OP_ST_TABLE(width) \
2106 static GenOpFunc *gen_op_st##width[] = { \
2107 &gen_op_st##width##_user, \
2108 &gen_op_st##width##_le_user, \
2109 &gen_op_st##width##_kernel, \
2110 &gen_op_st##width##_le_kernel, \
2113 /* Byte access routine are endian safe */
2114 #define gen_op_stb_le_user gen_op_stb_user
2115 #define gen_op_lbz_le_user gen_op_lbz_user
2116 #define gen_op_stb_le_kernel gen_op_stb_kernel
2117 #define gen_op_lbz_le_kernel gen_op_lbz_kernel
2120 #define GEN_LD(width, opc, type) \
2121 GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
2123 gen_addr_imm_index(ctx, 0); \
2124 op_ldst(l##width); \
2125 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2128 #define GEN_LDU(width, opc, type) \
2129 GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2131 if (unlikely(rA(ctx->opcode) == 0 || \
2132 rA(ctx->opcode) == rD(ctx->opcode))) { \
2133 GEN_EXCP_INVAL(ctx); \
2136 if (type == PPC_64B) \
2137 gen_addr_imm_index(ctx, 0x03); \
2139 gen_addr_imm_index(ctx, 0); \
2140 op_ldst(l##width); \
2141 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2142 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2145 #define GEN_LDUX(width, opc2, opc3, type) \
2146 GEN_HANDLER(l##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2148 if (unlikely(rA(ctx->opcode) == 0 || \
2149 rA(ctx->opcode) == rD(ctx->opcode))) { \
2150 GEN_EXCP_INVAL(ctx); \
2153 gen_addr_reg_index(ctx); \
2154 op_ldst(l##width); \
2155 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2156 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2159 #define GEN_LDX(width, opc2, opc3, type) \
2160 GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
2162 gen_addr_reg_index(ctx); \
2163 op_ldst(l##width); \
2164 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2167 #define GEN_LDS(width, op, type) \
2168 OP_LD_TABLE(width); \
2169 GEN_LD(width, op | 0x20, type); \
2170 GEN_LDU(width, op | 0x21, type); \
2171 GEN_LDUX(width, 0x17, op | 0x01, type); \
2172 GEN_LDX(width, 0x17, op | 0x00, type)
2174 /* lbz lbzu lbzux lbzx */
2175 GEN_LDS(bz, 0x02, PPC_INTEGER);
2176 /* lha lhau lhaux lhax */
2177 GEN_LDS(ha, 0x0A, PPC_INTEGER);
2178 /* lhz lhzu lhzux lhzx */
2179 GEN_LDS(hz, 0x08, PPC_INTEGER);
2180 /* lwz lwzu lwzux lwzx */
2181 GEN_LDS(wz, 0x00, PPC_INTEGER);
2182 #if defined(TARGET_PPC64)
2186 GEN_LDUX(wa, 0x15, 0x0B, PPC_64B);
2188 GEN_LDX(wa, 0x15, 0x0A, PPC_64B);
2190 GEN_LDUX(d, 0x15, 0x01, PPC_64B);
2192 GEN_LDX(d, 0x15, 0x00, PPC_64B);
2193 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2195 if (Rc(ctx->opcode)) {
2196 if (unlikely(rA(ctx->opcode) == 0 ||
2197 rA(ctx->opcode) == rD(ctx->opcode))) {
2198 GEN_EXCP_INVAL(ctx);
2202 gen_addr_imm_index(ctx, 0x03);
2203 if (ctx->opcode & 0x02) {
2204 /* lwa (lwau is undefined) */
2210 gen_op_store_T1_gpr(rD(ctx->opcode));
2211 if (Rc(ctx->opcode))
2212 gen_op_store_T0_gpr(rA(ctx->opcode));
2215 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2217 #if defined(CONFIG_USER_ONLY)
2218 GEN_EXCP_PRIVOPC(ctx);
2222 /* Restore CPU state */
2223 if (unlikely(ctx->supervisor == 0)) {
2224 GEN_EXCP_PRIVOPC(ctx);
2227 ra = rA(ctx->opcode);
2228 rd = rD(ctx->opcode);
2229 if (unlikely((rd & 1) || rd == ra)) {
2230 GEN_EXCP_INVAL(ctx);
2233 if (unlikely(ctx->mem_idx & 1)) {
2234 /* Little-endian mode is not handled */
2235 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2238 gen_addr_imm_index(ctx, 0x0F);
2240 gen_op_store_T1_gpr(rd);
2243 gen_op_store_T1_gpr(rd + 1);
2248 /*** Integer store ***/
2249 #define GEN_ST(width, opc, type) \
2250 GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
2252 gen_addr_imm_index(ctx, 0); \
2253 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2254 op_ldst(st##width); \
2257 #define GEN_STU(width, opc, type) \
2258 GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2260 if (unlikely(rA(ctx->opcode) == 0)) { \
2261 GEN_EXCP_INVAL(ctx); \
2264 if (type == PPC_64B) \
2265 gen_addr_imm_index(ctx, 0x03); \
2267 gen_addr_imm_index(ctx, 0); \
2268 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2269 op_ldst(st##width); \
2270 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2273 #define GEN_STUX(width, opc2, opc3, type) \
2274 GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2276 if (unlikely(rA(ctx->opcode) == 0)) { \
2277 GEN_EXCP_INVAL(ctx); \
2280 gen_addr_reg_index(ctx); \
2281 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2282 op_ldst(st##width); \
2283 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2286 #define GEN_STX(width, opc2, opc3, type) \
2287 GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
2289 gen_addr_reg_index(ctx); \
2290 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2291 op_ldst(st##width); \
2294 #define GEN_STS(width, op, type) \
2295 OP_ST_TABLE(width); \
2296 GEN_ST(width, op | 0x20, type); \
2297 GEN_STU(width, op | 0x21, type); \
2298 GEN_STUX(width, 0x17, op | 0x01, type); \
2299 GEN_STX(width, 0x17, op | 0x00, type)
2301 /* stb stbu stbux stbx */
2302 GEN_STS(b, 0x06, PPC_INTEGER);
2303 /* sth sthu sthux sthx */
2304 GEN_STS(h, 0x0C, PPC_INTEGER);
2305 /* stw stwu stwux stwx */
2306 GEN_STS(w, 0x04, PPC_INTEGER);
2307 #if defined(TARGET_PPC64)
2309 GEN_STUX(d, 0x15, 0x05, PPC_64B);
2310 GEN_STX(d, 0x15, 0x04, PPC_64B);
2311 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
2315 rs = rS(ctx->opcode);
2316 if ((ctx->opcode & 0x3) == 0x2) {
2317 #if defined(CONFIG_USER_ONLY)
2318 GEN_EXCP_PRIVOPC(ctx);
2321 if (unlikely(ctx->supervisor == 0)) {
2322 GEN_EXCP_PRIVOPC(ctx);
2325 if (unlikely(rs & 1)) {
2326 GEN_EXCP_INVAL(ctx);
2329 if (unlikely(ctx->mem_idx & 1)) {
2330 /* Little-endian mode is not handled */
2331 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2334 gen_addr_imm_index(ctx, 0x03);
2335 gen_op_load_gpr_T1(rs);
2338 gen_op_load_gpr_T1(rs + 1);
2343 if (Rc(ctx->opcode)) {
2344 if (unlikely(rA(ctx->opcode) == 0)) {
2345 GEN_EXCP_INVAL(ctx);
2349 gen_addr_imm_index(ctx, 0x03);
2350 gen_op_load_gpr_T1(rs);
2352 if (Rc(ctx->opcode))
2353 gen_op_store_T0_gpr(rA(ctx->opcode));
2357 /*** Integer load and store with byte reverse ***/
2360 GEN_LDX(hbr, 0x16, 0x18, PPC_INTEGER);
2363 GEN_LDX(wbr, 0x16, 0x10, PPC_INTEGER);
2366 GEN_STX(hbr, 0x16, 0x1C, PPC_INTEGER);
2369 GEN_STX(wbr, 0x16, 0x14, PPC_INTEGER);
2371 /*** Integer load and store multiple ***/
2372 #define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
2373 #if defined(CONFIG_USER_ONLY)
2374 /* User-mode only */
2375 static GenOpFunc1 *gen_op_lmw[] = {
2378 #if defined(TARGET_PPC64)
2380 &gen_op_lmw_le_64_raw,
2383 static GenOpFunc1 *gen_op_stmw[] = {
2385 &gen_op_stmw_le_raw,
2386 #if defined(TARGET_PPC64)
2387 &gen_op_stmw_64_raw,
2388 &gen_op_stmw_le_64_raw,
2392 #if defined(TARGET_PPC64)
2393 /* Full system - 64 bits mode */
2394 static GenOpFunc1 *gen_op_lmw[] = {
2396 &gen_op_lmw_le_user,
2397 &gen_op_lmw_64_user,
2398 &gen_op_lmw_le_64_user,
2400 &gen_op_lmw_le_kernel,
2401 &gen_op_lmw_64_kernel,
2402 &gen_op_lmw_le_64_kernel,
2403 #if defined(TARGET_PPC64H)
2405 &gen_op_lmw_le_hypv,
2406 &gen_op_lmw_64_hypv,
2407 &gen_op_lmw_le_64_hypv,
2410 static GenOpFunc1 *gen_op_stmw[] = {
2412 &gen_op_stmw_le_user,
2413 &gen_op_stmw_64_user,
2414 &gen_op_stmw_le_64_user,
2415 &gen_op_stmw_kernel,
2416 &gen_op_stmw_le_kernel,
2417 &gen_op_stmw_64_kernel,
2418 &gen_op_stmw_le_64_kernel,
2419 #if defined(TARGET_PPC64H)
2421 &gen_op_stmw_le_hypv,
2422 &gen_op_stmw_64_hypv,
2423 &gen_op_stmw_le_64_hypv,
2427 /* Full system - 32 bits mode */
2428 static GenOpFunc1 *gen_op_lmw[] = {
2430 &gen_op_lmw_le_user,
2432 &gen_op_lmw_le_kernel,
2434 static GenOpFunc1 *gen_op_stmw[] = {
2436 &gen_op_stmw_le_user,
2437 &gen_op_stmw_kernel,
2438 &gen_op_stmw_le_kernel,
2444 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
2446 /* NIP cannot be restored if the memory exception comes from an helper */
2447 gen_update_nip(ctx, ctx->nip - 4);
2448 gen_addr_imm_index(ctx, 0);
2449 op_ldstm(lmw, rD(ctx->opcode));
2453 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
2455 /* NIP cannot be restored if the memory exception comes from an helper */
2456 gen_update_nip(ctx, ctx->nip - 4);
2457 gen_addr_imm_index(ctx, 0);
2458 op_ldstm(stmw, rS(ctx->opcode));
2461 /*** Integer load and store strings ***/
2462 #define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
2463 #define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
2464 #if defined(CONFIG_USER_ONLY)
2465 /* User-mode only */
2466 static GenOpFunc1 *gen_op_lswi[] = {
2468 &gen_op_lswi_le_raw,
2469 #if defined(TARGET_PPC64)
2470 &gen_op_lswi_64_raw,
2471 &gen_op_lswi_le_64_raw,
2474 static GenOpFunc3 *gen_op_lswx[] = {
2476 &gen_op_lswx_le_raw,
2477 #if defined(TARGET_PPC64)
2478 &gen_op_lswx_64_raw,
2479 &gen_op_lswx_le_64_raw,
2482 static GenOpFunc1 *gen_op_stsw[] = {
2484 &gen_op_stsw_le_raw,
2485 #if defined(TARGET_PPC64)
2486 &gen_op_stsw_64_raw,
2487 &gen_op_stsw_le_64_raw,
2491 #if defined(TARGET_PPC64)
2492 /* Full system - 64 bits mode */
2493 static GenOpFunc1 *gen_op_lswi[] = {
2495 &gen_op_lswi_le_user,
2496 &gen_op_lswi_64_user,
2497 &gen_op_lswi_le_64_user,
2498 &gen_op_lswi_kernel,
2499 &gen_op_lswi_le_kernel,
2500 &gen_op_lswi_64_kernel,
2501 &gen_op_lswi_le_64_kernel,
2502 #if defined(TARGET_PPC64H)
2504 &gen_op_lswi_le_hypv,
2505 &gen_op_lswi_64_hypv,
2506 &gen_op_lswi_le_64_hypv,
2509 static GenOpFunc3 *gen_op_lswx[] = {
2511 &gen_op_lswx_le_user,
2512 &gen_op_lswx_64_user,
2513 &gen_op_lswx_le_64_user,
2514 &gen_op_lswx_kernel,
2515 &gen_op_lswx_le_kernel,
2516 &gen_op_lswx_64_kernel,
2517 &gen_op_lswx_le_64_kernel,
2518 #if defined(TARGET_PPC64H)
2520 &gen_op_lswx_le_hypv,
2521 &gen_op_lswx_64_hypv,
2522 &gen_op_lswx_le_64_hypv,
2525 static GenOpFunc1 *gen_op_stsw[] = {
2527 &gen_op_stsw_le_user,
2528 &gen_op_stsw_64_user,
2529 &gen_op_stsw_le_64_user,
2530 &gen_op_stsw_kernel,
2531 &gen_op_stsw_le_kernel,
2532 &gen_op_stsw_64_kernel,
2533 &gen_op_stsw_le_64_kernel,
2534 #if defined(TARGET_PPC64H)
2536 &gen_op_stsw_le_hypv,
2537 &gen_op_stsw_64_hypv,
2538 &gen_op_stsw_le_64_hypv,
2542 /* Full system - 32 bits mode */
2543 static GenOpFunc1 *gen_op_lswi[] = {
2545 &gen_op_lswi_le_user,
2546 &gen_op_lswi_kernel,
2547 &gen_op_lswi_le_kernel,
2549 static GenOpFunc3 *gen_op_lswx[] = {
2551 &gen_op_lswx_le_user,
2552 &gen_op_lswx_kernel,
2553 &gen_op_lswx_le_kernel,
2555 static GenOpFunc1 *gen_op_stsw[] = {
2557 &gen_op_stsw_le_user,
2558 &gen_op_stsw_kernel,
2559 &gen_op_stsw_le_kernel,
2565 /* PowerPC32 specification says we must generate an exception if
2566 * rA is in the range of registers to be loaded.
2567 * In an other hand, IBM says this is valid, but rA won't be loaded.
2568 * For now, I'll follow the spec...
2570 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_INTEGER)
2572 int nb = NB(ctx->opcode);
2573 int start = rD(ctx->opcode);
2574 int ra = rA(ctx->opcode);
2580 if (unlikely(((start + nr) > 32 &&
2581 start <= ra && (start + nr - 32) > ra) ||
2582 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
2583 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
2584 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_LSWX);
2587 /* NIP cannot be restored if the memory exception comes from an helper */
2588 gen_update_nip(ctx, ctx->nip - 4);
2589 gen_addr_register(ctx);
2591 op_ldsts(lswi, start);
2595 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_INTEGER)
2597 int ra = rA(ctx->opcode);
2598 int rb = rB(ctx->opcode);
2600 /* NIP cannot be restored if the memory exception comes from an helper */
2601 gen_update_nip(ctx, ctx->nip - 4);
2602 gen_addr_reg_index(ctx);
2606 gen_op_load_xer_bc();
2607 op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
2611 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_INTEGER)
2613 int nb = NB(ctx->opcode);
2615 /* NIP cannot be restored if the memory exception comes from an helper */
2616 gen_update_nip(ctx, ctx->nip - 4);
2617 gen_addr_register(ctx);
2621 op_ldsts(stsw, rS(ctx->opcode));
2625 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_INTEGER)
2627 /* NIP cannot be restored if the memory exception comes from an helper */
2628 gen_update_nip(ctx, ctx->nip - 4);
2629 gen_addr_reg_index(ctx);
2630 gen_op_load_xer_bc();
2631 op_ldsts(stsw, rS(ctx->opcode));
2634 /*** Memory synchronisation ***/
2636 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
2641 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
2646 #define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
2647 #define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
2648 #if defined(CONFIG_USER_ONLY)
2649 /* User-mode only */
2650 static GenOpFunc *gen_op_lwarx[] = {
2652 &gen_op_lwarx_le_raw,
2653 #if defined(TARGET_PPC64)
2654 &gen_op_lwarx_64_raw,
2655 &gen_op_lwarx_le_64_raw,
2658 static GenOpFunc *gen_op_stwcx[] = {
2660 &gen_op_stwcx_le_raw,
2661 #if defined(TARGET_PPC64)
2662 &gen_op_stwcx_64_raw,
2663 &gen_op_stwcx_le_64_raw,
2667 #if defined(TARGET_PPC64)
2668 /* Full system - 64 bits mode */
2669 static GenOpFunc *gen_op_lwarx[] = {
2671 &gen_op_lwarx_le_user,
2672 &gen_op_lwarx_64_user,
2673 &gen_op_lwarx_le_64_user,
2674 &gen_op_lwarx_kernel,
2675 &gen_op_lwarx_le_kernel,
2676 &gen_op_lwarx_64_kernel,
2677 &gen_op_lwarx_le_64_kernel,
2678 #if defined(TARGET_PPC64H)
2680 &gen_op_lwarx_le_hypv,
2681 &gen_op_lwarx_64_hypv,
2682 &gen_op_lwarx_le_64_hypv,
2685 static GenOpFunc *gen_op_stwcx[] = {
2687 &gen_op_stwcx_le_user,
2688 &gen_op_stwcx_64_user,
2689 &gen_op_stwcx_le_64_user,
2690 &gen_op_stwcx_kernel,
2691 &gen_op_stwcx_le_kernel,
2692 &gen_op_stwcx_64_kernel,
2693 &gen_op_stwcx_le_64_kernel,
2694 #if defined(TARGET_PPC64H)
2696 &gen_op_stwcx_le_hypv,
2697 &gen_op_stwcx_64_hypv,
2698 &gen_op_stwcx_le_64_hypv,
2702 /* Full system - 32 bits mode */
2703 static GenOpFunc *gen_op_lwarx[] = {
2705 &gen_op_lwarx_le_user,
2706 &gen_op_lwarx_kernel,
2707 &gen_op_lwarx_le_kernel,
2709 static GenOpFunc *gen_op_stwcx[] = {
2711 &gen_op_stwcx_le_user,
2712 &gen_op_stwcx_kernel,
2713 &gen_op_stwcx_le_kernel,
2719 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
2721 /* NIP cannot be restored if the memory exception comes from an helper */
2722 gen_update_nip(ctx, ctx->nip - 4);
2723 gen_addr_reg_index(ctx);
2725 gen_op_store_T1_gpr(rD(ctx->opcode));
2729 GEN_HANDLER(stwcx_, 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
2731 /* NIP cannot be restored if the memory exception comes from an helper */
2732 gen_update_nip(ctx, ctx->nip - 4);
2733 gen_addr_reg_index(ctx);
2734 gen_op_load_gpr_T1(rS(ctx->opcode));
2738 #if defined(TARGET_PPC64)
2739 #define op_ldarx() (*gen_op_ldarx[ctx->mem_idx])()
2740 #define op_stdcx() (*gen_op_stdcx[ctx->mem_idx])()
2741 #if defined(CONFIG_USER_ONLY)
2742 /* User-mode only */
2743 static GenOpFunc *gen_op_ldarx[] = {
2745 &gen_op_ldarx_le_raw,
2746 &gen_op_ldarx_64_raw,
2747 &gen_op_ldarx_le_64_raw,
2749 static GenOpFunc *gen_op_stdcx[] = {
2751 &gen_op_stdcx_le_raw,
2752 &gen_op_stdcx_64_raw,
2753 &gen_op_stdcx_le_64_raw,
2757 static GenOpFunc *gen_op_ldarx[] = {
2759 &gen_op_ldarx_le_user,
2760 &gen_op_ldarx_64_user,
2761 &gen_op_ldarx_le_64_user,
2762 &gen_op_ldarx_kernel,
2763 &gen_op_ldarx_le_kernel,
2764 &gen_op_ldarx_64_kernel,
2765 &gen_op_ldarx_le_64_kernel,
2766 #if defined(TARGET_PPC64H)
2768 &gen_op_ldarx_le_hypv,
2769 &gen_op_ldarx_64_hypv,
2770 &gen_op_ldarx_le_64_hypv,
2773 static GenOpFunc *gen_op_stdcx[] = {
2775 &gen_op_stdcx_le_user,
2776 &gen_op_stdcx_64_user,
2777 &gen_op_stdcx_le_64_user,
2778 &gen_op_stdcx_kernel,
2779 &gen_op_stdcx_le_kernel,
2780 &gen_op_stdcx_64_kernel,
2781 &gen_op_stdcx_le_64_kernel,
2782 #if defined(TARGET_PPC64H)
2784 &gen_op_stdcx_le_hypv,
2785 &gen_op_stdcx_64_hypv,
2786 &gen_op_stdcx_le_64_hypv,
2792 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
2794 /* NIP cannot be restored if the memory exception comes from an helper */
2795 gen_update_nip(ctx, ctx->nip - 4);
2796 gen_addr_reg_index(ctx);
2798 gen_op_store_T1_gpr(rD(ctx->opcode));
2802 GEN_HANDLER(stdcx_, 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
2804 /* NIP cannot be restored if the memory exception comes from an helper */
2805 gen_update_nip(ctx, ctx->nip - 4);
2806 gen_addr_reg_index(ctx);
2807 gen_op_load_gpr_T1(rS(ctx->opcode));
2810 #endif /* defined(TARGET_PPC64) */
2813 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
2818 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
2820 /* Stop translation, as the CPU is supposed to sleep from now */
2822 GEN_EXCP(ctx, EXCP_HLT, 1);
2825 /*** Floating-point load ***/
2826 #define GEN_LDF(width, opc, type) \
2827 GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
2829 if (unlikely(!ctx->fpu_enabled)) { \
2830 GEN_EXCP_NO_FP(ctx); \
2833 gen_addr_imm_index(ctx, 0); \
2834 op_ldst(l##width); \
2835 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
2838 #define GEN_LDUF(width, opc, type) \
2839 GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2841 if (unlikely(!ctx->fpu_enabled)) { \
2842 GEN_EXCP_NO_FP(ctx); \
2845 if (unlikely(rA(ctx->opcode) == 0)) { \
2846 GEN_EXCP_INVAL(ctx); \
2849 gen_addr_imm_index(ctx, 0); \
2850 op_ldst(l##width); \
2851 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
2852 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2855 #define GEN_LDUXF(width, opc, type) \
2856 GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
2858 if (unlikely(!ctx->fpu_enabled)) { \
2859 GEN_EXCP_NO_FP(ctx); \
2862 if (unlikely(rA(ctx->opcode) == 0)) { \
2863 GEN_EXCP_INVAL(ctx); \
2866 gen_addr_reg_index(ctx); \
2867 op_ldst(l##width); \
2868 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
2869 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2872 #define GEN_LDXF(width, opc2, opc3, type) \
2873 GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
2875 if (unlikely(!ctx->fpu_enabled)) { \
2876 GEN_EXCP_NO_FP(ctx); \
2879 gen_addr_reg_index(ctx); \
2880 op_ldst(l##width); \
2881 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
2884 #define GEN_LDFS(width, op, type) \
2885 OP_LD_TABLE(width); \
2886 GEN_LDF(width, op | 0x20, type); \
2887 GEN_LDUF(width, op | 0x21, type); \
2888 GEN_LDUXF(width, op | 0x01, type); \
2889 GEN_LDXF(width, 0x17, op | 0x00, type)
2891 /* lfd lfdu lfdux lfdx */
2892 GEN_LDFS(fd, 0x12, PPC_FLOAT);
2893 /* lfs lfsu lfsux lfsx */
2894 GEN_LDFS(fs, 0x10, PPC_FLOAT);
2896 /*** Floating-point store ***/
2897 #define GEN_STF(width, opc, type) \
2898 GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
2900 if (unlikely(!ctx->fpu_enabled)) { \
2901 GEN_EXCP_NO_FP(ctx); \
2904 gen_addr_imm_index(ctx, 0); \
2905 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
2906 op_ldst(st##width); \
2909 #define GEN_STUF(width, opc, type) \
2910 GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2912 if (unlikely(!ctx->fpu_enabled)) { \
2913 GEN_EXCP_NO_FP(ctx); \
2916 if (unlikely(rA(ctx->opcode) == 0)) { \
2917 GEN_EXCP_INVAL(ctx); \
2920 gen_addr_imm_index(ctx, 0); \
2921 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
2922 op_ldst(st##width); \
2923 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2926 #define GEN_STUXF(width, opc, type) \
2927 GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
2929 if (unlikely(!ctx->fpu_enabled)) { \
2930 GEN_EXCP_NO_FP(ctx); \
2933 if (unlikely(rA(ctx->opcode) == 0)) { \
2934 GEN_EXCP_INVAL(ctx); \
2937 gen_addr_reg_index(ctx); \
2938 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
2939 op_ldst(st##width); \
2940 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2943 #define GEN_STXF(width, opc2, opc3, type) \
2944 GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
2946 if (unlikely(!ctx->fpu_enabled)) { \
2947 GEN_EXCP_NO_FP(ctx); \
2950 gen_addr_reg_index(ctx); \
2951 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
2952 op_ldst(st##width); \
2955 #define GEN_STFS(width, op, type) \
2956 OP_ST_TABLE(width); \
2957 GEN_STF(width, op | 0x20, type); \
2958 GEN_STUF(width, op | 0x21, type); \
2959 GEN_STUXF(width, op | 0x01, type); \
2960 GEN_STXF(width, 0x17, op | 0x00, type)
2962 /* stfd stfdu stfdux stfdx */
2963 GEN_STFS(fd, 0x16, PPC_FLOAT);
2964 /* stfs stfsu stfsux stfsx */
2965 GEN_STFS(fs, 0x14, PPC_FLOAT);
2970 GEN_STXF(fiwx, 0x17, 0x1E, PPC_FLOAT_STFIWX);
2973 static always_inline void gen_goto_tb (DisasContext *ctx, int n,
2976 TranslationBlock *tb;
2978 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
2980 gen_op_goto_tb0(TBPARAM(tb));
2982 gen_op_goto_tb1(TBPARAM(tb));
2984 #if defined(TARGET_PPC64)
2990 gen_op_set_T0((long)tb + n);
2991 if (ctx->singlestep_enabled)
2996 #if defined(TARGET_PPC64)
3003 if (ctx->singlestep_enabled)
3009 static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
3011 #if defined(TARGET_PPC64)
3012 if (ctx->sf_mode != 0 && (nip >> 32))
3013 gen_op_setlr_64(ctx->nip >> 32, ctx->nip);
3016 gen_op_setlr(ctx->nip);
3020 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3022 target_ulong li, target;
3024 /* sign extend LI */
3025 #if defined(TARGET_PPC64)
3027 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3030 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
3031 if (likely(AA(ctx->opcode) == 0))
3032 target = ctx->nip + li - 4;
3035 #if defined(TARGET_PPC64)
3037 target = (uint32_t)target;
3039 if (LK(ctx->opcode))
3040 gen_setlr(ctx, ctx->nip);
3041 gen_goto_tb(ctx, 0, target);
3042 ctx->exception = POWERPC_EXCP_BRANCH;
3049 static always_inline void gen_bcond (DisasContext *ctx, int type)
3051 target_ulong target = 0;
3053 uint32_t bo = BO(ctx->opcode);
3054 uint32_t bi = BI(ctx->opcode);
3057 if ((bo & 0x4) == 0)
3061 li = (target_long)((int16_t)(BD(ctx->opcode)));
3062 if (likely(AA(ctx->opcode) == 0)) {
3063 target = ctx->nip + li - 4;
3067 #if defined(TARGET_PPC64)
3069 target = (uint32_t)target;
3073 gen_op_movl_T1_ctr();
3077 gen_op_movl_T1_lr();
3080 if (LK(ctx->opcode))
3081 gen_setlr(ctx, ctx->nip);
3083 /* No CR condition */
3086 #if defined(TARGET_PPC64)
3088 gen_op_test_ctr_64();
3094 #if defined(TARGET_PPC64)
3096 gen_op_test_ctrz_64();
3104 if (type == BCOND_IM) {
3105 gen_goto_tb(ctx, 0, target);
3108 #if defined(TARGET_PPC64)
3120 mask = 1 << (3 - (bi & 0x03));
3121 gen_op_load_crf_T0(bi >> 2);
3125 #if defined(TARGET_PPC64)
3127 gen_op_test_ctr_true_64(mask);
3130 gen_op_test_ctr_true(mask);
3133 #if defined(TARGET_PPC64)
3135 gen_op_test_ctrz_true_64(mask);
3138 gen_op_test_ctrz_true(mask);
3143 gen_op_test_true(mask);
3149 #if defined(TARGET_PPC64)
3151 gen_op_test_ctr_false_64(mask);
3154 gen_op_test_ctr_false(mask);
3157 #if defined(TARGET_PPC64)
3159 gen_op_test_ctrz_false_64(mask);
3162 gen_op_test_ctrz_false(mask);
3167 gen_op_test_false(mask);
3172 if (type == BCOND_IM) {
3173 int l1 = gen_new_label();
3175 gen_goto_tb(ctx, 0, target);
3177 gen_goto_tb(ctx, 1, ctx->nip);
3179 #if defined(TARGET_PPC64)
3181 gen_op_btest_T1_64(ctx->nip >> 32, ctx->nip);
3184 gen_op_btest_T1(ctx->nip);
3187 if (ctx->singlestep_enabled)
3192 ctx->exception = POWERPC_EXCP_BRANCH;
3195 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3197 gen_bcond(ctx, BCOND_IM);
3200 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3202 gen_bcond(ctx, BCOND_CTR);
3205 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3207 gen_bcond(ctx, BCOND_LR);
3210 /*** Condition register logical ***/
3211 #define GEN_CRLOGIC(op, opc) \
3212 GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
3214 gen_op_load_crf_T0(crbA(ctx->opcode) >> 2); \
3215 gen_op_getbit_T0(3 - (crbA(ctx->opcode) & 0x03)); \
3216 gen_op_load_crf_T1(crbB(ctx->opcode) >> 2); \
3217 gen_op_getbit_T1(3 - (crbB(ctx->opcode) & 0x03)); \
3219 gen_op_load_crf_T1(crbD(ctx->opcode) >> 2); \
3220 gen_op_setcrfbit(~(1 << (3 - (crbD(ctx->opcode) & 0x03))), \
3221 3 - (crbD(ctx->opcode) & 0x03)); \
3222 gen_op_store_T1_crf(crbD(ctx->opcode) >> 2); \
3226 GEN_CRLOGIC(and, 0x08);
3228 GEN_CRLOGIC(andc, 0x04);
3230 GEN_CRLOGIC(eqv, 0x09);
3232 GEN_CRLOGIC(nand, 0x07);
3234 GEN_CRLOGIC(nor, 0x01);
3236 GEN_CRLOGIC(or, 0x0E);
3238 GEN_CRLOGIC(orc, 0x0D);
3240 GEN_CRLOGIC(xor, 0x06);
3242 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3244 gen_op_load_crf_T0(crfS(ctx->opcode));
3245 gen_op_store_T0_crf(crfD(ctx->opcode));
3248 /*** System linkage ***/
3249 /* rfi (supervisor only) */
3250 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
3252 #if defined(CONFIG_USER_ONLY)
3253 GEN_EXCP_PRIVOPC(ctx);
3255 /* Restore CPU state */
3256 if (unlikely(!ctx->supervisor)) {
3257 GEN_EXCP_PRIVOPC(ctx);
3265 #if defined(TARGET_PPC64)
3266 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
3268 #if defined(CONFIG_USER_ONLY)
3269 GEN_EXCP_PRIVOPC(ctx);
3271 /* Restore CPU state */
3272 if (unlikely(!ctx->supervisor)) {
3273 GEN_EXCP_PRIVOPC(ctx);
3282 #if defined(TARGET_PPC64H)
3283 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64B)
3285 #if defined(CONFIG_USER_ONLY)
3286 GEN_EXCP_PRIVOPC(ctx);
3288 /* Restore CPU state */
3289 if (unlikely(ctx->supervisor <= 1)) {
3290 GEN_EXCP_PRIVOPC(ctx);
3300 #if defined(CONFIG_USER_ONLY)
3301 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3303 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3305 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
3309 lev = (ctx->opcode >> 5) & 0x7F;
3310 GEN_EXCP(ctx, POWERPC_SYSCALL, lev);
3315 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
3317 gen_op_load_gpr_T0(rA(ctx->opcode));
3318 gen_op_load_gpr_T1(rB(ctx->opcode));
3319 /* Update the nip since this might generate a trap exception */
3320 gen_update_nip(ctx, ctx->nip);
3321 gen_op_tw(TO(ctx->opcode));
3325 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3327 gen_op_load_gpr_T0(rA(ctx->opcode));
3328 gen_set_T1(SIMM(ctx->opcode));
3329 /* Update the nip since this might generate a trap exception */
3330 gen_update_nip(ctx, ctx->nip);
3331 gen_op_tw(TO(ctx->opcode));
3334 #if defined(TARGET_PPC64)
3336 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3338 gen_op_load_gpr_T0(rA(ctx->opcode));
3339 gen_op_load_gpr_T1(rB(ctx->opcode));
3340 /* Update the nip since this might generate a trap exception */
3341 gen_update_nip(ctx, ctx->nip);
3342 gen_op_td(TO(ctx->opcode));
3346 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3348 gen_op_load_gpr_T0(rA(ctx->opcode));
3349 gen_set_T1(SIMM(ctx->opcode));
3350 /* Update the nip since this might generate a trap exception */
3351 gen_update_nip(ctx, ctx->nip);
3352 gen_op_td(TO(ctx->opcode));
3356 /*** Processor control ***/
3358 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3360 gen_op_load_xer_cr();
3361 gen_op_store_T0_crf(crfD(ctx->opcode));
3362 gen_op_clear_xer_ov();
3363 gen_op_clear_xer_ca();
3367 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
3371 if (likely(ctx->opcode & 0x00100000)) {
3372 crm = CRM(ctx->opcode);
3373 if (likely((crm ^ (crm - 1)) == 0)) {
3375 gen_op_load_cro(7 - crn);
3380 gen_op_store_T0_gpr(rD(ctx->opcode));
3384 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3386 #if defined(CONFIG_USER_ONLY)
3387 GEN_EXCP_PRIVREG(ctx);
3389 if (unlikely(!ctx->supervisor)) {
3390 GEN_EXCP_PRIVREG(ctx);
3394 gen_op_store_T0_gpr(rD(ctx->opcode));
3399 #define SPR_NOACCESS ((void *)(-1))
3401 static void spr_noaccess (void *opaque, int sprn)
3403 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3404 printf("ERROR: try to access SPR %d !\n", sprn);
3406 #define SPR_NOACCESS (&spr_noaccess)
3410 static always_inline void gen_op_mfspr (DisasContext *ctx)
3412 void (*read_cb)(void *opaque, int sprn);
3413 uint32_t sprn = SPR(ctx->opcode);
3415 #if !defined(CONFIG_USER_ONLY)
3416 #if defined(TARGET_PPC64H)
3417 if (ctx->supervisor == 2)
3418 read_cb = ctx->spr_cb[sprn].hea_read;
3421 if (ctx->supervisor)
3422 read_cb = ctx->spr_cb[sprn].oea_read;
3425 read_cb = ctx->spr_cb[sprn].uea_read;
3426 if (likely(read_cb != NULL)) {
3427 if (likely(read_cb != SPR_NOACCESS)) {
3428 (*read_cb)(ctx, sprn);
3429 gen_op_store_T0_gpr(rD(ctx->opcode));
3431 /* Privilege exception */
3432 if (loglevel != 0) {
3433 fprintf(logfile, "Trying to read privileged spr %d %03x\n",
3436 printf("Trying to read privileged spr %d %03x\n", sprn, sprn);
3437 GEN_EXCP_PRIVREG(ctx);
3441 if (loglevel != 0) {
3442 fprintf(logfile, "Trying to read invalid spr %d %03x\n",
3445 printf("Trying to read invalid spr %d %03x\n", sprn, sprn);
3446 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3447 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
3451 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
3457 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3463 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
3467 gen_op_load_gpr_T0(rS(ctx->opcode));
3468 crm = CRM(ctx->opcode);
3469 if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
3471 gen_op_srli_T0(crn * 4);
3472 gen_op_andi_T0(0xF);
3473 gen_op_store_cro(7 - crn);
3475 gen_op_store_cr(crm);
3480 #if defined(TARGET_PPC64)
3481 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
3483 #if defined(CONFIG_USER_ONLY)
3484 GEN_EXCP_PRIVREG(ctx);
3486 if (unlikely(!ctx->supervisor)) {
3487 GEN_EXCP_PRIVREG(ctx);
3490 gen_op_load_gpr_T0(rS(ctx->opcode));
3491 if (ctx->opcode & 0x00010000) {
3492 /* Special form that does not need any synchronisation */
3493 gen_op_update_riee();
3495 /* XXX: we need to update nip before the store
3496 * if we enter power saving mode, we will exit the loop
3497 * directly from ppc_store_msr
3499 gen_update_nip(ctx, ctx->nip);
3501 /* Must stop the translation as machine state (may have) changed */
3502 /* Note that mtmsr is not always defined as context-synchronizing */
3503 ctx->exception = POWERPC_EXCP_STOP;
3509 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3511 #if defined(CONFIG_USER_ONLY)
3512 GEN_EXCP_PRIVREG(ctx);
3514 if (unlikely(!ctx->supervisor)) {
3515 GEN_EXCP_PRIVREG(ctx);
3518 gen_op_load_gpr_T0(rS(ctx->opcode));
3519 if (ctx->opcode & 0x00010000) {
3520 /* Special form that does not need any synchronisation */
3521 gen_op_update_riee();
3523 /* XXX: we need to update nip before the store
3524 * if we enter power saving mode, we will exit the loop
3525 * directly from ppc_store_msr
3527 gen_update_nip(ctx, ctx->nip);
3528 #if defined(TARGET_PPC64)
3530 gen_op_store_msr_32();
3534 /* Must stop the translation as machine state (may have) changed */
3535 /* Note that mtmsrd is not always defined as context-synchronizing */
3536 ctx->exception = POWERPC_EXCP_STOP;
3542 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
3544 void (*write_cb)(void *opaque, int sprn);
3545 uint32_t sprn = SPR(ctx->opcode);
3547 #if !defined(CONFIG_USER_ONLY)
3548 #if defined(TARGET_PPC64H)
3549 if (ctx->supervisor == 2)
3550 write_cb = ctx->spr_cb[sprn].hea_write;
3553 if (ctx->supervisor)
3554 write_cb = ctx->spr_cb[sprn].oea_write;
3557 write_cb = ctx->spr_cb[sprn].uea_write;
3558 if (likely(write_cb != NULL)) {
3559 if (likely(write_cb != SPR_NOACCESS)) {
3560 gen_op_load_gpr_T0(rS(ctx->opcode));
3561 (*write_cb)(ctx, sprn);
3563 /* Privilege exception */
3564 if (loglevel != 0) {
3565 fprintf(logfile, "Trying to write privileged spr %d %03x\n",
3568 printf("Trying to write privileged spr %d %03x\n", sprn, sprn);
3569 GEN_EXCP_PRIVREG(ctx);
3573 if (loglevel != 0) {
3574 fprintf(logfile, "Trying to write invalid spr %d %03x\n",
3577 printf("Trying to write invalid spr %d %03x\n", sprn, sprn);
3578 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3579 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
3583 /*** Cache management ***/
3584 /* For now, all those will be implemented as nop:
3585 * this is valid, regarding the PowerPC specs...
3586 * We just have to flush tb while invalidating instruction cache lines...
3589 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
3591 gen_addr_reg_index(ctx);
3595 /* dcbi (Supervisor only) */
3596 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
3598 #if defined(CONFIG_USER_ONLY)
3599 GEN_EXCP_PRIVOPC(ctx);
3601 if (unlikely(!ctx->supervisor)) {
3602 GEN_EXCP_PRIVOPC(ctx);
3605 gen_addr_reg_index(ctx);
3606 /* XXX: specification says this should be treated as a store by the MMU */
3613 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
3615 /* XXX: specification say this is treated as a load by the MMU */
3616 gen_addr_reg_index(ctx);
3621 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
3623 /* interpreted as no-op */
3624 /* XXX: specification say this is treated as a load by the MMU
3625 * but does not generate any exception
3630 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
3632 /* interpreted as no-op */
3633 /* XXX: specification say this is treated as a load by the MMU
3634 * but does not generate any exception
3639 #define op_dcbz(n) (*gen_op_dcbz[n][ctx->mem_idx])()
3640 #if defined(CONFIG_USER_ONLY)
3641 /* User-mode only */
3642 static GenOpFunc *gen_op_dcbz[4][4] = {
3644 &gen_op_dcbz_l32_raw,
3645 &gen_op_dcbz_l32_raw,
3646 #if defined(TARGET_PPC64)
3647 &gen_op_dcbz_l32_64_raw,
3648 &gen_op_dcbz_l32_64_raw,
3652 &gen_op_dcbz_l64_raw,
3653 &gen_op_dcbz_l64_raw,
3654 #if defined(TARGET_PPC64)
3655 &gen_op_dcbz_l64_64_raw,
3656 &gen_op_dcbz_l64_64_raw,
3660 &gen_op_dcbz_l128_raw,
3661 &gen_op_dcbz_l128_raw,
3662 #if defined(TARGET_PPC64)
3663 &gen_op_dcbz_l128_64_raw,
3664 &gen_op_dcbz_l128_64_raw,
3670 #if defined(TARGET_PPC64)
3671 &gen_op_dcbz_64_raw,
3672 &gen_op_dcbz_64_raw,
3677 #if defined(TARGET_PPC64)
3678 /* Full system - 64 bits mode */
3679 static GenOpFunc *gen_op_dcbz[4][12] = {
3681 &gen_op_dcbz_l32_user,
3682 &gen_op_dcbz_l32_user,
3683 &gen_op_dcbz_l32_64_user,
3684 &gen_op_dcbz_l32_64_user,
3685 &gen_op_dcbz_l32_kernel,
3686 &gen_op_dcbz_l32_kernel,
3687 &gen_op_dcbz_l32_64_kernel,
3688 &gen_op_dcbz_l32_64_kernel,
3689 #if defined(TARGET_PPC64H)
3690 &gen_op_dcbz_l32_hypv,
3691 &gen_op_dcbz_l32_hypv,
3692 &gen_op_dcbz_l32_64_hypv,
3693 &gen_op_dcbz_l32_64_hypv,
3697 &gen_op_dcbz_l64_user,
3698 &gen_op_dcbz_l64_user,
3699 &gen_op_dcbz_l64_64_user,
3700 &gen_op_dcbz_l64_64_user,
3701 &gen_op_dcbz_l64_kernel,
3702 &gen_op_dcbz_l64_kernel,
3703 &gen_op_dcbz_l64_64_kernel,
3704 &gen_op_dcbz_l64_64_kernel,
3705 #if defined(TARGET_PPC64H)
3706 &gen_op_dcbz_l64_hypv,
3707 &gen_op_dcbz_l64_hypv,
3708 &gen_op_dcbz_l64_64_hypv,
3709 &gen_op_dcbz_l64_64_hypv,
3713 &gen_op_dcbz_l128_user,
3714 &gen_op_dcbz_l128_user,
3715 &gen_op_dcbz_l128_64_user,
3716 &gen_op_dcbz_l128_64_user,
3717 &gen_op_dcbz_l128_kernel,
3718 &gen_op_dcbz_l128_kernel,
3719 &gen_op_dcbz_l128_64_kernel,
3720 &gen_op_dcbz_l128_64_kernel,
3721 #if defined(TARGET_PPC64H)
3722 &gen_op_dcbz_l128_hypv,
3723 &gen_op_dcbz_l128_hypv,
3724 &gen_op_dcbz_l128_64_hypv,
3725 &gen_op_dcbz_l128_64_hypv,
3731 &gen_op_dcbz_64_user,
3732 &gen_op_dcbz_64_user,
3733 &gen_op_dcbz_kernel,
3734 &gen_op_dcbz_kernel,
3735 &gen_op_dcbz_64_kernel,
3736 &gen_op_dcbz_64_kernel,
3737 #if defined(TARGET_PPC64H)
3740 &gen_op_dcbz_64_hypv,
3741 &gen_op_dcbz_64_hypv,
3746 /* Full system - 32 bits mode */
3747 static GenOpFunc *gen_op_dcbz[4][4] = {
3749 &gen_op_dcbz_l32_user,
3750 &gen_op_dcbz_l32_user,
3751 &gen_op_dcbz_l32_kernel,
3752 &gen_op_dcbz_l32_kernel,
3755 &gen_op_dcbz_l64_user,
3756 &gen_op_dcbz_l64_user,
3757 &gen_op_dcbz_l64_kernel,
3758 &gen_op_dcbz_l64_kernel,
3761 &gen_op_dcbz_l128_user,
3762 &gen_op_dcbz_l128_user,
3763 &gen_op_dcbz_l128_kernel,
3764 &gen_op_dcbz_l128_kernel,
3769 &gen_op_dcbz_kernel,
3770 &gen_op_dcbz_kernel,
3776 static always_inline void handler_dcbz (DisasContext *ctx,
3777 int dcache_line_size)
3781 switch (dcache_line_size) {
3798 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
3800 gen_addr_reg_index(ctx);
3801 handler_dcbz(ctx, ctx->dcache_line_size);
3802 gen_op_check_reservation();
3805 GEN_HANDLER(dcbz_970, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
3807 gen_addr_reg_index(ctx);
3808 if (ctx->opcode & 0x00200000)
3809 handler_dcbz(ctx, ctx->dcache_line_size);
3811 handler_dcbz(ctx, -1);
3812 gen_op_check_reservation();
3816 #define op_icbi() (*gen_op_icbi[ctx->mem_idx])()
3817 #if defined(CONFIG_USER_ONLY)
3818 /* User-mode only */
3819 static GenOpFunc *gen_op_icbi[] = {
3822 #if defined(TARGET_PPC64)
3823 &gen_op_icbi_64_raw,
3824 &gen_op_icbi_64_raw,
3828 /* Full system - 64 bits mode */
3829 #if defined(TARGET_PPC64)
3830 static GenOpFunc *gen_op_icbi[] = {
3833 &gen_op_icbi_64_user,
3834 &gen_op_icbi_64_user,
3835 &gen_op_icbi_kernel,
3836 &gen_op_icbi_kernel,
3837 &gen_op_icbi_64_kernel,
3838 &gen_op_icbi_64_kernel,
3839 #if defined(TARGET_PPC64H)
3842 &gen_op_icbi_64_hypv,
3843 &gen_op_icbi_64_hypv,
3847 /* Full system - 32 bits mode */
3848 static GenOpFunc *gen_op_icbi[] = {
3851 &gen_op_icbi_kernel,
3852 &gen_op_icbi_kernel,
3857 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE)
3859 /* NIP cannot be restored if the memory exception comes from an helper */
3860 gen_update_nip(ctx, ctx->nip - 4);
3861 gen_addr_reg_index(ctx);
3867 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
3869 /* interpreted as no-op */
3870 /* XXX: specification say this is treated as a store by the MMU
3871 * but does not generate any exception
3875 /*** Segment register manipulation ***/
3876 /* Supervisor only: */
3878 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
3880 #if defined(CONFIG_USER_ONLY)
3881 GEN_EXCP_PRIVREG(ctx);
3883 if (unlikely(!ctx->supervisor)) {
3884 GEN_EXCP_PRIVREG(ctx);
3887 gen_op_set_T1(SR(ctx->opcode));
3889 gen_op_store_T0_gpr(rD(ctx->opcode));
3894 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
3896 #if defined(CONFIG_USER_ONLY)
3897 GEN_EXCP_PRIVREG(ctx);
3899 if (unlikely(!ctx->supervisor)) {
3900 GEN_EXCP_PRIVREG(ctx);
3903 gen_op_load_gpr_T1(rB(ctx->opcode));
3906 gen_op_store_T0_gpr(rD(ctx->opcode));
3911 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
3913 #if defined(CONFIG_USER_ONLY)
3914 GEN_EXCP_PRIVREG(ctx);
3916 if (unlikely(!ctx->supervisor)) {
3917 GEN_EXCP_PRIVREG(ctx);
3920 gen_op_load_gpr_T0(rS(ctx->opcode));
3921 gen_op_set_T1(SR(ctx->opcode));
3927 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
3929 #if defined(CONFIG_USER_ONLY)
3930 GEN_EXCP_PRIVREG(ctx);
3932 if (unlikely(!ctx->supervisor)) {
3933 GEN_EXCP_PRIVREG(ctx);
3936 gen_op_load_gpr_T0(rS(ctx->opcode));
3937 gen_op_load_gpr_T1(rB(ctx->opcode));
3943 #if defined(TARGET_PPC64)
3944 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
3946 GEN_HANDLER(mfsr_64b, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
3948 #if defined(CONFIG_USER_ONLY)
3949 GEN_EXCP_PRIVREG(ctx);
3951 if (unlikely(!ctx->supervisor)) {
3952 GEN_EXCP_PRIVREG(ctx);
3955 gen_op_set_T1(SR(ctx->opcode));
3957 gen_op_store_T0_gpr(rD(ctx->opcode));
3962 GEN_HANDLER(mfsrin_64b, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT_64B)
3964 #if defined(CONFIG_USER_ONLY)
3965 GEN_EXCP_PRIVREG(ctx);
3967 if (unlikely(!ctx->supervisor)) {
3968 GEN_EXCP_PRIVREG(ctx);
3971 gen_op_load_gpr_T1(rB(ctx->opcode));
3974 gen_op_store_T0_gpr(rD(ctx->opcode));
3979 GEN_HANDLER(mtsr_64b, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
3981 #if defined(CONFIG_USER_ONLY)
3982 GEN_EXCP_PRIVREG(ctx);
3984 if (unlikely(!ctx->supervisor)) {
3985 GEN_EXCP_PRIVREG(ctx);
3988 gen_op_load_gpr_T0(rS(ctx->opcode));
3989 gen_op_set_T1(SR(ctx->opcode));
3995 GEN_HANDLER(mtsrin_64b, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT_64B)
3997 #if defined(CONFIG_USER_ONLY)
3998 GEN_EXCP_PRIVREG(ctx);
4000 if (unlikely(!ctx->supervisor)) {
4001 GEN_EXCP_PRIVREG(ctx);
4004 gen_op_load_gpr_T0(rS(ctx->opcode));
4005 gen_op_load_gpr_T1(rB(ctx->opcode));
4010 #endif /* defined(TARGET_PPC64) */
4012 /*** Lookaside buffer management ***/
4013 /* Optional & supervisor only: */
4015 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
4017 #if defined(CONFIG_USER_ONLY)
4018 GEN_EXCP_PRIVOPC(ctx);
4020 if (unlikely(!ctx->supervisor)) {
4022 fprintf(logfile, "%s: ! supervisor\n", __func__);
4023 GEN_EXCP_PRIVOPC(ctx);
4031 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
4033 #if defined(CONFIG_USER_ONLY)
4034 GEN_EXCP_PRIVOPC(ctx);
4036 if (unlikely(!ctx->supervisor)) {
4037 GEN_EXCP_PRIVOPC(ctx);
4040 gen_op_load_gpr_T0(rB(ctx->opcode));
4041 #if defined(TARGET_PPC64)
4051 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
4053 #if defined(CONFIG_USER_ONLY)
4054 GEN_EXCP_PRIVOPC(ctx);
4056 if (unlikely(!ctx->supervisor)) {
4057 GEN_EXCP_PRIVOPC(ctx);
4060 /* This has no effect: it should ensure that all previous
4061 * tlbie have completed
4067 #if defined(TARGET_PPC64)
4069 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4071 #if defined(CONFIG_USER_ONLY)
4072 GEN_EXCP_PRIVOPC(ctx);
4074 if (unlikely(!ctx->supervisor)) {
4076 fprintf(logfile, "%s: ! supervisor\n", __func__);
4077 GEN_EXCP_PRIVOPC(ctx);
4085 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4087 #if defined(CONFIG_USER_ONLY)
4088 GEN_EXCP_PRIVOPC(ctx);
4090 if (unlikely(!ctx->supervisor)) {
4091 GEN_EXCP_PRIVOPC(ctx);
4094 gen_op_load_gpr_T0(rB(ctx->opcode));
4100 /*** External control ***/
4102 #define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
4103 #define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
4104 #if defined(CONFIG_USER_ONLY)
4105 /* User-mode only */
4106 static GenOpFunc *gen_op_eciwx[] = {
4108 &gen_op_eciwx_le_raw,
4109 #if defined(TARGET_PPC64)
4110 &gen_op_eciwx_64_raw,
4111 &gen_op_eciwx_le_64_raw,
4114 static GenOpFunc *gen_op_ecowx[] = {
4116 &gen_op_ecowx_le_raw,
4117 #if defined(TARGET_PPC64)
4118 &gen_op_ecowx_64_raw,
4119 &gen_op_ecowx_le_64_raw,
4123 #if defined(TARGET_PPC64)
4124 /* Full system - 64 bits mode */
4125 static GenOpFunc *gen_op_eciwx[] = {
4127 &gen_op_eciwx_le_user,
4128 &gen_op_eciwx_64_user,
4129 &gen_op_eciwx_le_64_user,
4130 &gen_op_eciwx_kernel,
4131 &gen_op_eciwx_le_kernel,
4132 &gen_op_eciwx_64_kernel,
4133 &gen_op_eciwx_le_64_kernel,
4134 #if defined(TARGET_PPC64H)
4136 &gen_op_eciwx_le_hypv,
4137 &gen_op_eciwx_64_hypv,
4138 &gen_op_eciwx_le_64_hypv,
4141 static GenOpFunc *gen_op_ecowx[] = {
4143 &gen_op_ecowx_le_user,
4144 &gen_op_ecowx_64_user,
4145 &gen_op_ecowx_le_64_user,
4146 &gen_op_ecowx_kernel,
4147 &gen_op_ecowx_le_kernel,
4148 &gen_op_ecowx_64_kernel,
4149 &gen_op_ecowx_le_64_kernel,
4150 #if defined(TARGET_PPC64H)
4152 &gen_op_ecowx_le_hypv,
4153 &gen_op_ecowx_64_hypv,
4154 &gen_op_ecowx_le_64_hypv,
4158 /* Full system - 32 bits mode */
4159 static GenOpFunc *gen_op_eciwx[] = {
4161 &gen_op_eciwx_le_user,
4162 &gen_op_eciwx_kernel,
4163 &gen_op_eciwx_le_kernel,
4165 static GenOpFunc *gen_op_ecowx[] = {
4167 &gen_op_ecowx_le_user,
4168 &gen_op_ecowx_kernel,
4169 &gen_op_ecowx_le_kernel,
4175 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4177 /* Should check EAR[E] & alignment ! */
4178 gen_addr_reg_index(ctx);
4180 gen_op_store_T0_gpr(rD(ctx->opcode));
4184 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4186 /* Should check EAR[E] & alignment ! */
4187 gen_addr_reg_index(ctx);
4188 gen_op_load_gpr_T1(rS(ctx->opcode));
4192 /* PowerPC 601 specific instructions */
4194 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
4196 gen_op_load_gpr_T0(rA(ctx->opcode));
4198 gen_op_store_T0_gpr(rD(ctx->opcode));
4199 if (unlikely(Rc(ctx->opcode) != 0))
4204 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
4206 gen_op_load_gpr_T0(rA(ctx->opcode));
4207 gen_op_POWER_abso();
4208 gen_op_store_T0_gpr(rD(ctx->opcode));
4209 if (unlikely(Rc(ctx->opcode) != 0))
4214 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
4216 gen_op_load_gpr_T0(rA(ctx->opcode));
4217 gen_op_POWER_clcs();
4218 gen_op_store_T0_gpr(rD(ctx->opcode));
4222 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
4224 gen_op_load_gpr_T0(rA(ctx->opcode));
4225 gen_op_load_gpr_T1(rB(ctx->opcode));
4227 gen_op_store_T0_gpr(rD(ctx->opcode));
4228 if (unlikely(Rc(ctx->opcode) != 0))
4233 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
4235 gen_op_load_gpr_T0(rA(ctx->opcode));
4236 gen_op_load_gpr_T1(rB(ctx->opcode));
4237 gen_op_POWER_divo();
4238 gen_op_store_T0_gpr(rD(ctx->opcode));
4239 if (unlikely(Rc(ctx->opcode) != 0))
4244 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
4246 gen_op_load_gpr_T0(rA(ctx->opcode));
4247 gen_op_load_gpr_T1(rB(ctx->opcode));
4248 gen_op_POWER_divs();
4249 gen_op_store_T0_gpr(rD(ctx->opcode));
4250 if (unlikely(Rc(ctx->opcode) != 0))
4254 /* divso - divso. */
4255 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
4257 gen_op_load_gpr_T0(rA(ctx->opcode));
4258 gen_op_load_gpr_T1(rB(ctx->opcode));
4259 gen_op_POWER_divso();
4260 gen_op_store_T0_gpr(rD(ctx->opcode));
4261 if (unlikely(Rc(ctx->opcode) != 0))
4266 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
4268 gen_op_load_gpr_T0(rA(ctx->opcode));
4269 gen_op_load_gpr_T1(rB(ctx->opcode));
4271 gen_op_store_T0_gpr(rD(ctx->opcode));
4272 if (unlikely(Rc(ctx->opcode) != 0))
4277 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
4279 gen_op_load_gpr_T0(rA(ctx->opcode));
4280 gen_op_load_gpr_T1(rB(ctx->opcode));
4281 gen_op_POWER_dozo();
4282 gen_op_store_T0_gpr(rD(ctx->opcode));
4283 if (unlikely(Rc(ctx->opcode) != 0))
4288 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4290 gen_op_load_gpr_T0(rA(ctx->opcode));
4291 gen_op_set_T1(SIMM(ctx->opcode));
4293 gen_op_store_T0_gpr(rD(ctx->opcode));
4296 /* As lscbx load from memory byte after byte, it's always endian safe */
4297 #define op_POWER_lscbx(start, ra, rb) \
4298 (*gen_op_POWER_lscbx[ctx->mem_idx])(start, ra, rb)
4299 #if defined(CONFIG_USER_ONLY)
4300 static GenOpFunc3 *gen_op_POWER_lscbx[] = {
4301 &gen_op_POWER_lscbx_raw,
4302 &gen_op_POWER_lscbx_raw,
4305 static GenOpFunc3 *gen_op_POWER_lscbx[] = {
4306 &gen_op_POWER_lscbx_user,
4307 &gen_op_POWER_lscbx_user,
4308 &gen_op_POWER_lscbx_kernel,
4309 &gen_op_POWER_lscbx_kernel,
4313 /* lscbx - lscbx. */
4314 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4316 int ra = rA(ctx->opcode);
4317 int rb = rB(ctx->opcode);
4319 gen_addr_reg_index(ctx);
4323 /* NIP cannot be restored if the memory exception comes from an helper */
4324 gen_update_nip(ctx, ctx->nip - 4);
4325 gen_op_load_xer_bc();
4326 gen_op_load_xer_cmp();
4327 op_POWER_lscbx(rD(ctx->opcode), ra, rb);
4328 gen_op_store_xer_bc();
4329 if (unlikely(Rc(ctx->opcode) != 0))
4333 /* maskg - maskg. */
4334 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4336 gen_op_load_gpr_T0(rS(ctx->opcode));
4337 gen_op_load_gpr_T1(rB(ctx->opcode));
4338 gen_op_POWER_maskg();
4339 gen_op_store_T0_gpr(rA(ctx->opcode));
4340 if (unlikely(Rc(ctx->opcode) != 0))
4344 /* maskir - maskir. */
4345 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4347 gen_op_load_gpr_T0(rA(ctx->opcode));
4348 gen_op_load_gpr_T1(rS(ctx->opcode));
4349 gen_op_load_gpr_T2(rB(ctx->opcode));
4350 gen_op_POWER_maskir();
4351 gen_op_store_T0_gpr(rA(ctx->opcode));
4352 if (unlikely(Rc(ctx->opcode) != 0))
4357 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4359 gen_op_load_gpr_T0(rA(ctx->opcode));
4360 gen_op_load_gpr_T1(rB(ctx->opcode));
4362 gen_op_store_T0_gpr(rD(ctx->opcode));
4363 if (unlikely(Rc(ctx->opcode) != 0))
4368 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4370 gen_op_load_gpr_T0(rA(ctx->opcode));
4371 gen_op_load_gpr_T1(rB(ctx->opcode));
4372 gen_op_POWER_mulo();
4373 gen_op_store_T0_gpr(rD(ctx->opcode));
4374 if (unlikely(Rc(ctx->opcode) != 0))
4379 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4381 gen_op_load_gpr_T0(rA(ctx->opcode));
4382 gen_op_POWER_nabs();
4383 gen_op_store_T0_gpr(rD(ctx->opcode));
4384 if (unlikely(Rc(ctx->opcode) != 0))
4388 /* nabso - nabso. */
4389 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4391 gen_op_load_gpr_T0(rA(ctx->opcode));
4392 gen_op_POWER_nabso();
4393 gen_op_store_T0_gpr(rD(ctx->opcode));
4394 if (unlikely(Rc(ctx->opcode) != 0))
4399 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4403 mb = MB(ctx->opcode);
4404 me = ME(ctx->opcode);
4405 gen_op_load_gpr_T0(rS(ctx->opcode));
4406 gen_op_load_gpr_T1(rA(ctx->opcode));
4407 gen_op_load_gpr_T2(rB(ctx->opcode));
4408 gen_op_POWER_rlmi(MASK(mb, me), ~MASK(mb, me));
4409 gen_op_store_T0_gpr(rA(ctx->opcode));
4410 if (unlikely(Rc(ctx->opcode) != 0))
4415 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4417 gen_op_load_gpr_T0(rS(ctx->opcode));
4418 gen_op_load_gpr_T1(rA(ctx->opcode));
4419 gen_op_load_gpr_T2(rB(ctx->opcode));
4420 gen_op_POWER_rrib();
4421 gen_op_store_T0_gpr(rA(ctx->opcode));
4422 if (unlikely(Rc(ctx->opcode) != 0))
4427 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4429 gen_op_load_gpr_T0(rS(ctx->opcode));
4430 gen_op_load_gpr_T1(rB(ctx->opcode));
4432 gen_op_store_T0_gpr(rA(ctx->opcode));
4433 if (unlikely(Rc(ctx->opcode) != 0))
4438 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4440 gen_op_load_gpr_T0(rS(ctx->opcode));
4441 gen_op_load_gpr_T1(rB(ctx->opcode));
4442 gen_op_POWER_sleq();
4443 gen_op_store_T0_gpr(rA(ctx->opcode));
4444 if (unlikely(Rc(ctx->opcode) != 0))
4449 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4451 gen_op_load_gpr_T0(rS(ctx->opcode));
4452 gen_op_set_T1(SH(ctx->opcode));
4454 gen_op_store_T0_gpr(rA(ctx->opcode));
4455 if (unlikely(Rc(ctx->opcode) != 0))
4459 /* slliq - slliq. */
4460 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4462 gen_op_load_gpr_T0(rS(ctx->opcode));
4463 gen_op_set_T1(SH(ctx->opcode));
4464 gen_op_POWER_sleq();
4465 gen_op_store_T0_gpr(rA(ctx->opcode));
4466 if (unlikely(Rc(ctx->opcode) != 0))
4471 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4473 gen_op_load_gpr_T0(rS(ctx->opcode));
4474 gen_op_load_gpr_T1(rB(ctx->opcode));
4475 gen_op_POWER_sllq();
4476 gen_op_store_T0_gpr(rA(ctx->opcode));
4477 if (unlikely(Rc(ctx->opcode) != 0))
4482 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4484 gen_op_load_gpr_T0(rS(ctx->opcode));
4485 gen_op_load_gpr_T1(rB(ctx->opcode));
4487 gen_op_store_T0_gpr(rA(ctx->opcode));
4488 if (unlikely(Rc(ctx->opcode) != 0))
4492 /* sraiq - sraiq. */
4493 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4495 gen_op_load_gpr_T0(rS(ctx->opcode));
4496 gen_op_set_T1(SH(ctx->opcode));
4497 gen_op_POWER_sraq();
4498 gen_op_store_T0_gpr(rA(ctx->opcode));
4499 if (unlikely(Rc(ctx->opcode) != 0))
4504 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4506 gen_op_load_gpr_T0(rS(ctx->opcode));
4507 gen_op_load_gpr_T1(rB(ctx->opcode));
4508 gen_op_POWER_sraq();
4509 gen_op_store_T0_gpr(rA(ctx->opcode));
4510 if (unlikely(Rc(ctx->opcode) != 0))
4515 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4517 gen_op_load_gpr_T0(rS(ctx->opcode));
4518 gen_op_load_gpr_T1(rB(ctx->opcode));
4520 gen_op_store_T0_gpr(rA(ctx->opcode));
4521 if (unlikely(Rc(ctx->opcode) != 0))
4526 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4528 gen_op_load_gpr_T0(rS(ctx->opcode));
4529 gen_op_load_gpr_T1(rB(ctx->opcode));
4530 gen_op_POWER_srea();
4531 gen_op_store_T0_gpr(rA(ctx->opcode));
4532 if (unlikely(Rc(ctx->opcode) != 0))
4537 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
4539 gen_op_load_gpr_T0(rS(ctx->opcode));
4540 gen_op_load_gpr_T1(rB(ctx->opcode));
4541 gen_op_POWER_sreq();
4542 gen_op_store_T0_gpr(rA(ctx->opcode));
4543 if (unlikely(Rc(ctx->opcode) != 0))
4548 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
4550 gen_op_load_gpr_T0(rS(ctx->opcode));
4551 gen_op_set_T1(SH(ctx->opcode));
4553 gen_op_store_T0_gpr(rA(ctx->opcode));
4554 if (unlikely(Rc(ctx->opcode) != 0))
4559 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
4561 gen_op_load_gpr_T0(rS(ctx->opcode));
4562 gen_op_load_gpr_T1(rB(ctx->opcode));
4563 gen_op_set_T1(SH(ctx->opcode));
4564 gen_op_POWER_srlq();
4565 gen_op_store_T0_gpr(rA(ctx->opcode));
4566 if (unlikely(Rc(ctx->opcode) != 0))
4571 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
4573 gen_op_load_gpr_T0(rS(ctx->opcode));
4574 gen_op_load_gpr_T1(rB(ctx->opcode));
4575 gen_op_POWER_srlq();
4576 gen_op_store_T0_gpr(rA(ctx->opcode));
4577 if (unlikely(Rc(ctx->opcode) != 0))
4582 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
4584 gen_op_load_gpr_T0(rS(ctx->opcode));
4585 gen_op_load_gpr_T1(rB(ctx->opcode));
4587 gen_op_store_T0_gpr(rA(ctx->opcode));
4588 if (unlikely(Rc(ctx->opcode) != 0))
4592 /* PowerPC 602 specific instructions */
4594 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
4597 GEN_EXCP_INVAL(ctx);
4601 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
4604 GEN_EXCP_INVAL(ctx);
4608 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
4610 #if defined(CONFIG_USER_ONLY)
4611 GEN_EXCP_PRIVOPC(ctx);
4613 if (unlikely(!ctx->supervisor)) {
4614 GEN_EXCP_PRIVOPC(ctx);
4617 gen_op_load_gpr_T0(rA(ctx->opcode));
4619 gen_op_store_T0_gpr(rD(ctx->opcode));
4623 /* 602 - 603 - G2 TLB management */
4625 GEN_HANDLER(tlbld_6xx, 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
4627 #if defined(CONFIG_USER_ONLY)
4628 GEN_EXCP_PRIVOPC(ctx);
4630 if (unlikely(!ctx->supervisor)) {
4631 GEN_EXCP_PRIVOPC(ctx);
4634 gen_op_load_gpr_T0(rB(ctx->opcode));
4640 GEN_HANDLER(tlbli_6xx, 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
4642 #if defined(CONFIG_USER_ONLY)
4643 GEN_EXCP_PRIVOPC(ctx);
4645 if (unlikely(!ctx->supervisor)) {
4646 GEN_EXCP_PRIVOPC(ctx);
4649 gen_op_load_gpr_T0(rB(ctx->opcode));
4654 /* 74xx TLB management */
4656 GEN_HANDLER(tlbld_74xx, 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
4658 #if defined(CONFIG_USER_ONLY)
4659 GEN_EXCP_PRIVOPC(ctx);
4661 if (unlikely(!ctx->supervisor)) {
4662 GEN_EXCP_PRIVOPC(ctx);
4665 gen_op_load_gpr_T0(rB(ctx->opcode));
4666 gen_op_74xx_tlbld();
4671 GEN_HANDLER(tlbli_74xx, 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
4673 #if defined(CONFIG_USER_ONLY)
4674 GEN_EXCP_PRIVOPC(ctx);
4676 if (unlikely(!ctx->supervisor)) {
4677 GEN_EXCP_PRIVOPC(ctx);
4680 gen_op_load_gpr_T0(rB(ctx->opcode));
4681 gen_op_74xx_tlbli();
4685 /* POWER instructions not in PowerPC 601 */
4687 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
4689 /* Cache line flush: implemented as no-op */
4693 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
4695 /* Cache line invalidate: privileged and treated as no-op */
4696 #if defined(CONFIG_USER_ONLY)
4697 GEN_EXCP_PRIVOPC(ctx);
4699 if (unlikely(!ctx->supervisor)) {
4700 GEN_EXCP_PRIVOPC(ctx);
4707 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
4709 /* Data cache line store: treated as no-op */
4712 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
4714 #if defined(CONFIG_USER_ONLY)
4715 GEN_EXCP_PRIVOPC(ctx);
4717 if (unlikely(!ctx->supervisor)) {
4718 GEN_EXCP_PRIVOPC(ctx);
4721 int ra = rA(ctx->opcode);
4722 int rd = rD(ctx->opcode);
4724 gen_addr_reg_index(ctx);
4725 gen_op_POWER_mfsri();
4726 gen_op_store_T0_gpr(rd);
4727 if (ra != 0 && ra != rd)
4728 gen_op_store_T1_gpr(ra);
4732 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
4734 #if defined(CONFIG_USER_ONLY)
4735 GEN_EXCP_PRIVOPC(ctx);
4737 if (unlikely(!ctx->supervisor)) {
4738 GEN_EXCP_PRIVOPC(ctx);
4741 gen_addr_reg_index(ctx);
4743 gen_op_store_T0_gpr(rD(ctx->opcode));
4747 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
4749 #if defined(CONFIG_USER_ONLY)
4750 GEN_EXCP_PRIVOPC(ctx);
4752 if (unlikely(!ctx->supervisor)) {
4753 GEN_EXCP_PRIVOPC(ctx);
4756 gen_op_POWER_rfsvc();
4761 /* svc is not implemented for now */
4763 /* POWER2 specific instructions */
4764 /* Quad manipulation (load/store two floats at a time) */
4765 #define op_POWER2_lfq() (*gen_op_POWER2_lfq[ctx->mem_idx])()
4766 #define op_POWER2_stfq() (*gen_op_POWER2_stfq[ctx->mem_idx])()
4767 #if defined(CONFIG_USER_ONLY)
4768 static GenOpFunc *gen_op_POWER2_lfq[] = {
4769 &gen_op_POWER2_lfq_le_raw,
4770 &gen_op_POWER2_lfq_raw,
4772 static GenOpFunc *gen_op_POWER2_stfq[] = {
4773 &gen_op_POWER2_stfq_le_raw,
4774 &gen_op_POWER2_stfq_raw,
4777 static GenOpFunc *gen_op_POWER2_lfq[] = {
4778 &gen_op_POWER2_lfq_le_user,
4779 &gen_op_POWER2_lfq_user,
4780 &gen_op_POWER2_lfq_le_kernel,
4781 &gen_op_POWER2_lfq_kernel,
4783 static GenOpFunc *gen_op_POWER2_stfq[] = {
4784 &gen_op_POWER2_stfq_le_user,
4785 &gen_op_POWER2_stfq_user,
4786 &gen_op_POWER2_stfq_le_kernel,
4787 &gen_op_POWER2_stfq_kernel,
4792 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4794 /* NIP cannot be restored if the memory exception comes from an helper */
4795 gen_update_nip(ctx, ctx->nip - 4);
4796 gen_addr_imm_index(ctx, 0);
4798 gen_op_store_FT0_fpr(rD(ctx->opcode));
4799 gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4803 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4805 int ra = rA(ctx->opcode);
4807 /* NIP cannot be restored if the memory exception comes from an helper */
4808 gen_update_nip(ctx, ctx->nip - 4);
4809 gen_addr_imm_index(ctx, 0);
4811 gen_op_store_FT0_fpr(rD(ctx->opcode));
4812 gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4814 gen_op_store_T0_gpr(ra);
4818 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
4820 int ra = rA(ctx->opcode);
4822 /* NIP cannot be restored if the memory exception comes from an helper */
4823 gen_update_nip(ctx, ctx->nip - 4);
4824 gen_addr_reg_index(ctx);
4826 gen_op_store_FT0_fpr(rD(ctx->opcode));
4827 gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4829 gen_op_store_T0_gpr(ra);
4833 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
4835 /* NIP cannot be restored if the memory exception comes from an helper */
4836 gen_update_nip(ctx, ctx->nip - 4);
4837 gen_addr_reg_index(ctx);
4839 gen_op_store_FT0_fpr(rD(ctx->opcode));
4840 gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4844 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4846 /* NIP cannot be restored if the memory exception comes from an helper */
4847 gen_update_nip(ctx, ctx->nip - 4);
4848 gen_addr_imm_index(ctx, 0);
4849 gen_op_load_fpr_FT0(rS(ctx->opcode));
4850 gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
4855 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4857 int ra = rA(ctx->opcode);
4859 /* NIP cannot be restored if the memory exception comes from an helper */
4860 gen_update_nip(ctx, ctx->nip - 4);
4861 gen_addr_imm_index(ctx, 0);
4862 gen_op_load_fpr_FT0(rS(ctx->opcode));
4863 gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
4866 gen_op_store_T0_gpr(ra);
4870 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
4872 int ra = rA(ctx->opcode);
4874 /* NIP cannot be restored if the memory exception comes from an helper */
4875 gen_update_nip(ctx, ctx->nip - 4);
4876 gen_addr_reg_index(ctx);
4877 gen_op_load_fpr_FT0(rS(ctx->opcode));
4878 gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
4881 gen_op_store_T0_gpr(ra);
4885 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
4887 /* NIP cannot be restored if the memory exception comes from an helper */
4888 gen_update_nip(ctx, ctx->nip - 4);
4889 gen_addr_reg_index(ctx);
4890 gen_op_load_fpr_FT0(rS(ctx->opcode));
4891 gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
4895 /* BookE specific instructions */
4896 /* XXX: not implemented on 440 ? */
4897 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_BOOKE_EXT)
4900 GEN_EXCP_INVAL(ctx);
4903 /* XXX: not implemented on 440 ? */
4904 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_BOOKE_EXT)
4906 #if defined(CONFIG_USER_ONLY)
4907 GEN_EXCP_PRIVOPC(ctx);
4909 if (unlikely(!ctx->supervisor)) {
4910 GEN_EXCP_PRIVOPC(ctx);
4913 gen_addr_reg_index(ctx);
4914 /* Use the same micro-ops as for tlbie */
4915 #if defined(TARGET_PPC64)
4924 /* All 405 MAC instructions are translated here */
4925 static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
4927 int ra, int rb, int rt, int Rc)
4929 gen_op_load_gpr_T0(ra);
4930 gen_op_load_gpr_T1(rb);
4931 switch (opc3 & 0x0D) {
4933 /* macchw - macchw. - macchwo - macchwo. */
4934 /* macchws - macchws. - macchwso - macchwso. */
4935 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
4936 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
4937 /* mulchw - mulchw. */
4938 gen_op_405_mulchw();
4941 /* macchwu - macchwu. - macchwuo - macchwuo. */
4942 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
4943 /* mulchwu - mulchwu. */
4944 gen_op_405_mulchwu();
4947 /* machhw - machhw. - machhwo - machhwo. */
4948 /* machhws - machhws. - machhwso - machhwso. */
4949 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
4950 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
4951 /* mulhhw - mulhhw. */
4952 gen_op_405_mulhhw();
4955 /* machhwu - machhwu. - machhwuo - machhwuo. */
4956 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
4957 /* mulhhwu - mulhhwu. */
4958 gen_op_405_mulhhwu();
4961 /* maclhw - maclhw. - maclhwo - maclhwo. */
4962 /* maclhws - maclhws. - maclhwso - maclhwso. */
4963 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
4964 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
4965 /* mullhw - mullhw. */
4966 gen_op_405_mullhw();
4969 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
4970 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
4971 /* mullhwu - mullhwu. */
4972 gen_op_405_mullhwu();
4976 /* nmultiply-and-accumulate (0x0E) */
4980 /* (n)multiply-and-accumulate (0x0C - 0x0E) */
4981 gen_op_load_gpr_T2(rt);
4982 gen_op_move_T1_T0();
4983 gen_op_405_add_T0_T2();
4986 /* Check overflow */
4988 gen_op_405_check_ov();
4990 gen_op_405_check_ovu();
4995 gen_op_405_check_sat();
4997 gen_op_405_check_satu();
4999 gen_op_store_T0_gpr(rt);
5000 if (unlikely(Rc) != 0) {
5006 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5007 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
5009 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5010 rD(ctx->opcode), Rc(ctx->opcode)); \
5013 /* macchw - macchw. */
5014 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5015 /* macchwo - macchwo. */
5016 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5017 /* macchws - macchws. */
5018 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5019 /* macchwso - macchwso. */
5020 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5021 /* macchwsu - macchwsu. */
5022 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5023 /* macchwsuo - macchwsuo. */
5024 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5025 /* macchwu - macchwu. */
5026 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5027 /* macchwuo - macchwuo. */
5028 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5029 /* machhw - machhw. */
5030 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5031 /* machhwo - machhwo. */
5032 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5033 /* machhws - machhws. */
5034 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5035 /* machhwso - machhwso. */
5036 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5037 /* machhwsu - machhwsu. */
5038 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5039 /* machhwsuo - machhwsuo. */
5040 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5041 /* machhwu - machhwu. */
5042 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5043 /* machhwuo - machhwuo. */
5044 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5045 /* maclhw - maclhw. */
5046 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5047 /* maclhwo - maclhwo. */
5048 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5049 /* maclhws - maclhws. */
5050 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5051 /* maclhwso - maclhwso. */
5052 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5053 /* maclhwu - maclhwu. */
5054 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5055 /* maclhwuo - maclhwuo. */
5056 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5057 /* maclhwsu - maclhwsu. */
5058 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5059 /* maclhwsuo - maclhwsuo. */
5060 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5061 /* nmacchw - nmacchw. */
5062 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5063 /* nmacchwo - nmacchwo. */
5064 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5065 /* nmacchws - nmacchws. */
5066 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5067 /* nmacchwso - nmacchwso. */
5068 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5069 /* nmachhw - nmachhw. */
5070 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5071 /* nmachhwo - nmachhwo. */
5072 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5073 /* nmachhws - nmachhws. */
5074 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5075 /* nmachhwso - nmachhwso. */
5076 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5077 /* nmaclhw - nmaclhw. */
5078 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5079 /* nmaclhwo - nmaclhwo. */
5080 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5081 /* nmaclhws - nmaclhws. */
5082 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5083 /* nmaclhwso - nmaclhwso. */
5084 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5086 /* mulchw - mulchw. */
5087 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5088 /* mulchwu - mulchwu. */
5089 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5090 /* mulhhw - mulhhw. */
5091 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5092 /* mulhhwu - mulhhwu. */
5093 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5094 /* mullhw - mullhw. */
5095 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5096 /* mullhwu - mullhwu. */
5097 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5100 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_EMB_COMMON)
5102 #if defined(CONFIG_USER_ONLY)
5103 GEN_EXCP_PRIVREG(ctx);
5105 uint32_t dcrn = SPR(ctx->opcode);
5107 if (unlikely(!ctx->supervisor)) {
5108 GEN_EXCP_PRIVREG(ctx);
5111 gen_op_set_T0(dcrn);
5113 gen_op_store_T0_gpr(rD(ctx->opcode));
5118 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_EMB_COMMON)
5120 #if defined(CONFIG_USER_ONLY)
5121 GEN_EXCP_PRIVREG(ctx);
5123 uint32_t dcrn = SPR(ctx->opcode);
5125 if (unlikely(!ctx->supervisor)) {
5126 GEN_EXCP_PRIVREG(ctx);
5129 gen_op_set_T0(dcrn);
5130 gen_op_load_gpr_T1(rS(ctx->opcode));
5136 /* XXX: not implemented on 440 ? */
5137 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_BOOKE_EXT)
5139 #if defined(CONFIG_USER_ONLY)
5140 GEN_EXCP_PRIVREG(ctx);
5142 if (unlikely(!ctx->supervisor)) {
5143 GEN_EXCP_PRIVREG(ctx);
5146 gen_op_load_gpr_T0(rA(ctx->opcode));
5148 gen_op_store_T0_gpr(rD(ctx->opcode));
5149 /* Note: Rc update flag set leads to undefined state of Rc0 */
5154 /* XXX: not implemented on 440 ? */
5155 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_BOOKE_EXT)
5157 #if defined(CONFIG_USER_ONLY)
5158 GEN_EXCP_PRIVREG(ctx);
5160 if (unlikely(!ctx->supervisor)) {
5161 GEN_EXCP_PRIVREG(ctx);
5164 gen_op_load_gpr_T0(rA(ctx->opcode));
5165 gen_op_load_gpr_T1(rS(ctx->opcode));
5167 /* Note: Rc update flag set leads to undefined state of Rc0 */
5171 /* mfdcrux (PPC 460) : user-mode access to DCR */
5172 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
5174 gen_op_load_gpr_T0(rA(ctx->opcode));
5176 gen_op_store_T0_gpr(rD(ctx->opcode));
5177 /* Note: Rc update flag set leads to undefined state of Rc0 */
5180 /* mtdcrux (PPC 460) : user-mode access to DCR */
5181 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
5183 gen_op_load_gpr_T0(rA(ctx->opcode));
5184 gen_op_load_gpr_T1(rS(ctx->opcode));
5186 /* Note: Rc update flag set leads to undefined state of Rc0 */
5190 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
5192 #if defined(CONFIG_USER_ONLY)
5193 GEN_EXCP_PRIVOPC(ctx);
5195 if (unlikely(!ctx->supervisor)) {
5196 GEN_EXCP_PRIVOPC(ctx);
5199 /* interpreted as no-op */
5204 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
5206 #if defined(CONFIG_USER_ONLY)
5207 GEN_EXCP_PRIVOPC(ctx);
5209 if (unlikely(!ctx->supervisor)) {
5210 GEN_EXCP_PRIVOPC(ctx);
5213 gen_addr_reg_index(ctx);
5215 gen_op_store_T0_gpr(rD(ctx->opcode));
5220 GEN_HANDLER(icbt_40x, 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
5222 /* interpreted as no-op */
5223 /* XXX: specification say this is treated as a load by the MMU
5224 * but does not generate any exception
5229 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
5231 #if defined(CONFIG_USER_ONLY)
5232 GEN_EXCP_PRIVOPC(ctx);
5234 if (unlikely(!ctx->supervisor)) {
5235 GEN_EXCP_PRIVOPC(ctx);
5238 /* interpreted as no-op */
5243 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
5245 #if defined(CONFIG_USER_ONLY)
5246 GEN_EXCP_PRIVOPC(ctx);
5248 if (unlikely(!ctx->supervisor)) {
5249 GEN_EXCP_PRIVOPC(ctx);
5252 /* interpreted as no-op */
5256 /* rfci (supervisor only) */
5257 GEN_HANDLER(rfci_40x, 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
5259 #if defined(CONFIG_USER_ONLY)
5260 GEN_EXCP_PRIVOPC(ctx);
5262 if (unlikely(!ctx->supervisor)) {
5263 GEN_EXCP_PRIVOPC(ctx);
5266 /* Restore CPU state */
5272 GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
5274 #if defined(CONFIG_USER_ONLY)
5275 GEN_EXCP_PRIVOPC(ctx);
5277 if (unlikely(!ctx->supervisor)) {
5278 GEN_EXCP_PRIVOPC(ctx);
5281 /* Restore CPU state */
5287 /* BookE specific */
5288 /* XXX: not implemented on 440 ? */
5289 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_BOOKE_EXT)
5291 #if defined(CONFIG_USER_ONLY)
5292 GEN_EXCP_PRIVOPC(ctx);
5294 if (unlikely(!ctx->supervisor)) {
5295 GEN_EXCP_PRIVOPC(ctx);
5298 /* Restore CPU state */
5304 /* XXX: not implemented on 440 ? */
5305 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
5307 #if defined(CONFIG_USER_ONLY)
5308 GEN_EXCP_PRIVOPC(ctx);
5310 if (unlikely(!ctx->supervisor)) {
5311 GEN_EXCP_PRIVOPC(ctx);
5314 /* Restore CPU state */
5320 /* TLB management - PowerPC 405 implementation */
5322 GEN_HANDLER(tlbre_40x, 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
5324 #if defined(CONFIG_USER_ONLY)
5325 GEN_EXCP_PRIVOPC(ctx);
5327 if (unlikely(!ctx->supervisor)) {
5328 GEN_EXCP_PRIVOPC(ctx);
5331 switch (rB(ctx->opcode)) {
5333 gen_op_load_gpr_T0(rA(ctx->opcode));
5334 gen_op_4xx_tlbre_hi();
5335 gen_op_store_T0_gpr(rD(ctx->opcode));
5338 gen_op_load_gpr_T0(rA(ctx->opcode));
5339 gen_op_4xx_tlbre_lo();
5340 gen_op_store_T0_gpr(rD(ctx->opcode));
5343 GEN_EXCP_INVAL(ctx);
5349 /* tlbsx - tlbsx. */
5350 GEN_HANDLER(tlbsx_40x, 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
5352 #if defined(CONFIG_USER_ONLY)
5353 GEN_EXCP_PRIVOPC(ctx);
5355 if (unlikely(!ctx->supervisor)) {
5356 GEN_EXCP_PRIVOPC(ctx);
5359 gen_addr_reg_index(ctx);
5361 if (Rc(ctx->opcode))
5362 gen_op_4xx_tlbsx_check();
5363 gen_op_store_T0_gpr(rD(ctx->opcode));
5368 GEN_HANDLER(tlbwe_40x, 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
5370 #if defined(CONFIG_USER_ONLY)
5371 GEN_EXCP_PRIVOPC(ctx);
5373 if (unlikely(!ctx->supervisor)) {
5374 GEN_EXCP_PRIVOPC(ctx);
5377 switch (rB(ctx->opcode)) {
5379 gen_op_load_gpr_T0(rA(ctx->opcode));
5380 gen_op_load_gpr_T1(rS(ctx->opcode));
5381 gen_op_4xx_tlbwe_hi();
5384 gen_op_load_gpr_T0(rA(ctx->opcode));
5385 gen_op_load_gpr_T1(rS(ctx->opcode));
5386 gen_op_4xx_tlbwe_lo();
5389 GEN_EXCP_INVAL(ctx);
5395 /* TLB management - PowerPC 440 implementation */
5397 GEN_HANDLER(tlbre_440, 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5399 #if defined(CONFIG_USER_ONLY)
5400 GEN_EXCP_PRIVOPC(ctx);
5402 if (unlikely(!ctx->supervisor)) {
5403 GEN_EXCP_PRIVOPC(ctx);
5406 switch (rB(ctx->opcode)) {
5410 gen_op_load_gpr_T0(rA(ctx->opcode));
5411 gen_op_440_tlbre(rB(ctx->opcode));
5412 gen_op_store_T0_gpr(rD(ctx->opcode));
5415 GEN_EXCP_INVAL(ctx);
5421 /* tlbsx - tlbsx. */
5422 GEN_HANDLER(tlbsx_440, 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5424 #if defined(CONFIG_USER_ONLY)
5425 GEN_EXCP_PRIVOPC(ctx);
5427 if (unlikely(!ctx->supervisor)) {
5428 GEN_EXCP_PRIVOPC(ctx);
5431 gen_addr_reg_index(ctx);
5433 if (Rc(ctx->opcode))
5434 gen_op_4xx_tlbsx_check();
5435 gen_op_store_T0_gpr(rD(ctx->opcode));
5440 GEN_HANDLER(tlbwe_440, 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5442 #if defined(CONFIG_USER_ONLY)
5443 GEN_EXCP_PRIVOPC(ctx);
5445 if (unlikely(!ctx->supervisor)) {
5446 GEN_EXCP_PRIVOPC(ctx);
5449 switch (rB(ctx->opcode)) {
5453 gen_op_load_gpr_T0(rA(ctx->opcode));
5454 gen_op_load_gpr_T1(rS(ctx->opcode));
5455 gen_op_440_tlbwe(rB(ctx->opcode));
5458 GEN_EXCP_INVAL(ctx);
5465 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_EMB_COMMON)
5467 #if defined(CONFIG_USER_ONLY)
5468 GEN_EXCP_PRIVOPC(ctx);
5470 if (unlikely(!ctx->supervisor)) {
5471 GEN_EXCP_PRIVOPC(ctx);
5474 gen_op_load_gpr_T0(rD(ctx->opcode));
5476 /* Stop translation to have a chance to raise an exception
5477 * if we just set msr_ee to 1
5484 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_EMB_COMMON)
5486 #if defined(CONFIG_USER_ONLY)
5487 GEN_EXCP_PRIVOPC(ctx);
5489 if (unlikely(!ctx->supervisor)) {
5490 GEN_EXCP_PRIVOPC(ctx);
5493 gen_op_set_T0(ctx->opcode & 0x00010000);
5495 /* Stop translation to have a chance to raise an exception
5496 * if we just set msr_ee to 1
5502 /* PowerPC 440 specific instructions */
5504 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
5506 gen_op_load_gpr_T0(rS(ctx->opcode));
5507 gen_op_load_gpr_T1(rB(ctx->opcode));
5509 gen_op_store_T0_gpr(rA(ctx->opcode));
5510 gen_op_store_xer_bc();
5511 if (Rc(ctx->opcode)) {
5512 gen_op_440_dlmzb_update_Rc();
5513 gen_op_store_T0_crf(0);
5517 /* mbar replaces eieio on 440 */
5518 GEN_HANDLER(mbar, 0x1F, 0x16, 0x13, 0x001FF801, PPC_BOOKE)
5520 /* interpreted as no-op */
5523 /* msync replaces sync on 440 */
5524 GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
5526 /* interpreted as no-op */
5530 GEN_HANDLER(icbt_440, 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
5532 /* interpreted as no-op */
5533 /* XXX: specification say this is treated as a load by the MMU
5534 * but does not generate any exception
5538 /*** Altivec vector extension ***/
5539 /* Altivec registers moves */
5540 GEN32(gen_op_load_avr_A0, gen_op_load_avr_A0_avr);
5541 GEN32(gen_op_load_avr_A1, gen_op_load_avr_A1_avr);
5542 GEN32(gen_op_load_avr_A2, gen_op_load_avr_A2_avr);
5544 GEN32(gen_op_store_A0_avr, gen_op_store_A0_avr_avr);
5545 GEN32(gen_op_store_A1_avr, gen_op_store_A1_avr_avr);
5547 GEN32(gen_op_store_A2_avr, gen_op_store_A2_avr_avr);
5550 #define op_vr_ldst(name) (*gen_op_##name[ctx->mem_idx])()
5551 #if defined(CONFIG_USER_ONLY)
5552 #if defined(TARGET_PPC64)
5553 /* User-mode only - 64 bits mode */
5554 #define OP_VR_LD_TABLE(name) \
5555 static GenOpFunc *gen_op_vr_l##name[] = { \
5556 &gen_op_vr_l##name##_raw, \
5557 &gen_op_vr_l##name##_le_raw, \
5558 &gen_op_vr_l##name##_64_raw, \
5559 &gen_op_vr_l##name##_le_64_raw, \
5561 #define OP_VR_ST_TABLE(name) \
5562 static GenOpFunc *gen_op_vr_st##name[] = { \
5563 &gen_op_vr_st##name##_raw, \
5564 &gen_op_vr_st##name##_le_raw, \
5565 &gen_op_vr_st##name##_64_raw, \
5566 &gen_op_vr_st##name##_le_64_raw, \
5568 #else /* defined(TARGET_PPC64) */
5569 /* User-mode only - 32 bits mode */
5570 #define OP_VR_LD_TABLE(name) \
5571 static GenOpFunc *gen_op_vr_l##name[] = { \
5572 &gen_op_vr_l##name##_raw, \
5573 &gen_op_vr_l##name##_le_raw, \
5575 #define OP_VR_ST_TABLE(name) \
5576 static GenOpFunc *gen_op_vr_st##name[] = { \
5577 &gen_op_vr_st##name##_raw, \
5578 &gen_op_vr_st##name##_le_raw, \
5580 #endif /* defined(TARGET_PPC64) */
5581 #else /* defined(CONFIG_USER_ONLY) */
5582 #if defined(TARGET_PPC64H)
5583 /* Full system with hypervisor mode */
5584 #define OP_VR_LD_TABLE(name) \
5585 static GenOpFunc *gen_op_vr_l##name[] = { \
5586 &gen_op_vr_l##name##_user, \
5587 &gen_op_vr_l##name##_le_user, \
5588 &gen_op_vr_l##name##_64_user, \
5589 &gen_op_vr_l##name##_le_64_user, \
5590 &gen_op_vr_l##name##_kernel, \
5591 &gen_op_vr_l##name##_le_kernel, \
5592 &gen_op_vr_l##name##_64_kernel, \
5593 &gen_op_vr_l##name##_le_64_kernel, \
5594 &gen_op_vr_l##name##_hypv, \
5595 &gen_op_vr_l##name##_le_hypv, \
5596 &gen_op_vr_l##name##_64_hypv, \
5597 &gen_op_vr_l##name##_le_64_hypv, \
5599 #define OP_VR_ST_TABLE(name) \
5600 static GenOpFunc *gen_op_vr_st##name[] = { \
5601 &gen_op_vr_st##name##_user, \
5602 &gen_op_vr_st##name##_le_user, \
5603 &gen_op_vr_st##name##_64_user, \
5604 &gen_op_vr_st##name##_le_64_user, \
5605 &gen_op_vr_st##name##_kernel, \
5606 &gen_op_vr_st##name##_le_kernel, \
5607 &gen_op_vr_st##name##_64_kernel, \
5608 &gen_op_vr_st##name##_le_64_kernel, \
5609 &gen_op_vr_st##name##_hypv, \
5610 &gen_op_vr_st##name##_le_hypv, \
5611 &gen_op_vr_st##name##_64_hypv, \
5612 &gen_op_vr_st##name##_le_64_hypv, \
5614 #elif defined(TARGET_PPC64)
5615 /* Full system - 64 bits mode */
5616 #define OP_VR_LD_TABLE(name) \
5617 static GenOpFunc *gen_op_vr_l##name[] = { \
5618 &gen_op_vr_l##name##_user, \
5619 &gen_op_vr_l##name##_le_user, \
5620 &gen_op_vr_l##name##_64_user, \
5621 &gen_op_vr_l##name##_le_64_user, \
5622 &gen_op_vr_l##name##_kernel, \
5623 &gen_op_vr_l##name##_le_kernel, \
5624 &gen_op_vr_l##name##_64_kernel, \
5625 &gen_op_vr_l##name##_le_64_kernel, \
5627 #define OP_VR_ST_TABLE(name) \
5628 static GenOpFunc *gen_op_vr_st##name[] = { \
5629 &gen_op_vr_st##name##_user, \
5630 &gen_op_vr_st##name##_le_user, \
5631 &gen_op_vr_st##name##_64_user, \
5632 &gen_op_vr_st##name##_le_64_user, \
5633 &gen_op_vr_st##name##_kernel, \
5634 &gen_op_vr_st##name##_le_kernel, \
5635 &gen_op_vr_st##name##_64_kernel, \
5636 &gen_op_vr_st##name##_le_64_kernel, \
5638 #else /* defined(TARGET_PPC64) */
5639 /* Full system - 32 bits mode */
5640 #define OP_VR_LD_TABLE(name) \
5641 static GenOpFunc *gen_op_vr_l##name[] = { \
5642 &gen_op_vr_l##name##_user, \
5643 &gen_op_vr_l##name##_le_user, \
5644 &gen_op_vr_l##name##_kernel, \
5645 &gen_op_vr_l##name##_le_kernel, \
5647 #define OP_VR_ST_TABLE(name) \
5648 static GenOpFunc *gen_op_vr_st##name[] = { \
5649 &gen_op_vr_st##name##_user, \
5650 &gen_op_vr_st##name##_le_user, \
5651 &gen_op_vr_st##name##_kernel, \
5652 &gen_op_vr_st##name##_le_kernel, \
5654 #endif /* defined(TARGET_PPC64) */
5655 #endif /* defined(CONFIG_USER_ONLY) */
5657 #define GEN_VR_LDX(name, opc2, opc3) \
5658 GEN_HANDLER(l##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5660 if (unlikely(!ctx->altivec_enabled)) { \
5661 GEN_EXCP_NO_VR(ctx); \
5664 gen_addr_reg_index(ctx); \
5665 op_vr_ldst(vr_l##name); \
5666 gen_op_store_A0_avr(rD(ctx->opcode)); \
5669 #define GEN_VR_STX(name, opc2, opc3) \
5670 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5672 if (unlikely(!ctx->altivec_enabled)) { \
5673 GEN_EXCP_NO_VR(ctx); \
5676 gen_addr_reg_index(ctx); \
5677 gen_op_load_avr_A0(rS(ctx->opcode)); \
5678 op_vr_ldst(vr_st##name); \
5682 GEN_VR_LDX(vx, 0x07, 0x03);
5683 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
5684 #define gen_op_vr_lvxl gen_op_vr_lvx
5685 GEN_VR_LDX(vxl, 0x07, 0x0B);
5688 GEN_VR_STX(vx, 0x07, 0x07);
5689 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
5690 #define gen_op_vr_stvxl gen_op_vr_stvx
5691 GEN_VR_STX(vxl, 0x07, 0x0F);
5693 #if defined(TARGET_PPCEMB)
5694 /*** SPE extension ***/
5696 /* Register moves */
5697 GEN32(gen_op_load_gpr64_T0, gen_op_load_gpr64_T0_gpr);
5698 GEN32(gen_op_load_gpr64_T1, gen_op_load_gpr64_T1_gpr);
5700 GEN32(gen_op_load_gpr64_T2, gen_op_load_gpr64_T2_gpr);
5703 GEN32(gen_op_store_T0_gpr64, gen_op_store_T0_gpr64_gpr);
5704 GEN32(gen_op_store_T1_gpr64, gen_op_store_T1_gpr64_gpr);
5706 GEN32(gen_op_store_T2_gpr64, gen_op_store_T2_gpr64_gpr);
5709 #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
5710 GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
5712 if (Rc(ctx->opcode)) \
5718 /* Handler for undefined SPE opcodes */
5719 static always_inline void gen_speundef (DisasContext *ctx)
5721 GEN_EXCP_INVAL(ctx);
5724 /* SPE load and stores */
5725 static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, int sh)
5727 target_long simm = rB(ctx->opcode);
5729 if (rA(ctx->opcode) == 0) {
5730 gen_set_T0(simm << sh);
5732 gen_op_load_gpr_T0(rA(ctx->opcode));
5733 if (likely(simm != 0))
5734 gen_op_addi(simm << sh);
5738 #define op_spe_ldst(name) (*gen_op_##name[ctx->mem_idx])()
5739 #if defined(CONFIG_USER_ONLY)
5740 #if defined(TARGET_PPC64)
5741 /* User-mode only - 64 bits mode */
5742 #define OP_SPE_LD_TABLE(name) \
5743 static GenOpFunc *gen_op_spe_l##name[] = { \
5744 &gen_op_spe_l##name##_raw, \
5745 &gen_op_spe_l##name##_le_raw, \
5746 &gen_op_spe_l##name##_64_raw, \
5747 &gen_op_spe_l##name##_le_64_raw, \
5749 #define OP_SPE_ST_TABLE(name) \
5750 static GenOpFunc *gen_op_spe_st##name[] = { \
5751 &gen_op_spe_st##name##_raw, \
5752 &gen_op_spe_st##name##_le_raw, \
5753 &gen_op_spe_st##name##_64_raw, \
5754 &gen_op_spe_st##name##_le_64_raw, \
5756 #else /* defined(TARGET_PPC64) */
5757 /* User-mode only - 32 bits mode */
5758 #define OP_SPE_LD_TABLE(name) \
5759 static GenOpFunc *gen_op_spe_l##name[] = { \
5760 &gen_op_spe_l##name##_raw, \
5761 &gen_op_spe_l##name##_le_raw, \
5763 #define OP_SPE_ST_TABLE(name) \
5764 static GenOpFunc *gen_op_spe_st##name[] = { \
5765 &gen_op_spe_st##name##_raw, \
5766 &gen_op_spe_st##name##_le_raw, \
5768 #endif /* defined(TARGET_PPC64) */
5769 #else /* defined(CONFIG_USER_ONLY) */
5770 #if defined(TARGET_PPC64H)
5771 /* Full system with hypervisor mode */
5772 #define OP_SPE_LD_TABLE(name) \
5773 static GenOpFunc *gen_op_spe_l##name[] = { \
5774 &gen_op_spe_l##name##_user, \
5775 &gen_op_spe_l##name##_le_user, \
5776 &gen_op_spe_l##name##_64_user, \
5777 &gen_op_spe_l##name##_le_64_user, \
5778 &gen_op_spe_l##name##_kernel, \
5779 &gen_op_spe_l##name##_le_kernel, \
5780 &gen_op_spe_l##name##_64_kernel, \
5781 &gen_op_spe_l##name##_le_64_kernel, \
5782 &gen_op_spe_l##name##_hypv, \
5783 &gen_op_spe_l##name##_le_hypv, \
5784 &gen_op_spe_l##name##_64_hypv, \
5785 &gen_op_spe_l##name##_le_64_hypv, \
5787 #define OP_SPE_ST_TABLE(name) \
5788 static GenOpFunc *gen_op_spe_st##name[] = { \
5789 &gen_op_spe_st##name##_user, \
5790 &gen_op_spe_st##name##_le_user, \
5791 &gen_op_spe_st##name##_64_user, \
5792 &gen_op_spe_st##name##_le_64_user, \
5793 &gen_op_spe_st##name##_kernel, \
5794 &gen_op_spe_st##name##_le_kernel, \
5795 &gen_op_spe_st##name##_64_kernel, \
5796 &gen_op_spe_st##name##_le_64_kernel, \
5797 &gen_op_spe_st##name##_hypv, \
5798 &gen_op_spe_st##name##_le_hypv, \
5799 &gen_op_spe_st##name##_64_hypv, \
5800 &gen_op_spe_st##name##_le_64_hypv, \
5802 #elif defined(TARGET_PPC64)
5803 /* Full system - 64 bits mode */
5804 #define OP_SPE_LD_TABLE(name) \
5805 static GenOpFunc *gen_op_spe_l##name[] = { \
5806 &gen_op_spe_l##name##_user, \
5807 &gen_op_spe_l##name##_le_user, \
5808 &gen_op_spe_l##name##_64_user, \
5809 &gen_op_spe_l##name##_le_64_user, \
5810 &gen_op_spe_l##name##_kernel, \
5811 &gen_op_spe_l##name##_le_kernel, \
5812 &gen_op_spe_l##name##_64_kernel, \
5813 &gen_op_spe_l##name##_le_64_kernel, \
5815 #define OP_SPE_ST_TABLE(name) \
5816 static GenOpFunc *gen_op_spe_st##name[] = { \
5817 &gen_op_spe_st##name##_user, \
5818 &gen_op_spe_st##name##_le_user, \
5819 &gen_op_spe_st##name##_64_user, \
5820 &gen_op_spe_st##name##_le_64_user, \
5821 &gen_op_spe_st##name##_kernel, \
5822 &gen_op_spe_st##name##_le_kernel, \
5823 &gen_op_spe_st##name##_64_kernel, \
5824 &gen_op_spe_st##name##_le_64_kernel, \
5826 #else /* defined(TARGET_PPC64) */
5827 /* Full system - 32 bits mode */
5828 #define OP_SPE_LD_TABLE(name) \
5829 static GenOpFunc *gen_op_spe_l##name[] = { \
5830 &gen_op_spe_l##name##_user, \
5831 &gen_op_spe_l##name##_le_user, \
5832 &gen_op_spe_l##name##_kernel, \
5833 &gen_op_spe_l##name##_le_kernel, \
5835 #define OP_SPE_ST_TABLE(name) \
5836 static GenOpFunc *gen_op_spe_st##name[] = { \
5837 &gen_op_spe_st##name##_user, \
5838 &gen_op_spe_st##name##_le_user, \
5839 &gen_op_spe_st##name##_kernel, \
5840 &gen_op_spe_st##name##_le_kernel, \
5842 #endif /* defined(TARGET_PPC64) */
5843 #endif /* defined(CONFIG_USER_ONLY) */
5845 #define GEN_SPE_LD(name, sh) \
5846 static always_inline void gen_evl##name (DisasContext *ctx) \
5848 if (unlikely(!ctx->spe_enabled)) { \
5849 GEN_EXCP_NO_AP(ctx); \
5852 gen_addr_spe_imm_index(ctx, sh); \
5853 op_spe_ldst(spe_l##name); \
5854 gen_op_store_T1_gpr64(rD(ctx->opcode)); \
5857 #define GEN_SPE_LDX(name) \
5858 static always_inline void gen_evl##name##x (DisasContext *ctx) \
5860 if (unlikely(!ctx->spe_enabled)) { \
5861 GEN_EXCP_NO_AP(ctx); \
5864 gen_addr_reg_index(ctx); \
5865 op_spe_ldst(spe_l##name); \
5866 gen_op_store_T1_gpr64(rD(ctx->opcode)); \
5869 #define GEN_SPEOP_LD(name, sh) \
5870 OP_SPE_LD_TABLE(name); \
5871 GEN_SPE_LD(name, sh); \
5874 #define GEN_SPE_ST(name, sh) \
5875 static always_inline void gen_evst##name (DisasContext *ctx) \
5877 if (unlikely(!ctx->spe_enabled)) { \
5878 GEN_EXCP_NO_AP(ctx); \
5881 gen_addr_spe_imm_index(ctx, sh); \
5882 gen_op_load_gpr64_T1(rS(ctx->opcode)); \
5883 op_spe_ldst(spe_st##name); \
5886 #define GEN_SPE_STX(name) \
5887 static always_inline void gen_evst##name##x (DisasContext *ctx) \
5889 if (unlikely(!ctx->spe_enabled)) { \
5890 GEN_EXCP_NO_AP(ctx); \
5893 gen_addr_reg_index(ctx); \
5894 gen_op_load_gpr64_T1(rS(ctx->opcode)); \
5895 op_spe_ldst(spe_st##name); \
5898 #define GEN_SPEOP_ST(name, sh) \
5899 OP_SPE_ST_TABLE(name); \
5900 GEN_SPE_ST(name, sh); \
5903 #define GEN_SPEOP_LDST(name, sh) \
5904 GEN_SPEOP_LD(name, sh); \
5905 GEN_SPEOP_ST(name, sh)
5907 /* SPE arithmetic and logic */
5908 #define GEN_SPEOP_ARITH2(name) \
5909 static always_inline void gen_##name (DisasContext *ctx) \
5911 if (unlikely(!ctx->spe_enabled)) { \
5912 GEN_EXCP_NO_AP(ctx); \
5915 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
5916 gen_op_load_gpr64_T1(rB(ctx->opcode)); \
5918 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
5921 #define GEN_SPEOP_ARITH1(name) \
5922 static always_inline void gen_##name (DisasContext *ctx) \
5924 if (unlikely(!ctx->spe_enabled)) { \
5925 GEN_EXCP_NO_AP(ctx); \
5928 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
5930 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
5933 #define GEN_SPEOP_COMP(name) \
5934 static always_inline void gen_##name (DisasContext *ctx) \
5936 if (unlikely(!ctx->spe_enabled)) { \
5937 GEN_EXCP_NO_AP(ctx); \
5940 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
5941 gen_op_load_gpr64_T1(rB(ctx->opcode)); \
5943 gen_op_store_T0_crf(crfD(ctx->opcode)); \
5947 GEN_SPEOP_ARITH2(evand);
5948 GEN_SPEOP_ARITH2(evandc);
5949 GEN_SPEOP_ARITH2(evxor);
5950 GEN_SPEOP_ARITH2(evor);
5951 GEN_SPEOP_ARITH2(evnor);
5952 GEN_SPEOP_ARITH2(eveqv);
5953 GEN_SPEOP_ARITH2(evorc);
5954 GEN_SPEOP_ARITH2(evnand);
5955 GEN_SPEOP_ARITH2(evsrwu);
5956 GEN_SPEOP_ARITH2(evsrws);
5957 GEN_SPEOP_ARITH2(evslw);
5958 GEN_SPEOP_ARITH2(evrlw);
5959 GEN_SPEOP_ARITH2(evmergehi);
5960 GEN_SPEOP_ARITH2(evmergelo);
5961 GEN_SPEOP_ARITH2(evmergehilo);
5962 GEN_SPEOP_ARITH2(evmergelohi);
5965 GEN_SPEOP_ARITH2(evaddw);
5966 GEN_SPEOP_ARITH2(evsubfw);
5967 GEN_SPEOP_ARITH1(evabs);
5968 GEN_SPEOP_ARITH1(evneg);
5969 GEN_SPEOP_ARITH1(evextsb);
5970 GEN_SPEOP_ARITH1(evextsh);
5971 GEN_SPEOP_ARITH1(evrndw);
5972 GEN_SPEOP_ARITH1(evcntlzw);
5973 GEN_SPEOP_ARITH1(evcntlsw);
5974 static always_inline void gen_brinc (DisasContext *ctx)
5976 /* Note: brinc is usable even if SPE is disabled */
5977 gen_op_load_gpr64_T0(rA(ctx->opcode));
5978 gen_op_load_gpr64_T1(rB(ctx->opcode));
5980 gen_op_store_T0_gpr64(rD(ctx->opcode));
5983 #define GEN_SPEOP_ARITH_IMM2(name) \
5984 static always_inline void gen_##name##i (DisasContext *ctx) \
5986 if (unlikely(!ctx->spe_enabled)) { \
5987 GEN_EXCP_NO_AP(ctx); \
5990 gen_op_load_gpr64_T0(rB(ctx->opcode)); \
5991 gen_op_splatwi_T1_64(rA(ctx->opcode)); \
5993 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
5996 #define GEN_SPEOP_LOGIC_IMM2(name) \
5997 static always_inline void gen_##name##i (DisasContext *ctx) \
5999 if (unlikely(!ctx->spe_enabled)) { \
6000 GEN_EXCP_NO_AP(ctx); \
6003 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
6004 gen_op_splatwi_T1_64(rB(ctx->opcode)); \
6006 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
6009 GEN_SPEOP_ARITH_IMM2(evaddw);
6010 #define gen_evaddiw gen_evaddwi
6011 GEN_SPEOP_ARITH_IMM2(evsubfw);
6012 #define gen_evsubifw gen_evsubfwi
6013 GEN_SPEOP_LOGIC_IMM2(evslw);
6014 GEN_SPEOP_LOGIC_IMM2(evsrwu);
6015 #define gen_evsrwis gen_evsrwsi
6016 GEN_SPEOP_LOGIC_IMM2(evsrws);
6017 #define gen_evsrwiu gen_evsrwui
6018 GEN_SPEOP_LOGIC_IMM2(evrlw);
6020 static always_inline void gen_evsplati (DisasContext *ctx)
6022 int32_t imm = (int32_t)(rA(ctx->opcode) << 27) >> 27;
6024 gen_op_splatwi_T0_64(imm);
6025 gen_op_store_T0_gpr64(rD(ctx->opcode));
6028 static always_inline void gen_evsplatfi (DisasContext *ctx)
6030 uint32_t imm = rA(ctx->opcode) << 27;
6032 gen_op_splatwi_T0_64(imm);
6033 gen_op_store_T0_gpr64(rD(ctx->opcode));
6037 GEN_SPEOP_COMP(evcmpgtu);
6038 GEN_SPEOP_COMP(evcmpgts);
6039 GEN_SPEOP_COMP(evcmpltu);
6040 GEN_SPEOP_COMP(evcmplts);
6041 GEN_SPEOP_COMP(evcmpeq);
6043 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
6044 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
6045 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
6046 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
6047 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
6048 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
6049 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
6050 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
6051 GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
6052 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
6053 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
6054 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
6055 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
6056 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
6057 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
6058 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
6059 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
6060 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
6061 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
6062 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
6063 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
6064 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
6065 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
6066 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
6067 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
6069 static always_inline void gen_evsel (DisasContext *ctx)
6071 if (unlikely(!ctx->spe_enabled)) {
6072 GEN_EXCP_NO_AP(ctx);
6075 gen_op_load_crf_T0(ctx->opcode & 0x7);
6076 gen_op_load_gpr64_T0(rA(ctx->opcode));
6077 gen_op_load_gpr64_T1(rB(ctx->opcode));
6079 gen_op_store_T0_gpr64(rD(ctx->opcode));
6082 GEN_HANDLER(evsel0, 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
6086 GEN_HANDLER(evsel1, 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
6090 GEN_HANDLER(evsel2, 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
6094 GEN_HANDLER(evsel3, 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
6099 /* Load and stores */
6100 #if defined(TARGET_PPC64)
6101 /* In that case, we already have 64 bits load & stores
6102 * so, spe_ldd is equivalent to ld and spe_std is equivalent to std
6104 #if defined(CONFIG_USER_ONLY)
6105 #define gen_op_spe_ldd_raw gen_op_ld_raw
6106 #define gen_op_spe_ldd_64_raw gen_op_ld_64_raw
6107 #define gen_op_spe_ldd_le_raw gen_op_ld_le_raw
6108 #define gen_op_spe_ldd_le_64_raw gen_op_ld_le_64_raw
6109 #define gen_op_spe_stdd_raw gen_op_ld_raw
6110 #define gen_op_spe_stdd_64_raw gen_op_std_64_raw
6111 #define gen_op_spe_stdd_le_raw gen_op_std_le_raw
6112 #define gen_op_spe_stdd_le_64_raw gen_op_std_le_64_raw
6113 #else /* defined(CONFIG_USER_ONLY) */
6114 #define gen_op_spe_ldd_kernel gen_op_ld_kernel
6115 #define gen_op_spe_ldd_64_kernel gen_op_ld_64_kernel
6116 #define gen_op_spe_ldd_le_kernel gen_op_ld_kernel
6117 #define gen_op_spe_ldd_le_64_kernel gen_op_ld_64_kernel
6118 #define gen_op_spe_ldd_user gen_op_ld_user
6119 #define gen_op_spe_ldd_64_user gen_op_ld_64_user
6120 #define gen_op_spe_ldd_le_user gen_op_ld_le_user
6121 #define gen_op_spe_ldd_le_64_user gen_op_ld_le_64_user
6122 #define gen_op_spe_stdd_kernel gen_op_std_kernel
6123 #define gen_op_spe_stdd_64_kernel gen_op_std_64_kernel
6124 #define gen_op_spe_stdd_le_kernel gen_op_std_kernel
6125 #define gen_op_spe_stdd_le_64_kernel gen_op_std_64_kernel
6126 #define gen_op_spe_stdd_user gen_op_std_user
6127 #define gen_op_spe_stdd_64_user gen_op_std_64_user
6128 #define gen_op_spe_stdd_le_user gen_op_std_le_user
6129 #define gen_op_spe_stdd_le_64_user gen_op_std_le_64_user
6130 #endif /* defined(CONFIG_USER_ONLY) */
6131 #endif /* defined(TARGET_PPC64) */
6132 GEN_SPEOP_LDST(dd, 3);
6133 GEN_SPEOP_LDST(dw, 3);
6134 GEN_SPEOP_LDST(dh, 3);
6135 GEN_SPEOP_LDST(whe, 2);
6136 GEN_SPEOP_LD(whou, 2);
6137 GEN_SPEOP_LD(whos, 2);
6138 GEN_SPEOP_ST(who, 2);
6140 #if defined(TARGET_PPC64)
6141 /* In that case, spe_stwwo is equivalent to stw */
6142 #if defined(CONFIG_USER_ONLY)
6143 #define gen_op_spe_stwwo_raw gen_op_stw_raw
6144 #define gen_op_spe_stwwo_le_raw gen_op_stw_le_raw
6145 #define gen_op_spe_stwwo_64_raw gen_op_stw_64_raw
6146 #define gen_op_spe_stwwo_le_64_raw gen_op_stw_le_64_raw
6148 #define gen_op_spe_stwwo_user gen_op_stw_user
6149 #define gen_op_spe_stwwo_le_user gen_op_stw_le_user
6150 #define gen_op_spe_stwwo_64_user gen_op_stw_64_user
6151 #define gen_op_spe_stwwo_le_64_user gen_op_stw_le_64_user
6152 #define gen_op_spe_stwwo_kernel gen_op_stw_kernel
6153 #define gen_op_spe_stwwo_le_kernel gen_op_stw_le_kernel
6154 #define gen_op_spe_stwwo_64_kernel gen_op_stw_64_kernel
6155 #define gen_op_spe_stwwo_le_64_kernel gen_op_stw_le_64_kernel
6158 #define _GEN_OP_SPE_STWWE(suffix) \
6159 static always_inline void gen_op_spe_stwwe_##suffix (void) \
6161 gen_op_srli32_T1_64(); \
6162 gen_op_spe_stwwo_##suffix(); \
6164 #define _GEN_OP_SPE_STWWE_LE(suffix) \
6165 static always_inline void gen_op_spe_stwwe_le_##suffix (void) \
6167 gen_op_srli32_T1_64(); \
6168 gen_op_spe_stwwo_le_##suffix(); \
6170 #if defined(TARGET_PPC64)
6171 #define GEN_OP_SPE_STWWE(suffix) \
6172 _GEN_OP_SPE_STWWE(suffix); \
6173 _GEN_OP_SPE_STWWE_LE(suffix); \
6174 static always_inline void gen_op_spe_stwwe_64_##suffix (void) \
6176 gen_op_srli32_T1_64(); \
6177 gen_op_spe_stwwo_64_##suffix(); \
6179 static always_inline void gen_op_spe_stwwe_le_64_##suffix (void) \
6181 gen_op_srli32_T1_64(); \
6182 gen_op_spe_stwwo_le_64_##suffix(); \
6185 #define GEN_OP_SPE_STWWE(suffix) \
6186 _GEN_OP_SPE_STWWE(suffix); \
6187 _GEN_OP_SPE_STWWE_LE(suffix)
6189 #if defined(CONFIG_USER_ONLY)
6190 GEN_OP_SPE_STWWE(raw);
6191 #else /* defined(CONFIG_USER_ONLY) */
6192 GEN_OP_SPE_STWWE(kernel);
6193 GEN_OP_SPE_STWWE(user);
6194 #endif /* defined(CONFIG_USER_ONLY) */
6195 GEN_SPEOP_ST(wwe, 2);
6196 GEN_SPEOP_ST(wwo, 2);
6198 #define GEN_SPE_LDSPLAT(name, op, suffix) \
6199 static always_inline void gen_op_spe_l##name##_##suffix (void) \
6201 gen_op_##op##_##suffix(); \
6202 gen_op_splatw_T1_64(); \
6205 #define GEN_OP_SPE_LHE(suffix) \
6206 static always_inline void gen_op_spe_lhe_##suffix (void) \
6208 gen_op_spe_lh_##suffix(); \
6209 gen_op_sli16_T1_64(); \
6212 #define GEN_OP_SPE_LHX(suffix) \
6213 static always_inline void gen_op_spe_lhx_##suffix (void) \
6215 gen_op_spe_lh_##suffix(); \
6216 gen_op_extsh_T1_64(); \
6219 #if defined(CONFIG_USER_ONLY)
6220 GEN_OP_SPE_LHE(raw);
6221 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, raw);
6222 GEN_OP_SPE_LHE(le_raw);
6223 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_raw);
6224 GEN_SPE_LDSPLAT(hhousplat, spe_lh, raw);
6225 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_raw);
6226 GEN_OP_SPE_LHX(raw);
6227 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, raw);
6228 GEN_OP_SPE_LHX(le_raw);
6229 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_raw);
6230 #if defined(TARGET_PPC64)
6231 GEN_OP_SPE_LHE(64_raw);
6232 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_raw);
6233 GEN_OP_SPE_LHE(le_64_raw);
6234 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_raw);
6235 GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_raw);
6236 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_raw);
6237 GEN_OP_SPE_LHX(64_raw);
6238 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_raw);
6239 GEN_OP_SPE_LHX(le_64_raw);
6240 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_raw);
6243 GEN_OP_SPE_LHE(kernel);
6244 GEN_OP_SPE_LHE(user);
6245 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, kernel);
6246 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, user);
6247 GEN_OP_SPE_LHE(le_kernel);
6248 GEN_OP_SPE_LHE(le_user);
6249 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_kernel);
6250 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_user);
6251 GEN_SPE_LDSPLAT(hhousplat, spe_lh, kernel);
6252 GEN_SPE_LDSPLAT(hhousplat, spe_lh, user);
6253 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_kernel);
6254 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_user);
6255 GEN_OP_SPE_LHX(kernel);
6256 GEN_OP_SPE_LHX(user);
6257 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, kernel);
6258 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, user);
6259 GEN_OP_SPE_LHX(le_kernel);
6260 GEN_OP_SPE_LHX(le_user);
6261 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_kernel);
6262 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_user);
6263 #if defined(TARGET_PPC64)
6264 GEN_OP_SPE_LHE(64_kernel);
6265 GEN_OP_SPE_LHE(64_user);
6266 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_kernel);
6267 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_user);
6268 GEN_OP_SPE_LHE(le_64_kernel);
6269 GEN_OP_SPE_LHE(le_64_user);
6270 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_kernel);
6271 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_user);
6272 GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_kernel);
6273 GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_user);
6274 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_kernel);
6275 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_user);
6276 GEN_OP_SPE_LHX(64_kernel);
6277 GEN_OP_SPE_LHX(64_user);
6278 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_kernel);
6279 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_user);
6280 GEN_OP_SPE_LHX(le_64_kernel);
6281 GEN_OP_SPE_LHX(le_64_user);
6282 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_kernel);
6283 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_user);
6286 GEN_SPEOP_LD(hhesplat, 1);
6287 GEN_SPEOP_LD(hhousplat, 1);
6288 GEN_SPEOP_LD(hhossplat, 1);
6289 GEN_SPEOP_LD(wwsplat, 2);
6290 GEN_SPEOP_LD(whsplat, 2);
6292 GEN_SPE(evlddx, evldd, 0x00, 0x0C, 0x00000000, PPC_SPE); //
6293 GEN_SPE(evldwx, evldw, 0x01, 0x0C, 0x00000000, PPC_SPE); //
6294 GEN_SPE(evldhx, evldh, 0x02, 0x0C, 0x00000000, PPC_SPE); //
6295 GEN_SPE(evlhhesplatx, evlhhesplat, 0x04, 0x0C, 0x00000000, PPC_SPE); //
6296 GEN_SPE(evlhhousplatx, evlhhousplat, 0x06, 0x0C, 0x00000000, PPC_SPE); //
6297 GEN_SPE(evlhhossplatx, evlhhossplat, 0x07, 0x0C, 0x00000000, PPC_SPE); //
6298 GEN_SPE(evlwhex, evlwhe, 0x08, 0x0C, 0x00000000, PPC_SPE); //
6299 GEN_SPE(evlwhoux, evlwhou, 0x0A, 0x0C, 0x00000000, PPC_SPE); //
6300 GEN_SPE(evlwhosx, evlwhos, 0x0B, 0x0C, 0x00000000, PPC_SPE); //
6301 GEN_SPE(evlwwsplatx, evlwwsplat, 0x0C, 0x0C, 0x00000000, PPC_SPE); //
6302 GEN_SPE(evlwhsplatx, evlwhsplat, 0x0E, 0x0C, 0x00000000, PPC_SPE); //
6303 GEN_SPE(evstddx, evstdd, 0x10, 0x0C, 0x00000000, PPC_SPE); //
6304 GEN_SPE(evstdwx, evstdw, 0x11, 0x0C, 0x00000000, PPC_SPE); //
6305 GEN_SPE(evstdhx, evstdh, 0x12, 0x0C, 0x00000000, PPC_SPE); //
6306 GEN_SPE(evstwhex, evstwhe, 0x18, 0x0C, 0x00000000, PPC_SPE); //
6307 GEN_SPE(evstwhox, evstwho, 0x1A, 0x0C, 0x00000000, PPC_SPE); //
6308 GEN_SPE(evstwwex, evstwwe, 0x1C, 0x0C, 0x00000000, PPC_SPE); //
6309 GEN_SPE(evstwwox, evstwwo, 0x1E, 0x0C, 0x00000000, PPC_SPE); //
6311 /* Multiply and add - TODO */
6313 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
6314 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
6315 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
6316 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
6317 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
6318 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
6319 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
6320 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
6321 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
6322 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
6323 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
6324 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
6326 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
6327 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
6328 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
6329 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
6330 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
6331 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
6332 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
6333 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
6334 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
6335 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
6336 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
6337 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
6338 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
6339 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
6341 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
6342 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
6343 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
6344 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
6345 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
6346 GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
6348 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
6349 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
6350 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
6351 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
6352 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
6353 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
6354 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
6355 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
6356 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
6357 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
6358 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
6359 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
6361 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
6362 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
6363 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
6364 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
6365 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
6367 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
6368 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
6369 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
6370 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
6371 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
6372 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
6373 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
6374 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
6375 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
6376 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
6377 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
6378 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
6380 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
6381 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
6382 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
6383 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
6384 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
6387 /*** SPE floating-point extension ***/
6388 #define GEN_SPEFPUOP_CONV(name) \
6389 static always_inline void gen_##name (DisasContext *ctx) \
6391 gen_op_load_gpr64_T0(rB(ctx->opcode)); \
6393 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
6396 /* Single precision floating-point vectors operations */
6398 GEN_SPEOP_ARITH2(evfsadd);
6399 GEN_SPEOP_ARITH2(evfssub);
6400 GEN_SPEOP_ARITH2(evfsmul);
6401 GEN_SPEOP_ARITH2(evfsdiv);
6402 GEN_SPEOP_ARITH1(evfsabs);
6403 GEN_SPEOP_ARITH1(evfsnabs);
6404 GEN_SPEOP_ARITH1(evfsneg);
6406 GEN_SPEFPUOP_CONV(evfscfui);
6407 GEN_SPEFPUOP_CONV(evfscfsi);
6408 GEN_SPEFPUOP_CONV(evfscfuf);
6409 GEN_SPEFPUOP_CONV(evfscfsf);
6410 GEN_SPEFPUOP_CONV(evfsctui);
6411 GEN_SPEFPUOP_CONV(evfsctsi);
6412 GEN_SPEFPUOP_CONV(evfsctuf);
6413 GEN_SPEFPUOP_CONV(evfsctsf);
6414 GEN_SPEFPUOP_CONV(evfsctuiz);
6415 GEN_SPEFPUOP_CONV(evfsctsiz);
6417 GEN_SPEOP_COMP(evfscmpgt);
6418 GEN_SPEOP_COMP(evfscmplt);
6419 GEN_SPEOP_COMP(evfscmpeq);
6420 GEN_SPEOP_COMP(evfststgt);
6421 GEN_SPEOP_COMP(evfststlt);
6422 GEN_SPEOP_COMP(evfststeq);
6424 /* Opcodes definitions */
6425 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
6426 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPEFPU); //
6427 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPEFPU); //
6428 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPEFPU); //
6429 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPEFPU); //
6430 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPEFPU); //
6431 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPEFPU); //
6432 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPEFPU); //
6433 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPEFPU); //
6434 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPEFPU); //
6435 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPEFPU); //
6436 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPEFPU); //
6437 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPEFPU); //
6438 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPEFPU); //
6440 /* Single precision floating-point operations */
6442 GEN_SPEOP_ARITH2(efsadd);
6443 GEN_SPEOP_ARITH2(efssub);
6444 GEN_SPEOP_ARITH2(efsmul);
6445 GEN_SPEOP_ARITH2(efsdiv);
6446 GEN_SPEOP_ARITH1(efsabs);
6447 GEN_SPEOP_ARITH1(efsnabs);
6448 GEN_SPEOP_ARITH1(efsneg);
6450 GEN_SPEFPUOP_CONV(efscfui);
6451 GEN_SPEFPUOP_CONV(efscfsi);
6452 GEN_SPEFPUOP_CONV(efscfuf);
6453 GEN_SPEFPUOP_CONV(efscfsf);
6454 GEN_SPEFPUOP_CONV(efsctui);
6455 GEN_SPEFPUOP_CONV(efsctsi);
6456 GEN_SPEFPUOP_CONV(efsctuf);
6457 GEN_SPEFPUOP_CONV(efsctsf);
6458 GEN_SPEFPUOP_CONV(efsctuiz);
6459 GEN_SPEFPUOP_CONV(efsctsiz);
6460 GEN_SPEFPUOP_CONV(efscfd);
6462 GEN_SPEOP_COMP(efscmpgt);
6463 GEN_SPEOP_COMP(efscmplt);
6464 GEN_SPEOP_COMP(efscmpeq);
6465 GEN_SPEOP_COMP(efststgt);
6466 GEN_SPEOP_COMP(efststlt);
6467 GEN_SPEOP_COMP(efststeq);
6469 /* Opcodes definitions */
6470 GEN_SPE(efsadd, efssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
6471 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU); //
6472 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU); //
6473 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPEFPU); //
6474 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPEFPU); //
6475 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPEFPU); //
6476 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPEFPU); //
6477 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPEFPU); //
6478 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPEFPU); //
6479 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPEFPU); //
6480 GEN_SPE(efsctuiz, efsctsiz, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU); //
6481 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPEFPU); //
6482 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPEFPU); //
6484 /* Double precision floating-point operations */
6486 GEN_SPEOP_ARITH2(efdadd);
6487 GEN_SPEOP_ARITH2(efdsub);
6488 GEN_SPEOP_ARITH2(efdmul);
6489 GEN_SPEOP_ARITH2(efddiv);
6490 GEN_SPEOP_ARITH1(efdabs);
6491 GEN_SPEOP_ARITH1(efdnabs);
6492 GEN_SPEOP_ARITH1(efdneg);
6495 GEN_SPEFPUOP_CONV(efdcfui);
6496 GEN_SPEFPUOP_CONV(efdcfsi);
6497 GEN_SPEFPUOP_CONV(efdcfuf);
6498 GEN_SPEFPUOP_CONV(efdcfsf);
6499 GEN_SPEFPUOP_CONV(efdctui);
6500 GEN_SPEFPUOP_CONV(efdctsi);
6501 GEN_SPEFPUOP_CONV(efdctuf);
6502 GEN_SPEFPUOP_CONV(efdctsf);
6503 GEN_SPEFPUOP_CONV(efdctuiz);
6504 GEN_SPEFPUOP_CONV(efdctsiz);
6505 GEN_SPEFPUOP_CONV(efdcfs);
6506 GEN_SPEFPUOP_CONV(efdcfuid);
6507 GEN_SPEFPUOP_CONV(efdcfsid);
6508 GEN_SPEFPUOP_CONV(efdctuidz);
6509 GEN_SPEFPUOP_CONV(efdctsidz);
6511 GEN_SPEOP_COMP(efdcmpgt);
6512 GEN_SPEOP_COMP(efdcmplt);
6513 GEN_SPEOP_COMP(efdcmpeq);
6514 GEN_SPEOP_COMP(efdtstgt);
6515 GEN_SPEOP_COMP(efdtstlt);
6516 GEN_SPEOP_COMP(efdtsteq);
6518 /* Opcodes definitions */
6519 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPEFPU); //
6520 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPEFPU); //
6521 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPEFPU); //
6522 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPEFPU); //
6523 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPEFPU); //
6524 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPEFPU); //
6525 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPEFPU); //
6526 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPEFPU); //
6527 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPEFPU); //
6528 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPEFPU); //
6529 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPEFPU); //
6530 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPEFPU); //
6531 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPEFPU); //
6532 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU); //
6533 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU); //
6534 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU); //
6537 /* End opcode list */
6538 GEN_OPCODE_MARK(end);
6540 #include "translate_init.c"
6541 #include "helper_regs.h"
6543 /*****************************************************************************/
6544 /* Misc PowerPC helpers */
6545 void cpu_dump_state (CPUState *env, FILE *f,
6546 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
6549 #if defined(TARGET_PPC64) || 1
6561 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " idx %d\n",
6562 env->nip, env->lr, env->ctr, env->mmu_idx);
6563 cpu_fprintf(f, "MSR " REGX FILL " XER %08x "
6564 #if !defined(NO_TIMER_DUMP)
6566 #if !defined(CONFIG_USER_ONLY)
6571 env->msr, hreg_load_xer(env)
6572 #if !defined(NO_TIMER_DUMP)
6573 , cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
6574 #if !defined(CONFIG_USER_ONLY)
6575 , cpu_ppc_load_decr(env)
6579 for (i = 0; i < 32; i++) {
6580 if ((i & (RGPL - 1)) == 0)
6581 cpu_fprintf(f, "GPR%02d", i);
6582 cpu_fprintf(f, " " REGX, (target_ulong)env->gpr[i]);
6583 if ((i & (RGPL - 1)) == (RGPL - 1))
6584 cpu_fprintf(f, "\n");
6586 cpu_fprintf(f, "CR ");
6587 for (i = 0; i < 8; i++)
6588 cpu_fprintf(f, "%01x", env->crf[i]);
6589 cpu_fprintf(f, " [");
6590 for (i = 0; i < 8; i++) {
6592 if (env->crf[i] & 0x08)
6594 else if (env->crf[i] & 0x04)
6596 else if (env->crf[i] & 0x02)
6598 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
6600 cpu_fprintf(f, " ] " FILL "RES " REGX "\n", env->reserve);
6601 for (i = 0; i < 32; i++) {
6602 if ((i & (RFPL - 1)) == 0)
6603 cpu_fprintf(f, "FPR%02d", i);
6604 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
6605 if ((i & (RFPL - 1)) == (RFPL - 1))
6606 cpu_fprintf(f, "\n");
6608 #if !defined(CONFIG_USER_ONLY)
6609 cpu_fprintf(f, "SRR0 " REGX " SRR1 " REGX " " FILL FILL FILL
6611 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
6619 void cpu_dump_statistics (CPUState *env, FILE*f,
6620 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
6623 #if defined(DO_PPC_STATISTICS)
6624 opc_handler_t **t1, **t2, **t3, *handler;
6628 for (op1 = 0; op1 < 64; op1++) {
6630 if (is_indirect_opcode(handler)) {
6631 t2 = ind_table(handler);
6632 for (op2 = 0; op2 < 32; op2++) {
6634 if (is_indirect_opcode(handler)) {
6635 t3 = ind_table(handler);
6636 for (op3 = 0; op3 < 32; op3++) {
6638 if (handler->count == 0)
6640 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
6642 op1, op2, op3, op1, (op3 << 5) | op2,
6644 handler->count, handler->count);
6647 if (handler->count == 0)
6649 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
6651 op1, op2, op1, op2, handler->oname,
6652 handler->count, handler->count);
6656 if (handler->count == 0)
6658 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
6659 op1, op1, handler->oname,
6660 handler->count, handler->count);
6666 /*****************************************************************************/
6667 static always_inline int gen_intermediate_code_internal (CPUState *env,
6668 TranslationBlock *tb,
6671 DisasContext ctx, *ctxp = &ctx;
6672 opc_handler_t **table, *handler;
6673 target_ulong pc_start;
6674 uint16_t *gen_opc_end;
6676 int single_step, branch_step;
6680 gen_opc_ptr = gen_opc_buf;
6681 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
6682 gen_opparam_ptr = gen_opparam_buf;
6686 ctx.exception = POWERPC_EXCP_NONE;
6687 ctx.spr_cb = env->spr_cb;
6688 supervisor = env->mmu_idx;
6689 #if !defined(CONFIG_USER_ONLY)
6690 ctx.supervisor = supervisor;
6692 #if defined(TARGET_PPC64)
6693 ctx.sf_mode = msr_sf;
6694 ctx.mem_idx = (supervisor << 2) | (msr_sf << 1) | msr_le;
6696 ctx.mem_idx = (supervisor << 1) | msr_le;
6698 ctx.dcache_line_size = env->dcache_line_size;
6699 ctx.fpu_enabled = msr_fp;
6700 #if defined(TARGET_PPCEMB)
6701 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
6702 ctx.spe_enabled = msr_spe;
6704 ctx.spe_enabled = 0;
6706 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
6707 ctx.altivec_enabled = msr_vr;
6709 ctx.altivec_enabled = 0;
6710 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
6714 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
6718 ctx.singlestep_enabled = env->singlestep_enabled || single_step == 1;
6719 #if defined (DO_SINGLE_STEP) && 0
6720 /* Single step trace mode */
6723 /* Set env in case of segfault during code fetch */
6724 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
6725 if (unlikely(env->nb_breakpoints > 0)) {
6726 for (j = 0; j < env->nb_breakpoints; j++) {
6727 if (env->breakpoints[j] == ctx.nip) {
6728 gen_update_nip(&ctx, ctx.nip);
6734 if (unlikely(search_pc)) {
6735 j = gen_opc_ptr - gen_opc_buf;
6739 gen_opc_instr_start[lj++] = 0;
6740 gen_opc_pc[lj] = ctx.nip;
6741 gen_opc_instr_start[lj] = 1;
6744 #if defined PPC_DEBUG_DISAS
6745 if (loglevel & CPU_LOG_TB_IN_ASM) {
6746 fprintf(logfile, "----------------\n");
6747 fprintf(logfile, "nip=" ADDRX " super=%d ir=%d\n",
6748 ctx.nip, supervisor, (int)msr_ir);
6751 ctx.opcode = ldl_code(ctx.nip);
6753 ctx.opcode = ((ctx.opcode & 0xFF000000) >> 24) |
6754 ((ctx.opcode & 0x00FF0000) >> 8) |
6755 ((ctx.opcode & 0x0000FF00) << 8) |
6756 ((ctx.opcode & 0x000000FF) << 24);
6758 #if defined PPC_DEBUG_DISAS
6759 if (loglevel & CPU_LOG_TB_IN_ASM) {
6760 fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n",
6761 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
6762 opc3(ctx.opcode), msr_le ? "little" : "big");
6766 table = env->opcodes;
6767 handler = table[opc1(ctx.opcode)];
6768 if (is_indirect_opcode(handler)) {
6769 table = ind_table(handler);
6770 handler = table[opc2(ctx.opcode)];
6771 if (is_indirect_opcode(handler)) {
6772 table = ind_table(handler);
6773 handler = table[opc3(ctx.opcode)];
6776 /* Is opcode *REALLY* valid ? */
6777 if (unlikely(handler->handler == &gen_invalid)) {
6778 if (loglevel != 0) {
6779 fprintf(logfile, "invalid/unsupported opcode: "
6780 "%02x - %02x - %02x (%08x) 0x" ADDRX " %d\n",
6781 opc1(ctx.opcode), opc2(ctx.opcode),
6782 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
6784 printf("invalid/unsupported opcode: "
6785 "%02x - %02x - %02x (%08x) 0x" ADDRX " %d\n",
6786 opc1(ctx.opcode), opc2(ctx.opcode),
6787 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
6790 if (unlikely((ctx.opcode & handler->inval) != 0)) {
6791 if (loglevel != 0) {
6792 fprintf(logfile, "invalid bits: %08x for opcode: "
6793 "%02x - %02x - %02x (%08x) 0x" ADDRX "\n",
6794 ctx.opcode & handler->inval, opc1(ctx.opcode),
6795 opc2(ctx.opcode), opc3(ctx.opcode),
6796 ctx.opcode, ctx.nip - 4);
6798 printf("invalid bits: %08x for opcode: "
6799 "%02x - %02x - %02x (%08x) 0x" ADDRX "\n",
6800 ctx.opcode & handler->inval, opc1(ctx.opcode),
6801 opc2(ctx.opcode), opc3(ctx.opcode),
6802 ctx.opcode, ctx.nip - 4);
6804 GEN_EXCP_INVAL(ctxp);
6808 (*(handler->handler))(&ctx);
6809 #if defined(DO_PPC_STATISTICS)
6812 /* Check trace mode exceptions */
6813 if (unlikely(branch_step != 0 &&
6814 ctx.exception == POWERPC_EXCP_BRANCH)) {
6815 GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0);
6816 } else if (unlikely(single_step != 0 &&
6817 (ctx.nip <= 0x100 || ctx.nip > 0xF00 ||
6818 (ctx.nip & 0xFC) != 0x04) &&
6819 ctx.exception != POWERPC_SYSCALL &&
6820 ctx.exception != POWERPC_EXCP_TRAP)) {
6821 GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0);
6822 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
6823 (env->singlestep_enabled))) {
6824 /* if we reach a page boundary or are single stepping, stop
6829 #if defined (DO_SINGLE_STEP)
6833 if (ctx.exception == POWERPC_EXCP_NONE) {
6834 gen_goto_tb(&ctx, 0, ctx.nip);
6835 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
6837 /* Generate the return instruction */
6840 *gen_opc_ptr = INDEX_op_end;
6841 if (unlikely(search_pc)) {
6842 j = gen_opc_ptr - gen_opc_buf;
6845 gen_opc_instr_start[lj++] = 0;
6847 tb->size = ctx.nip - pc_start;
6849 #if defined(DEBUG_DISAS)
6850 if (loglevel & CPU_LOG_TB_CPU) {
6851 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
6852 cpu_dump_state(env, logfile, fprintf, 0);
6854 if (loglevel & CPU_LOG_TB_IN_ASM) {
6856 flags = env->bfd_mach;
6857 flags |= msr_le << 16;
6858 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
6859 target_disas(logfile, pc_start, ctx.nip - pc_start, flags);
6860 fprintf(logfile, "\n");
6862 if (loglevel & CPU_LOG_TB_OP) {
6863 fprintf(logfile, "OP:\n");
6864 dump_ops(gen_opc_buf, gen_opparam_buf);
6865 fprintf(logfile, "\n");
6871 int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
6873 return gen_intermediate_code_internal(env, tb, 0);
6876 int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
6878 return gen_intermediate_code_internal(env, tb, 1);