2 * PowerPC emulation for qemu: main translation routines.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30 /* Include definitions for instructions classes and implementations flags */
31 //#define DO_SINGLE_STEP
32 //#define PPC_DEBUG_DISAS
33 //#define DEBUG_MEMORY_ACCESSES
34 //#define DO_PPC_STATISTICS
35 //#define OPTIMIZE_FPRF_UPDATE
37 /*****************************************************************************/
38 /* Code translation helpers */
39 #if defined(USE_DIRECT_JUMP)
42 #define TBPARAM(x) (long)(x)
46 #define DEF(s, n, copy_size) INDEX_op_ ## s,
52 static uint16_t *gen_opc_ptr;
53 static uint32_t *gen_opparam_ptr;
54 #if defined(OPTIMIZE_FPRF_UPDATE)
55 static uint16_t *gen_fprf_buf[OPC_BUF_SIZE];
56 static uint16_t **gen_fprf_ptr;
61 static always_inline void gen_set_T0 (target_ulong val)
63 #if defined(TARGET_PPC64)
65 gen_op_set_T0_64(val >> 32, val);
71 static always_inline void gen_set_T1 (target_ulong val)
73 #if defined(TARGET_PPC64)
75 gen_op_set_T1_64(val >> 32, val);
81 #define GEN8(func, NAME) \
82 static GenOpFunc *NAME ## _table [8] = { \
83 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
84 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
86 static always_inline void func (int n) \
88 NAME ## _table[n](); \
91 #define GEN16(func, NAME) \
92 static GenOpFunc *NAME ## _table [16] = { \
93 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
94 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
95 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
96 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
98 static always_inline void func (int n) \
100 NAME ## _table[n](); \
103 #define GEN32(func, NAME) \
104 static GenOpFunc *NAME ## _table [32] = { \
105 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
106 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
107 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
108 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
109 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
110 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
111 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
112 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
114 static always_inline void func (int n) \
116 NAME ## _table[n](); \
119 /* Condition register moves */
120 GEN8(gen_op_load_crf_T0, gen_op_load_crf_T0_crf);
121 GEN8(gen_op_load_crf_T1, gen_op_load_crf_T1_crf);
122 GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf);
124 GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf);
127 /* General purpose registers moves */
128 GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);
129 GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);
130 GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);
132 GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
133 GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
135 GEN32(gen_op_store_T2_gpr, gen_op_store_T2_gpr_gpr);
138 /* floating point registers moves */
139 GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr);
140 GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr);
141 GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fpr);
142 GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fpr);
143 GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fpr);
145 GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fpr);
148 /* internal defines */
149 typedef struct DisasContext {
150 struct TranslationBlock *tb;
154 /* Routine used to access memory */
156 /* Translation flags */
157 #if !defined(CONFIG_USER_ONLY)
160 #if defined(TARGET_PPC64)
165 #if defined(TARGET_PPCEMB)
168 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
169 int singlestep_enabled;
170 int dcache_line_size;
173 struct opc_handler_t {
176 /* instruction type */
179 void (*handler)(DisasContext *ctx);
180 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
181 const unsigned char *oname;
183 #if defined(DO_PPC_STATISTICS)
188 static always_inline void gen_set_Rc0 (DisasContext *ctx)
190 #if defined(TARGET_PPC64)
199 static always_inline void gen_reset_fpstatus (void)
201 #ifdef CONFIG_SOFTFLOAT
202 gen_op_reset_fpstatus();
206 static always_inline void gen_compute_fprf (int set_fprf, int set_rc)
209 /* This case might be optimized later */
210 #if defined(OPTIMIZE_FPRF_UPDATE)
211 *gen_fprf_ptr++ = gen_opc_ptr;
213 gen_op_compute_fprf(1);
214 if (unlikely(set_rc))
215 gen_op_store_T0_crf(1);
216 gen_op_float_check_status();
217 } else if (unlikely(set_rc)) {
218 /* We always need to compute fpcc */
219 gen_op_compute_fprf(0);
220 gen_op_store_T0_crf(1);
222 gen_op_float_check_status();
226 static always_inline void gen_optimize_fprf (void)
228 #if defined(OPTIMIZE_FPRF_UPDATE)
231 for (ptr = gen_fprf_buf; ptr != (gen_fprf_ptr - 1); ptr++)
232 *ptr = INDEX_op_nop1;
233 gen_fprf_ptr = gen_fprf_buf;
237 static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
239 #if defined(TARGET_PPC64)
241 gen_op_update_nip_64(nip >> 32, nip);
244 gen_op_update_nip(nip);
247 #define GEN_EXCP(ctx, excp, error) \
249 if ((ctx)->exception == POWERPC_EXCP_NONE) { \
250 gen_update_nip(ctx, (ctx)->nip); \
252 gen_op_raise_exception_err((excp), (error)); \
253 ctx->exception = (excp); \
256 #define GEN_EXCP_INVAL(ctx) \
257 GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
258 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL)
260 #define GEN_EXCP_PRIVOPC(ctx) \
261 GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
262 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC)
264 #define GEN_EXCP_PRIVREG(ctx) \
265 GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
266 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG)
268 #define GEN_EXCP_NO_FP(ctx) \
269 GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0)
271 #define GEN_EXCP_NO_AP(ctx) \
272 GEN_EXCP(ctx, POWERPC_EXCP_APU, 0)
274 #define GEN_EXCP_NO_VR(ctx) \
275 GEN_EXCP(ctx, POWERPC_EXCP_VPU, 0)
277 /* Stop translation */
278 static always_inline void GEN_STOP (DisasContext *ctx)
280 gen_update_nip(ctx, ctx->nip);
281 ctx->exception = POWERPC_EXCP_STOP;
284 /* No need to update nip here, as execution flow will change */
285 static always_inline void GEN_SYNC (DisasContext *ctx)
287 ctx->exception = POWERPC_EXCP_SYNC;
290 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
291 static void gen_##name (DisasContext *ctx); \
292 GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
293 static void gen_##name (DisasContext *ctx)
295 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
296 static void gen_##name (DisasContext *ctx); \
297 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
298 static void gen_##name (DisasContext *ctx)
300 typedef struct opcode_t {
301 unsigned char opc1, opc2, opc3;
302 #if HOST_LONG_BITS == 64 /* Explicitely align to 64 bits */
303 unsigned char pad[5];
305 unsigned char pad[1];
307 opc_handler_t handler;
308 const unsigned char *oname;
311 /*****************************************************************************/
312 /*** Instruction decoding ***/
313 #define EXTRACT_HELPER(name, shift, nb) \
314 static always_inline uint32_t name (uint32_t opcode) \
316 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
319 #define EXTRACT_SHELPER(name, shift, nb) \
320 static always_inline int32_t name (uint32_t opcode) \
322 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
326 EXTRACT_HELPER(opc1, 26, 6);
328 EXTRACT_HELPER(opc2, 1, 5);
330 EXTRACT_HELPER(opc3, 6, 5);
331 /* Update Cr0 flags */
332 EXTRACT_HELPER(Rc, 0, 1);
334 EXTRACT_HELPER(rD, 21, 5);
336 EXTRACT_HELPER(rS, 21, 5);
338 EXTRACT_HELPER(rA, 16, 5);
340 EXTRACT_HELPER(rB, 11, 5);
342 EXTRACT_HELPER(rC, 6, 5);
344 EXTRACT_HELPER(crfD, 23, 3);
345 EXTRACT_HELPER(crfS, 18, 3);
346 EXTRACT_HELPER(crbD, 21, 5);
347 EXTRACT_HELPER(crbA, 16, 5);
348 EXTRACT_HELPER(crbB, 11, 5);
350 EXTRACT_HELPER(_SPR, 11, 10);
351 static always_inline uint32_t SPR (uint32_t opcode)
353 uint32_t sprn = _SPR(opcode);
355 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
357 /*** Get constants ***/
358 EXTRACT_HELPER(IMM, 12, 8);
359 /* 16 bits signed immediate value */
360 EXTRACT_SHELPER(SIMM, 0, 16);
361 /* 16 bits unsigned immediate value */
362 EXTRACT_HELPER(UIMM, 0, 16);
364 EXTRACT_HELPER(NB, 11, 5);
366 EXTRACT_HELPER(SH, 11, 5);
368 EXTRACT_HELPER(MB, 6, 5);
370 EXTRACT_HELPER(ME, 1, 5);
372 EXTRACT_HELPER(TO, 21, 5);
374 EXTRACT_HELPER(CRM, 12, 8);
375 EXTRACT_HELPER(FM, 17, 8);
376 EXTRACT_HELPER(SR, 16, 4);
377 EXTRACT_HELPER(FPIMM, 20, 4);
379 /*** Jump target decoding ***/
381 EXTRACT_SHELPER(d, 0, 16);
382 /* Immediate address */
383 static always_inline target_ulong LI (uint32_t opcode)
385 return (opcode >> 0) & 0x03FFFFFC;
388 static always_inline uint32_t BD (uint32_t opcode)
390 return (opcode >> 0) & 0xFFFC;
393 EXTRACT_HELPER(BO, 21, 5);
394 EXTRACT_HELPER(BI, 16, 5);
395 /* Absolute/relative address */
396 EXTRACT_HELPER(AA, 1, 1);
398 EXTRACT_HELPER(LK, 0, 1);
400 /* Create a mask between <start> and <end> bits */
401 static always_inline target_ulong MASK (uint32_t start, uint32_t end)
405 #if defined(TARGET_PPC64)
406 if (likely(start == 0)) {
407 ret = (uint64_t)(-1ULL) << (63 - end);
408 } else if (likely(end == 63)) {
409 ret = (uint64_t)(-1ULL) >> start;
412 if (likely(start == 0)) {
413 ret = (uint32_t)(-1ULL) << (31 - end);
414 } else if (likely(end == 31)) {
415 ret = (uint32_t)(-1ULL) >> start;
419 ret = (((target_ulong)(-1ULL)) >> (start)) ^
420 (((target_ulong)(-1ULL) >> (end)) >> 1);
421 if (unlikely(start > end))
428 /*****************************************************************************/
429 /* PowerPC Instructions types definitions */
431 PPC_NONE = 0x0000000000000000ULL,
432 /* PowerPC base instructions set */
433 PPC_INSNS_BASE = 0x0000000000000001ULL,
434 /* integer operations instructions */
435 #define PPC_INTEGER PPC_INSNS_BASE
436 /* flow control instructions */
437 #define PPC_FLOW PPC_INSNS_BASE
438 /* virtual memory instructions */
439 #define PPC_MEM PPC_INSNS_BASE
440 /* ld/st with reservation instructions */
441 #define PPC_RES PPC_INSNS_BASE
442 /* cache control instructions */
443 #define PPC_CACHE PPC_INSNS_BASE
444 /* spr/msr access instructions */
445 #define PPC_MISC PPC_INSNS_BASE
446 /* Optional floating point instructions */
447 PPC_FLOAT = 0x0000000000000002ULL,
448 PPC_FLOAT_FSQRT = 0x0000000000000004ULL,
449 PPC_FLOAT_FRES = 0x0000000000000008ULL,
450 PPC_FLOAT_FRSQRTE = 0x0000000000000010ULL,
451 PPC_FLOAT_FSEL = 0x0000000000000020ULL,
452 PPC_FLOAT_STFIWX = 0x0000000000000040ULL,
453 /* external control instructions */
454 PPC_EXTERN = 0x0000000000000080ULL,
455 /* segment register access instructions */
456 PPC_SEGMENT = 0x0000000000000100ULL,
457 /* Optional cache control instruction */
458 PPC_CACHE_DCBA = 0x0000000000000200ULL,
459 /* Optional memory control instructions */
460 PPC_MEM_TLBIA = 0x0000000000000400ULL,
461 PPC_MEM_TLBIE = 0x0000000000000800ULL,
462 PPC_MEM_TLBSYNC = 0x0000000000001000ULL,
464 PPC_MEM_SYNC = 0x0000000000002000ULL,
465 /* PowerPC 6xx TLB management instructions */
466 PPC_6xx_TLB = 0x0000000000004000ULL,
467 /* Altivec support */
468 PPC_ALTIVEC = 0x0000000000008000ULL,
469 /* Time base mftb instruction */
470 PPC_MFTB = 0x0000000000010000ULL,
471 /* Embedded PowerPC dedicated instructions */
472 PPC_EMB_COMMON = 0x0000000000020000ULL,
473 /* PowerPC 40x exception model */
474 PPC_40x_EXCP = 0x0000000000040000ULL,
475 /* PowerPC 40x TLB management instructions */
476 PPC_40x_TLB = 0x0000000000080000ULL,
477 /* PowerPC 405 Mac instructions */
478 PPC_405_MAC = 0x0000000000100000ULL,
479 /* PowerPC 440 specific instructions */
480 PPC_440_SPEC = 0x0000000000200000ULL,
481 /* Power-to-PowerPC bridge (601) */
482 PPC_POWER_BR = 0x0000000000400000ULL,
483 /* PowerPC 602 specific */
484 PPC_602_SPEC = 0x0000000000800000ULL,
485 /* Deprecated instructions */
486 /* Original POWER instruction set */
487 PPC_POWER = 0x0000000001000000ULL,
488 /* POWER2 instruction set extension */
489 PPC_POWER2 = 0x0000000002000000ULL,
490 /* Power RTC support */
491 PPC_POWER_RTC = 0x0000000004000000ULL,
492 /* 64 bits PowerPC instruction set */
493 PPC_64B = 0x0000000008000000ULL,
494 /* 64 bits hypervisor extensions */
495 PPC_64H = 0x0000000010000000ULL,
496 /* segment register access instructions for PowerPC 64 "bridge" */
497 PPC_SEGMENT_64B = 0x0000000020000000ULL,
498 /* BookE (embedded) PowerPC specification */
499 PPC_BOOKE = 0x0000000040000000ULL,
501 PPC_MEM_EIEIO = 0x0000000080000000ULL,
502 /* e500 vector instructions */
503 PPC_E500_VECTOR = 0x0000000100000000ULL,
504 /* PowerPC 4xx dedicated instructions */
505 PPC_4xx_COMMON = 0x0000000200000000ULL,
506 /* PowerPC 2.03 specification extensions */
507 PPC_203 = 0x0000000400000000ULL,
508 /* PowerPC 2.03 SPE extension */
509 PPC_SPE = 0x0000000800000000ULL,
510 /* PowerPC 2.03 SPE floating-point extension */
511 PPC_SPEFPU = 0x0000001000000000ULL,
513 PPC_SLBI = 0x0000002000000000ULL,
514 /* PowerPC 40x ibct instructions */
515 PPC_40x_ICBT = 0x0000004000000000ULL,
516 /* PowerPC 74xx TLB management instructions */
517 PPC_74xx_TLB = 0x0000008000000000ULL,
518 /* More BookE (embedded) instructions... */
519 PPC_BOOKE_EXT = 0x0000010000000000ULL,
520 /* rfmci is not implemented in all BookE PowerPC */
521 PPC_RFMCI = 0x0000020000000000ULL,
522 /* user-mode DCR access, implemented in PowerPC 460 */
523 PPC_DCRUX = 0x0000040000000000ULL,
524 /* New floating-point extensions (PowerPC 2.0x) */
525 PPC_FLOAT_EXT = 0x0000080000000000ULL,
526 /* New wait instruction (PowerPC 2.0x) */
527 PPC_WAIT = 0x0000100000000000ULL,
528 /* New 64 bits extensions (PowerPC 2.0x) */
529 PPC_64BX = 0x0000200000000000ULL,
530 /* dcbz instruction with fixed cache line size */
531 PPC_CACHE_DCBZ = 0x0000400000000000ULL,
532 /* dcbz instruction with tunable cache line size */
533 PPC_CACHE_DCBZT = 0x0000800000000000ULL,
534 /* frsqrtes extension */
535 PPC_FLOAT_FRSQRTES = 0x0001000000000000ULL,
538 /*****************************************************************************/
539 /* PowerPC instructions table */
540 #if HOST_LONG_BITS == 64
545 #if defined(__APPLE__)
546 #define OPCODES_SECTION \
547 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
549 #define OPCODES_SECTION \
550 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
553 #if defined(DO_PPC_STATISTICS)
554 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
555 OPCODES_SECTION opcode_t opc_##name = { \
563 .handler = &gen_##name, \
564 .oname = stringify(name), \
566 .oname = stringify(name), \
568 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
569 OPCODES_SECTION opcode_t opc_##name = { \
577 .handler = &gen_##name, \
583 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
584 OPCODES_SECTION opcode_t opc_##name = { \
592 .handler = &gen_##name, \
594 .oname = stringify(name), \
596 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
597 OPCODES_SECTION opcode_t opc_##name = { \
605 .handler = &gen_##name, \
611 #define GEN_OPCODE_MARK(name) \
612 OPCODES_SECTION opcode_t opc_##name = { \
618 .inval = 0x00000000, \
622 .oname = stringify(name), \
625 /* Start opcode list */
626 GEN_OPCODE_MARK(start);
628 /* Invalid instruction */
629 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
634 static opc_handler_t invalid_handler = {
637 .handler = gen_invalid,
640 /*** Integer arithmetic ***/
641 #define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval, type) \
642 GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
644 gen_op_load_gpr_T0(rA(ctx->opcode)); \
645 gen_op_load_gpr_T1(rB(ctx->opcode)); \
647 gen_op_store_T0_gpr(rD(ctx->opcode)); \
648 if (unlikely(Rc(ctx->opcode) != 0)) \
652 #define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval, type) \
653 GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
655 gen_op_load_gpr_T0(rA(ctx->opcode)); \
656 gen_op_load_gpr_T1(rB(ctx->opcode)); \
658 gen_op_store_T0_gpr(rD(ctx->opcode)); \
659 if (unlikely(Rc(ctx->opcode) != 0)) \
663 #define __GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
664 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
666 gen_op_load_gpr_T0(rA(ctx->opcode)); \
668 gen_op_store_T0_gpr(rD(ctx->opcode)); \
669 if (unlikely(Rc(ctx->opcode) != 0)) \
672 #define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3, type) \
673 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
675 gen_op_load_gpr_T0(rA(ctx->opcode)); \
677 gen_op_store_T0_gpr(rD(ctx->opcode)); \
678 if (unlikely(Rc(ctx->opcode) != 0)) \
682 /* Two operands arithmetic functions */
683 #define GEN_INT_ARITH2(name, opc1, opc2, opc3, type) \
684 __GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000, type) \
685 __GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
687 /* Two operands arithmetic functions with no overflow allowed */
688 #define GEN_INT_ARITHN(name, opc1, opc2, opc3, type) \
689 __GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400, type)
691 /* One operand arithmetic functions */
692 #define GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
693 __GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
694 __GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10, type)
696 #if defined(TARGET_PPC64)
697 #define __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, inval, type) \
698 GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
700 gen_op_load_gpr_T0(rA(ctx->opcode)); \
701 gen_op_load_gpr_T1(rB(ctx->opcode)); \
703 gen_op_##name##_64(); \
706 gen_op_store_T0_gpr(rD(ctx->opcode)); \
707 if (unlikely(Rc(ctx->opcode) != 0)) \
711 #define __GEN_INT_ARITH2_O_64(name, opc1, opc2, opc3, inval, type) \
712 GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
714 gen_op_load_gpr_T0(rA(ctx->opcode)); \
715 gen_op_load_gpr_T1(rB(ctx->opcode)); \
717 gen_op_##name##_64(); \
720 gen_op_store_T0_gpr(rD(ctx->opcode)); \
721 if (unlikely(Rc(ctx->opcode) != 0)) \
725 #define __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
726 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
728 gen_op_load_gpr_T0(rA(ctx->opcode)); \
730 gen_op_##name##_64(); \
733 gen_op_store_T0_gpr(rD(ctx->opcode)); \
734 if (unlikely(Rc(ctx->opcode) != 0)) \
737 #define __GEN_INT_ARITH1_O_64(name, opc1, opc2, opc3, type) \
738 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
740 gen_op_load_gpr_T0(rA(ctx->opcode)); \
742 gen_op_##name##_64(); \
745 gen_op_store_T0_gpr(rD(ctx->opcode)); \
746 if (unlikely(Rc(ctx->opcode) != 0)) \
750 /* Two operands arithmetic functions */
751 #define GEN_INT_ARITH2_64(name, opc1, opc2, opc3, type) \
752 __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000000, type) \
753 __GEN_INT_ARITH2_O_64(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
755 /* Two operands arithmetic functions with no overflow allowed */
756 #define GEN_INT_ARITHN_64(name, opc1, opc2, opc3, type) \
757 __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000400, type)
759 /* One operand arithmetic functions */
760 #define GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
761 __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
762 __GEN_INT_ARITH1_O_64(name##o, opc1, opc2, opc3 | 0x10, type)
764 #define GEN_INT_ARITH2_64 GEN_INT_ARITH2
765 #define GEN_INT_ARITHN_64 GEN_INT_ARITHN
766 #define GEN_INT_ARITH1_64 GEN_INT_ARITH1
769 /* add add. addo addo. */
770 static always_inline void gen_op_addo (void)
776 #if defined(TARGET_PPC64)
777 #define gen_op_add_64 gen_op_add
778 static always_inline void gen_op_addo_64 (void)
782 gen_op_check_addo_64();
785 GEN_INT_ARITH2_64 (add, 0x1F, 0x0A, 0x08, PPC_INTEGER);
786 /* addc addc. addco addco. */
787 static always_inline void gen_op_addc (void)
793 static always_inline void gen_op_addco (void)
800 #if defined(TARGET_PPC64)
801 static always_inline void gen_op_addc_64 (void)
805 gen_op_check_addc_64();
807 static always_inline void gen_op_addco_64 (void)
811 gen_op_check_addc_64();
812 gen_op_check_addo_64();
815 GEN_INT_ARITH2_64 (addc, 0x1F, 0x0A, 0x00, PPC_INTEGER);
816 /* adde adde. addeo addeo. */
817 static always_inline void gen_op_addeo (void)
823 #if defined(TARGET_PPC64)
824 static always_inline void gen_op_addeo_64 (void)
828 gen_op_check_addo_64();
831 GEN_INT_ARITH2_64 (adde, 0x1F, 0x0A, 0x04, PPC_INTEGER);
832 /* addme addme. addmeo addmeo. */
833 static always_inline void gen_op_addme (void)
838 #if defined(TARGET_PPC64)
839 static always_inline void gen_op_addme_64 (void)
845 GEN_INT_ARITH1_64 (addme, 0x1F, 0x0A, 0x07, PPC_INTEGER);
846 /* addze addze. addzeo addzeo. */
847 static always_inline void gen_op_addze (void)
853 static always_inline void gen_op_addzeo (void)
860 #if defined(TARGET_PPC64)
861 static always_inline void gen_op_addze_64 (void)
865 gen_op_check_addc_64();
867 static always_inline void gen_op_addzeo_64 (void)
871 gen_op_check_addc_64();
872 gen_op_check_addo_64();
875 GEN_INT_ARITH1_64 (addze, 0x1F, 0x0A, 0x06, PPC_INTEGER);
876 /* divw divw. divwo divwo. */
877 GEN_INT_ARITH2 (divw, 0x1F, 0x0B, 0x0F, PPC_INTEGER);
878 /* divwu divwu. divwuo divwuo. */
879 GEN_INT_ARITH2 (divwu, 0x1F, 0x0B, 0x0E, PPC_INTEGER);
881 GEN_INT_ARITHN (mulhw, 0x1F, 0x0B, 0x02, PPC_INTEGER);
883 GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00, PPC_INTEGER);
884 /* mullw mullw. mullwo mullwo. */
885 GEN_INT_ARITH2 (mullw, 0x1F, 0x0B, 0x07, PPC_INTEGER);
886 /* neg neg. nego nego. */
887 GEN_INT_ARITH1_64 (neg, 0x1F, 0x08, 0x03, PPC_INTEGER);
888 /* subf subf. subfo subfo. */
889 static always_inline void gen_op_subfo (void)
893 gen_op_check_subfo();
895 #if defined(TARGET_PPC64)
896 #define gen_op_subf_64 gen_op_subf
897 static always_inline void gen_op_subfo_64 (void)
901 gen_op_check_subfo_64();
904 GEN_INT_ARITH2_64 (subf, 0x1F, 0x08, 0x01, PPC_INTEGER);
905 /* subfc subfc. subfco subfco. */
906 static always_inline void gen_op_subfc (void)
909 gen_op_check_subfc();
911 static always_inline void gen_op_subfco (void)
915 gen_op_check_subfc();
916 gen_op_check_subfo();
918 #if defined(TARGET_PPC64)
919 static always_inline void gen_op_subfc_64 (void)
922 gen_op_check_subfc_64();
924 static always_inline void gen_op_subfco_64 (void)
928 gen_op_check_subfc_64();
929 gen_op_check_subfo_64();
932 GEN_INT_ARITH2_64 (subfc, 0x1F, 0x08, 0x00, PPC_INTEGER);
933 /* subfe subfe. subfeo subfeo. */
934 static always_inline void gen_op_subfeo (void)
938 gen_op_check_subfo();
940 #if defined(TARGET_PPC64)
941 #define gen_op_subfe_64 gen_op_subfe
942 static always_inline void gen_op_subfeo_64 (void)
946 gen_op_check_subfo_64();
949 GEN_INT_ARITH2_64 (subfe, 0x1F, 0x08, 0x04, PPC_INTEGER);
950 /* subfme subfme. subfmeo subfmeo. */
951 GEN_INT_ARITH1_64 (subfme, 0x1F, 0x08, 0x07, PPC_INTEGER);
952 /* subfze subfze. subfzeo subfzeo. */
953 GEN_INT_ARITH1_64 (subfze, 0x1F, 0x08, 0x06, PPC_INTEGER);
955 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
957 target_long simm = SIMM(ctx->opcode);
959 if (rA(ctx->opcode) == 0) {
963 gen_op_load_gpr_T0(rA(ctx->opcode));
964 if (likely(simm != 0))
967 gen_op_store_T0_gpr(rD(ctx->opcode));
970 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
972 target_long simm = SIMM(ctx->opcode);
974 gen_op_load_gpr_T0(rA(ctx->opcode));
975 if (likely(simm != 0)) {
978 #if defined(TARGET_PPC64)
980 gen_op_check_addc_64();
985 gen_op_clear_xer_ca();
987 gen_op_store_T0_gpr(rD(ctx->opcode));
990 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
992 target_long simm = SIMM(ctx->opcode);
994 gen_op_load_gpr_T0(rA(ctx->opcode));
995 if (likely(simm != 0)) {
998 #if defined(TARGET_PPC64)
1000 gen_op_check_addc_64();
1003 gen_op_check_addc();
1005 gen_op_clear_xer_ca();
1007 gen_op_store_T0_gpr(rD(ctx->opcode));
1011 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1013 target_long simm = SIMM(ctx->opcode);
1015 if (rA(ctx->opcode) == 0) {
1017 gen_set_T0(simm << 16);
1019 gen_op_load_gpr_T0(rA(ctx->opcode));
1020 if (likely(simm != 0))
1021 gen_op_addi(simm << 16);
1023 gen_op_store_T0_gpr(rD(ctx->opcode));
1026 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1028 gen_op_load_gpr_T0(rA(ctx->opcode));
1029 gen_op_mulli(SIMM(ctx->opcode));
1030 gen_op_store_T0_gpr(rD(ctx->opcode));
1033 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1035 gen_op_load_gpr_T0(rA(ctx->opcode));
1036 #if defined(TARGET_PPC64)
1038 gen_op_subfic_64(SIMM(ctx->opcode));
1041 gen_op_subfic(SIMM(ctx->opcode));
1042 gen_op_store_T0_gpr(rD(ctx->opcode));
1045 #if defined(TARGET_PPC64)
1047 GEN_INT_ARITHN (mulhd, 0x1F, 0x09, 0x02, PPC_64B);
1048 /* mulhdu mulhdu. */
1049 GEN_INT_ARITHN (mulhdu, 0x1F, 0x09, 0x00, PPC_64B);
1050 /* mulld mulld. mulldo mulldo. */
1051 GEN_INT_ARITH2 (mulld, 0x1F, 0x09, 0x07, PPC_64B);
1052 /* divd divd. divdo divdo. */
1053 GEN_INT_ARITH2 (divd, 0x1F, 0x09, 0x0F, PPC_64B);
1054 /* divdu divdu. divduo divduo. */
1055 GEN_INT_ARITH2 (divdu, 0x1F, 0x09, 0x0E, PPC_64B);
1058 /*** Integer comparison ***/
1059 #if defined(TARGET_PPC64)
1060 #define GEN_CMP(name, opc, type) \
1061 GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \
1063 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1064 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1065 if (ctx->sf_mode && (ctx->opcode & 0x00200000)) \
1066 gen_op_##name##_64(); \
1069 gen_op_store_T0_crf(crfD(ctx->opcode)); \
1072 #define GEN_CMP(name, opc, type) \
1073 GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \
1075 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1076 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1078 gen_op_store_T0_crf(crfD(ctx->opcode)); \
1083 GEN_CMP(cmp, 0x00, PPC_INTEGER);
1085 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
1087 gen_op_load_gpr_T0(rA(ctx->opcode));
1088 #if defined(TARGET_PPC64)
1089 if (ctx->sf_mode && (ctx->opcode & 0x00200000))
1090 gen_op_cmpi_64(SIMM(ctx->opcode));
1093 gen_op_cmpi(SIMM(ctx->opcode));
1094 gen_op_store_T0_crf(crfD(ctx->opcode));
1097 GEN_CMP(cmpl, 0x01, PPC_INTEGER);
1099 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
1101 gen_op_load_gpr_T0(rA(ctx->opcode));
1102 #if defined(TARGET_PPC64)
1103 if (ctx->sf_mode && (ctx->opcode & 0x00200000))
1104 gen_op_cmpli_64(UIMM(ctx->opcode));
1107 gen_op_cmpli(UIMM(ctx->opcode));
1108 gen_op_store_T0_crf(crfD(ctx->opcode));
1111 /* isel (PowerPC 2.03 specification) */
1112 GEN_HANDLER(isel, 0x1F, 0x0F, 0x00, 0x00000001, PPC_203)
1114 uint32_t bi = rC(ctx->opcode);
1117 if (rA(ctx->opcode) == 0) {
1120 gen_op_load_gpr_T1(rA(ctx->opcode));
1122 gen_op_load_gpr_T2(rB(ctx->opcode));
1123 mask = 1 << (3 - (bi & 0x03));
1124 gen_op_load_crf_T0(bi >> 2);
1125 gen_op_test_true(mask);
1127 gen_op_store_T0_gpr(rD(ctx->opcode));
1130 /*** Integer logical ***/
1131 #define __GEN_LOGICAL2(name, opc2, opc3, type) \
1132 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, type) \
1134 gen_op_load_gpr_T0(rS(ctx->opcode)); \
1135 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1137 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1138 if (unlikely(Rc(ctx->opcode) != 0)) \
1141 #define GEN_LOGICAL2(name, opc, type) \
1142 __GEN_LOGICAL2(name, 0x1C, opc, type)
1144 #define GEN_LOGICAL1(name, opc, type) \
1145 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
1147 gen_op_load_gpr_T0(rS(ctx->opcode)); \
1149 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1150 if (unlikely(Rc(ctx->opcode) != 0)) \
1155 GEN_LOGICAL2(and, 0x00, PPC_INTEGER);
1157 GEN_LOGICAL2(andc, 0x01, PPC_INTEGER);
1159 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1161 gen_op_load_gpr_T0(rS(ctx->opcode));
1162 gen_op_andi_T0(UIMM(ctx->opcode));
1163 gen_op_store_T0_gpr(rA(ctx->opcode));
1167 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1169 gen_op_load_gpr_T0(rS(ctx->opcode));
1170 gen_op_andi_T0(UIMM(ctx->opcode) << 16);
1171 gen_op_store_T0_gpr(rA(ctx->opcode));
1176 GEN_LOGICAL1(cntlzw, 0x00, PPC_INTEGER);
1178 GEN_LOGICAL2(eqv, 0x08, PPC_INTEGER);
1179 /* extsb & extsb. */
1180 GEN_LOGICAL1(extsb, 0x1D, PPC_INTEGER);
1181 /* extsh & extsh. */
1182 GEN_LOGICAL1(extsh, 0x1C, PPC_INTEGER);
1184 GEN_LOGICAL2(nand, 0x0E, PPC_INTEGER);
1186 GEN_LOGICAL2(nor, 0x03, PPC_INTEGER);
1189 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1193 rs = rS(ctx->opcode);
1194 ra = rA(ctx->opcode);
1195 rb = rB(ctx->opcode);
1196 /* Optimisation for mr. ri case */
1197 if (rs != ra || rs != rb) {
1198 gen_op_load_gpr_T0(rs);
1200 gen_op_load_gpr_T1(rb);
1203 gen_op_store_T0_gpr(ra);
1204 if (unlikely(Rc(ctx->opcode) != 0))
1206 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1207 gen_op_load_gpr_T0(rs);
1209 #if defined(TARGET_PPC64)
1213 /* Set process priority to low */
1214 gen_op_store_pri(2);
1217 /* Set process priority to medium-low */
1218 gen_op_store_pri(3);
1221 /* Set process priority to normal */
1222 gen_op_store_pri(4);
1224 #if !defined(CONFIG_USER_ONLY)
1226 if (ctx->supervisor > 0) {
1227 /* Set process priority to very low */
1228 gen_op_store_pri(1);
1232 if (ctx->supervisor > 0) {
1233 /* Set process priority to medium-hight */
1234 gen_op_store_pri(5);
1238 if (ctx->supervisor > 0) {
1239 /* Set process priority to high */
1240 gen_op_store_pri(6);
1243 #if defined(TARGET_PPC64H)
1245 if (ctx->supervisor > 1) {
1246 /* Set process priority to very high */
1247 gen_op_store_pri(7);
1261 GEN_LOGICAL2(orc, 0x0C, PPC_INTEGER);
1263 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1265 gen_op_load_gpr_T0(rS(ctx->opcode));
1266 /* Optimisation for "set to zero" case */
1267 if (rS(ctx->opcode) != rB(ctx->opcode)) {
1268 gen_op_load_gpr_T1(rB(ctx->opcode));
1273 gen_op_store_T0_gpr(rA(ctx->opcode));
1274 if (unlikely(Rc(ctx->opcode) != 0))
1278 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1280 target_ulong uimm = UIMM(ctx->opcode);
1282 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1284 /* XXX: should handle special NOPs for POWER series */
1287 gen_op_load_gpr_T0(rS(ctx->opcode));
1288 if (likely(uimm != 0))
1290 gen_op_store_T0_gpr(rA(ctx->opcode));
1293 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1295 target_ulong uimm = UIMM(ctx->opcode);
1297 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1301 gen_op_load_gpr_T0(rS(ctx->opcode));
1302 if (likely(uimm != 0))
1303 gen_op_ori(uimm << 16);
1304 gen_op_store_T0_gpr(rA(ctx->opcode));
1307 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1309 target_ulong uimm = UIMM(ctx->opcode);
1311 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1315 gen_op_load_gpr_T0(rS(ctx->opcode));
1316 if (likely(uimm != 0))
1318 gen_op_store_T0_gpr(rA(ctx->opcode));
1322 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1324 target_ulong uimm = UIMM(ctx->opcode);
1326 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1330 gen_op_load_gpr_T0(rS(ctx->opcode));
1331 if (likely(uimm != 0))
1332 gen_op_xori(uimm << 16);
1333 gen_op_store_T0_gpr(rA(ctx->opcode));
1336 /* popcntb : PowerPC 2.03 specification */
1337 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_203)
1339 gen_op_load_gpr_T0(rS(ctx->opcode));
1340 #if defined(TARGET_PPC64)
1342 gen_op_popcntb_64();
1346 gen_op_store_T0_gpr(rA(ctx->opcode));
1349 #if defined(TARGET_PPC64)
1350 /* extsw & extsw. */
1351 GEN_LOGICAL1(extsw, 0x1E, PPC_64B);
1353 GEN_LOGICAL1(cntlzd, 0x01, PPC_64B);
1356 /*** Integer rotate ***/
1357 /* rlwimi & rlwimi. */
1358 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1361 uint32_t mb, me, sh;
1363 mb = MB(ctx->opcode);
1364 me = ME(ctx->opcode);
1365 sh = SH(ctx->opcode);
1366 if (likely(sh == 0)) {
1367 if (likely(mb == 0 && me == 31)) {
1368 gen_op_load_gpr_T0(rS(ctx->opcode));
1370 } else if (likely(mb == 31 && me == 0)) {
1371 gen_op_load_gpr_T0(rA(ctx->opcode));
1374 gen_op_load_gpr_T0(rS(ctx->opcode));
1375 gen_op_load_gpr_T1(rA(ctx->opcode));
1378 gen_op_load_gpr_T0(rS(ctx->opcode));
1379 gen_op_load_gpr_T1(rA(ctx->opcode));
1380 gen_op_rotli32_T0(SH(ctx->opcode));
1382 #if defined(TARGET_PPC64)
1386 mask = MASK(mb, me);
1387 gen_op_andi_T0(mask);
1388 gen_op_andi_T1(~mask);
1391 gen_op_store_T0_gpr(rA(ctx->opcode));
1392 if (unlikely(Rc(ctx->opcode) != 0))
1395 /* rlwinm & rlwinm. */
1396 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1398 uint32_t mb, me, sh;
1400 sh = SH(ctx->opcode);
1401 mb = MB(ctx->opcode);
1402 me = ME(ctx->opcode);
1403 gen_op_load_gpr_T0(rS(ctx->opcode));
1404 if (likely(sh == 0)) {
1407 if (likely(mb == 0)) {
1408 if (likely(me == 31)) {
1409 gen_op_rotli32_T0(sh);
1411 } else if (likely(me == (31 - sh))) {
1415 } else if (likely(me == 31)) {
1416 if (likely(sh == (32 - mb))) {
1421 gen_op_rotli32_T0(sh);
1423 #if defined(TARGET_PPC64)
1427 gen_op_andi_T0(MASK(mb, me));
1429 gen_op_store_T0_gpr(rA(ctx->opcode));
1430 if (unlikely(Rc(ctx->opcode) != 0))
1433 /* rlwnm & rlwnm. */
1434 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1438 mb = MB(ctx->opcode);
1439 me = ME(ctx->opcode);
1440 gen_op_load_gpr_T0(rS(ctx->opcode));
1441 gen_op_load_gpr_T1(rB(ctx->opcode));
1442 gen_op_rotl32_T0_T1();
1443 if (unlikely(mb != 0 || me != 31)) {
1444 #if defined(TARGET_PPC64)
1448 gen_op_andi_T0(MASK(mb, me));
1450 gen_op_store_T0_gpr(rA(ctx->opcode));
1451 if (unlikely(Rc(ctx->opcode) != 0))
1455 #if defined(TARGET_PPC64)
1456 #define GEN_PPC64_R2(name, opc1, opc2) \
1457 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1459 gen_##name(ctx, 0); \
1461 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1464 gen_##name(ctx, 1); \
1466 #define GEN_PPC64_R4(name, opc1, opc2) \
1467 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1469 gen_##name(ctx, 0, 0); \
1471 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1474 gen_##name(ctx, 0, 1); \
1476 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1479 gen_##name(ctx, 1, 0); \
1481 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1484 gen_##name(ctx, 1, 1); \
1487 static always_inline void gen_andi_T0_64 (DisasContext *ctx, uint64_t mask)
1490 gen_op_andi_T0_64(mask >> 32, mask & 0xFFFFFFFF);
1492 gen_op_andi_T0(mask);
1495 static always_inline void gen_andi_T1_64 (DisasContext *ctx, uint64_t mask)
1498 gen_op_andi_T1_64(mask >> 32, mask & 0xFFFFFFFF);
1500 gen_op_andi_T1(mask);
1503 static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1504 uint32_t me, uint32_t sh)
1506 gen_op_load_gpr_T0(rS(ctx->opcode));
1507 if (likely(sh == 0)) {
1510 if (likely(mb == 0)) {
1511 if (likely(me == 63)) {
1512 gen_op_rotli64_T0(sh);
1514 } else if (likely(me == (63 - sh))) {
1518 } else if (likely(me == 63)) {
1519 if (likely(sh == (64 - mb))) {
1520 gen_op_srli_T0_64(mb);
1524 gen_op_rotli64_T0(sh);
1526 gen_andi_T0_64(ctx, MASK(mb, me));
1528 gen_op_store_T0_gpr(rA(ctx->opcode));
1529 if (unlikely(Rc(ctx->opcode) != 0))
1532 /* rldicl - rldicl. */
1533 static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
1537 sh = SH(ctx->opcode) | (shn << 5);
1538 mb = MB(ctx->opcode) | (mbn << 5);
1539 gen_rldinm(ctx, mb, 63, sh);
1541 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1542 /* rldicr - rldicr. */
1543 static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
1547 sh = SH(ctx->opcode) | (shn << 5);
1548 me = MB(ctx->opcode) | (men << 5);
1549 gen_rldinm(ctx, 0, me, sh);
1551 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1552 /* rldic - rldic. */
1553 static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
1557 sh = SH(ctx->opcode) | (shn << 5);
1558 mb = MB(ctx->opcode) | (mbn << 5);
1559 gen_rldinm(ctx, mb, 63 - sh, sh);
1561 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1563 static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1566 gen_op_load_gpr_T0(rS(ctx->opcode));
1567 gen_op_load_gpr_T1(rB(ctx->opcode));
1568 gen_op_rotl64_T0_T1();
1569 if (unlikely(mb != 0 || me != 63)) {
1570 gen_andi_T0_64(ctx, MASK(mb, me));
1572 gen_op_store_T0_gpr(rA(ctx->opcode));
1573 if (unlikely(Rc(ctx->opcode) != 0))
1577 /* rldcl - rldcl. */
1578 static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
1582 mb = MB(ctx->opcode) | (mbn << 5);
1583 gen_rldnm(ctx, mb, 63);
1585 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1586 /* rldcr - rldcr. */
1587 static always_inline void gen_rldcr (DisasContext *ctx, int men)
1591 me = MB(ctx->opcode) | (men << 5);
1592 gen_rldnm(ctx, 0, me);
1594 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1595 /* rldimi - rldimi. */
1596 static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
1601 sh = SH(ctx->opcode) | (shn << 5);
1602 mb = MB(ctx->opcode) | (mbn << 5);
1603 if (likely(sh == 0)) {
1604 if (likely(mb == 0)) {
1605 gen_op_load_gpr_T0(rS(ctx->opcode));
1607 } else if (likely(mb == 63)) {
1608 gen_op_load_gpr_T0(rA(ctx->opcode));
1611 gen_op_load_gpr_T0(rS(ctx->opcode));
1612 gen_op_load_gpr_T1(rA(ctx->opcode));
1615 gen_op_load_gpr_T0(rS(ctx->opcode));
1616 gen_op_load_gpr_T1(rA(ctx->opcode));
1617 gen_op_rotli64_T0(sh);
1619 mask = MASK(mb, 63 - sh);
1620 gen_andi_T0_64(ctx, mask);
1621 gen_andi_T1_64(ctx, ~mask);
1624 gen_op_store_T0_gpr(rA(ctx->opcode));
1625 if (unlikely(Rc(ctx->opcode) != 0))
1628 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1631 /*** Integer shift ***/
1633 __GEN_LOGICAL2(slw, 0x18, 0x00, PPC_INTEGER);
1635 __GEN_LOGICAL2(sraw, 0x18, 0x18, PPC_INTEGER);
1636 /* srawi & srawi. */
1637 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1640 gen_op_load_gpr_T0(rS(ctx->opcode));
1641 if (SH(ctx->opcode) != 0) {
1642 gen_op_move_T1_T0();
1643 mb = 32 - SH(ctx->opcode);
1645 #if defined(TARGET_PPC64)
1649 gen_op_srawi(SH(ctx->opcode), MASK(mb, me));
1651 gen_op_store_T0_gpr(rA(ctx->opcode));
1652 if (unlikely(Rc(ctx->opcode) != 0))
1656 __GEN_LOGICAL2(srw, 0x18, 0x10, PPC_INTEGER);
1658 #if defined(TARGET_PPC64)
1660 __GEN_LOGICAL2(sld, 0x1B, 0x00, PPC_64B);
1662 __GEN_LOGICAL2(srad, 0x1A, 0x18, PPC_64B);
1663 /* sradi & sradi. */
1664 static always_inline void gen_sradi (DisasContext *ctx, int n)
1669 gen_op_load_gpr_T0(rS(ctx->opcode));
1670 sh = SH(ctx->opcode) + (n << 5);
1672 gen_op_move_T1_T0();
1673 mb = 64 - SH(ctx->opcode);
1675 mask = MASK(mb, me);
1676 gen_op_sradi(sh, mask >> 32, mask);
1678 gen_op_store_T0_gpr(rA(ctx->opcode));
1679 if (unlikely(Rc(ctx->opcode) != 0))
1682 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
1686 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
1691 __GEN_LOGICAL2(srd, 0x1B, 0x10, PPC_64B);
1694 /*** Floating-Point arithmetic ***/
1695 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
1696 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
1698 if (unlikely(!ctx->fpu_enabled)) { \
1699 GEN_EXCP_NO_FP(ctx); \
1702 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1703 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
1704 gen_op_load_fpr_FT2(rB(ctx->opcode)); \
1705 gen_reset_fpstatus(); \
1710 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1711 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
1714 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
1715 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
1716 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
1718 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1719 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
1721 if (unlikely(!ctx->fpu_enabled)) { \
1722 GEN_EXCP_NO_FP(ctx); \
1725 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1726 gen_op_load_fpr_FT1(rB(ctx->opcode)); \
1727 gen_reset_fpstatus(); \
1732 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1733 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
1735 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
1736 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1737 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
1739 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1740 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
1742 if (unlikely(!ctx->fpu_enabled)) { \
1743 GEN_EXCP_NO_FP(ctx); \
1746 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1747 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
1748 gen_reset_fpstatus(); \
1753 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1754 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
1756 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
1757 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1758 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
1760 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
1761 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
1763 if (unlikely(!ctx->fpu_enabled)) { \
1764 GEN_EXCP_NO_FP(ctx); \
1767 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
1768 gen_reset_fpstatus(); \
1770 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1771 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
1774 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
1775 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
1777 if (unlikely(!ctx->fpu_enabled)) { \
1778 GEN_EXCP_NO_FP(ctx); \
1781 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
1782 gen_reset_fpstatus(); \
1784 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1785 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
1789 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
1791 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
1793 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
1796 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
1799 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
1802 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
1805 static always_inline void gen_op_frsqrtes (void)
1810 GEN_FLOAT_BS(rsqrtes, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTES);
1813 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
1815 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
1818 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
1820 if (unlikely(!ctx->fpu_enabled)) {
1821 GEN_EXCP_NO_FP(ctx);
1824 gen_op_load_fpr_FT0(rB(ctx->opcode));
1825 gen_reset_fpstatus();
1827 gen_op_store_FT0_fpr(rD(ctx->opcode));
1828 gen_compute_fprf(1, Rc(ctx->opcode) != 0);
1831 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
1833 if (unlikely(!ctx->fpu_enabled)) {
1834 GEN_EXCP_NO_FP(ctx);
1837 gen_op_load_fpr_FT0(rB(ctx->opcode));
1838 gen_reset_fpstatus();
1841 gen_op_store_FT0_fpr(rD(ctx->opcode));
1842 gen_compute_fprf(1, Rc(ctx->opcode) != 0);
1845 /*** Floating-Point multiply-and-add ***/
1846 /* fmadd - fmadds */
1847 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
1848 /* fmsub - fmsubs */
1849 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
1850 /* fnmadd - fnmadds */
1851 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
1852 /* fnmsub - fnmsubs */
1853 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
1855 /*** Floating-Point round & convert ***/
1857 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
1859 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
1861 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
1862 #if defined(TARGET_PPC64)
1864 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
1866 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
1868 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
1872 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
1874 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
1876 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
1878 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
1880 /*** Floating-Point compare ***/
1882 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
1884 if (unlikely(!ctx->fpu_enabled)) {
1885 GEN_EXCP_NO_FP(ctx);
1888 gen_op_load_fpr_FT0(rA(ctx->opcode));
1889 gen_op_load_fpr_FT1(rB(ctx->opcode));
1890 gen_reset_fpstatus();
1892 gen_op_store_T0_crf(crfD(ctx->opcode));
1893 gen_op_float_check_status();
1897 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
1899 if (unlikely(!ctx->fpu_enabled)) {
1900 GEN_EXCP_NO_FP(ctx);
1903 gen_op_load_fpr_FT0(rA(ctx->opcode));
1904 gen_op_load_fpr_FT1(rB(ctx->opcode));
1905 gen_reset_fpstatus();
1907 gen_op_store_T0_crf(crfD(ctx->opcode));
1908 gen_op_float_check_status();
1911 /*** Floating-point move ***/
1913 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
1914 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
1917 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
1918 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
1920 if (unlikely(!ctx->fpu_enabled)) {
1921 GEN_EXCP_NO_FP(ctx);
1924 gen_op_load_fpr_FT0(rB(ctx->opcode));
1925 gen_op_store_FT0_fpr(rD(ctx->opcode));
1926 gen_compute_fprf(0, Rc(ctx->opcode) != 0);
1930 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
1931 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
1933 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
1934 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
1936 /*** Floating-Point status & ctrl register ***/
1938 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
1942 if (unlikely(!ctx->fpu_enabled)) {
1943 GEN_EXCP_NO_FP(ctx);
1946 gen_optimize_fprf();
1947 bfa = 4 * (7 - crfS(ctx->opcode));
1948 gen_op_load_fpscr_T0(bfa);
1949 gen_op_store_T0_crf(crfD(ctx->opcode));
1950 gen_op_fpscr_resetbit(~(0xF << bfa));
1954 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
1956 if (unlikely(!ctx->fpu_enabled)) {
1957 GEN_EXCP_NO_FP(ctx);
1960 gen_optimize_fprf();
1961 gen_reset_fpstatus();
1962 gen_op_load_fpscr_FT0();
1963 gen_op_store_FT0_fpr(rD(ctx->opcode));
1964 gen_compute_fprf(0, Rc(ctx->opcode) != 0);
1968 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
1972 if (unlikely(!ctx->fpu_enabled)) {
1973 GEN_EXCP_NO_FP(ctx);
1976 crb = 32 - (crbD(ctx->opcode) >> 2);
1977 gen_optimize_fprf();
1978 gen_reset_fpstatus();
1979 if (likely(crb != 30 && crb != 29))
1980 gen_op_fpscr_resetbit(~(1 << crb));
1981 if (unlikely(Rc(ctx->opcode) != 0)) {
1988 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
1992 if (unlikely(!ctx->fpu_enabled)) {
1993 GEN_EXCP_NO_FP(ctx);
1996 crb = 32 - (crbD(ctx->opcode) >> 2);
1997 gen_optimize_fprf();
1998 gen_reset_fpstatus();
1999 /* XXX: we pretend we can only do IEEE floating-point computations */
2000 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI))
2001 gen_op_fpscr_setbit(crb);
2002 if (unlikely(Rc(ctx->opcode) != 0)) {
2006 /* We can raise a differed exception */
2007 gen_op_float_check_status();
2011 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2013 if (unlikely(!ctx->fpu_enabled)) {
2014 GEN_EXCP_NO_FP(ctx);
2017 gen_optimize_fprf();
2018 gen_op_load_fpr_FT0(rB(ctx->opcode));
2019 gen_reset_fpstatus();
2020 gen_op_store_fpscr(FM(ctx->opcode));
2021 if (unlikely(Rc(ctx->opcode) != 0)) {
2025 /* We can raise a differed exception */
2026 gen_op_float_check_status();
2030 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2034 if (unlikely(!ctx->fpu_enabled)) {
2035 GEN_EXCP_NO_FP(ctx);
2038 bf = crbD(ctx->opcode) >> 2;
2040 gen_optimize_fprf();
2041 gen_op_set_FT0(FPIMM(ctx->opcode) << (4 * sh));
2042 gen_reset_fpstatus();
2043 gen_op_store_fpscr(1 << sh);
2044 if (unlikely(Rc(ctx->opcode) != 0)) {
2048 /* We can raise a differed exception */
2049 gen_op_float_check_status();
2052 /*** Addressing modes ***/
2053 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2054 static always_inline void gen_addr_imm_index (DisasContext *ctx,
2057 target_long simm = SIMM(ctx->opcode);
2060 if (rA(ctx->opcode) == 0) {
2063 gen_op_load_gpr_T0(rA(ctx->opcode));
2064 if (likely(simm != 0))
2067 #ifdef DEBUG_MEMORY_ACCESSES
2068 gen_op_print_mem_EA();
2072 static always_inline void gen_addr_reg_index (DisasContext *ctx)
2074 if (rA(ctx->opcode) == 0) {
2075 gen_op_load_gpr_T0(rB(ctx->opcode));
2077 gen_op_load_gpr_T0(rA(ctx->opcode));
2078 gen_op_load_gpr_T1(rB(ctx->opcode));
2081 #ifdef DEBUG_MEMORY_ACCESSES
2082 gen_op_print_mem_EA();
2086 static always_inline void gen_addr_register (DisasContext *ctx)
2088 if (rA(ctx->opcode) == 0) {
2091 gen_op_load_gpr_T0(rA(ctx->opcode));
2093 #ifdef DEBUG_MEMORY_ACCESSES
2094 gen_op_print_mem_EA();
2098 /*** Integer load ***/
2099 #define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
2100 #if defined(CONFIG_USER_ONLY)
2101 #if defined(TARGET_PPC64)
2102 /* User mode only - 64 bits */
2103 #define OP_LD_TABLE(width) \
2104 static GenOpFunc *gen_op_l##width[] = { \
2105 &gen_op_l##width##_raw, \
2106 &gen_op_l##width##_le_raw, \
2107 &gen_op_l##width##_64_raw, \
2108 &gen_op_l##width##_le_64_raw, \
2110 #define OP_ST_TABLE(width) \
2111 static GenOpFunc *gen_op_st##width[] = { \
2112 &gen_op_st##width##_raw, \
2113 &gen_op_st##width##_le_raw, \
2114 &gen_op_st##width##_64_raw, \
2115 &gen_op_st##width##_le_64_raw, \
2117 /* Byte access routine are endian safe */
2118 #define gen_op_stb_le_64_raw gen_op_stb_64_raw
2119 #define gen_op_lbz_le_64_raw gen_op_lbz_64_raw
2121 /* User mode only - 32 bits */
2122 #define OP_LD_TABLE(width) \
2123 static GenOpFunc *gen_op_l##width[] = { \
2124 &gen_op_l##width##_raw, \
2125 &gen_op_l##width##_le_raw, \
2127 #define OP_ST_TABLE(width) \
2128 static GenOpFunc *gen_op_st##width[] = { \
2129 &gen_op_st##width##_raw, \
2130 &gen_op_st##width##_le_raw, \
2133 /* Byte access routine are endian safe */
2134 #define gen_op_stb_le_raw gen_op_stb_raw
2135 #define gen_op_lbz_le_raw gen_op_lbz_raw
2137 #if defined(TARGET_PPC64)
2138 #if defined(TARGET_PPC64H)
2139 /* Full system - 64 bits with hypervisor mode */
2140 #define OP_LD_TABLE(width) \
2141 static GenOpFunc *gen_op_l##width[] = { \
2142 &gen_op_l##width##_user, \
2143 &gen_op_l##width##_le_user, \
2144 &gen_op_l##width##_64_user, \
2145 &gen_op_l##width##_le_64_user, \
2146 &gen_op_l##width##_kernel, \
2147 &gen_op_l##width##_le_kernel, \
2148 &gen_op_l##width##_64_kernel, \
2149 &gen_op_l##width##_le_64_kernel, \
2150 &gen_op_l##width##_hypv, \
2151 &gen_op_l##width##_le_hypv, \
2152 &gen_op_l##width##_64_hypv, \
2153 &gen_op_l##width##_le_64_hypv, \
2155 #define OP_ST_TABLE(width) \
2156 static GenOpFunc *gen_op_st##width[] = { \
2157 &gen_op_st##width##_user, \
2158 &gen_op_st##width##_le_user, \
2159 &gen_op_st##width##_64_user, \
2160 &gen_op_st##width##_le_64_user, \
2161 &gen_op_st##width##_kernel, \
2162 &gen_op_st##width##_le_kernel, \
2163 &gen_op_st##width##_64_kernel, \
2164 &gen_op_st##width##_le_64_kernel, \
2165 &gen_op_st##width##_hypv, \
2166 &gen_op_st##width##_le_hypv, \
2167 &gen_op_st##width##_64_hypv, \
2168 &gen_op_st##width##_le_64_hypv, \
2170 /* Byte access routine are endian safe */
2171 #define gen_op_stb_le_hypv gen_op_stb_64_hypv
2172 #define gen_op_lbz_le_hypv gen_op_lbz_64_hypv
2173 #define gen_op_stb_le_64_hypv gen_op_stb_64_hypv
2174 #define gen_op_lbz_le_64_hypv gen_op_lbz_64_hypv
2176 /* Full system - 64 bits */
2177 #define OP_LD_TABLE(width) \
2178 static GenOpFunc *gen_op_l##width[] = { \
2179 &gen_op_l##width##_user, \
2180 &gen_op_l##width##_le_user, \
2181 &gen_op_l##width##_64_user, \
2182 &gen_op_l##width##_le_64_user, \
2183 &gen_op_l##width##_kernel, \
2184 &gen_op_l##width##_le_kernel, \
2185 &gen_op_l##width##_64_kernel, \
2186 &gen_op_l##width##_le_64_kernel, \
2188 #define OP_ST_TABLE(width) \
2189 static GenOpFunc *gen_op_st##width[] = { \
2190 &gen_op_st##width##_user, \
2191 &gen_op_st##width##_le_user, \
2192 &gen_op_st##width##_64_user, \
2193 &gen_op_st##width##_le_64_user, \
2194 &gen_op_st##width##_kernel, \
2195 &gen_op_st##width##_le_kernel, \
2196 &gen_op_st##width##_64_kernel, \
2197 &gen_op_st##width##_le_64_kernel, \
2200 /* Byte access routine are endian safe */
2201 #define gen_op_stb_le_64_user gen_op_stb_64_user
2202 #define gen_op_lbz_le_64_user gen_op_lbz_64_user
2203 #define gen_op_stb_le_64_kernel gen_op_stb_64_kernel
2204 #define gen_op_lbz_le_64_kernel gen_op_lbz_64_kernel
2206 /* Full system - 32 bits */
2207 #define OP_LD_TABLE(width) \
2208 static GenOpFunc *gen_op_l##width[] = { \
2209 &gen_op_l##width##_user, \
2210 &gen_op_l##width##_le_user, \
2211 &gen_op_l##width##_kernel, \
2212 &gen_op_l##width##_le_kernel, \
2214 #define OP_ST_TABLE(width) \
2215 static GenOpFunc *gen_op_st##width[] = { \
2216 &gen_op_st##width##_user, \
2217 &gen_op_st##width##_le_user, \
2218 &gen_op_st##width##_kernel, \
2219 &gen_op_st##width##_le_kernel, \
2222 /* Byte access routine are endian safe */
2223 #define gen_op_stb_le_user gen_op_stb_user
2224 #define gen_op_lbz_le_user gen_op_lbz_user
2225 #define gen_op_stb_le_kernel gen_op_stb_kernel
2226 #define gen_op_lbz_le_kernel gen_op_lbz_kernel
2229 #define GEN_LD(width, opc, type) \
2230 GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
2232 gen_addr_imm_index(ctx, 0); \
2233 op_ldst(l##width); \
2234 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2237 #define GEN_LDU(width, opc, type) \
2238 GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2240 if (unlikely(rA(ctx->opcode) == 0 || \
2241 rA(ctx->opcode) == rD(ctx->opcode))) { \
2242 GEN_EXCP_INVAL(ctx); \
2245 if (type == PPC_64B) \
2246 gen_addr_imm_index(ctx, 0x03); \
2248 gen_addr_imm_index(ctx, 0); \
2249 op_ldst(l##width); \
2250 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2251 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2254 #define GEN_LDUX(width, opc2, opc3, type) \
2255 GEN_HANDLER(l##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2257 if (unlikely(rA(ctx->opcode) == 0 || \
2258 rA(ctx->opcode) == rD(ctx->opcode))) { \
2259 GEN_EXCP_INVAL(ctx); \
2262 gen_addr_reg_index(ctx); \
2263 op_ldst(l##width); \
2264 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2265 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2268 #define GEN_LDX(width, opc2, opc3, type) \
2269 GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
2271 gen_addr_reg_index(ctx); \
2272 op_ldst(l##width); \
2273 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2276 #define GEN_LDS(width, op, type) \
2277 OP_LD_TABLE(width); \
2278 GEN_LD(width, op | 0x20, type); \
2279 GEN_LDU(width, op | 0x21, type); \
2280 GEN_LDUX(width, 0x17, op | 0x01, type); \
2281 GEN_LDX(width, 0x17, op | 0x00, type)
2283 /* lbz lbzu lbzux lbzx */
2284 GEN_LDS(bz, 0x02, PPC_INTEGER);
2285 /* lha lhau lhaux lhax */
2286 GEN_LDS(ha, 0x0A, PPC_INTEGER);
2287 /* lhz lhzu lhzux lhzx */
2288 GEN_LDS(hz, 0x08, PPC_INTEGER);
2289 /* lwz lwzu lwzux lwzx */
2290 GEN_LDS(wz, 0x00, PPC_INTEGER);
2291 #if defined(TARGET_PPC64)
2295 GEN_LDUX(wa, 0x15, 0x0B, PPC_64B);
2297 GEN_LDX(wa, 0x15, 0x0A, PPC_64B);
2299 GEN_LDUX(d, 0x15, 0x01, PPC_64B);
2301 GEN_LDX(d, 0x15, 0x00, PPC_64B);
2302 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2304 if (Rc(ctx->opcode)) {
2305 if (unlikely(rA(ctx->opcode) == 0 ||
2306 rA(ctx->opcode) == rD(ctx->opcode))) {
2307 GEN_EXCP_INVAL(ctx);
2311 gen_addr_imm_index(ctx, 0x03);
2312 if (ctx->opcode & 0x02) {
2313 /* lwa (lwau is undefined) */
2319 gen_op_store_T1_gpr(rD(ctx->opcode));
2320 if (Rc(ctx->opcode))
2321 gen_op_store_T0_gpr(rA(ctx->opcode));
2324 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2326 #if defined(CONFIG_USER_ONLY)
2327 GEN_EXCP_PRIVOPC(ctx);
2331 /* Restore CPU state */
2332 if (unlikely(ctx->supervisor == 0)) {
2333 GEN_EXCP_PRIVOPC(ctx);
2336 ra = rA(ctx->opcode);
2337 rd = rD(ctx->opcode);
2338 if (unlikely((rd & 1) || rd == ra)) {
2339 GEN_EXCP_INVAL(ctx);
2342 if (unlikely(ctx->mem_idx & 1)) {
2343 /* Little-endian mode is not handled */
2344 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2347 gen_addr_imm_index(ctx, 0x0F);
2349 gen_op_store_T1_gpr(rd);
2352 gen_op_store_T1_gpr(rd + 1);
2357 /*** Integer store ***/
2358 #define GEN_ST(width, opc, type) \
2359 GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
2361 gen_addr_imm_index(ctx, 0); \
2362 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2363 op_ldst(st##width); \
2366 #define GEN_STU(width, opc, type) \
2367 GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2369 if (unlikely(rA(ctx->opcode) == 0)) { \
2370 GEN_EXCP_INVAL(ctx); \
2373 if (type == PPC_64B) \
2374 gen_addr_imm_index(ctx, 0x03); \
2376 gen_addr_imm_index(ctx, 0); \
2377 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2378 op_ldst(st##width); \
2379 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2382 #define GEN_STUX(width, opc2, opc3, type) \
2383 GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2385 if (unlikely(rA(ctx->opcode) == 0)) { \
2386 GEN_EXCP_INVAL(ctx); \
2389 gen_addr_reg_index(ctx); \
2390 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2391 op_ldst(st##width); \
2392 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2395 #define GEN_STX(width, opc2, opc3, type) \
2396 GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
2398 gen_addr_reg_index(ctx); \
2399 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2400 op_ldst(st##width); \
2403 #define GEN_STS(width, op, type) \
2404 OP_ST_TABLE(width); \
2405 GEN_ST(width, op | 0x20, type); \
2406 GEN_STU(width, op | 0x21, type); \
2407 GEN_STUX(width, 0x17, op | 0x01, type); \
2408 GEN_STX(width, 0x17, op | 0x00, type)
2410 /* stb stbu stbux stbx */
2411 GEN_STS(b, 0x06, PPC_INTEGER);
2412 /* sth sthu sthux sthx */
2413 GEN_STS(h, 0x0C, PPC_INTEGER);
2414 /* stw stwu stwux stwx */
2415 GEN_STS(w, 0x04, PPC_INTEGER);
2416 #if defined(TARGET_PPC64)
2418 GEN_STUX(d, 0x15, 0x05, PPC_64B);
2419 GEN_STX(d, 0x15, 0x04, PPC_64B);
2420 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
2424 rs = rS(ctx->opcode);
2425 if ((ctx->opcode & 0x3) == 0x2) {
2426 #if defined(CONFIG_USER_ONLY)
2427 GEN_EXCP_PRIVOPC(ctx);
2430 if (unlikely(ctx->supervisor == 0)) {
2431 GEN_EXCP_PRIVOPC(ctx);
2434 if (unlikely(rs & 1)) {
2435 GEN_EXCP_INVAL(ctx);
2438 if (unlikely(ctx->mem_idx & 1)) {
2439 /* Little-endian mode is not handled */
2440 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2443 gen_addr_imm_index(ctx, 0x03);
2444 gen_op_load_gpr_T1(rs);
2447 gen_op_load_gpr_T1(rs + 1);
2452 if (Rc(ctx->opcode)) {
2453 if (unlikely(rA(ctx->opcode) == 0)) {
2454 GEN_EXCP_INVAL(ctx);
2458 gen_addr_imm_index(ctx, 0x03);
2459 gen_op_load_gpr_T1(rs);
2461 if (Rc(ctx->opcode))
2462 gen_op_store_T0_gpr(rA(ctx->opcode));
2466 /*** Integer load and store with byte reverse ***/
2469 GEN_LDX(hbr, 0x16, 0x18, PPC_INTEGER);
2472 GEN_LDX(wbr, 0x16, 0x10, PPC_INTEGER);
2475 GEN_STX(hbr, 0x16, 0x1C, PPC_INTEGER);
2478 GEN_STX(wbr, 0x16, 0x14, PPC_INTEGER);
2480 /*** Integer load and store multiple ***/
2481 #define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
2482 #if defined(CONFIG_USER_ONLY)
2483 /* User-mode only */
2484 static GenOpFunc1 *gen_op_lmw[] = {
2487 #if defined(TARGET_PPC64)
2489 &gen_op_lmw_le_64_raw,
2492 static GenOpFunc1 *gen_op_stmw[] = {
2494 &gen_op_stmw_le_raw,
2495 #if defined(TARGET_PPC64)
2496 &gen_op_stmw_64_raw,
2497 &gen_op_stmw_le_64_raw,
2501 #if defined(TARGET_PPC64)
2502 /* Full system - 64 bits mode */
2503 static GenOpFunc1 *gen_op_lmw[] = {
2505 &gen_op_lmw_le_user,
2506 &gen_op_lmw_64_user,
2507 &gen_op_lmw_le_64_user,
2509 &gen_op_lmw_le_kernel,
2510 &gen_op_lmw_64_kernel,
2511 &gen_op_lmw_le_64_kernel,
2512 #if defined(TARGET_PPC64H)
2514 &gen_op_lmw_le_hypv,
2515 &gen_op_lmw_64_hypv,
2516 &gen_op_lmw_le_64_hypv,
2519 static GenOpFunc1 *gen_op_stmw[] = {
2521 &gen_op_stmw_le_user,
2522 &gen_op_stmw_64_user,
2523 &gen_op_stmw_le_64_user,
2524 &gen_op_stmw_kernel,
2525 &gen_op_stmw_le_kernel,
2526 &gen_op_stmw_64_kernel,
2527 &gen_op_stmw_le_64_kernel,
2528 #if defined(TARGET_PPC64H)
2530 &gen_op_stmw_le_hypv,
2531 &gen_op_stmw_64_hypv,
2532 &gen_op_stmw_le_64_hypv,
2536 /* Full system - 32 bits mode */
2537 static GenOpFunc1 *gen_op_lmw[] = {
2539 &gen_op_lmw_le_user,
2541 &gen_op_lmw_le_kernel,
2543 static GenOpFunc1 *gen_op_stmw[] = {
2545 &gen_op_stmw_le_user,
2546 &gen_op_stmw_kernel,
2547 &gen_op_stmw_le_kernel,
2553 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
2555 /* NIP cannot be restored if the memory exception comes from an helper */
2556 gen_update_nip(ctx, ctx->nip - 4);
2557 gen_addr_imm_index(ctx, 0);
2558 op_ldstm(lmw, rD(ctx->opcode));
2562 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
2564 /* NIP cannot be restored if the memory exception comes from an helper */
2565 gen_update_nip(ctx, ctx->nip - 4);
2566 gen_addr_imm_index(ctx, 0);
2567 op_ldstm(stmw, rS(ctx->opcode));
2570 /*** Integer load and store strings ***/
2571 #define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
2572 #define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
2573 #if defined(CONFIG_USER_ONLY)
2574 /* User-mode only */
2575 static GenOpFunc1 *gen_op_lswi[] = {
2577 &gen_op_lswi_le_raw,
2578 #if defined(TARGET_PPC64)
2579 &gen_op_lswi_64_raw,
2580 &gen_op_lswi_le_64_raw,
2583 static GenOpFunc3 *gen_op_lswx[] = {
2585 &gen_op_lswx_le_raw,
2586 #if defined(TARGET_PPC64)
2587 &gen_op_lswx_64_raw,
2588 &gen_op_lswx_le_64_raw,
2591 static GenOpFunc1 *gen_op_stsw[] = {
2593 &gen_op_stsw_le_raw,
2594 #if defined(TARGET_PPC64)
2595 &gen_op_stsw_64_raw,
2596 &gen_op_stsw_le_64_raw,
2600 #if defined(TARGET_PPC64)
2601 /* Full system - 64 bits mode */
2602 static GenOpFunc1 *gen_op_lswi[] = {
2604 &gen_op_lswi_le_user,
2605 &gen_op_lswi_64_user,
2606 &gen_op_lswi_le_64_user,
2607 &gen_op_lswi_kernel,
2608 &gen_op_lswi_le_kernel,
2609 &gen_op_lswi_64_kernel,
2610 &gen_op_lswi_le_64_kernel,
2611 #if defined(TARGET_PPC64H)
2613 &gen_op_lswi_le_hypv,
2614 &gen_op_lswi_64_hypv,
2615 &gen_op_lswi_le_64_hypv,
2618 static GenOpFunc3 *gen_op_lswx[] = {
2620 &gen_op_lswx_le_user,
2621 &gen_op_lswx_64_user,
2622 &gen_op_lswx_le_64_user,
2623 &gen_op_lswx_kernel,
2624 &gen_op_lswx_le_kernel,
2625 &gen_op_lswx_64_kernel,
2626 &gen_op_lswx_le_64_kernel,
2627 #if defined(TARGET_PPC64H)
2629 &gen_op_lswx_le_hypv,
2630 &gen_op_lswx_64_hypv,
2631 &gen_op_lswx_le_64_hypv,
2634 static GenOpFunc1 *gen_op_stsw[] = {
2636 &gen_op_stsw_le_user,
2637 &gen_op_stsw_64_user,
2638 &gen_op_stsw_le_64_user,
2639 &gen_op_stsw_kernel,
2640 &gen_op_stsw_le_kernel,
2641 &gen_op_stsw_64_kernel,
2642 &gen_op_stsw_le_64_kernel,
2643 #if defined(TARGET_PPC64H)
2645 &gen_op_stsw_le_hypv,
2646 &gen_op_stsw_64_hypv,
2647 &gen_op_stsw_le_64_hypv,
2651 /* Full system - 32 bits mode */
2652 static GenOpFunc1 *gen_op_lswi[] = {
2654 &gen_op_lswi_le_user,
2655 &gen_op_lswi_kernel,
2656 &gen_op_lswi_le_kernel,
2658 static GenOpFunc3 *gen_op_lswx[] = {
2660 &gen_op_lswx_le_user,
2661 &gen_op_lswx_kernel,
2662 &gen_op_lswx_le_kernel,
2664 static GenOpFunc1 *gen_op_stsw[] = {
2666 &gen_op_stsw_le_user,
2667 &gen_op_stsw_kernel,
2668 &gen_op_stsw_le_kernel,
2674 /* PowerPC32 specification says we must generate an exception if
2675 * rA is in the range of registers to be loaded.
2676 * In an other hand, IBM says this is valid, but rA won't be loaded.
2677 * For now, I'll follow the spec...
2679 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_INTEGER)
2681 int nb = NB(ctx->opcode);
2682 int start = rD(ctx->opcode);
2683 int ra = rA(ctx->opcode);
2689 if (unlikely(((start + nr) > 32 &&
2690 start <= ra && (start + nr - 32) > ra) ||
2691 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
2692 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
2693 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_LSWX);
2696 /* NIP cannot be restored if the memory exception comes from an helper */
2697 gen_update_nip(ctx, ctx->nip - 4);
2698 gen_addr_register(ctx);
2700 op_ldsts(lswi, start);
2704 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_INTEGER)
2706 int ra = rA(ctx->opcode);
2707 int rb = rB(ctx->opcode);
2709 /* NIP cannot be restored if the memory exception comes from an helper */
2710 gen_update_nip(ctx, ctx->nip - 4);
2711 gen_addr_reg_index(ctx);
2715 gen_op_load_xer_bc();
2716 op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
2720 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_INTEGER)
2722 int nb = NB(ctx->opcode);
2724 /* NIP cannot be restored if the memory exception comes from an helper */
2725 gen_update_nip(ctx, ctx->nip - 4);
2726 gen_addr_register(ctx);
2730 op_ldsts(stsw, rS(ctx->opcode));
2734 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_INTEGER)
2736 /* NIP cannot be restored if the memory exception comes from an helper */
2737 gen_update_nip(ctx, ctx->nip - 4);
2738 gen_addr_reg_index(ctx);
2739 gen_op_load_xer_bc();
2740 op_ldsts(stsw, rS(ctx->opcode));
2743 /*** Memory synchronisation ***/
2745 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
2750 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
2755 #define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
2756 #define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
2757 #if defined(CONFIG_USER_ONLY)
2758 /* User-mode only */
2759 static GenOpFunc *gen_op_lwarx[] = {
2761 &gen_op_lwarx_le_raw,
2762 #if defined(TARGET_PPC64)
2763 &gen_op_lwarx_64_raw,
2764 &gen_op_lwarx_le_64_raw,
2767 static GenOpFunc *gen_op_stwcx[] = {
2769 &gen_op_stwcx_le_raw,
2770 #if defined(TARGET_PPC64)
2771 &gen_op_stwcx_64_raw,
2772 &gen_op_stwcx_le_64_raw,
2776 #if defined(TARGET_PPC64)
2777 /* Full system - 64 bits mode */
2778 static GenOpFunc *gen_op_lwarx[] = {
2780 &gen_op_lwarx_le_user,
2781 &gen_op_lwarx_64_user,
2782 &gen_op_lwarx_le_64_user,
2783 &gen_op_lwarx_kernel,
2784 &gen_op_lwarx_le_kernel,
2785 &gen_op_lwarx_64_kernel,
2786 &gen_op_lwarx_le_64_kernel,
2787 #if defined(TARGET_PPC64H)
2789 &gen_op_lwarx_le_hypv,
2790 &gen_op_lwarx_64_hypv,
2791 &gen_op_lwarx_le_64_hypv,
2794 static GenOpFunc *gen_op_stwcx[] = {
2796 &gen_op_stwcx_le_user,
2797 &gen_op_stwcx_64_user,
2798 &gen_op_stwcx_le_64_user,
2799 &gen_op_stwcx_kernel,
2800 &gen_op_stwcx_le_kernel,
2801 &gen_op_stwcx_64_kernel,
2802 &gen_op_stwcx_le_64_kernel,
2803 #if defined(TARGET_PPC64H)
2805 &gen_op_stwcx_le_hypv,
2806 &gen_op_stwcx_64_hypv,
2807 &gen_op_stwcx_le_64_hypv,
2811 /* Full system - 32 bits mode */
2812 static GenOpFunc *gen_op_lwarx[] = {
2814 &gen_op_lwarx_le_user,
2815 &gen_op_lwarx_kernel,
2816 &gen_op_lwarx_le_kernel,
2818 static GenOpFunc *gen_op_stwcx[] = {
2820 &gen_op_stwcx_le_user,
2821 &gen_op_stwcx_kernel,
2822 &gen_op_stwcx_le_kernel,
2828 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
2830 /* NIP cannot be restored if the memory exception comes from an helper */
2831 gen_update_nip(ctx, ctx->nip - 4);
2832 gen_addr_reg_index(ctx);
2834 gen_op_store_T1_gpr(rD(ctx->opcode));
2838 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
2840 /* NIP cannot be restored if the memory exception comes from an helper */
2841 gen_update_nip(ctx, ctx->nip - 4);
2842 gen_addr_reg_index(ctx);
2843 gen_op_load_gpr_T1(rS(ctx->opcode));
2847 #if defined(TARGET_PPC64)
2848 #define op_ldarx() (*gen_op_ldarx[ctx->mem_idx])()
2849 #define op_stdcx() (*gen_op_stdcx[ctx->mem_idx])()
2850 #if defined(CONFIG_USER_ONLY)
2851 /* User-mode only */
2852 static GenOpFunc *gen_op_ldarx[] = {
2854 &gen_op_ldarx_le_raw,
2855 &gen_op_ldarx_64_raw,
2856 &gen_op_ldarx_le_64_raw,
2858 static GenOpFunc *gen_op_stdcx[] = {
2860 &gen_op_stdcx_le_raw,
2861 &gen_op_stdcx_64_raw,
2862 &gen_op_stdcx_le_64_raw,
2866 static GenOpFunc *gen_op_ldarx[] = {
2868 &gen_op_ldarx_le_user,
2869 &gen_op_ldarx_64_user,
2870 &gen_op_ldarx_le_64_user,
2871 &gen_op_ldarx_kernel,
2872 &gen_op_ldarx_le_kernel,
2873 &gen_op_ldarx_64_kernel,
2874 &gen_op_ldarx_le_64_kernel,
2875 #if defined(TARGET_PPC64H)
2877 &gen_op_ldarx_le_hypv,
2878 &gen_op_ldarx_64_hypv,
2879 &gen_op_ldarx_le_64_hypv,
2882 static GenOpFunc *gen_op_stdcx[] = {
2884 &gen_op_stdcx_le_user,
2885 &gen_op_stdcx_64_user,
2886 &gen_op_stdcx_le_64_user,
2887 &gen_op_stdcx_kernel,
2888 &gen_op_stdcx_le_kernel,
2889 &gen_op_stdcx_64_kernel,
2890 &gen_op_stdcx_le_64_kernel,
2891 #if defined(TARGET_PPC64H)
2893 &gen_op_stdcx_le_hypv,
2894 &gen_op_stdcx_64_hypv,
2895 &gen_op_stdcx_le_64_hypv,
2901 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
2903 /* NIP cannot be restored if the memory exception comes from an helper */
2904 gen_update_nip(ctx, ctx->nip - 4);
2905 gen_addr_reg_index(ctx);
2907 gen_op_store_T1_gpr(rD(ctx->opcode));
2911 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
2913 /* NIP cannot be restored if the memory exception comes from an helper */
2914 gen_update_nip(ctx, ctx->nip - 4);
2915 gen_addr_reg_index(ctx);
2916 gen_op_load_gpr_T1(rS(ctx->opcode));
2919 #endif /* defined(TARGET_PPC64) */
2922 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
2927 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
2929 /* Stop translation, as the CPU is supposed to sleep from now */
2931 GEN_EXCP(ctx, EXCP_HLT, 1);
2934 /*** Floating-point load ***/
2935 #define GEN_LDF(width, opc, type) \
2936 GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
2938 if (unlikely(!ctx->fpu_enabled)) { \
2939 GEN_EXCP_NO_FP(ctx); \
2942 gen_addr_imm_index(ctx, 0); \
2943 op_ldst(l##width); \
2944 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
2947 #define GEN_LDUF(width, opc, type) \
2948 GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2950 if (unlikely(!ctx->fpu_enabled)) { \
2951 GEN_EXCP_NO_FP(ctx); \
2954 if (unlikely(rA(ctx->opcode) == 0)) { \
2955 GEN_EXCP_INVAL(ctx); \
2958 gen_addr_imm_index(ctx, 0); \
2959 op_ldst(l##width); \
2960 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
2961 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2964 #define GEN_LDUXF(width, opc, type) \
2965 GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
2967 if (unlikely(!ctx->fpu_enabled)) { \
2968 GEN_EXCP_NO_FP(ctx); \
2971 if (unlikely(rA(ctx->opcode) == 0)) { \
2972 GEN_EXCP_INVAL(ctx); \
2975 gen_addr_reg_index(ctx); \
2976 op_ldst(l##width); \
2977 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
2978 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2981 #define GEN_LDXF(width, opc2, opc3, type) \
2982 GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
2984 if (unlikely(!ctx->fpu_enabled)) { \
2985 GEN_EXCP_NO_FP(ctx); \
2988 gen_addr_reg_index(ctx); \
2989 op_ldst(l##width); \
2990 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
2993 #define GEN_LDFS(width, op, type) \
2994 OP_LD_TABLE(width); \
2995 GEN_LDF(width, op | 0x20, type); \
2996 GEN_LDUF(width, op | 0x21, type); \
2997 GEN_LDUXF(width, op | 0x01, type); \
2998 GEN_LDXF(width, 0x17, op | 0x00, type)
3000 /* lfd lfdu lfdux lfdx */
3001 GEN_LDFS(fd, 0x12, PPC_FLOAT);
3002 /* lfs lfsu lfsux lfsx */
3003 GEN_LDFS(fs, 0x10, PPC_FLOAT);
3005 /*** Floating-point store ***/
3006 #define GEN_STF(width, opc, type) \
3007 GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
3009 if (unlikely(!ctx->fpu_enabled)) { \
3010 GEN_EXCP_NO_FP(ctx); \
3013 gen_addr_imm_index(ctx, 0); \
3014 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
3015 op_ldst(st##width); \
3018 #define GEN_STUF(width, opc, type) \
3019 GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
3021 if (unlikely(!ctx->fpu_enabled)) { \
3022 GEN_EXCP_NO_FP(ctx); \
3025 if (unlikely(rA(ctx->opcode) == 0)) { \
3026 GEN_EXCP_INVAL(ctx); \
3029 gen_addr_imm_index(ctx, 0); \
3030 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
3031 op_ldst(st##width); \
3032 gen_op_store_T0_gpr(rA(ctx->opcode)); \
3035 #define GEN_STUXF(width, opc, type) \
3036 GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
3038 if (unlikely(!ctx->fpu_enabled)) { \
3039 GEN_EXCP_NO_FP(ctx); \
3042 if (unlikely(rA(ctx->opcode) == 0)) { \
3043 GEN_EXCP_INVAL(ctx); \
3046 gen_addr_reg_index(ctx); \
3047 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
3048 op_ldst(st##width); \
3049 gen_op_store_T0_gpr(rA(ctx->opcode)); \
3052 #define GEN_STXF(width, opc2, opc3, type) \
3053 GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
3055 if (unlikely(!ctx->fpu_enabled)) { \
3056 GEN_EXCP_NO_FP(ctx); \
3059 gen_addr_reg_index(ctx); \
3060 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
3061 op_ldst(st##width); \
3064 #define GEN_STFS(width, op, type) \
3065 OP_ST_TABLE(width); \
3066 GEN_STF(width, op | 0x20, type); \
3067 GEN_STUF(width, op | 0x21, type); \
3068 GEN_STUXF(width, op | 0x01, type); \
3069 GEN_STXF(width, 0x17, op | 0x00, type)
3071 /* stfd stfdu stfdux stfdx */
3072 GEN_STFS(fd, 0x16, PPC_FLOAT);
3073 /* stfs stfsu stfsux stfsx */
3074 GEN_STFS(fs, 0x14, PPC_FLOAT);
3079 GEN_STXF(fiwx, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3082 static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3085 TranslationBlock *tb;
3087 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
3089 gen_op_goto_tb0(TBPARAM(tb));
3091 gen_op_goto_tb1(TBPARAM(tb));
3093 #if defined(TARGET_PPC64)
3099 gen_op_set_T0((long)tb + n);
3100 if (ctx->singlestep_enabled)
3105 #if defined(TARGET_PPC64)
3112 if (ctx->singlestep_enabled)
3118 static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
3120 #if defined(TARGET_PPC64)
3121 if (ctx->sf_mode != 0 && (nip >> 32))
3122 gen_op_setlr_64(ctx->nip >> 32, ctx->nip);
3125 gen_op_setlr(ctx->nip);
3129 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3131 target_ulong li, target;
3133 /* sign extend LI */
3134 #if defined(TARGET_PPC64)
3136 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3139 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
3140 if (likely(AA(ctx->opcode) == 0))
3141 target = ctx->nip + li - 4;
3144 #if defined(TARGET_PPC64)
3146 target = (uint32_t)target;
3148 if (LK(ctx->opcode))
3149 gen_setlr(ctx, ctx->nip);
3150 gen_goto_tb(ctx, 0, target);
3151 ctx->exception = POWERPC_EXCP_BRANCH;
3158 static always_inline void gen_bcond (DisasContext *ctx, int type)
3160 target_ulong target = 0;
3162 uint32_t bo = BO(ctx->opcode);
3163 uint32_t bi = BI(ctx->opcode);
3166 if ((bo & 0x4) == 0)
3170 li = (target_long)((int16_t)(BD(ctx->opcode)));
3171 if (likely(AA(ctx->opcode) == 0)) {
3172 target = ctx->nip + li - 4;
3176 #if defined(TARGET_PPC64)
3178 target = (uint32_t)target;
3182 gen_op_movl_T1_ctr();
3186 gen_op_movl_T1_lr();
3189 if (LK(ctx->opcode))
3190 gen_setlr(ctx, ctx->nip);
3192 /* No CR condition */
3195 #if defined(TARGET_PPC64)
3197 gen_op_test_ctr_64();
3203 #if defined(TARGET_PPC64)
3205 gen_op_test_ctrz_64();
3213 if (type == BCOND_IM) {
3214 gen_goto_tb(ctx, 0, target);
3217 #if defined(TARGET_PPC64)
3229 mask = 1 << (3 - (bi & 0x03));
3230 gen_op_load_crf_T0(bi >> 2);
3234 #if defined(TARGET_PPC64)
3236 gen_op_test_ctr_true_64(mask);
3239 gen_op_test_ctr_true(mask);
3242 #if defined(TARGET_PPC64)
3244 gen_op_test_ctrz_true_64(mask);
3247 gen_op_test_ctrz_true(mask);
3252 gen_op_test_true(mask);
3258 #if defined(TARGET_PPC64)
3260 gen_op_test_ctr_false_64(mask);
3263 gen_op_test_ctr_false(mask);
3266 #if defined(TARGET_PPC64)
3268 gen_op_test_ctrz_false_64(mask);
3271 gen_op_test_ctrz_false(mask);
3276 gen_op_test_false(mask);
3281 if (type == BCOND_IM) {
3282 int l1 = gen_new_label();
3284 gen_goto_tb(ctx, 0, target);
3286 gen_goto_tb(ctx, 1, ctx->nip);
3288 #if defined(TARGET_PPC64)
3290 gen_op_btest_T1_64(ctx->nip >> 32, ctx->nip);
3293 gen_op_btest_T1(ctx->nip);
3296 if (ctx->singlestep_enabled)
3301 ctx->exception = POWERPC_EXCP_BRANCH;
3304 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3306 gen_bcond(ctx, BCOND_IM);
3309 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3311 gen_bcond(ctx, BCOND_CTR);
3314 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3316 gen_bcond(ctx, BCOND_LR);
3319 /*** Condition register logical ***/
3320 #define GEN_CRLOGIC(op, opc) \
3321 GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
3325 gen_op_load_crf_T0(crbA(ctx->opcode) >> 2); \
3326 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3328 gen_op_srli_T0(sh); \
3330 gen_op_sli_T0(-sh); \
3331 gen_op_load_crf_T1(crbB(ctx->opcode) >> 2); \
3332 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3334 gen_op_srli_T1(sh); \
3336 gen_op_sli_T1(-sh); \
3338 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3339 gen_op_andi_T0(bitmask); \
3340 gen_op_load_crf_T1(crbD(ctx->opcode) >> 2); \
3341 gen_op_andi_T1(~bitmask); \
3343 gen_op_store_T0_crf(crbD(ctx->opcode) >> 2); \
3347 GEN_CRLOGIC(and, 0x08);
3349 GEN_CRLOGIC(andc, 0x04);
3351 GEN_CRLOGIC(eqv, 0x09);
3353 GEN_CRLOGIC(nand, 0x07);
3355 GEN_CRLOGIC(nor, 0x01);
3357 GEN_CRLOGIC(or, 0x0E);
3359 GEN_CRLOGIC(orc, 0x0D);
3361 GEN_CRLOGIC(xor, 0x06);
3363 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3365 gen_op_load_crf_T0(crfS(ctx->opcode));
3366 gen_op_store_T0_crf(crfD(ctx->opcode));
3369 /*** System linkage ***/
3370 /* rfi (supervisor only) */
3371 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
3373 #if defined(CONFIG_USER_ONLY)
3374 GEN_EXCP_PRIVOPC(ctx);
3376 /* Restore CPU state */
3377 if (unlikely(!ctx->supervisor)) {
3378 GEN_EXCP_PRIVOPC(ctx);
3386 #if defined(TARGET_PPC64)
3387 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
3389 #if defined(CONFIG_USER_ONLY)
3390 GEN_EXCP_PRIVOPC(ctx);
3392 /* Restore CPU state */
3393 if (unlikely(!ctx->supervisor)) {
3394 GEN_EXCP_PRIVOPC(ctx);
3403 #if defined(TARGET_PPC64H)
3404 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64B)
3406 #if defined(CONFIG_USER_ONLY)
3407 GEN_EXCP_PRIVOPC(ctx);
3409 /* Restore CPU state */
3410 if (unlikely(ctx->supervisor <= 1)) {
3411 GEN_EXCP_PRIVOPC(ctx);
3421 #if defined(CONFIG_USER_ONLY)
3422 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3424 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3426 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
3430 lev = (ctx->opcode >> 5) & 0x7F;
3431 GEN_EXCP(ctx, POWERPC_SYSCALL, lev);
3436 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
3438 gen_op_load_gpr_T0(rA(ctx->opcode));
3439 gen_op_load_gpr_T1(rB(ctx->opcode));
3440 /* Update the nip since this might generate a trap exception */
3441 gen_update_nip(ctx, ctx->nip);
3442 gen_op_tw(TO(ctx->opcode));
3446 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3448 gen_op_load_gpr_T0(rA(ctx->opcode));
3449 gen_set_T1(SIMM(ctx->opcode));
3450 /* Update the nip since this might generate a trap exception */
3451 gen_update_nip(ctx, ctx->nip);
3452 gen_op_tw(TO(ctx->opcode));
3455 #if defined(TARGET_PPC64)
3457 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3459 gen_op_load_gpr_T0(rA(ctx->opcode));
3460 gen_op_load_gpr_T1(rB(ctx->opcode));
3461 /* Update the nip since this might generate a trap exception */
3462 gen_update_nip(ctx, ctx->nip);
3463 gen_op_td(TO(ctx->opcode));
3467 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3469 gen_op_load_gpr_T0(rA(ctx->opcode));
3470 gen_set_T1(SIMM(ctx->opcode));
3471 /* Update the nip since this might generate a trap exception */
3472 gen_update_nip(ctx, ctx->nip);
3473 gen_op_td(TO(ctx->opcode));
3477 /*** Processor control ***/
3479 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3481 gen_op_load_xer_cr();
3482 gen_op_store_T0_crf(crfD(ctx->opcode));
3483 gen_op_clear_xer_ov();
3484 gen_op_clear_xer_ca();
3488 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
3492 if (likely(ctx->opcode & 0x00100000)) {
3493 crm = CRM(ctx->opcode);
3494 if (likely((crm ^ (crm - 1)) == 0)) {
3496 gen_op_load_cro(7 - crn);
3501 gen_op_store_T0_gpr(rD(ctx->opcode));
3505 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3507 #if defined(CONFIG_USER_ONLY)
3508 GEN_EXCP_PRIVREG(ctx);
3510 if (unlikely(!ctx->supervisor)) {
3511 GEN_EXCP_PRIVREG(ctx);
3515 gen_op_store_T0_gpr(rD(ctx->opcode));
3520 #define SPR_NOACCESS ((void *)(-1))
3522 static void spr_noaccess (void *opaque, int sprn)
3524 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3525 printf("ERROR: try to access SPR %d !\n", sprn);
3527 #define SPR_NOACCESS (&spr_noaccess)
3531 static always_inline void gen_op_mfspr (DisasContext *ctx)
3533 void (*read_cb)(void *opaque, int sprn);
3534 uint32_t sprn = SPR(ctx->opcode);
3536 #if !defined(CONFIG_USER_ONLY)
3537 #if defined(TARGET_PPC64H)
3538 if (ctx->supervisor == 2)
3539 read_cb = ctx->spr_cb[sprn].hea_read;
3542 if (ctx->supervisor)
3543 read_cb = ctx->spr_cb[sprn].oea_read;
3546 read_cb = ctx->spr_cb[sprn].uea_read;
3547 if (likely(read_cb != NULL)) {
3548 if (likely(read_cb != SPR_NOACCESS)) {
3549 (*read_cb)(ctx, sprn);
3550 gen_op_store_T0_gpr(rD(ctx->opcode));
3552 /* Privilege exception */
3553 /* This is a hack to avoid warnings when running Linux:
3554 * this OS breaks the PowerPC virtualisation model,
3555 * allowing userland application to read the PVR
3557 if (sprn != SPR_PVR) {
3558 if (loglevel != 0) {
3559 fprintf(logfile, "Trying to read privileged spr %d %03x\n",
3562 printf("Trying to read privileged spr %d %03x\n", sprn, sprn);
3564 GEN_EXCP_PRIVREG(ctx);
3568 if (loglevel != 0) {
3569 fprintf(logfile, "Trying to read invalid spr %d %03x\n",
3572 printf("Trying to read invalid spr %d %03x\n", sprn, sprn);
3573 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3574 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
3578 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
3584 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3590 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
3594 gen_op_load_gpr_T0(rS(ctx->opcode));
3595 crm = CRM(ctx->opcode);
3596 if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
3598 gen_op_srli_T0(crn * 4);
3599 gen_op_andi_T0(0xF);
3600 gen_op_store_cro(7 - crn);
3602 gen_op_store_cr(crm);
3607 #if defined(TARGET_PPC64)
3608 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
3610 #if defined(CONFIG_USER_ONLY)
3611 GEN_EXCP_PRIVREG(ctx);
3613 if (unlikely(!ctx->supervisor)) {
3614 GEN_EXCP_PRIVREG(ctx);
3617 gen_op_load_gpr_T0(rS(ctx->opcode));
3618 if (ctx->opcode & 0x00010000) {
3619 /* Special form that does not need any synchronisation */
3620 gen_op_update_riee();
3622 /* XXX: we need to update nip before the store
3623 * if we enter power saving mode, we will exit the loop
3624 * directly from ppc_store_msr
3626 gen_update_nip(ctx, ctx->nip);
3628 /* Must stop the translation as machine state (may have) changed */
3629 /* Note that mtmsr is not always defined as context-synchronizing */
3630 ctx->exception = POWERPC_EXCP_STOP;
3636 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3638 #if defined(CONFIG_USER_ONLY)
3639 GEN_EXCP_PRIVREG(ctx);
3641 if (unlikely(!ctx->supervisor)) {
3642 GEN_EXCP_PRIVREG(ctx);
3645 gen_op_load_gpr_T0(rS(ctx->opcode));
3646 if (ctx->opcode & 0x00010000) {
3647 /* Special form that does not need any synchronisation */
3648 gen_op_update_riee();
3650 /* XXX: we need to update nip before the store
3651 * if we enter power saving mode, we will exit the loop
3652 * directly from ppc_store_msr
3654 gen_update_nip(ctx, ctx->nip);
3655 #if defined(TARGET_PPC64)
3657 gen_op_store_msr_32();
3661 /* Must stop the translation as machine state (may have) changed */
3662 /* Note that mtmsrd is not always defined as context-synchronizing */
3663 ctx->exception = POWERPC_EXCP_STOP;
3669 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
3671 void (*write_cb)(void *opaque, int sprn);
3672 uint32_t sprn = SPR(ctx->opcode);
3674 #if !defined(CONFIG_USER_ONLY)
3675 #if defined(TARGET_PPC64H)
3676 if (ctx->supervisor == 2)
3677 write_cb = ctx->spr_cb[sprn].hea_write;
3680 if (ctx->supervisor)
3681 write_cb = ctx->spr_cb[sprn].oea_write;
3684 write_cb = ctx->spr_cb[sprn].uea_write;
3685 if (likely(write_cb != NULL)) {
3686 if (likely(write_cb != SPR_NOACCESS)) {
3687 gen_op_load_gpr_T0(rS(ctx->opcode));
3688 (*write_cb)(ctx, sprn);
3690 /* Privilege exception */
3691 if (loglevel != 0) {
3692 fprintf(logfile, "Trying to write privileged spr %d %03x\n",
3695 printf("Trying to write privileged spr %d %03x\n", sprn, sprn);
3696 GEN_EXCP_PRIVREG(ctx);
3700 if (loglevel != 0) {
3701 fprintf(logfile, "Trying to write invalid spr %d %03x\n",
3704 printf("Trying to write invalid spr %d %03x\n", sprn, sprn);
3705 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3706 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
3710 /*** Cache management ***/
3712 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
3714 /* XXX: specification says this is treated as a load by the MMU */
3715 gen_addr_reg_index(ctx);
3719 /* dcbi (Supervisor only) */
3720 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
3722 #if defined(CONFIG_USER_ONLY)
3723 GEN_EXCP_PRIVOPC(ctx);
3725 if (unlikely(!ctx->supervisor)) {
3726 GEN_EXCP_PRIVOPC(ctx);
3729 gen_addr_reg_index(ctx);
3730 /* XXX: specification says this should be treated as a store by the MMU */
3737 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
3739 /* XXX: specification say this is treated as a load by the MMU */
3740 gen_addr_reg_index(ctx);
3745 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
3747 /* interpreted as no-op */
3748 /* XXX: specification say this is treated as a load by the MMU
3749 * but does not generate any exception
3754 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
3756 /* interpreted as no-op */
3757 /* XXX: specification say this is treated as a load by the MMU
3758 * but does not generate any exception
3763 #define op_dcbz(n) (*gen_op_dcbz[n][ctx->mem_idx])()
3764 #if defined(CONFIG_USER_ONLY)
3765 /* User-mode only */
3766 static GenOpFunc *gen_op_dcbz[4][4] = {
3768 &gen_op_dcbz_l32_raw,
3769 &gen_op_dcbz_l32_raw,
3770 #if defined(TARGET_PPC64)
3771 &gen_op_dcbz_l32_64_raw,
3772 &gen_op_dcbz_l32_64_raw,
3776 &gen_op_dcbz_l64_raw,
3777 &gen_op_dcbz_l64_raw,
3778 #if defined(TARGET_PPC64)
3779 &gen_op_dcbz_l64_64_raw,
3780 &gen_op_dcbz_l64_64_raw,
3784 &gen_op_dcbz_l128_raw,
3785 &gen_op_dcbz_l128_raw,
3786 #if defined(TARGET_PPC64)
3787 &gen_op_dcbz_l128_64_raw,
3788 &gen_op_dcbz_l128_64_raw,
3794 #if defined(TARGET_PPC64)
3795 &gen_op_dcbz_64_raw,
3796 &gen_op_dcbz_64_raw,
3801 #if defined(TARGET_PPC64)
3802 /* Full system - 64 bits mode */
3803 static GenOpFunc *gen_op_dcbz[4][12] = {
3805 &gen_op_dcbz_l32_user,
3806 &gen_op_dcbz_l32_user,
3807 &gen_op_dcbz_l32_64_user,
3808 &gen_op_dcbz_l32_64_user,
3809 &gen_op_dcbz_l32_kernel,
3810 &gen_op_dcbz_l32_kernel,
3811 &gen_op_dcbz_l32_64_kernel,
3812 &gen_op_dcbz_l32_64_kernel,
3813 #if defined(TARGET_PPC64H)
3814 &gen_op_dcbz_l32_hypv,
3815 &gen_op_dcbz_l32_hypv,
3816 &gen_op_dcbz_l32_64_hypv,
3817 &gen_op_dcbz_l32_64_hypv,
3821 &gen_op_dcbz_l64_user,
3822 &gen_op_dcbz_l64_user,
3823 &gen_op_dcbz_l64_64_user,
3824 &gen_op_dcbz_l64_64_user,
3825 &gen_op_dcbz_l64_kernel,
3826 &gen_op_dcbz_l64_kernel,
3827 &gen_op_dcbz_l64_64_kernel,
3828 &gen_op_dcbz_l64_64_kernel,
3829 #if defined(TARGET_PPC64H)
3830 &gen_op_dcbz_l64_hypv,
3831 &gen_op_dcbz_l64_hypv,
3832 &gen_op_dcbz_l64_64_hypv,
3833 &gen_op_dcbz_l64_64_hypv,
3837 &gen_op_dcbz_l128_user,
3838 &gen_op_dcbz_l128_user,
3839 &gen_op_dcbz_l128_64_user,
3840 &gen_op_dcbz_l128_64_user,
3841 &gen_op_dcbz_l128_kernel,
3842 &gen_op_dcbz_l128_kernel,
3843 &gen_op_dcbz_l128_64_kernel,
3844 &gen_op_dcbz_l128_64_kernel,
3845 #if defined(TARGET_PPC64H)
3846 &gen_op_dcbz_l128_hypv,
3847 &gen_op_dcbz_l128_hypv,
3848 &gen_op_dcbz_l128_64_hypv,
3849 &gen_op_dcbz_l128_64_hypv,
3855 &gen_op_dcbz_64_user,
3856 &gen_op_dcbz_64_user,
3857 &gen_op_dcbz_kernel,
3858 &gen_op_dcbz_kernel,
3859 &gen_op_dcbz_64_kernel,
3860 &gen_op_dcbz_64_kernel,
3861 #if defined(TARGET_PPC64H)
3864 &gen_op_dcbz_64_hypv,
3865 &gen_op_dcbz_64_hypv,
3870 /* Full system - 32 bits mode */
3871 static GenOpFunc *gen_op_dcbz[4][4] = {
3873 &gen_op_dcbz_l32_user,
3874 &gen_op_dcbz_l32_user,
3875 &gen_op_dcbz_l32_kernel,
3876 &gen_op_dcbz_l32_kernel,
3879 &gen_op_dcbz_l64_user,
3880 &gen_op_dcbz_l64_user,
3881 &gen_op_dcbz_l64_kernel,
3882 &gen_op_dcbz_l64_kernel,
3885 &gen_op_dcbz_l128_user,
3886 &gen_op_dcbz_l128_user,
3887 &gen_op_dcbz_l128_kernel,
3888 &gen_op_dcbz_l128_kernel,
3893 &gen_op_dcbz_kernel,
3894 &gen_op_dcbz_kernel,
3900 static always_inline void handler_dcbz (DisasContext *ctx,
3901 int dcache_line_size)
3905 switch (dcache_line_size) {
3922 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
3924 gen_addr_reg_index(ctx);
3925 handler_dcbz(ctx, ctx->dcache_line_size);
3926 gen_op_check_reservation();
3929 GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
3931 gen_addr_reg_index(ctx);
3932 if (ctx->opcode & 0x00200000)
3933 handler_dcbz(ctx, ctx->dcache_line_size);
3935 handler_dcbz(ctx, -1);
3936 gen_op_check_reservation();
3940 #define op_icbi() (*gen_op_icbi[ctx->mem_idx])()
3941 #if defined(CONFIG_USER_ONLY)
3942 /* User-mode only */
3943 static GenOpFunc *gen_op_icbi[] = {
3946 #if defined(TARGET_PPC64)
3947 &gen_op_icbi_64_raw,
3948 &gen_op_icbi_64_raw,
3952 /* Full system - 64 bits mode */
3953 #if defined(TARGET_PPC64)
3954 static GenOpFunc *gen_op_icbi[] = {
3957 &gen_op_icbi_64_user,
3958 &gen_op_icbi_64_user,
3959 &gen_op_icbi_kernel,
3960 &gen_op_icbi_kernel,
3961 &gen_op_icbi_64_kernel,
3962 &gen_op_icbi_64_kernel,
3963 #if defined(TARGET_PPC64H)
3966 &gen_op_icbi_64_hypv,
3967 &gen_op_icbi_64_hypv,
3971 /* Full system - 32 bits mode */
3972 static GenOpFunc *gen_op_icbi[] = {
3975 &gen_op_icbi_kernel,
3976 &gen_op_icbi_kernel,
3981 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE)
3983 /* NIP cannot be restored if the memory exception comes from an helper */
3984 gen_update_nip(ctx, ctx->nip - 4);
3985 gen_addr_reg_index(ctx);
3991 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
3993 /* interpreted as no-op */
3994 /* XXX: specification say this is treated as a store by the MMU
3995 * but does not generate any exception
3999 /*** Segment register manipulation ***/
4000 /* Supervisor only: */
4002 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
4004 #if defined(CONFIG_USER_ONLY)
4005 GEN_EXCP_PRIVREG(ctx);
4007 if (unlikely(!ctx->supervisor)) {
4008 GEN_EXCP_PRIVREG(ctx);
4011 gen_op_set_T1(SR(ctx->opcode));
4013 gen_op_store_T0_gpr(rD(ctx->opcode));
4018 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
4020 #if defined(CONFIG_USER_ONLY)
4021 GEN_EXCP_PRIVREG(ctx);
4023 if (unlikely(!ctx->supervisor)) {
4024 GEN_EXCP_PRIVREG(ctx);
4027 gen_op_load_gpr_T1(rB(ctx->opcode));
4030 gen_op_store_T0_gpr(rD(ctx->opcode));
4035 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
4037 #if defined(CONFIG_USER_ONLY)
4038 GEN_EXCP_PRIVREG(ctx);
4040 if (unlikely(!ctx->supervisor)) {
4041 GEN_EXCP_PRIVREG(ctx);
4044 gen_op_load_gpr_T0(rS(ctx->opcode));
4045 gen_op_set_T1(SR(ctx->opcode));
4051 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
4053 #if defined(CONFIG_USER_ONLY)
4054 GEN_EXCP_PRIVREG(ctx);
4056 if (unlikely(!ctx->supervisor)) {
4057 GEN_EXCP_PRIVREG(ctx);
4060 gen_op_load_gpr_T0(rS(ctx->opcode));
4061 gen_op_load_gpr_T1(rB(ctx->opcode));
4067 #if defined(TARGET_PPC64)
4068 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4070 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
4072 #if defined(CONFIG_USER_ONLY)
4073 GEN_EXCP_PRIVREG(ctx);
4075 if (unlikely(!ctx->supervisor)) {
4076 GEN_EXCP_PRIVREG(ctx);
4079 gen_op_set_T1(SR(ctx->opcode));
4081 gen_op_store_T0_gpr(rD(ctx->opcode));
4086 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4089 #if defined(CONFIG_USER_ONLY)
4090 GEN_EXCP_PRIVREG(ctx);
4092 if (unlikely(!ctx->supervisor)) {
4093 GEN_EXCP_PRIVREG(ctx);
4096 gen_op_load_gpr_T1(rB(ctx->opcode));
4099 gen_op_store_T0_gpr(rD(ctx->opcode));
4104 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
4106 #if defined(CONFIG_USER_ONLY)
4107 GEN_EXCP_PRIVREG(ctx);
4109 if (unlikely(!ctx->supervisor)) {
4110 GEN_EXCP_PRIVREG(ctx);
4113 gen_op_load_gpr_T0(rS(ctx->opcode));
4114 gen_op_set_T1(SR(ctx->opcode));
4120 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4123 #if defined(CONFIG_USER_ONLY)
4124 GEN_EXCP_PRIVREG(ctx);
4126 if (unlikely(!ctx->supervisor)) {
4127 GEN_EXCP_PRIVREG(ctx);
4130 gen_op_load_gpr_T0(rS(ctx->opcode));
4131 gen_op_load_gpr_T1(rB(ctx->opcode));
4136 #endif /* defined(TARGET_PPC64) */
4138 /*** Lookaside buffer management ***/
4139 /* Optional & supervisor only: */
4141 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
4143 #if defined(CONFIG_USER_ONLY)
4144 GEN_EXCP_PRIVOPC(ctx);
4146 if (unlikely(!ctx->supervisor)) {
4148 fprintf(logfile, "%s: ! supervisor\n", __func__);
4149 GEN_EXCP_PRIVOPC(ctx);
4157 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
4159 #if defined(CONFIG_USER_ONLY)
4160 GEN_EXCP_PRIVOPC(ctx);
4162 if (unlikely(!ctx->supervisor)) {
4163 GEN_EXCP_PRIVOPC(ctx);
4166 gen_op_load_gpr_T0(rB(ctx->opcode));
4167 #if defined(TARGET_PPC64)
4177 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
4179 #if defined(CONFIG_USER_ONLY)
4180 GEN_EXCP_PRIVOPC(ctx);
4182 if (unlikely(!ctx->supervisor)) {
4183 GEN_EXCP_PRIVOPC(ctx);
4186 /* This has no effect: it should ensure that all previous
4187 * tlbie have completed
4193 #if defined(TARGET_PPC64)
4195 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4197 #if defined(CONFIG_USER_ONLY)
4198 GEN_EXCP_PRIVOPC(ctx);
4200 if (unlikely(!ctx->supervisor)) {
4202 fprintf(logfile, "%s: ! supervisor\n", __func__);
4203 GEN_EXCP_PRIVOPC(ctx);
4211 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4213 #if defined(CONFIG_USER_ONLY)
4214 GEN_EXCP_PRIVOPC(ctx);
4216 if (unlikely(!ctx->supervisor)) {
4217 GEN_EXCP_PRIVOPC(ctx);
4220 gen_op_load_gpr_T0(rB(ctx->opcode));
4226 /*** External control ***/
4228 #define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
4229 #define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
4230 #if defined(CONFIG_USER_ONLY)
4231 /* User-mode only */
4232 static GenOpFunc *gen_op_eciwx[] = {
4234 &gen_op_eciwx_le_raw,
4235 #if defined(TARGET_PPC64)
4236 &gen_op_eciwx_64_raw,
4237 &gen_op_eciwx_le_64_raw,
4240 static GenOpFunc *gen_op_ecowx[] = {
4242 &gen_op_ecowx_le_raw,
4243 #if defined(TARGET_PPC64)
4244 &gen_op_ecowx_64_raw,
4245 &gen_op_ecowx_le_64_raw,
4249 #if defined(TARGET_PPC64)
4250 /* Full system - 64 bits mode */
4251 static GenOpFunc *gen_op_eciwx[] = {
4253 &gen_op_eciwx_le_user,
4254 &gen_op_eciwx_64_user,
4255 &gen_op_eciwx_le_64_user,
4256 &gen_op_eciwx_kernel,
4257 &gen_op_eciwx_le_kernel,
4258 &gen_op_eciwx_64_kernel,
4259 &gen_op_eciwx_le_64_kernel,
4260 #if defined(TARGET_PPC64H)
4262 &gen_op_eciwx_le_hypv,
4263 &gen_op_eciwx_64_hypv,
4264 &gen_op_eciwx_le_64_hypv,
4267 static GenOpFunc *gen_op_ecowx[] = {
4269 &gen_op_ecowx_le_user,
4270 &gen_op_ecowx_64_user,
4271 &gen_op_ecowx_le_64_user,
4272 &gen_op_ecowx_kernel,
4273 &gen_op_ecowx_le_kernel,
4274 &gen_op_ecowx_64_kernel,
4275 &gen_op_ecowx_le_64_kernel,
4276 #if defined(TARGET_PPC64H)
4278 &gen_op_ecowx_le_hypv,
4279 &gen_op_ecowx_64_hypv,
4280 &gen_op_ecowx_le_64_hypv,
4284 /* Full system - 32 bits mode */
4285 static GenOpFunc *gen_op_eciwx[] = {
4287 &gen_op_eciwx_le_user,
4288 &gen_op_eciwx_kernel,
4289 &gen_op_eciwx_le_kernel,
4291 static GenOpFunc *gen_op_ecowx[] = {
4293 &gen_op_ecowx_le_user,
4294 &gen_op_ecowx_kernel,
4295 &gen_op_ecowx_le_kernel,
4301 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4303 /* Should check EAR[E] & alignment ! */
4304 gen_addr_reg_index(ctx);
4306 gen_op_store_T0_gpr(rD(ctx->opcode));
4310 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4312 /* Should check EAR[E] & alignment ! */
4313 gen_addr_reg_index(ctx);
4314 gen_op_load_gpr_T1(rS(ctx->opcode));
4318 /* PowerPC 601 specific instructions */
4320 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
4322 gen_op_load_gpr_T0(rA(ctx->opcode));
4324 gen_op_store_T0_gpr(rD(ctx->opcode));
4325 if (unlikely(Rc(ctx->opcode) != 0))
4330 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
4332 gen_op_load_gpr_T0(rA(ctx->opcode));
4333 gen_op_POWER_abso();
4334 gen_op_store_T0_gpr(rD(ctx->opcode));
4335 if (unlikely(Rc(ctx->opcode) != 0))
4340 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
4342 gen_op_load_gpr_T0(rA(ctx->opcode));
4343 gen_op_POWER_clcs();
4344 /* Rc=1 sets CR0 to an undefined state */
4345 gen_op_store_T0_gpr(rD(ctx->opcode));
4349 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
4351 gen_op_load_gpr_T0(rA(ctx->opcode));
4352 gen_op_load_gpr_T1(rB(ctx->opcode));
4354 gen_op_store_T0_gpr(rD(ctx->opcode));
4355 if (unlikely(Rc(ctx->opcode) != 0))
4360 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
4362 gen_op_load_gpr_T0(rA(ctx->opcode));
4363 gen_op_load_gpr_T1(rB(ctx->opcode));
4364 gen_op_POWER_divo();
4365 gen_op_store_T0_gpr(rD(ctx->opcode));
4366 if (unlikely(Rc(ctx->opcode) != 0))
4371 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
4373 gen_op_load_gpr_T0(rA(ctx->opcode));
4374 gen_op_load_gpr_T1(rB(ctx->opcode));
4375 gen_op_POWER_divs();
4376 gen_op_store_T0_gpr(rD(ctx->opcode));
4377 if (unlikely(Rc(ctx->opcode) != 0))
4381 /* divso - divso. */
4382 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
4384 gen_op_load_gpr_T0(rA(ctx->opcode));
4385 gen_op_load_gpr_T1(rB(ctx->opcode));
4386 gen_op_POWER_divso();
4387 gen_op_store_T0_gpr(rD(ctx->opcode));
4388 if (unlikely(Rc(ctx->opcode) != 0))
4393 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
4395 gen_op_load_gpr_T0(rA(ctx->opcode));
4396 gen_op_load_gpr_T1(rB(ctx->opcode));
4398 gen_op_store_T0_gpr(rD(ctx->opcode));
4399 if (unlikely(Rc(ctx->opcode) != 0))
4404 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
4406 gen_op_load_gpr_T0(rA(ctx->opcode));
4407 gen_op_load_gpr_T1(rB(ctx->opcode));
4408 gen_op_POWER_dozo();
4409 gen_op_store_T0_gpr(rD(ctx->opcode));
4410 if (unlikely(Rc(ctx->opcode) != 0))
4415 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4417 gen_op_load_gpr_T0(rA(ctx->opcode));
4418 gen_op_set_T1(SIMM(ctx->opcode));
4420 gen_op_store_T0_gpr(rD(ctx->opcode));
4423 /* As lscbx load from memory byte after byte, it's always endian safe */
4424 #define op_POWER_lscbx(start, ra, rb) \
4425 (*gen_op_POWER_lscbx[ctx->mem_idx])(start, ra, rb)
4426 #if defined(CONFIG_USER_ONLY)
4427 static GenOpFunc3 *gen_op_POWER_lscbx[] = {
4428 &gen_op_POWER_lscbx_raw,
4429 &gen_op_POWER_lscbx_raw,
4432 static GenOpFunc3 *gen_op_POWER_lscbx[] = {
4433 &gen_op_POWER_lscbx_user,
4434 &gen_op_POWER_lscbx_user,
4435 &gen_op_POWER_lscbx_kernel,
4436 &gen_op_POWER_lscbx_kernel,
4440 /* lscbx - lscbx. */
4441 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4443 int ra = rA(ctx->opcode);
4444 int rb = rB(ctx->opcode);
4446 gen_addr_reg_index(ctx);
4450 /* NIP cannot be restored if the memory exception comes from an helper */
4451 gen_update_nip(ctx, ctx->nip - 4);
4452 gen_op_load_xer_bc();
4453 gen_op_load_xer_cmp();
4454 op_POWER_lscbx(rD(ctx->opcode), ra, rb);
4455 gen_op_store_xer_bc();
4456 if (unlikely(Rc(ctx->opcode) != 0))
4460 /* maskg - maskg. */
4461 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4463 gen_op_load_gpr_T0(rS(ctx->opcode));
4464 gen_op_load_gpr_T1(rB(ctx->opcode));
4465 gen_op_POWER_maskg();
4466 gen_op_store_T0_gpr(rA(ctx->opcode));
4467 if (unlikely(Rc(ctx->opcode) != 0))
4471 /* maskir - maskir. */
4472 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4474 gen_op_load_gpr_T0(rA(ctx->opcode));
4475 gen_op_load_gpr_T1(rS(ctx->opcode));
4476 gen_op_load_gpr_T2(rB(ctx->opcode));
4477 gen_op_POWER_maskir();
4478 gen_op_store_T0_gpr(rA(ctx->opcode));
4479 if (unlikely(Rc(ctx->opcode) != 0))
4484 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4486 gen_op_load_gpr_T0(rA(ctx->opcode));
4487 gen_op_load_gpr_T1(rB(ctx->opcode));
4489 gen_op_store_T0_gpr(rD(ctx->opcode));
4490 if (unlikely(Rc(ctx->opcode) != 0))
4495 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4497 gen_op_load_gpr_T0(rA(ctx->opcode));
4498 gen_op_load_gpr_T1(rB(ctx->opcode));
4499 gen_op_POWER_mulo();
4500 gen_op_store_T0_gpr(rD(ctx->opcode));
4501 if (unlikely(Rc(ctx->opcode) != 0))
4506 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4508 gen_op_load_gpr_T0(rA(ctx->opcode));
4509 gen_op_POWER_nabs();
4510 gen_op_store_T0_gpr(rD(ctx->opcode));
4511 if (unlikely(Rc(ctx->opcode) != 0))
4515 /* nabso - nabso. */
4516 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4518 gen_op_load_gpr_T0(rA(ctx->opcode));
4519 gen_op_POWER_nabso();
4520 gen_op_store_T0_gpr(rD(ctx->opcode));
4521 if (unlikely(Rc(ctx->opcode) != 0))
4526 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4530 mb = MB(ctx->opcode);
4531 me = ME(ctx->opcode);
4532 gen_op_load_gpr_T0(rS(ctx->opcode));
4533 gen_op_load_gpr_T1(rA(ctx->opcode));
4534 gen_op_load_gpr_T2(rB(ctx->opcode));
4535 gen_op_POWER_rlmi(MASK(mb, me), ~MASK(mb, me));
4536 gen_op_store_T0_gpr(rA(ctx->opcode));
4537 if (unlikely(Rc(ctx->opcode) != 0))
4542 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4544 gen_op_load_gpr_T0(rS(ctx->opcode));
4545 gen_op_load_gpr_T1(rA(ctx->opcode));
4546 gen_op_load_gpr_T2(rB(ctx->opcode));
4547 gen_op_POWER_rrib();
4548 gen_op_store_T0_gpr(rA(ctx->opcode));
4549 if (unlikely(Rc(ctx->opcode) != 0))
4554 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4556 gen_op_load_gpr_T0(rS(ctx->opcode));
4557 gen_op_load_gpr_T1(rB(ctx->opcode));
4559 gen_op_store_T0_gpr(rA(ctx->opcode));
4560 if (unlikely(Rc(ctx->opcode) != 0))
4565 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4567 gen_op_load_gpr_T0(rS(ctx->opcode));
4568 gen_op_load_gpr_T1(rB(ctx->opcode));
4569 gen_op_POWER_sleq();
4570 gen_op_store_T0_gpr(rA(ctx->opcode));
4571 if (unlikely(Rc(ctx->opcode) != 0))
4576 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4578 gen_op_load_gpr_T0(rS(ctx->opcode));
4579 gen_op_set_T1(SH(ctx->opcode));
4581 gen_op_store_T0_gpr(rA(ctx->opcode));
4582 if (unlikely(Rc(ctx->opcode) != 0))
4586 /* slliq - slliq. */
4587 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4589 gen_op_load_gpr_T0(rS(ctx->opcode));
4590 gen_op_set_T1(SH(ctx->opcode));
4591 gen_op_POWER_sleq();
4592 gen_op_store_T0_gpr(rA(ctx->opcode));
4593 if (unlikely(Rc(ctx->opcode) != 0))
4598 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4600 gen_op_load_gpr_T0(rS(ctx->opcode));
4601 gen_op_load_gpr_T1(rB(ctx->opcode));
4602 gen_op_POWER_sllq();
4603 gen_op_store_T0_gpr(rA(ctx->opcode));
4604 if (unlikely(Rc(ctx->opcode) != 0))
4609 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4611 gen_op_load_gpr_T0(rS(ctx->opcode));
4612 gen_op_load_gpr_T1(rB(ctx->opcode));
4614 gen_op_store_T0_gpr(rA(ctx->opcode));
4615 if (unlikely(Rc(ctx->opcode) != 0))
4619 /* sraiq - sraiq. */
4620 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4622 gen_op_load_gpr_T0(rS(ctx->opcode));
4623 gen_op_set_T1(SH(ctx->opcode));
4624 gen_op_POWER_sraq();
4625 gen_op_store_T0_gpr(rA(ctx->opcode));
4626 if (unlikely(Rc(ctx->opcode) != 0))
4631 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4633 gen_op_load_gpr_T0(rS(ctx->opcode));
4634 gen_op_load_gpr_T1(rB(ctx->opcode));
4635 gen_op_POWER_sraq();
4636 gen_op_store_T0_gpr(rA(ctx->opcode));
4637 if (unlikely(Rc(ctx->opcode) != 0))
4642 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4644 gen_op_load_gpr_T0(rS(ctx->opcode));
4645 gen_op_load_gpr_T1(rB(ctx->opcode));
4647 gen_op_store_T0_gpr(rA(ctx->opcode));
4648 if (unlikely(Rc(ctx->opcode) != 0))
4653 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4655 gen_op_load_gpr_T0(rS(ctx->opcode));
4656 gen_op_load_gpr_T1(rB(ctx->opcode));
4657 gen_op_POWER_srea();
4658 gen_op_store_T0_gpr(rA(ctx->opcode));
4659 if (unlikely(Rc(ctx->opcode) != 0))
4664 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
4666 gen_op_load_gpr_T0(rS(ctx->opcode));
4667 gen_op_load_gpr_T1(rB(ctx->opcode));
4668 gen_op_POWER_sreq();
4669 gen_op_store_T0_gpr(rA(ctx->opcode));
4670 if (unlikely(Rc(ctx->opcode) != 0))
4675 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
4677 gen_op_load_gpr_T0(rS(ctx->opcode));
4678 gen_op_set_T1(SH(ctx->opcode));
4680 gen_op_store_T0_gpr(rA(ctx->opcode));
4681 if (unlikely(Rc(ctx->opcode) != 0))
4686 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
4688 gen_op_load_gpr_T0(rS(ctx->opcode));
4689 gen_op_load_gpr_T1(rB(ctx->opcode));
4690 gen_op_set_T1(SH(ctx->opcode));
4691 gen_op_POWER_srlq();
4692 gen_op_store_T0_gpr(rA(ctx->opcode));
4693 if (unlikely(Rc(ctx->opcode) != 0))
4698 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
4700 gen_op_load_gpr_T0(rS(ctx->opcode));
4701 gen_op_load_gpr_T1(rB(ctx->opcode));
4702 gen_op_POWER_srlq();
4703 gen_op_store_T0_gpr(rA(ctx->opcode));
4704 if (unlikely(Rc(ctx->opcode) != 0))
4709 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
4711 gen_op_load_gpr_T0(rS(ctx->opcode));
4712 gen_op_load_gpr_T1(rB(ctx->opcode));
4714 gen_op_store_T0_gpr(rA(ctx->opcode));
4715 if (unlikely(Rc(ctx->opcode) != 0))
4719 /* PowerPC 602 specific instructions */
4721 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
4724 GEN_EXCP_INVAL(ctx);
4728 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
4731 GEN_EXCP_INVAL(ctx);
4735 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
4737 #if defined(CONFIG_USER_ONLY)
4738 GEN_EXCP_PRIVOPC(ctx);
4740 if (unlikely(!ctx->supervisor)) {
4741 GEN_EXCP_PRIVOPC(ctx);
4744 gen_op_load_gpr_T0(rA(ctx->opcode));
4746 gen_op_store_T0_gpr(rD(ctx->opcode));
4750 /* 602 - 603 - G2 TLB management */
4752 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
4754 #if defined(CONFIG_USER_ONLY)
4755 GEN_EXCP_PRIVOPC(ctx);
4757 if (unlikely(!ctx->supervisor)) {
4758 GEN_EXCP_PRIVOPC(ctx);
4761 gen_op_load_gpr_T0(rB(ctx->opcode));
4767 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
4769 #if defined(CONFIG_USER_ONLY)
4770 GEN_EXCP_PRIVOPC(ctx);
4772 if (unlikely(!ctx->supervisor)) {
4773 GEN_EXCP_PRIVOPC(ctx);
4776 gen_op_load_gpr_T0(rB(ctx->opcode));
4781 /* 74xx TLB management */
4783 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
4785 #if defined(CONFIG_USER_ONLY)
4786 GEN_EXCP_PRIVOPC(ctx);
4788 if (unlikely(!ctx->supervisor)) {
4789 GEN_EXCP_PRIVOPC(ctx);
4792 gen_op_load_gpr_T0(rB(ctx->opcode));
4793 gen_op_74xx_tlbld();
4798 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
4800 #if defined(CONFIG_USER_ONLY)
4801 GEN_EXCP_PRIVOPC(ctx);
4803 if (unlikely(!ctx->supervisor)) {
4804 GEN_EXCP_PRIVOPC(ctx);
4807 gen_op_load_gpr_T0(rB(ctx->opcode));
4808 gen_op_74xx_tlbli();
4812 /* POWER instructions not in PowerPC 601 */
4814 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
4816 /* Cache line flush: implemented as no-op */
4820 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
4822 /* Cache line invalidate: privileged and treated as no-op */
4823 #if defined(CONFIG_USER_ONLY)
4824 GEN_EXCP_PRIVOPC(ctx);
4826 if (unlikely(!ctx->supervisor)) {
4827 GEN_EXCP_PRIVOPC(ctx);
4834 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
4836 /* Data cache line store: treated as no-op */
4839 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
4841 #if defined(CONFIG_USER_ONLY)
4842 GEN_EXCP_PRIVOPC(ctx);
4844 if (unlikely(!ctx->supervisor)) {
4845 GEN_EXCP_PRIVOPC(ctx);
4848 int ra = rA(ctx->opcode);
4849 int rd = rD(ctx->opcode);
4851 gen_addr_reg_index(ctx);
4852 gen_op_POWER_mfsri();
4853 gen_op_store_T0_gpr(rd);
4854 if (ra != 0 && ra != rd)
4855 gen_op_store_T1_gpr(ra);
4859 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
4861 #if defined(CONFIG_USER_ONLY)
4862 GEN_EXCP_PRIVOPC(ctx);
4864 if (unlikely(!ctx->supervisor)) {
4865 GEN_EXCP_PRIVOPC(ctx);
4868 gen_addr_reg_index(ctx);
4870 gen_op_store_T0_gpr(rD(ctx->opcode));
4874 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
4876 #if defined(CONFIG_USER_ONLY)
4877 GEN_EXCP_PRIVOPC(ctx);
4879 if (unlikely(!ctx->supervisor)) {
4880 GEN_EXCP_PRIVOPC(ctx);
4883 gen_op_POWER_rfsvc();
4888 /* svc is not implemented for now */
4890 /* POWER2 specific instructions */
4891 /* Quad manipulation (load/store two floats at a time) */
4892 #define op_POWER2_lfq() (*gen_op_POWER2_lfq[ctx->mem_idx])()
4893 #define op_POWER2_stfq() (*gen_op_POWER2_stfq[ctx->mem_idx])()
4894 #if defined(CONFIG_USER_ONLY)
4895 static GenOpFunc *gen_op_POWER2_lfq[] = {
4896 &gen_op_POWER2_lfq_le_raw,
4897 &gen_op_POWER2_lfq_raw,
4899 static GenOpFunc *gen_op_POWER2_stfq[] = {
4900 &gen_op_POWER2_stfq_le_raw,
4901 &gen_op_POWER2_stfq_raw,
4904 static GenOpFunc *gen_op_POWER2_lfq[] = {
4905 &gen_op_POWER2_lfq_le_user,
4906 &gen_op_POWER2_lfq_user,
4907 &gen_op_POWER2_lfq_le_kernel,
4908 &gen_op_POWER2_lfq_kernel,
4910 static GenOpFunc *gen_op_POWER2_stfq[] = {
4911 &gen_op_POWER2_stfq_le_user,
4912 &gen_op_POWER2_stfq_user,
4913 &gen_op_POWER2_stfq_le_kernel,
4914 &gen_op_POWER2_stfq_kernel,
4919 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4921 /* NIP cannot be restored if the memory exception comes from an helper */
4922 gen_update_nip(ctx, ctx->nip - 4);
4923 gen_addr_imm_index(ctx, 0);
4925 gen_op_store_FT0_fpr(rD(ctx->opcode));
4926 gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4930 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4932 int ra = rA(ctx->opcode);
4934 /* NIP cannot be restored if the memory exception comes from an helper */
4935 gen_update_nip(ctx, ctx->nip - 4);
4936 gen_addr_imm_index(ctx, 0);
4938 gen_op_store_FT0_fpr(rD(ctx->opcode));
4939 gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4941 gen_op_store_T0_gpr(ra);
4945 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
4947 int ra = rA(ctx->opcode);
4949 /* NIP cannot be restored if the memory exception comes from an helper */
4950 gen_update_nip(ctx, ctx->nip - 4);
4951 gen_addr_reg_index(ctx);
4953 gen_op_store_FT0_fpr(rD(ctx->opcode));
4954 gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4956 gen_op_store_T0_gpr(ra);
4960 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
4962 /* NIP cannot be restored if the memory exception comes from an helper */
4963 gen_update_nip(ctx, ctx->nip - 4);
4964 gen_addr_reg_index(ctx);
4966 gen_op_store_FT0_fpr(rD(ctx->opcode));
4967 gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4971 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4973 /* NIP cannot be restored if the memory exception comes from an helper */
4974 gen_update_nip(ctx, ctx->nip - 4);
4975 gen_addr_imm_index(ctx, 0);
4976 gen_op_load_fpr_FT0(rS(ctx->opcode));
4977 gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
4982 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4984 int ra = rA(ctx->opcode);
4986 /* NIP cannot be restored if the memory exception comes from an helper */
4987 gen_update_nip(ctx, ctx->nip - 4);
4988 gen_addr_imm_index(ctx, 0);
4989 gen_op_load_fpr_FT0(rS(ctx->opcode));
4990 gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
4993 gen_op_store_T0_gpr(ra);
4997 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
4999 int ra = rA(ctx->opcode);
5001 /* NIP cannot be restored if the memory exception comes from an helper */
5002 gen_update_nip(ctx, ctx->nip - 4);
5003 gen_addr_reg_index(ctx);
5004 gen_op_load_fpr_FT0(rS(ctx->opcode));
5005 gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
5008 gen_op_store_T0_gpr(ra);
5012 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
5014 /* NIP cannot be restored if the memory exception comes from an helper */
5015 gen_update_nip(ctx, ctx->nip - 4);
5016 gen_addr_reg_index(ctx);
5017 gen_op_load_fpr_FT0(rS(ctx->opcode));
5018 gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
5022 /* BookE specific instructions */
5023 /* XXX: not implemented on 440 ? */
5024 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_BOOKE_EXT)
5027 GEN_EXCP_INVAL(ctx);
5030 /* XXX: not implemented on 440 ? */
5031 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_BOOKE_EXT)
5033 #if defined(CONFIG_USER_ONLY)
5034 GEN_EXCP_PRIVOPC(ctx);
5036 if (unlikely(!ctx->supervisor)) {
5037 GEN_EXCP_PRIVOPC(ctx);
5040 gen_addr_reg_index(ctx);
5041 /* Use the same micro-ops as for tlbie */
5042 #if defined(TARGET_PPC64)
5051 /* All 405 MAC instructions are translated here */
5052 static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
5054 int ra, int rb, int rt, int Rc)
5056 gen_op_load_gpr_T0(ra);
5057 gen_op_load_gpr_T1(rb);
5058 switch (opc3 & 0x0D) {
5060 /* macchw - macchw. - macchwo - macchwo. */
5061 /* macchws - macchws. - macchwso - macchwso. */
5062 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5063 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5064 /* mulchw - mulchw. */
5065 gen_op_405_mulchw();
5068 /* macchwu - macchwu. - macchwuo - macchwuo. */
5069 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5070 /* mulchwu - mulchwu. */
5071 gen_op_405_mulchwu();
5074 /* machhw - machhw. - machhwo - machhwo. */
5075 /* machhws - machhws. - machhwso - machhwso. */
5076 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5077 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5078 /* mulhhw - mulhhw. */
5079 gen_op_405_mulhhw();
5082 /* machhwu - machhwu. - machhwuo - machhwuo. */
5083 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5084 /* mulhhwu - mulhhwu. */
5085 gen_op_405_mulhhwu();
5088 /* maclhw - maclhw. - maclhwo - maclhwo. */
5089 /* maclhws - maclhws. - maclhwso - maclhwso. */
5090 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5091 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5092 /* mullhw - mullhw. */
5093 gen_op_405_mullhw();
5096 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5097 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5098 /* mullhwu - mullhwu. */
5099 gen_op_405_mullhwu();
5103 /* nmultiply-and-accumulate (0x0E) */
5107 /* (n)multiply-and-accumulate (0x0C - 0x0E) */
5108 gen_op_load_gpr_T2(rt);
5109 gen_op_move_T1_T0();
5110 gen_op_405_add_T0_T2();
5113 /* Check overflow */
5115 gen_op_405_check_ov();
5117 gen_op_405_check_ovu();
5122 gen_op_405_check_sat();
5124 gen_op_405_check_satu();
5126 gen_op_store_T0_gpr(rt);
5127 if (unlikely(Rc) != 0) {
5133 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5134 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
5136 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5137 rD(ctx->opcode), Rc(ctx->opcode)); \
5140 /* macchw - macchw. */
5141 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5142 /* macchwo - macchwo. */
5143 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5144 /* macchws - macchws. */
5145 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5146 /* macchwso - macchwso. */
5147 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5148 /* macchwsu - macchwsu. */
5149 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5150 /* macchwsuo - macchwsuo. */
5151 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5152 /* macchwu - macchwu. */
5153 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5154 /* macchwuo - macchwuo. */
5155 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5156 /* machhw - machhw. */
5157 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5158 /* machhwo - machhwo. */
5159 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5160 /* machhws - machhws. */
5161 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5162 /* machhwso - machhwso. */
5163 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5164 /* machhwsu - machhwsu. */
5165 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5166 /* machhwsuo - machhwsuo. */
5167 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5168 /* machhwu - machhwu. */
5169 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5170 /* machhwuo - machhwuo. */
5171 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5172 /* maclhw - maclhw. */
5173 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5174 /* maclhwo - maclhwo. */
5175 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5176 /* maclhws - maclhws. */
5177 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5178 /* maclhwso - maclhwso. */
5179 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5180 /* maclhwu - maclhwu. */
5181 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5182 /* maclhwuo - maclhwuo. */
5183 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5184 /* maclhwsu - maclhwsu. */
5185 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5186 /* maclhwsuo - maclhwsuo. */
5187 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5188 /* nmacchw - nmacchw. */
5189 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5190 /* nmacchwo - nmacchwo. */
5191 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5192 /* nmacchws - nmacchws. */
5193 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5194 /* nmacchwso - nmacchwso. */
5195 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5196 /* nmachhw - nmachhw. */
5197 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5198 /* nmachhwo - nmachhwo. */
5199 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5200 /* nmachhws - nmachhws. */
5201 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5202 /* nmachhwso - nmachhwso. */
5203 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5204 /* nmaclhw - nmaclhw. */
5205 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5206 /* nmaclhwo - nmaclhwo. */
5207 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5208 /* nmaclhws - nmaclhws. */
5209 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5210 /* nmaclhwso - nmaclhwso. */
5211 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5213 /* mulchw - mulchw. */
5214 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5215 /* mulchwu - mulchwu. */
5216 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5217 /* mulhhw - mulhhw. */
5218 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5219 /* mulhhwu - mulhhwu. */
5220 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5221 /* mullhw - mullhw. */
5222 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5223 /* mullhwu - mullhwu. */
5224 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5227 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_EMB_COMMON)
5229 #if defined(CONFIG_USER_ONLY)
5230 GEN_EXCP_PRIVREG(ctx);
5232 uint32_t dcrn = SPR(ctx->opcode);
5234 if (unlikely(!ctx->supervisor)) {
5235 GEN_EXCP_PRIVREG(ctx);
5238 gen_op_set_T0(dcrn);
5240 gen_op_store_T0_gpr(rD(ctx->opcode));
5245 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_EMB_COMMON)
5247 #if defined(CONFIG_USER_ONLY)
5248 GEN_EXCP_PRIVREG(ctx);
5250 uint32_t dcrn = SPR(ctx->opcode);
5252 if (unlikely(!ctx->supervisor)) {
5253 GEN_EXCP_PRIVREG(ctx);
5256 gen_op_set_T0(dcrn);
5257 gen_op_load_gpr_T1(rS(ctx->opcode));
5263 /* XXX: not implemented on 440 ? */
5264 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_BOOKE_EXT)
5266 #if defined(CONFIG_USER_ONLY)
5267 GEN_EXCP_PRIVREG(ctx);
5269 if (unlikely(!ctx->supervisor)) {
5270 GEN_EXCP_PRIVREG(ctx);
5273 gen_op_load_gpr_T0(rA(ctx->opcode));
5275 gen_op_store_T0_gpr(rD(ctx->opcode));
5276 /* Note: Rc update flag set leads to undefined state of Rc0 */
5281 /* XXX: not implemented on 440 ? */
5282 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_BOOKE_EXT)
5284 #if defined(CONFIG_USER_ONLY)
5285 GEN_EXCP_PRIVREG(ctx);
5287 if (unlikely(!ctx->supervisor)) {
5288 GEN_EXCP_PRIVREG(ctx);
5291 gen_op_load_gpr_T0(rA(ctx->opcode));
5292 gen_op_load_gpr_T1(rS(ctx->opcode));
5294 /* Note: Rc update flag set leads to undefined state of Rc0 */
5298 /* mfdcrux (PPC 460) : user-mode access to DCR */
5299 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
5301 gen_op_load_gpr_T0(rA(ctx->opcode));
5303 gen_op_store_T0_gpr(rD(ctx->opcode));
5304 /* Note: Rc update flag set leads to undefined state of Rc0 */
5307 /* mtdcrux (PPC 460) : user-mode access to DCR */
5308 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
5310 gen_op_load_gpr_T0(rA(ctx->opcode));
5311 gen_op_load_gpr_T1(rS(ctx->opcode));
5313 /* Note: Rc update flag set leads to undefined state of Rc0 */
5317 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
5319 #if defined(CONFIG_USER_ONLY)
5320 GEN_EXCP_PRIVOPC(ctx);
5322 if (unlikely(!ctx->supervisor)) {
5323 GEN_EXCP_PRIVOPC(ctx);
5326 /* interpreted as no-op */
5331 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
5333 #if defined(CONFIG_USER_ONLY)
5334 GEN_EXCP_PRIVOPC(ctx);
5336 if (unlikely(!ctx->supervisor)) {
5337 GEN_EXCP_PRIVOPC(ctx);
5340 gen_addr_reg_index(ctx);
5342 gen_op_store_T0_gpr(rD(ctx->opcode));
5347 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
5349 /* interpreted as no-op */
5350 /* XXX: specification say this is treated as a load by the MMU
5351 * but does not generate any exception
5356 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
5358 #if defined(CONFIG_USER_ONLY)
5359 GEN_EXCP_PRIVOPC(ctx);
5361 if (unlikely(!ctx->supervisor)) {
5362 GEN_EXCP_PRIVOPC(ctx);
5365 /* interpreted as no-op */
5370 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
5372 #if defined(CONFIG_USER_ONLY)
5373 GEN_EXCP_PRIVOPC(ctx);
5375 if (unlikely(!ctx->supervisor)) {
5376 GEN_EXCP_PRIVOPC(ctx);
5379 /* interpreted as no-op */
5383 /* rfci (supervisor only) */
5384 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
5386 #if defined(CONFIG_USER_ONLY)
5387 GEN_EXCP_PRIVOPC(ctx);
5389 if (unlikely(!ctx->supervisor)) {
5390 GEN_EXCP_PRIVOPC(ctx);
5393 /* Restore CPU state */
5399 GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
5401 #if defined(CONFIG_USER_ONLY)
5402 GEN_EXCP_PRIVOPC(ctx);
5404 if (unlikely(!ctx->supervisor)) {
5405 GEN_EXCP_PRIVOPC(ctx);
5408 /* Restore CPU state */
5414 /* BookE specific */
5415 /* XXX: not implemented on 440 ? */
5416 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_BOOKE_EXT)
5418 #if defined(CONFIG_USER_ONLY)
5419 GEN_EXCP_PRIVOPC(ctx);
5421 if (unlikely(!ctx->supervisor)) {
5422 GEN_EXCP_PRIVOPC(ctx);
5425 /* Restore CPU state */
5431 /* XXX: not implemented on 440 ? */
5432 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
5434 #if defined(CONFIG_USER_ONLY)
5435 GEN_EXCP_PRIVOPC(ctx);
5437 if (unlikely(!ctx->supervisor)) {
5438 GEN_EXCP_PRIVOPC(ctx);
5441 /* Restore CPU state */
5447 /* TLB management - PowerPC 405 implementation */
5449 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
5451 #if defined(CONFIG_USER_ONLY)
5452 GEN_EXCP_PRIVOPC(ctx);
5454 if (unlikely(!ctx->supervisor)) {
5455 GEN_EXCP_PRIVOPC(ctx);
5458 switch (rB(ctx->opcode)) {
5460 gen_op_load_gpr_T0(rA(ctx->opcode));
5461 gen_op_4xx_tlbre_hi();
5462 gen_op_store_T0_gpr(rD(ctx->opcode));
5465 gen_op_load_gpr_T0(rA(ctx->opcode));
5466 gen_op_4xx_tlbre_lo();
5467 gen_op_store_T0_gpr(rD(ctx->opcode));
5470 GEN_EXCP_INVAL(ctx);
5476 /* tlbsx - tlbsx. */
5477 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
5479 #if defined(CONFIG_USER_ONLY)
5480 GEN_EXCP_PRIVOPC(ctx);
5482 if (unlikely(!ctx->supervisor)) {
5483 GEN_EXCP_PRIVOPC(ctx);
5486 gen_addr_reg_index(ctx);
5488 if (Rc(ctx->opcode))
5489 gen_op_4xx_tlbsx_check();
5490 gen_op_store_T0_gpr(rD(ctx->opcode));
5495 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
5497 #if defined(CONFIG_USER_ONLY)
5498 GEN_EXCP_PRIVOPC(ctx);
5500 if (unlikely(!ctx->supervisor)) {
5501 GEN_EXCP_PRIVOPC(ctx);
5504 switch (rB(ctx->opcode)) {
5506 gen_op_load_gpr_T0(rA(ctx->opcode));
5507 gen_op_load_gpr_T1(rS(ctx->opcode));
5508 gen_op_4xx_tlbwe_hi();
5511 gen_op_load_gpr_T0(rA(ctx->opcode));
5512 gen_op_load_gpr_T1(rS(ctx->opcode));
5513 gen_op_4xx_tlbwe_lo();
5516 GEN_EXCP_INVAL(ctx);
5522 /* TLB management - PowerPC 440 implementation */
5524 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5526 #if defined(CONFIG_USER_ONLY)
5527 GEN_EXCP_PRIVOPC(ctx);
5529 if (unlikely(!ctx->supervisor)) {
5530 GEN_EXCP_PRIVOPC(ctx);
5533 switch (rB(ctx->opcode)) {
5537 gen_op_load_gpr_T0(rA(ctx->opcode));
5538 gen_op_440_tlbre(rB(ctx->opcode));
5539 gen_op_store_T0_gpr(rD(ctx->opcode));
5542 GEN_EXCP_INVAL(ctx);
5548 /* tlbsx - tlbsx. */
5549 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5551 #if defined(CONFIG_USER_ONLY)
5552 GEN_EXCP_PRIVOPC(ctx);
5554 if (unlikely(!ctx->supervisor)) {
5555 GEN_EXCP_PRIVOPC(ctx);
5558 gen_addr_reg_index(ctx);
5560 if (Rc(ctx->opcode))
5561 gen_op_4xx_tlbsx_check();
5562 gen_op_store_T0_gpr(rD(ctx->opcode));
5567 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5569 #if defined(CONFIG_USER_ONLY)
5570 GEN_EXCP_PRIVOPC(ctx);
5572 if (unlikely(!ctx->supervisor)) {
5573 GEN_EXCP_PRIVOPC(ctx);
5576 switch (rB(ctx->opcode)) {
5580 gen_op_load_gpr_T0(rA(ctx->opcode));
5581 gen_op_load_gpr_T1(rS(ctx->opcode));
5582 gen_op_440_tlbwe(rB(ctx->opcode));
5585 GEN_EXCP_INVAL(ctx);
5592 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_EMB_COMMON)
5594 #if defined(CONFIG_USER_ONLY)
5595 GEN_EXCP_PRIVOPC(ctx);
5597 if (unlikely(!ctx->supervisor)) {
5598 GEN_EXCP_PRIVOPC(ctx);
5601 gen_op_load_gpr_T0(rD(ctx->opcode));
5603 /* Stop translation to have a chance to raise an exception
5604 * if we just set msr_ee to 1
5611 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_EMB_COMMON)
5613 #if defined(CONFIG_USER_ONLY)
5614 GEN_EXCP_PRIVOPC(ctx);
5616 if (unlikely(!ctx->supervisor)) {
5617 GEN_EXCP_PRIVOPC(ctx);
5620 gen_op_set_T0(ctx->opcode & 0x00010000);
5622 /* Stop translation to have a chance to raise an exception
5623 * if we just set msr_ee to 1
5629 /* PowerPC 440 specific instructions */
5631 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
5633 gen_op_load_gpr_T0(rS(ctx->opcode));
5634 gen_op_load_gpr_T1(rB(ctx->opcode));
5636 gen_op_store_T0_gpr(rA(ctx->opcode));
5637 gen_op_store_xer_bc();
5638 if (Rc(ctx->opcode)) {
5639 gen_op_440_dlmzb_update_Rc();
5640 gen_op_store_T0_crf(0);
5644 /* mbar replaces eieio on 440 */
5645 GEN_HANDLER(mbar, 0x1F, 0x16, 0x13, 0x001FF801, PPC_BOOKE)
5647 /* interpreted as no-op */
5650 /* msync replaces sync on 440 */
5651 GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
5653 /* interpreted as no-op */
5657 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
5659 /* interpreted as no-op */
5660 /* XXX: specification say this is treated as a load by the MMU
5661 * but does not generate any exception
5665 /*** Altivec vector extension ***/
5666 /* Altivec registers moves */
5667 GEN32(gen_op_load_avr_A0, gen_op_load_avr_A0_avr);
5668 GEN32(gen_op_load_avr_A1, gen_op_load_avr_A1_avr);
5669 GEN32(gen_op_load_avr_A2, gen_op_load_avr_A2_avr);
5671 GEN32(gen_op_store_A0_avr, gen_op_store_A0_avr_avr);
5672 GEN32(gen_op_store_A1_avr, gen_op_store_A1_avr_avr);
5674 GEN32(gen_op_store_A2_avr, gen_op_store_A2_avr_avr);
5677 #define op_vr_ldst(name) (*gen_op_##name[ctx->mem_idx])()
5678 #if defined(CONFIG_USER_ONLY)
5679 #if defined(TARGET_PPC64)
5680 /* User-mode only - 64 bits mode */
5681 #define OP_VR_LD_TABLE(name) \
5682 static GenOpFunc *gen_op_vr_l##name[] = { \
5683 &gen_op_vr_l##name##_raw, \
5684 &gen_op_vr_l##name##_le_raw, \
5685 &gen_op_vr_l##name##_64_raw, \
5686 &gen_op_vr_l##name##_le_64_raw, \
5688 #define OP_VR_ST_TABLE(name) \
5689 static GenOpFunc *gen_op_vr_st##name[] = { \
5690 &gen_op_vr_st##name##_raw, \
5691 &gen_op_vr_st##name##_le_raw, \
5692 &gen_op_vr_st##name##_64_raw, \
5693 &gen_op_vr_st##name##_le_64_raw, \
5695 #else /* defined(TARGET_PPC64) */
5696 /* User-mode only - 32 bits mode */
5697 #define OP_VR_LD_TABLE(name) \
5698 static GenOpFunc *gen_op_vr_l##name[] = { \
5699 &gen_op_vr_l##name##_raw, \
5700 &gen_op_vr_l##name##_le_raw, \
5702 #define OP_VR_ST_TABLE(name) \
5703 static GenOpFunc *gen_op_vr_st##name[] = { \
5704 &gen_op_vr_st##name##_raw, \
5705 &gen_op_vr_st##name##_le_raw, \
5707 #endif /* defined(TARGET_PPC64) */
5708 #else /* defined(CONFIG_USER_ONLY) */
5709 #if defined(TARGET_PPC64H)
5710 /* Full system with hypervisor mode */
5711 #define OP_VR_LD_TABLE(name) \
5712 static GenOpFunc *gen_op_vr_l##name[] = { \
5713 &gen_op_vr_l##name##_user, \
5714 &gen_op_vr_l##name##_le_user, \
5715 &gen_op_vr_l##name##_64_user, \
5716 &gen_op_vr_l##name##_le_64_user, \
5717 &gen_op_vr_l##name##_kernel, \
5718 &gen_op_vr_l##name##_le_kernel, \
5719 &gen_op_vr_l##name##_64_kernel, \
5720 &gen_op_vr_l##name##_le_64_kernel, \
5721 &gen_op_vr_l##name##_hypv, \
5722 &gen_op_vr_l##name##_le_hypv, \
5723 &gen_op_vr_l##name##_64_hypv, \
5724 &gen_op_vr_l##name##_le_64_hypv, \
5726 #define OP_VR_ST_TABLE(name) \
5727 static GenOpFunc *gen_op_vr_st##name[] = { \
5728 &gen_op_vr_st##name##_user, \
5729 &gen_op_vr_st##name##_le_user, \
5730 &gen_op_vr_st##name##_64_user, \
5731 &gen_op_vr_st##name##_le_64_user, \
5732 &gen_op_vr_st##name##_kernel, \
5733 &gen_op_vr_st##name##_le_kernel, \
5734 &gen_op_vr_st##name##_64_kernel, \
5735 &gen_op_vr_st##name##_le_64_kernel, \
5736 &gen_op_vr_st##name##_hypv, \
5737 &gen_op_vr_st##name##_le_hypv, \
5738 &gen_op_vr_st##name##_64_hypv, \
5739 &gen_op_vr_st##name##_le_64_hypv, \
5741 #elif defined(TARGET_PPC64)
5742 /* Full system - 64 bits mode */
5743 #define OP_VR_LD_TABLE(name) \
5744 static GenOpFunc *gen_op_vr_l##name[] = { \
5745 &gen_op_vr_l##name##_user, \
5746 &gen_op_vr_l##name##_le_user, \
5747 &gen_op_vr_l##name##_64_user, \
5748 &gen_op_vr_l##name##_le_64_user, \
5749 &gen_op_vr_l##name##_kernel, \
5750 &gen_op_vr_l##name##_le_kernel, \
5751 &gen_op_vr_l##name##_64_kernel, \
5752 &gen_op_vr_l##name##_le_64_kernel, \
5754 #define OP_VR_ST_TABLE(name) \
5755 static GenOpFunc *gen_op_vr_st##name[] = { \
5756 &gen_op_vr_st##name##_user, \
5757 &gen_op_vr_st##name##_le_user, \
5758 &gen_op_vr_st##name##_64_user, \
5759 &gen_op_vr_st##name##_le_64_user, \
5760 &gen_op_vr_st##name##_kernel, \
5761 &gen_op_vr_st##name##_le_kernel, \
5762 &gen_op_vr_st##name##_64_kernel, \
5763 &gen_op_vr_st##name##_le_64_kernel, \
5765 #else /* defined(TARGET_PPC64) */
5766 /* Full system - 32 bits mode */
5767 #define OP_VR_LD_TABLE(name) \
5768 static GenOpFunc *gen_op_vr_l##name[] = { \
5769 &gen_op_vr_l##name##_user, \
5770 &gen_op_vr_l##name##_le_user, \
5771 &gen_op_vr_l##name##_kernel, \
5772 &gen_op_vr_l##name##_le_kernel, \
5774 #define OP_VR_ST_TABLE(name) \
5775 static GenOpFunc *gen_op_vr_st##name[] = { \
5776 &gen_op_vr_st##name##_user, \
5777 &gen_op_vr_st##name##_le_user, \
5778 &gen_op_vr_st##name##_kernel, \
5779 &gen_op_vr_st##name##_le_kernel, \
5781 #endif /* defined(TARGET_PPC64) */
5782 #endif /* defined(CONFIG_USER_ONLY) */
5784 #define GEN_VR_LDX(name, opc2, opc3) \
5785 GEN_HANDLER(l##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5787 if (unlikely(!ctx->altivec_enabled)) { \
5788 GEN_EXCP_NO_VR(ctx); \
5791 gen_addr_reg_index(ctx); \
5792 op_vr_ldst(vr_l##name); \
5793 gen_op_store_A0_avr(rD(ctx->opcode)); \
5796 #define GEN_VR_STX(name, opc2, opc3) \
5797 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5799 if (unlikely(!ctx->altivec_enabled)) { \
5800 GEN_EXCP_NO_VR(ctx); \
5803 gen_addr_reg_index(ctx); \
5804 gen_op_load_avr_A0(rS(ctx->opcode)); \
5805 op_vr_ldst(vr_st##name); \
5809 GEN_VR_LDX(vx, 0x07, 0x03);
5810 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
5811 #define gen_op_vr_lvxl gen_op_vr_lvx
5812 GEN_VR_LDX(vxl, 0x07, 0x0B);
5815 GEN_VR_STX(vx, 0x07, 0x07);
5816 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
5817 #define gen_op_vr_stvxl gen_op_vr_stvx
5818 GEN_VR_STX(vxl, 0x07, 0x0F);
5820 #if defined(TARGET_PPCEMB)
5821 /*** SPE extension ***/
5823 /* Register moves */
5824 GEN32(gen_op_load_gpr64_T0, gen_op_load_gpr64_T0_gpr);
5825 GEN32(gen_op_load_gpr64_T1, gen_op_load_gpr64_T1_gpr);
5827 GEN32(gen_op_load_gpr64_T2, gen_op_load_gpr64_T2_gpr);
5830 GEN32(gen_op_store_T0_gpr64, gen_op_store_T0_gpr64_gpr);
5831 GEN32(gen_op_store_T1_gpr64, gen_op_store_T1_gpr64_gpr);
5833 GEN32(gen_op_store_T2_gpr64, gen_op_store_T2_gpr64_gpr);
5836 #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
5837 GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
5839 if (Rc(ctx->opcode)) \
5845 /* Handler for undefined SPE opcodes */
5846 static always_inline void gen_speundef (DisasContext *ctx)
5848 GEN_EXCP_INVAL(ctx);
5851 /* SPE load and stores */
5852 static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, int sh)
5854 target_long simm = rB(ctx->opcode);
5856 if (rA(ctx->opcode) == 0) {
5857 gen_set_T0(simm << sh);
5859 gen_op_load_gpr_T0(rA(ctx->opcode));
5860 if (likely(simm != 0))
5861 gen_op_addi(simm << sh);
5865 #define op_spe_ldst(name) (*gen_op_##name[ctx->mem_idx])()
5866 #if defined(CONFIG_USER_ONLY)
5867 #if defined(TARGET_PPC64)
5868 /* User-mode only - 64 bits mode */
5869 #define OP_SPE_LD_TABLE(name) \
5870 static GenOpFunc *gen_op_spe_l##name[] = { \
5871 &gen_op_spe_l##name##_raw, \
5872 &gen_op_spe_l##name##_le_raw, \
5873 &gen_op_spe_l##name##_64_raw, \
5874 &gen_op_spe_l##name##_le_64_raw, \
5876 #define OP_SPE_ST_TABLE(name) \
5877 static GenOpFunc *gen_op_spe_st##name[] = { \
5878 &gen_op_spe_st##name##_raw, \
5879 &gen_op_spe_st##name##_le_raw, \
5880 &gen_op_spe_st##name##_64_raw, \
5881 &gen_op_spe_st##name##_le_64_raw, \
5883 #else /* defined(TARGET_PPC64) */
5884 /* User-mode only - 32 bits mode */
5885 #define OP_SPE_LD_TABLE(name) \
5886 static GenOpFunc *gen_op_spe_l##name[] = { \
5887 &gen_op_spe_l##name##_raw, \
5888 &gen_op_spe_l##name##_le_raw, \
5890 #define OP_SPE_ST_TABLE(name) \
5891 static GenOpFunc *gen_op_spe_st##name[] = { \
5892 &gen_op_spe_st##name##_raw, \
5893 &gen_op_spe_st##name##_le_raw, \
5895 #endif /* defined(TARGET_PPC64) */
5896 #else /* defined(CONFIG_USER_ONLY) */
5897 #if defined(TARGET_PPC64H)
5898 /* Full system with hypervisor mode */
5899 #define OP_SPE_LD_TABLE(name) \
5900 static GenOpFunc *gen_op_spe_l##name[] = { \
5901 &gen_op_spe_l##name##_user, \
5902 &gen_op_spe_l##name##_le_user, \
5903 &gen_op_spe_l##name##_64_user, \
5904 &gen_op_spe_l##name##_le_64_user, \
5905 &gen_op_spe_l##name##_kernel, \
5906 &gen_op_spe_l##name##_le_kernel, \
5907 &gen_op_spe_l##name##_64_kernel, \
5908 &gen_op_spe_l##name##_le_64_kernel, \
5909 &gen_op_spe_l##name##_hypv, \
5910 &gen_op_spe_l##name##_le_hypv, \
5911 &gen_op_spe_l##name##_64_hypv, \
5912 &gen_op_spe_l##name##_le_64_hypv, \
5914 #define OP_SPE_ST_TABLE(name) \
5915 static GenOpFunc *gen_op_spe_st##name[] = { \
5916 &gen_op_spe_st##name##_user, \
5917 &gen_op_spe_st##name##_le_user, \
5918 &gen_op_spe_st##name##_64_user, \
5919 &gen_op_spe_st##name##_le_64_user, \
5920 &gen_op_spe_st##name##_kernel, \
5921 &gen_op_spe_st##name##_le_kernel, \
5922 &gen_op_spe_st##name##_64_kernel, \
5923 &gen_op_spe_st##name##_le_64_kernel, \
5924 &gen_op_spe_st##name##_hypv, \
5925 &gen_op_spe_st##name##_le_hypv, \
5926 &gen_op_spe_st##name##_64_hypv, \
5927 &gen_op_spe_st##name##_le_64_hypv, \
5929 #elif defined(TARGET_PPC64)
5930 /* Full system - 64 bits mode */
5931 #define OP_SPE_LD_TABLE(name) \
5932 static GenOpFunc *gen_op_spe_l##name[] = { \
5933 &gen_op_spe_l##name##_user, \
5934 &gen_op_spe_l##name##_le_user, \
5935 &gen_op_spe_l##name##_64_user, \
5936 &gen_op_spe_l##name##_le_64_user, \
5937 &gen_op_spe_l##name##_kernel, \
5938 &gen_op_spe_l##name##_le_kernel, \
5939 &gen_op_spe_l##name##_64_kernel, \
5940 &gen_op_spe_l##name##_le_64_kernel, \
5942 #define OP_SPE_ST_TABLE(name) \
5943 static GenOpFunc *gen_op_spe_st##name[] = { \
5944 &gen_op_spe_st##name##_user, \
5945 &gen_op_spe_st##name##_le_user, \
5946 &gen_op_spe_st##name##_64_user, \
5947 &gen_op_spe_st##name##_le_64_user, \
5948 &gen_op_spe_st##name##_kernel, \
5949 &gen_op_spe_st##name##_le_kernel, \
5950 &gen_op_spe_st##name##_64_kernel, \
5951 &gen_op_spe_st##name##_le_64_kernel, \
5953 #else /* defined(TARGET_PPC64) */
5954 /* Full system - 32 bits mode */
5955 #define OP_SPE_LD_TABLE(name) \
5956 static GenOpFunc *gen_op_spe_l##name[] = { \
5957 &gen_op_spe_l##name##_user, \
5958 &gen_op_spe_l##name##_le_user, \
5959 &gen_op_spe_l##name##_kernel, \
5960 &gen_op_spe_l##name##_le_kernel, \
5962 #define OP_SPE_ST_TABLE(name) \
5963 static GenOpFunc *gen_op_spe_st##name[] = { \
5964 &gen_op_spe_st##name##_user, \
5965 &gen_op_spe_st##name##_le_user, \
5966 &gen_op_spe_st##name##_kernel, \
5967 &gen_op_spe_st##name##_le_kernel, \
5969 #endif /* defined(TARGET_PPC64) */
5970 #endif /* defined(CONFIG_USER_ONLY) */
5972 #define GEN_SPE_LD(name, sh) \
5973 static always_inline void gen_evl##name (DisasContext *ctx) \
5975 if (unlikely(!ctx->spe_enabled)) { \
5976 GEN_EXCP_NO_AP(ctx); \
5979 gen_addr_spe_imm_index(ctx, sh); \
5980 op_spe_ldst(spe_l##name); \
5981 gen_op_store_T1_gpr64(rD(ctx->opcode)); \
5984 #define GEN_SPE_LDX(name) \
5985 static always_inline void gen_evl##name##x (DisasContext *ctx) \
5987 if (unlikely(!ctx->spe_enabled)) { \
5988 GEN_EXCP_NO_AP(ctx); \
5991 gen_addr_reg_index(ctx); \
5992 op_spe_ldst(spe_l##name); \
5993 gen_op_store_T1_gpr64(rD(ctx->opcode)); \
5996 #define GEN_SPEOP_LD(name, sh) \
5997 OP_SPE_LD_TABLE(name); \
5998 GEN_SPE_LD(name, sh); \
6001 #define GEN_SPE_ST(name, sh) \
6002 static always_inline void gen_evst##name (DisasContext *ctx) \
6004 if (unlikely(!ctx->spe_enabled)) { \
6005 GEN_EXCP_NO_AP(ctx); \
6008 gen_addr_spe_imm_index(ctx, sh); \
6009 gen_op_load_gpr64_T1(rS(ctx->opcode)); \
6010 op_spe_ldst(spe_st##name); \
6013 #define GEN_SPE_STX(name) \
6014 static always_inline void gen_evst##name##x (DisasContext *ctx) \
6016 if (unlikely(!ctx->spe_enabled)) { \
6017 GEN_EXCP_NO_AP(ctx); \
6020 gen_addr_reg_index(ctx); \
6021 gen_op_load_gpr64_T1(rS(ctx->opcode)); \
6022 op_spe_ldst(spe_st##name); \
6025 #define GEN_SPEOP_ST(name, sh) \
6026 OP_SPE_ST_TABLE(name); \
6027 GEN_SPE_ST(name, sh); \
6030 #define GEN_SPEOP_LDST(name, sh) \
6031 GEN_SPEOP_LD(name, sh); \
6032 GEN_SPEOP_ST(name, sh)
6034 /* SPE arithmetic and logic */
6035 #define GEN_SPEOP_ARITH2(name) \
6036 static always_inline void gen_##name (DisasContext *ctx) \
6038 if (unlikely(!ctx->spe_enabled)) { \
6039 GEN_EXCP_NO_AP(ctx); \
6042 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
6043 gen_op_load_gpr64_T1(rB(ctx->opcode)); \
6045 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
6048 #define GEN_SPEOP_ARITH1(name) \
6049 static always_inline void gen_##name (DisasContext *ctx) \
6051 if (unlikely(!ctx->spe_enabled)) { \
6052 GEN_EXCP_NO_AP(ctx); \
6055 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
6057 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
6060 #define GEN_SPEOP_COMP(name) \
6061 static always_inline void gen_##name (DisasContext *ctx) \
6063 if (unlikely(!ctx->spe_enabled)) { \
6064 GEN_EXCP_NO_AP(ctx); \
6067 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
6068 gen_op_load_gpr64_T1(rB(ctx->opcode)); \
6070 gen_op_store_T0_crf(crfD(ctx->opcode)); \
6074 GEN_SPEOP_ARITH2(evand);
6075 GEN_SPEOP_ARITH2(evandc);
6076 GEN_SPEOP_ARITH2(evxor);
6077 GEN_SPEOP_ARITH2(evor);
6078 GEN_SPEOP_ARITH2(evnor);
6079 GEN_SPEOP_ARITH2(eveqv);
6080 GEN_SPEOP_ARITH2(evorc);
6081 GEN_SPEOP_ARITH2(evnand);
6082 GEN_SPEOP_ARITH2(evsrwu);
6083 GEN_SPEOP_ARITH2(evsrws);
6084 GEN_SPEOP_ARITH2(evslw);
6085 GEN_SPEOP_ARITH2(evrlw);
6086 GEN_SPEOP_ARITH2(evmergehi);
6087 GEN_SPEOP_ARITH2(evmergelo);
6088 GEN_SPEOP_ARITH2(evmergehilo);
6089 GEN_SPEOP_ARITH2(evmergelohi);
6092 GEN_SPEOP_ARITH2(evaddw);
6093 GEN_SPEOP_ARITH2(evsubfw);
6094 GEN_SPEOP_ARITH1(evabs);
6095 GEN_SPEOP_ARITH1(evneg);
6096 GEN_SPEOP_ARITH1(evextsb);
6097 GEN_SPEOP_ARITH1(evextsh);
6098 GEN_SPEOP_ARITH1(evrndw);
6099 GEN_SPEOP_ARITH1(evcntlzw);
6100 GEN_SPEOP_ARITH1(evcntlsw);
6101 static always_inline void gen_brinc (DisasContext *ctx)
6103 /* Note: brinc is usable even if SPE is disabled */
6104 gen_op_load_gpr64_T0(rA(ctx->opcode));
6105 gen_op_load_gpr64_T1(rB(ctx->opcode));
6107 gen_op_store_T0_gpr64(rD(ctx->opcode));
6110 #define GEN_SPEOP_ARITH_IMM2(name) \
6111 static always_inline void gen_##name##i (DisasContext *ctx) \
6113 if (unlikely(!ctx->spe_enabled)) { \
6114 GEN_EXCP_NO_AP(ctx); \
6117 gen_op_load_gpr64_T0(rB(ctx->opcode)); \
6118 gen_op_splatwi_T1_64(rA(ctx->opcode)); \
6120 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
6123 #define GEN_SPEOP_LOGIC_IMM2(name) \
6124 static always_inline void gen_##name##i (DisasContext *ctx) \
6126 if (unlikely(!ctx->spe_enabled)) { \
6127 GEN_EXCP_NO_AP(ctx); \
6130 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
6131 gen_op_splatwi_T1_64(rB(ctx->opcode)); \
6133 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
6136 GEN_SPEOP_ARITH_IMM2(evaddw);
6137 #define gen_evaddiw gen_evaddwi
6138 GEN_SPEOP_ARITH_IMM2(evsubfw);
6139 #define gen_evsubifw gen_evsubfwi
6140 GEN_SPEOP_LOGIC_IMM2(evslw);
6141 GEN_SPEOP_LOGIC_IMM2(evsrwu);
6142 #define gen_evsrwis gen_evsrwsi
6143 GEN_SPEOP_LOGIC_IMM2(evsrws);
6144 #define gen_evsrwiu gen_evsrwui
6145 GEN_SPEOP_LOGIC_IMM2(evrlw);
6147 static always_inline void gen_evsplati (DisasContext *ctx)
6149 int32_t imm = (int32_t)(rA(ctx->opcode) << 27) >> 27;
6151 gen_op_splatwi_T0_64(imm);
6152 gen_op_store_T0_gpr64(rD(ctx->opcode));
6155 static always_inline void gen_evsplatfi (DisasContext *ctx)
6157 uint32_t imm = rA(ctx->opcode) << 27;
6159 gen_op_splatwi_T0_64(imm);
6160 gen_op_store_T0_gpr64(rD(ctx->opcode));
6164 GEN_SPEOP_COMP(evcmpgtu);
6165 GEN_SPEOP_COMP(evcmpgts);
6166 GEN_SPEOP_COMP(evcmpltu);
6167 GEN_SPEOP_COMP(evcmplts);
6168 GEN_SPEOP_COMP(evcmpeq);
6170 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
6171 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
6172 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
6173 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
6174 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
6175 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
6176 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
6177 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
6178 GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
6179 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
6180 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
6181 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
6182 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
6183 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
6184 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
6185 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
6186 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
6187 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
6188 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
6189 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
6190 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
6191 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
6192 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
6193 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
6194 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
6196 static always_inline void gen_evsel (DisasContext *ctx)
6198 if (unlikely(!ctx->spe_enabled)) {
6199 GEN_EXCP_NO_AP(ctx);
6202 gen_op_load_crf_T0(ctx->opcode & 0x7);
6203 gen_op_load_gpr64_T0(rA(ctx->opcode));
6204 gen_op_load_gpr64_T1(rB(ctx->opcode));
6206 gen_op_store_T0_gpr64(rD(ctx->opcode));
6209 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
6213 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
6217 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
6221 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
6226 /* Load and stores */
6227 #if defined(TARGET_PPC64)
6228 /* In that case, we already have 64 bits load & stores
6229 * so, spe_ldd is equivalent to ld and spe_std is equivalent to std
6231 #if defined(CONFIG_USER_ONLY)
6232 #define gen_op_spe_ldd_raw gen_op_ld_raw
6233 #define gen_op_spe_ldd_64_raw gen_op_ld_64_raw
6234 #define gen_op_spe_ldd_le_raw gen_op_ld_le_raw
6235 #define gen_op_spe_ldd_le_64_raw gen_op_ld_le_64_raw
6236 #define gen_op_spe_stdd_raw gen_op_ld_raw
6237 #define gen_op_spe_stdd_64_raw gen_op_std_64_raw
6238 #define gen_op_spe_stdd_le_raw gen_op_std_le_raw
6239 #define gen_op_spe_stdd_le_64_raw gen_op_std_le_64_raw
6240 #else /* defined(CONFIG_USER_ONLY) */
6241 #define gen_op_spe_ldd_kernel gen_op_ld_kernel
6242 #define gen_op_spe_ldd_64_kernel gen_op_ld_64_kernel
6243 #define gen_op_spe_ldd_le_kernel gen_op_ld_kernel
6244 #define gen_op_spe_ldd_le_64_kernel gen_op_ld_64_kernel
6245 #define gen_op_spe_ldd_user gen_op_ld_user
6246 #define gen_op_spe_ldd_64_user gen_op_ld_64_user
6247 #define gen_op_spe_ldd_le_user gen_op_ld_le_user
6248 #define gen_op_spe_ldd_le_64_user gen_op_ld_le_64_user
6249 #define gen_op_spe_stdd_kernel gen_op_std_kernel
6250 #define gen_op_spe_stdd_64_kernel gen_op_std_64_kernel
6251 #define gen_op_spe_stdd_le_kernel gen_op_std_kernel
6252 #define gen_op_spe_stdd_le_64_kernel gen_op_std_64_kernel
6253 #define gen_op_spe_stdd_user gen_op_std_user
6254 #define gen_op_spe_stdd_64_user gen_op_std_64_user
6255 #define gen_op_spe_stdd_le_user gen_op_std_le_user
6256 #define gen_op_spe_stdd_le_64_user gen_op_std_le_64_user
6257 #endif /* defined(CONFIG_USER_ONLY) */
6258 #endif /* defined(TARGET_PPC64) */
6259 GEN_SPEOP_LDST(dd, 3);
6260 GEN_SPEOP_LDST(dw, 3);
6261 GEN_SPEOP_LDST(dh, 3);
6262 GEN_SPEOP_LDST(whe, 2);
6263 GEN_SPEOP_LD(whou, 2);
6264 GEN_SPEOP_LD(whos, 2);
6265 GEN_SPEOP_ST(who, 2);
6267 #if defined(TARGET_PPC64)
6268 /* In that case, spe_stwwo is equivalent to stw */
6269 #if defined(CONFIG_USER_ONLY)
6270 #define gen_op_spe_stwwo_raw gen_op_stw_raw
6271 #define gen_op_spe_stwwo_le_raw gen_op_stw_le_raw
6272 #define gen_op_spe_stwwo_64_raw gen_op_stw_64_raw
6273 #define gen_op_spe_stwwo_le_64_raw gen_op_stw_le_64_raw
6275 #define gen_op_spe_stwwo_user gen_op_stw_user
6276 #define gen_op_spe_stwwo_le_user gen_op_stw_le_user
6277 #define gen_op_spe_stwwo_64_user gen_op_stw_64_user
6278 #define gen_op_spe_stwwo_le_64_user gen_op_stw_le_64_user
6279 #define gen_op_spe_stwwo_kernel gen_op_stw_kernel
6280 #define gen_op_spe_stwwo_le_kernel gen_op_stw_le_kernel
6281 #define gen_op_spe_stwwo_64_kernel gen_op_stw_64_kernel
6282 #define gen_op_spe_stwwo_le_64_kernel gen_op_stw_le_64_kernel
6285 #define _GEN_OP_SPE_STWWE(suffix) \
6286 static always_inline void gen_op_spe_stwwe_##suffix (void) \
6288 gen_op_srli32_T1_64(); \
6289 gen_op_spe_stwwo_##suffix(); \
6291 #define _GEN_OP_SPE_STWWE_LE(suffix) \
6292 static always_inline void gen_op_spe_stwwe_le_##suffix (void) \
6294 gen_op_srli32_T1_64(); \
6295 gen_op_spe_stwwo_le_##suffix(); \
6297 #if defined(TARGET_PPC64)
6298 #define GEN_OP_SPE_STWWE(suffix) \
6299 _GEN_OP_SPE_STWWE(suffix); \
6300 _GEN_OP_SPE_STWWE_LE(suffix); \
6301 static always_inline void gen_op_spe_stwwe_64_##suffix (void) \
6303 gen_op_srli32_T1_64(); \
6304 gen_op_spe_stwwo_64_##suffix(); \
6306 static always_inline void gen_op_spe_stwwe_le_64_##suffix (void) \
6308 gen_op_srli32_T1_64(); \
6309 gen_op_spe_stwwo_le_64_##suffix(); \
6312 #define GEN_OP_SPE_STWWE(suffix) \
6313 _GEN_OP_SPE_STWWE(suffix); \
6314 _GEN_OP_SPE_STWWE_LE(suffix)
6316 #if defined(CONFIG_USER_ONLY)
6317 GEN_OP_SPE_STWWE(raw);
6318 #else /* defined(CONFIG_USER_ONLY) */
6319 GEN_OP_SPE_STWWE(kernel);
6320 GEN_OP_SPE_STWWE(user);
6321 #endif /* defined(CONFIG_USER_ONLY) */
6322 GEN_SPEOP_ST(wwe, 2);
6323 GEN_SPEOP_ST(wwo, 2);
6325 #define GEN_SPE_LDSPLAT(name, op, suffix) \
6326 static always_inline void gen_op_spe_l##name##_##suffix (void) \
6328 gen_op_##op##_##suffix(); \
6329 gen_op_splatw_T1_64(); \
6332 #define GEN_OP_SPE_LHE(suffix) \
6333 static always_inline void gen_op_spe_lhe_##suffix (void) \
6335 gen_op_spe_lh_##suffix(); \
6336 gen_op_sli16_T1_64(); \
6339 #define GEN_OP_SPE_LHX(suffix) \
6340 static always_inline void gen_op_spe_lhx_##suffix (void) \
6342 gen_op_spe_lh_##suffix(); \
6343 gen_op_extsh_T1_64(); \
6346 #if defined(CONFIG_USER_ONLY)
6347 GEN_OP_SPE_LHE(raw);
6348 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, raw);
6349 GEN_OP_SPE_LHE(le_raw);
6350 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_raw);
6351 GEN_SPE_LDSPLAT(hhousplat, spe_lh, raw);
6352 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_raw);
6353 GEN_OP_SPE_LHX(raw);
6354 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, raw);
6355 GEN_OP_SPE_LHX(le_raw);
6356 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_raw);
6357 #if defined(TARGET_PPC64)
6358 GEN_OP_SPE_LHE(64_raw);
6359 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_raw);
6360 GEN_OP_SPE_LHE(le_64_raw);
6361 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_raw);
6362 GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_raw);
6363 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_raw);
6364 GEN_OP_SPE_LHX(64_raw);
6365 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_raw);
6366 GEN_OP_SPE_LHX(le_64_raw);
6367 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_raw);
6370 GEN_OP_SPE_LHE(kernel);
6371 GEN_OP_SPE_LHE(user);
6372 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, kernel);
6373 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, user);
6374 GEN_OP_SPE_LHE(le_kernel);
6375 GEN_OP_SPE_LHE(le_user);
6376 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_kernel);
6377 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_user);
6378 GEN_SPE_LDSPLAT(hhousplat, spe_lh, kernel);
6379 GEN_SPE_LDSPLAT(hhousplat, spe_lh, user);
6380 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_kernel);
6381 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_user);
6382 GEN_OP_SPE_LHX(kernel);
6383 GEN_OP_SPE_LHX(user);
6384 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, kernel);
6385 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, user);
6386 GEN_OP_SPE_LHX(le_kernel);
6387 GEN_OP_SPE_LHX(le_user);
6388 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_kernel);
6389 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_user);
6390 #if defined(TARGET_PPC64)
6391 GEN_OP_SPE_LHE(64_kernel);
6392 GEN_OP_SPE_LHE(64_user);
6393 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_kernel);
6394 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_user);
6395 GEN_OP_SPE_LHE(le_64_kernel);
6396 GEN_OP_SPE_LHE(le_64_user);
6397 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_kernel);
6398 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_user);
6399 GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_kernel);
6400 GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_user);
6401 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_kernel);
6402 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_user);
6403 GEN_OP_SPE_LHX(64_kernel);
6404 GEN_OP_SPE_LHX(64_user);
6405 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_kernel);
6406 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_user);
6407 GEN_OP_SPE_LHX(le_64_kernel);
6408 GEN_OP_SPE_LHX(le_64_user);
6409 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_kernel);
6410 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_user);
6413 GEN_SPEOP_LD(hhesplat, 1);
6414 GEN_SPEOP_LD(hhousplat, 1);
6415 GEN_SPEOP_LD(hhossplat, 1);
6416 GEN_SPEOP_LD(wwsplat, 2);
6417 GEN_SPEOP_LD(whsplat, 2);
6419 GEN_SPE(evlddx, evldd, 0x00, 0x0C, 0x00000000, PPC_SPE); //
6420 GEN_SPE(evldwx, evldw, 0x01, 0x0C, 0x00000000, PPC_SPE); //
6421 GEN_SPE(evldhx, evldh, 0x02, 0x0C, 0x00000000, PPC_SPE); //
6422 GEN_SPE(evlhhesplatx, evlhhesplat, 0x04, 0x0C, 0x00000000, PPC_SPE); //
6423 GEN_SPE(evlhhousplatx, evlhhousplat, 0x06, 0x0C, 0x00000000, PPC_SPE); //
6424 GEN_SPE(evlhhossplatx, evlhhossplat, 0x07, 0x0C, 0x00000000, PPC_SPE); //
6425 GEN_SPE(evlwhex, evlwhe, 0x08, 0x0C, 0x00000000, PPC_SPE); //
6426 GEN_SPE(evlwhoux, evlwhou, 0x0A, 0x0C, 0x00000000, PPC_SPE); //
6427 GEN_SPE(evlwhosx, evlwhos, 0x0B, 0x0C, 0x00000000, PPC_SPE); //
6428 GEN_SPE(evlwwsplatx, evlwwsplat, 0x0C, 0x0C, 0x00000000, PPC_SPE); //
6429 GEN_SPE(evlwhsplatx, evlwhsplat, 0x0E, 0x0C, 0x00000000, PPC_SPE); //
6430 GEN_SPE(evstddx, evstdd, 0x10, 0x0C, 0x00000000, PPC_SPE); //
6431 GEN_SPE(evstdwx, evstdw, 0x11, 0x0C, 0x00000000, PPC_SPE); //
6432 GEN_SPE(evstdhx, evstdh, 0x12, 0x0C, 0x00000000, PPC_SPE); //
6433 GEN_SPE(evstwhex, evstwhe, 0x18, 0x0C, 0x00000000, PPC_SPE); //
6434 GEN_SPE(evstwhox, evstwho, 0x1A, 0x0C, 0x00000000, PPC_SPE); //
6435 GEN_SPE(evstwwex, evstwwe, 0x1C, 0x0C, 0x00000000, PPC_SPE); //
6436 GEN_SPE(evstwwox, evstwwo, 0x1E, 0x0C, 0x00000000, PPC_SPE); //
6438 /* Multiply and add - TODO */
6440 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
6441 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
6442 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
6443 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
6444 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
6445 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
6446 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
6447 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
6448 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
6449 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
6450 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
6451 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
6453 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
6454 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
6455 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
6456 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
6457 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
6458 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
6459 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
6460 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
6461 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
6462 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
6463 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
6464 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
6465 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
6466 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
6468 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
6469 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
6470 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
6471 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
6472 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
6473 GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
6475 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
6476 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
6477 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
6478 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
6479 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
6480 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
6481 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
6482 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
6483 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
6484 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
6485 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
6486 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
6488 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
6489 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
6490 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
6491 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
6492 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
6494 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
6495 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
6496 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
6497 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
6498 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
6499 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
6500 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
6501 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
6502 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
6503 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
6504 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
6505 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
6507 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
6508 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
6509 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
6510 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
6511 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
6514 /*** SPE floating-point extension ***/
6515 #define GEN_SPEFPUOP_CONV(name) \
6516 static always_inline void gen_##name (DisasContext *ctx) \
6518 gen_op_load_gpr64_T0(rB(ctx->opcode)); \
6520 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
6523 /* Single precision floating-point vectors operations */
6525 GEN_SPEOP_ARITH2(evfsadd);
6526 GEN_SPEOP_ARITH2(evfssub);
6527 GEN_SPEOP_ARITH2(evfsmul);
6528 GEN_SPEOP_ARITH2(evfsdiv);
6529 GEN_SPEOP_ARITH1(evfsabs);
6530 GEN_SPEOP_ARITH1(evfsnabs);
6531 GEN_SPEOP_ARITH1(evfsneg);
6533 GEN_SPEFPUOP_CONV(evfscfui);
6534 GEN_SPEFPUOP_CONV(evfscfsi);
6535 GEN_SPEFPUOP_CONV(evfscfuf);
6536 GEN_SPEFPUOP_CONV(evfscfsf);
6537 GEN_SPEFPUOP_CONV(evfsctui);
6538 GEN_SPEFPUOP_CONV(evfsctsi);
6539 GEN_SPEFPUOP_CONV(evfsctuf);
6540 GEN_SPEFPUOP_CONV(evfsctsf);
6541 GEN_SPEFPUOP_CONV(evfsctuiz);
6542 GEN_SPEFPUOP_CONV(evfsctsiz);
6544 GEN_SPEOP_COMP(evfscmpgt);
6545 GEN_SPEOP_COMP(evfscmplt);
6546 GEN_SPEOP_COMP(evfscmpeq);
6547 GEN_SPEOP_COMP(evfststgt);
6548 GEN_SPEOP_COMP(evfststlt);
6549 GEN_SPEOP_COMP(evfststeq);
6551 /* Opcodes definitions */
6552 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
6553 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPEFPU); //
6554 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPEFPU); //
6555 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPEFPU); //
6556 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPEFPU); //
6557 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPEFPU); //
6558 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPEFPU); //
6559 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPEFPU); //
6560 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPEFPU); //
6561 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPEFPU); //
6562 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPEFPU); //
6563 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPEFPU); //
6564 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPEFPU); //
6565 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPEFPU); //
6567 /* Single precision floating-point operations */
6569 GEN_SPEOP_ARITH2(efsadd);
6570 GEN_SPEOP_ARITH2(efssub);
6571 GEN_SPEOP_ARITH2(efsmul);
6572 GEN_SPEOP_ARITH2(efsdiv);
6573 GEN_SPEOP_ARITH1(efsabs);
6574 GEN_SPEOP_ARITH1(efsnabs);
6575 GEN_SPEOP_ARITH1(efsneg);
6577 GEN_SPEFPUOP_CONV(efscfui);
6578 GEN_SPEFPUOP_CONV(efscfsi);
6579 GEN_SPEFPUOP_CONV(efscfuf);
6580 GEN_SPEFPUOP_CONV(efscfsf);
6581 GEN_SPEFPUOP_CONV(efsctui);
6582 GEN_SPEFPUOP_CONV(efsctsi);
6583 GEN_SPEFPUOP_CONV(efsctuf);
6584 GEN_SPEFPUOP_CONV(efsctsf);
6585 GEN_SPEFPUOP_CONV(efsctuiz);
6586 GEN_SPEFPUOP_CONV(efsctsiz);
6587 GEN_SPEFPUOP_CONV(efscfd);
6589 GEN_SPEOP_COMP(efscmpgt);
6590 GEN_SPEOP_COMP(efscmplt);
6591 GEN_SPEOP_COMP(efscmpeq);
6592 GEN_SPEOP_COMP(efststgt);
6593 GEN_SPEOP_COMP(efststlt);
6594 GEN_SPEOP_COMP(efststeq);
6596 /* Opcodes definitions */
6597 GEN_SPE(efsadd, efssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
6598 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU); //
6599 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU); //
6600 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPEFPU); //
6601 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPEFPU); //
6602 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPEFPU); //
6603 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPEFPU); //
6604 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPEFPU); //
6605 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPEFPU); //
6606 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPEFPU); //
6607 GEN_SPE(efsctuiz, efsctsiz, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU); //
6608 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPEFPU); //
6609 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPEFPU); //
6611 /* Double precision floating-point operations */
6613 GEN_SPEOP_ARITH2(efdadd);
6614 GEN_SPEOP_ARITH2(efdsub);
6615 GEN_SPEOP_ARITH2(efdmul);
6616 GEN_SPEOP_ARITH2(efddiv);
6617 GEN_SPEOP_ARITH1(efdabs);
6618 GEN_SPEOP_ARITH1(efdnabs);
6619 GEN_SPEOP_ARITH1(efdneg);
6622 GEN_SPEFPUOP_CONV(efdcfui);
6623 GEN_SPEFPUOP_CONV(efdcfsi);
6624 GEN_SPEFPUOP_CONV(efdcfuf);
6625 GEN_SPEFPUOP_CONV(efdcfsf);
6626 GEN_SPEFPUOP_CONV(efdctui);
6627 GEN_SPEFPUOP_CONV(efdctsi);
6628 GEN_SPEFPUOP_CONV(efdctuf);
6629 GEN_SPEFPUOP_CONV(efdctsf);
6630 GEN_SPEFPUOP_CONV(efdctuiz);
6631 GEN_SPEFPUOP_CONV(efdctsiz);
6632 GEN_SPEFPUOP_CONV(efdcfs);
6633 GEN_SPEFPUOP_CONV(efdcfuid);
6634 GEN_SPEFPUOP_CONV(efdcfsid);
6635 GEN_SPEFPUOP_CONV(efdctuidz);
6636 GEN_SPEFPUOP_CONV(efdctsidz);
6638 GEN_SPEOP_COMP(efdcmpgt);
6639 GEN_SPEOP_COMP(efdcmplt);
6640 GEN_SPEOP_COMP(efdcmpeq);
6641 GEN_SPEOP_COMP(efdtstgt);
6642 GEN_SPEOP_COMP(efdtstlt);
6643 GEN_SPEOP_COMP(efdtsteq);
6645 /* Opcodes definitions */
6646 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPEFPU); //
6647 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPEFPU); //
6648 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPEFPU); //
6649 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPEFPU); //
6650 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPEFPU); //
6651 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPEFPU); //
6652 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPEFPU); //
6653 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPEFPU); //
6654 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPEFPU); //
6655 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPEFPU); //
6656 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPEFPU); //
6657 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPEFPU); //
6658 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPEFPU); //
6659 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU); //
6660 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU); //
6661 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU); //
6664 /* End opcode list */
6665 GEN_OPCODE_MARK(end);
6667 #include "translate_init.c"
6668 #include "helper_regs.h"
6670 /*****************************************************************************/
6671 /* Misc PowerPC helpers */
6672 void cpu_dump_state (CPUState *env, FILE *f,
6673 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
6676 #if defined(TARGET_PPC64) || 1
6688 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " idx %d\n",
6689 env->nip, env->lr, env->ctr, env->mmu_idx);
6690 cpu_fprintf(f, "MSR " REGX FILL " XER %08x "
6691 #if !defined(NO_TIMER_DUMP)
6693 #if !defined(CONFIG_USER_ONLY)
6698 env->msr, hreg_load_xer(env)
6699 #if !defined(NO_TIMER_DUMP)
6700 , cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
6701 #if !defined(CONFIG_USER_ONLY)
6702 , cpu_ppc_load_decr(env)
6706 for (i = 0; i < 32; i++) {
6707 if ((i & (RGPL - 1)) == 0)
6708 cpu_fprintf(f, "GPR%02d", i);
6709 cpu_fprintf(f, " " REGX, (target_ulong)env->gpr[i]);
6710 if ((i & (RGPL - 1)) == (RGPL - 1))
6711 cpu_fprintf(f, "\n");
6713 cpu_fprintf(f, "CR ");
6714 for (i = 0; i < 8; i++)
6715 cpu_fprintf(f, "%01x", env->crf[i]);
6716 cpu_fprintf(f, " [");
6717 for (i = 0; i < 8; i++) {
6719 if (env->crf[i] & 0x08)
6721 else if (env->crf[i] & 0x04)
6723 else if (env->crf[i] & 0x02)
6725 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
6727 cpu_fprintf(f, " ] " FILL "RES " REGX "\n", env->reserve);
6728 for (i = 0; i < 32; i++) {
6729 if ((i & (RFPL - 1)) == 0)
6730 cpu_fprintf(f, "FPR%02d", i);
6731 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
6732 if ((i & (RFPL - 1)) == (RFPL - 1))
6733 cpu_fprintf(f, "\n");
6735 #if !defined(CONFIG_USER_ONLY)
6736 cpu_fprintf(f, "SRR0 " REGX " SRR1 " REGX " " FILL FILL FILL
6738 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
6746 void cpu_dump_statistics (CPUState *env, FILE*f,
6747 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
6750 #if defined(DO_PPC_STATISTICS)
6751 opc_handler_t **t1, **t2, **t3, *handler;
6755 for (op1 = 0; op1 < 64; op1++) {
6757 if (is_indirect_opcode(handler)) {
6758 t2 = ind_table(handler);
6759 for (op2 = 0; op2 < 32; op2++) {
6761 if (is_indirect_opcode(handler)) {
6762 t3 = ind_table(handler);
6763 for (op3 = 0; op3 < 32; op3++) {
6765 if (handler->count == 0)
6767 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
6769 op1, op2, op3, op1, (op3 << 5) | op2,
6771 handler->count, handler->count);
6774 if (handler->count == 0)
6776 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
6778 op1, op2, op1, op2, handler->oname,
6779 handler->count, handler->count);
6783 if (handler->count == 0)
6785 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
6786 op1, op1, handler->oname,
6787 handler->count, handler->count);
6793 /*****************************************************************************/
6794 static always_inline int gen_intermediate_code_internal (CPUState *env,
6795 TranslationBlock *tb,
6798 DisasContext ctx, *ctxp = &ctx;
6799 opc_handler_t **table, *handler;
6800 target_ulong pc_start;
6801 uint16_t *gen_opc_end;
6803 int single_step, branch_step;
6807 gen_opc_ptr = gen_opc_buf;
6808 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
6809 gen_opparam_ptr = gen_opparam_buf;
6810 #if defined(OPTIMIZE_FPRF_UPDATE)
6811 gen_fprf_ptr = gen_fprf_buf;
6816 ctx.exception = POWERPC_EXCP_NONE;
6817 ctx.spr_cb = env->spr_cb;
6818 supervisor = env->mmu_idx;
6819 #if !defined(CONFIG_USER_ONLY)
6820 ctx.supervisor = supervisor;
6822 #if defined(TARGET_PPC64)
6823 ctx.sf_mode = msr_sf;
6824 ctx.mem_idx = (supervisor << 2) | (msr_sf << 1) | msr_le;
6826 ctx.mem_idx = (supervisor << 1) | msr_le;
6828 ctx.dcache_line_size = env->dcache_line_size;
6829 ctx.fpu_enabled = msr_fp;
6830 #if defined(TARGET_PPCEMB)
6831 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
6832 ctx.spe_enabled = msr_spe;
6834 ctx.spe_enabled = 0;
6836 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
6837 ctx.altivec_enabled = msr_vr;
6839 ctx.altivec_enabled = 0;
6840 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
6844 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
6848 ctx.singlestep_enabled = env->singlestep_enabled || single_step == 1;
6849 #if defined (DO_SINGLE_STEP) && 0
6850 /* Single step trace mode */
6853 /* Set env in case of segfault during code fetch */
6854 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
6855 if (unlikely(env->nb_breakpoints > 0)) {
6856 for (j = 0; j < env->nb_breakpoints; j++) {
6857 if (env->breakpoints[j] == ctx.nip) {
6858 gen_update_nip(&ctx, ctx.nip);
6864 if (unlikely(search_pc)) {
6865 j = gen_opc_ptr - gen_opc_buf;
6869 gen_opc_instr_start[lj++] = 0;
6870 gen_opc_pc[lj] = ctx.nip;
6871 gen_opc_instr_start[lj] = 1;
6874 #if defined PPC_DEBUG_DISAS
6875 if (loglevel & CPU_LOG_TB_IN_ASM) {
6876 fprintf(logfile, "----------------\n");
6877 fprintf(logfile, "nip=" ADDRX " super=%d ir=%d\n",
6878 ctx.nip, supervisor, (int)msr_ir);
6881 ctx.opcode = ldl_code(ctx.nip);
6883 ctx.opcode = ((ctx.opcode & 0xFF000000) >> 24) |
6884 ((ctx.opcode & 0x00FF0000) >> 8) |
6885 ((ctx.opcode & 0x0000FF00) << 8) |
6886 ((ctx.opcode & 0x000000FF) << 24);
6888 #if defined PPC_DEBUG_DISAS
6889 if (loglevel & CPU_LOG_TB_IN_ASM) {
6890 fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n",
6891 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
6892 opc3(ctx.opcode), msr_le ? "little" : "big");
6896 table = env->opcodes;
6897 handler = table[opc1(ctx.opcode)];
6898 if (is_indirect_opcode(handler)) {
6899 table = ind_table(handler);
6900 handler = table[opc2(ctx.opcode)];
6901 if (is_indirect_opcode(handler)) {
6902 table = ind_table(handler);
6903 handler = table[opc3(ctx.opcode)];
6906 /* Is opcode *REALLY* valid ? */
6907 if (unlikely(handler->handler == &gen_invalid)) {
6908 if (loglevel != 0) {
6909 fprintf(logfile, "invalid/unsupported opcode: "
6910 "%02x - %02x - %02x (%08x) 0x" ADDRX " %d\n",
6911 opc1(ctx.opcode), opc2(ctx.opcode),
6912 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
6914 printf("invalid/unsupported opcode: "
6915 "%02x - %02x - %02x (%08x) 0x" ADDRX " %d\n",
6916 opc1(ctx.opcode), opc2(ctx.opcode),
6917 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
6920 if (unlikely((ctx.opcode & handler->inval) != 0)) {
6921 if (loglevel != 0) {
6922 fprintf(logfile, "invalid bits: %08x for opcode: "
6923 "%02x - %02x - %02x (%08x) 0x" ADDRX "\n",
6924 ctx.opcode & handler->inval, opc1(ctx.opcode),
6925 opc2(ctx.opcode), opc3(ctx.opcode),
6926 ctx.opcode, ctx.nip - 4);
6928 printf("invalid bits: %08x for opcode: "
6929 "%02x - %02x - %02x (%08x) 0x" ADDRX "\n",
6930 ctx.opcode & handler->inval, opc1(ctx.opcode),
6931 opc2(ctx.opcode), opc3(ctx.opcode),
6932 ctx.opcode, ctx.nip - 4);
6934 GEN_EXCP_INVAL(ctxp);
6938 (*(handler->handler))(&ctx);
6939 #if defined(DO_PPC_STATISTICS)
6942 /* Check trace mode exceptions */
6943 if (unlikely(branch_step != 0 &&
6944 ctx.exception == POWERPC_EXCP_BRANCH)) {
6945 GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0);
6946 } else if (unlikely(single_step != 0 &&
6947 (ctx.nip <= 0x100 || ctx.nip > 0xF00 ||
6948 (ctx.nip & 0xFC) != 0x04) &&
6949 ctx.exception != POWERPC_SYSCALL &&
6950 ctx.exception != POWERPC_EXCP_TRAP)) {
6951 GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0);
6952 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
6953 (env->singlestep_enabled))) {
6954 /* if we reach a page boundary or are single stepping, stop
6959 #if defined (DO_SINGLE_STEP)
6963 if (ctx.exception == POWERPC_EXCP_NONE) {
6964 gen_goto_tb(&ctx, 0, ctx.nip);
6965 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
6967 /* Generate the return instruction */
6970 *gen_opc_ptr = INDEX_op_end;
6971 if (unlikely(search_pc)) {
6972 j = gen_opc_ptr - gen_opc_buf;
6975 gen_opc_instr_start[lj++] = 0;
6977 tb->size = ctx.nip - pc_start;
6979 #if defined(DEBUG_DISAS)
6980 if (loglevel & CPU_LOG_TB_CPU) {
6981 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
6982 cpu_dump_state(env, logfile, fprintf, 0);
6984 if (loglevel & CPU_LOG_TB_IN_ASM) {
6986 flags = env->bfd_mach;
6987 flags |= msr_le << 16;
6988 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
6989 target_disas(logfile, pc_start, ctx.nip - pc_start, flags);
6990 fprintf(logfile, "\n");
6992 if (loglevel & CPU_LOG_TB_OP) {
6993 fprintf(logfile, "OP:\n");
6994 dump_ops(gen_opc_buf, gen_opparam_buf);
6995 fprintf(logfile, "\n");
7001 int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
7003 return gen_intermediate_code_internal(env, tb, 0);
7006 int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
7008 return gen_intermediate_code_internal(env, tb, 1);