2 * PowerPC emulation for qemu: main translation routines.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30 /* Include definitions for instructions classes and implementations flags */
31 //#define DO_SINGLE_STEP
32 //#define PPC_DEBUG_DISAS
33 //#define DEBUG_MEMORY_ACCESSES
34 //#define DO_PPC_STATISTICS
36 /*****************************************************************************/
37 /* Code translation helpers */
38 #if defined(USE_DIRECT_JUMP)
41 #define TBPARAM(x) (long)(x)
45 #define DEF(s, n, copy_size) INDEX_op_ ## s,
51 static uint16_t *gen_opc_ptr;
52 static uint32_t *gen_opparam_ptr;
56 static always_inline void gen_set_T0 (target_ulong val)
58 #if defined(TARGET_PPC64)
60 gen_op_set_T0_64(val >> 32, val);
66 static always_inline void gen_set_T1 (target_ulong val)
68 #if defined(TARGET_PPC64)
70 gen_op_set_T1_64(val >> 32, val);
76 #define GEN8(func, NAME) \
77 static GenOpFunc *NAME ## _table [8] = { \
78 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
79 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
81 static always_inline void func (int n) \
83 NAME ## _table[n](); \
86 #define GEN16(func, NAME) \
87 static GenOpFunc *NAME ## _table [16] = { \
88 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
89 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
90 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
91 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
93 static always_inline void func (int n) \
95 NAME ## _table[n](); \
98 #define GEN32(func, NAME) \
99 static GenOpFunc *NAME ## _table [32] = { \
100 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
101 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
102 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
103 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
104 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
105 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
106 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
107 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
109 static always_inline void func (int n) \
111 NAME ## _table[n](); \
114 /* Condition register moves */
115 GEN8(gen_op_load_crf_T0, gen_op_load_crf_T0_crf);
116 GEN8(gen_op_load_crf_T1, gen_op_load_crf_T1_crf);
117 GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf);
118 GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf);
120 /* Floating point condition and status register moves */
121 GEN8(gen_op_load_fpscr_T0, gen_op_load_fpscr_T0_fpscr);
122 GEN8(gen_op_store_T0_fpscr, gen_op_store_T0_fpscr_fpscr);
123 GEN8(gen_op_clear_fpscr, gen_op_clear_fpscr_fpscr);
124 static always_inline void gen_op_store_T0_fpscri (int n, uint8_t param)
126 gen_op_set_T0(param);
127 gen_op_store_T0_fpscr(n);
130 /* General purpose registers moves */
131 GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);
132 GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);
133 GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);
135 GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
136 GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
138 GEN32(gen_op_store_T2_gpr, gen_op_store_T2_gpr_gpr);
141 /* floating point registers moves */
142 GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr);
143 GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr);
144 GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fpr);
145 GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fpr);
146 GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fpr);
148 GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fpr);
151 /* internal defines */
152 typedef struct DisasContext {
153 struct TranslationBlock *tb;
157 /* Routine used to access memory */
159 /* Translation flags */
160 #if !defined(CONFIG_USER_ONLY)
163 #if defined(TARGET_PPC64)
167 #if defined(TARGET_PPCEMB)
170 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
171 int singlestep_enabled;
172 int dcache_line_size;
175 struct opc_handler_t {
178 /* instruction type */
181 void (*handler)(DisasContext *ctx);
182 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
183 const unsigned char *oname;
185 #if defined(DO_PPC_STATISTICS)
190 static always_inline void gen_set_Rc0 (DisasContext *ctx)
192 #if defined(TARGET_PPC64)
201 static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
203 #if defined(TARGET_PPC64)
205 gen_op_update_nip_64(nip >> 32, nip);
208 gen_op_update_nip(nip);
211 #define GEN_EXCP(ctx, excp, error) \
213 if ((ctx)->exception == POWERPC_EXCP_NONE) { \
214 gen_update_nip(ctx, (ctx)->nip); \
216 gen_op_raise_exception_err((excp), (error)); \
217 ctx->exception = (excp); \
220 #define GEN_EXCP_INVAL(ctx) \
221 GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
222 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL)
224 #define GEN_EXCP_PRIVOPC(ctx) \
225 GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
226 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC)
228 #define GEN_EXCP_PRIVREG(ctx) \
229 GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
230 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG)
232 #define GEN_EXCP_NO_FP(ctx) \
233 GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0)
235 #define GEN_EXCP_NO_AP(ctx) \
236 GEN_EXCP(ctx, POWERPC_EXCP_APU, 0)
238 /* Stop translation */
239 static always_inline void GEN_STOP (DisasContext *ctx)
241 gen_update_nip(ctx, ctx->nip);
242 ctx->exception = POWERPC_EXCP_STOP;
245 /* No need to update nip here, as execution flow will change */
246 static always_inline void GEN_SYNC (DisasContext *ctx)
248 ctx->exception = POWERPC_EXCP_SYNC;
251 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
252 static void gen_##name (DisasContext *ctx); \
253 GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
254 static void gen_##name (DisasContext *ctx)
256 typedef struct opcode_t {
257 unsigned char opc1, opc2, opc3;
258 #if HOST_LONG_BITS == 64 /* Explicitely align to 64 bits */
259 unsigned char pad[5];
261 unsigned char pad[1];
263 opc_handler_t handler;
264 const unsigned char *oname;
267 /*****************************************************************************/
268 /*** Instruction decoding ***/
269 #define EXTRACT_HELPER(name, shift, nb) \
270 static always_inline uint32_t name (uint32_t opcode) \
272 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
275 #define EXTRACT_SHELPER(name, shift, nb) \
276 static always_inline int32_t name (uint32_t opcode) \
278 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
282 EXTRACT_HELPER(opc1, 26, 6);
284 EXTRACT_HELPER(opc2, 1, 5);
286 EXTRACT_HELPER(opc3, 6, 5);
287 /* Update Cr0 flags */
288 EXTRACT_HELPER(Rc, 0, 1);
290 EXTRACT_HELPER(rD, 21, 5);
292 EXTRACT_HELPER(rS, 21, 5);
294 EXTRACT_HELPER(rA, 16, 5);
296 EXTRACT_HELPER(rB, 11, 5);
298 EXTRACT_HELPER(rC, 6, 5);
300 EXTRACT_HELPER(crfD, 23, 3);
301 EXTRACT_HELPER(crfS, 18, 3);
302 EXTRACT_HELPER(crbD, 21, 5);
303 EXTRACT_HELPER(crbA, 16, 5);
304 EXTRACT_HELPER(crbB, 11, 5);
306 EXTRACT_HELPER(_SPR, 11, 10);
307 static always_inline uint32_t SPR (uint32_t opcode)
309 uint32_t sprn = _SPR(opcode);
311 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
313 /*** Get constants ***/
314 EXTRACT_HELPER(IMM, 12, 8);
315 /* 16 bits signed immediate value */
316 EXTRACT_SHELPER(SIMM, 0, 16);
317 /* 16 bits unsigned immediate value */
318 EXTRACT_HELPER(UIMM, 0, 16);
320 EXTRACT_HELPER(NB, 11, 5);
322 EXTRACT_HELPER(SH, 11, 5);
324 EXTRACT_HELPER(MB, 6, 5);
326 EXTRACT_HELPER(ME, 1, 5);
328 EXTRACT_HELPER(TO, 21, 5);
330 EXTRACT_HELPER(CRM, 12, 8);
331 EXTRACT_HELPER(FM, 17, 8);
332 EXTRACT_HELPER(SR, 16, 4);
333 EXTRACT_HELPER(FPIMM, 20, 4);
335 /*** Jump target decoding ***/
337 EXTRACT_SHELPER(d, 0, 16);
338 /* Immediate address */
339 static always_inline target_ulong LI (uint32_t opcode)
341 return (opcode >> 0) & 0x03FFFFFC;
344 static always_inline uint32_t BD (uint32_t opcode)
346 return (opcode >> 0) & 0xFFFC;
349 EXTRACT_HELPER(BO, 21, 5);
350 EXTRACT_HELPER(BI, 16, 5);
351 /* Absolute/relative address */
352 EXTRACT_HELPER(AA, 1, 1);
354 EXTRACT_HELPER(LK, 0, 1);
356 /* Create a mask between <start> and <end> bits */
357 static always_inline target_ulong MASK (uint32_t start, uint32_t end)
361 #if defined(TARGET_PPC64)
362 if (likely(start == 0)) {
363 ret = (uint64_t)(-1ULL) << (63 - end);
364 } else if (likely(end == 63)) {
365 ret = (uint64_t)(-1ULL) >> start;
368 if (likely(start == 0)) {
369 ret = (uint32_t)(-1ULL) << (31 - end);
370 } else if (likely(end == 31)) {
371 ret = (uint32_t)(-1ULL) >> start;
375 ret = (((target_ulong)(-1ULL)) >> (start)) ^
376 (((target_ulong)(-1ULL) >> (end)) >> 1);
377 if (unlikely(start > end))
384 /*****************************************************************************/
385 /* PowerPC Instructions types definitions */
387 PPC_NONE = 0x0000000000000000ULL,
388 /* PowerPC base instructions set */
389 PPC_INSNS_BASE = 0x0000000000000001ULL,
390 /* integer operations instructions */
391 #define PPC_INTEGER PPC_INSNS_BASE
392 /* flow control instructions */
393 #define PPC_FLOW PPC_INSNS_BASE
394 /* virtual memory instructions */
395 #define PPC_MEM PPC_INSNS_BASE
396 /* ld/st with reservation instructions */
397 #define PPC_RES PPC_INSNS_BASE
398 /* cache control instructions */
399 #define PPC_CACHE PPC_INSNS_BASE
400 /* spr/msr access instructions */
401 #define PPC_MISC PPC_INSNS_BASE
402 /* Optional floating point instructions */
403 PPC_FLOAT = 0x0000000000000002ULL,
404 PPC_FLOAT_FSQRT = 0x0000000000000004ULL,
405 PPC_FLOAT_FRES = 0x0000000000000008ULL,
406 PPC_FLOAT_FRSQRTE = 0x0000000000000010ULL,
407 PPC_FLOAT_FSEL = 0x0000000000000020ULL,
408 PPC_FLOAT_STFIWX = 0x0000000000000040ULL,
409 /* external control instructions */
410 PPC_EXTERN = 0x0000000000000080ULL,
411 /* segment register access instructions */
412 PPC_SEGMENT = 0x0000000000000100ULL,
413 /* Optional cache control instruction */
414 PPC_CACHE_DCBA = 0x0000000000000200ULL,
415 /* Optional memory control instructions */
416 PPC_MEM_TLBIA = 0x0000000000000400ULL,
417 PPC_MEM_TLBIE = 0x0000000000000800ULL,
418 PPC_MEM_TLBSYNC = 0x0000000000001000ULL,
420 PPC_MEM_SYNC = 0x0000000000002000ULL,
421 /* PowerPC 6xx TLB management instructions */
422 PPC_6xx_TLB = 0x0000000000004000ULL,
423 /* Altivec support */
424 PPC_ALTIVEC = 0x0000000000008000ULL,
425 /* Time base mftb instruction */
426 PPC_MFTB = 0x0000000000010000ULL,
427 /* Embedded PowerPC dedicated instructions */
428 PPC_EMB_COMMON = 0x0000000000020000ULL,
429 /* PowerPC 40x exception model */
430 PPC_40x_EXCP = 0x0000000000040000ULL,
431 /* PowerPC 40x TLB management instructions */
432 PPC_40x_TLB = 0x0000000000080000ULL,
433 /* PowerPC 405 Mac instructions */
434 PPC_405_MAC = 0x0000000000100000ULL,
435 /* PowerPC 440 specific instructions */
436 PPC_440_SPEC = 0x0000000000200000ULL,
437 /* Power-to-PowerPC bridge (601) */
438 PPC_POWER_BR = 0x0000000000400000ULL,
439 /* PowerPC 602 specific */
440 PPC_602_SPEC = 0x0000000000800000ULL,
441 /* Deprecated instructions */
442 /* Original POWER instruction set */
443 PPC_POWER = 0x0000000001000000ULL,
444 /* POWER2 instruction set extension */
445 PPC_POWER2 = 0x0000000002000000ULL,
446 /* Power RTC support */
447 PPC_POWER_RTC = 0x0000000004000000ULL,
448 /* 64 bits PowerPC instruction set */
449 PPC_64B = 0x0000000008000000ULL,
450 /* 64 bits hypervisor extensions */
451 PPC_64H = 0x0000000010000000ULL,
452 /* segment register access instructions for PowerPC 64 "bridge" */
453 PPC_SEGMENT_64B = 0x0000000020000000ULL,
454 /* BookE (embedded) PowerPC specification */
455 PPC_BOOKE = 0x0000000040000000ULL,
457 PPC_MEM_EIEIO = 0x0000000080000000ULL,
458 /* e500 vector instructions */
459 PPC_E500_VECTOR = 0x0000000100000000ULL,
460 /* PowerPC 4xx dedicated instructions */
461 PPC_4xx_COMMON = 0x0000000200000000ULL,
462 /* PowerPC 2.03 specification extensions */
463 PPC_203 = 0x0000000400000000ULL,
464 /* PowerPC 2.03 SPE extension */
465 PPC_SPE = 0x0000000800000000ULL,
466 /* PowerPC 2.03 SPE floating-point extension */
467 PPC_SPEFPU = 0x0000001000000000ULL,
469 PPC_SLBI = 0x0000002000000000ULL,
470 /* PowerPC 40x ibct instructions */
471 PPC_40x_ICBT = 0x0000004000000000ULL,
472 /* PowerPC 74xx TLB management instructions */
473 PPC_74xx_TLB = 0x0000008000000000ULL,
474 /* More BookE (embedded) instructions... */
475 PPC_BOOKE_EXT = 0x0000010000000000ULL,
476 /* rfmci is not implemented in all BookE PowerPC */
477 PPC_RFMCI = 0x0000020000000000ULL,
478 /* user-mode DCR access, implemented in PowerPC 460 */
479 PPC_DCRUX = 0x0000040000000000ULL,
480 /* New floating-point extensions (PowerPC 2.0x) */
481 PPC_FLOAT_EXT = 0x0000080000000000ULL,
482 /* New wait instruction (PowerPC 2.0x) */
483 PPC_WAIT = 0x0000100000000000ULL,
484 /* New 64 bits extensions (PowerPC 2.0x) */
485 PPC_64BX = 0x0000200000000000ULL,
486 /* dcbz instruction with fixed cache line size */
487 PPC_CACHE_DCBZ = 0x0000400000000000ULL,
488 /* dcbz instruction with tunable cache line size */
489 PPC_CACHE_DCBZT = 0x0000800000000000ULL,
492 /*****************************************************************************/
493 /* PowerPC instructions table */
494 #if HOST_LONG_BITS == 64
499 #if defined(__APPLE__)
500 #define OPCODES_SECTION \
501 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
503 #define OPCODES_SECTION \
504 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
507 #if defined(DO_PPC_STATISTICS)
508 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
509 OPCODES_SECTION opcode_t opc_##name = { \
517 .handler = &gen_##name, \
518 .oname = stringify(name), \
520 .oname = stringify(name), \
523 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
524 OPCODES_SECTION opcode_t opc_##name = { \
532 .handler = &gen_##name, \
534 .oname = stringify(name), \
538 #define GEN_OPCODE_MARK(name) \
539 OPCODES_SECTION opcode_t opc_##name = { \
545 .inval = 0x00000000, \
549 .oname = stringify(name), \
552 /* Start opcode list */
553 GEN_OPCODE_MARK(start);
555 /* Invalid instruction */
556 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
561 static opc_handler_t invalid_handler = {
564 .handler = gen_invalid,
567 /*** Integer arithmetic ***/
568 #define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval, type) \
569 GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
571 gen_op_load_gpr_T0(rA(ctx->opcode)); \
572 gen_op_load_gpr_T1(rB(ctx->opcode)); \
574 gen_op_store_T0_gpr(rD(ctx->opcode)); \
575 if (unlikely(Rc(ctx->opcode) != 0)) \
579 #define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval, type) \
580 GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
582 gen_op_load_gpr_T0(rA(ctx->opcode)); \
583 gen_op_load_gpr_T1(rB(ctx->opcode)); \
585 gen_op_store_T0_gpr(rD(ctx->opcode)); \
586 if (unlikely(Rc(ctx->opcode) != 0)) \
590 #define __GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
591 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
593 gen_op_load_gpr_T0(rA(ctx->opcode)); \
595 gen_op_store_T0_gpr(rD(ctx->opcode)); \
596 if (unlikely(Rc(ctx->opcode) != 0)) \
599 #define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3, type) \
600 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
602 gen_op_load_gpr_T0(rA(ctx->opcode)); \
604 gen_op_store_T0_gpr(rD(ctx->opcode)); \
605 if (unlikely(Rc(ctx->opcode) != 0)) \
609 /* Two operands arithmetic functions */
610 #define GEN_INT_ARITH2(name, opc1, opc2, opc3, type) \
611 __GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000, type) \
612 __GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
614 /* Two operands arithmetic functions with no overflow allowed */
615 #define GEN_INT_ARITHN(name, opc1, opc2, opc3, type) \
616 __GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400, type)
618 /* One operand arithmetic functions */
619 #define GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
620 __GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
621 __GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10, type)
623 #if defined(TARGET_PPC64)
624 #define __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, inval, type) \
625 GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
627 gen_op_load_gpr_T0(rA(ctx->opcode)); \
628 gen_op_load_gpr_T1(rB(ctx->opcode)); \
630 gen_op_##name##_64(); \
633 gen_op_store_T0_gpr(rD(ctx->opcode)); \
634 if (unlikely(Rc(ctx->opcode) != 0)) \
638 #define __GEN_INT_ARITH2_O_64(name, opc1, opc2, opc3, inval, type) \
639 GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
641 gen_op_load_gpr_T0(rA(ctx->opcode)); \
642 gen_op_load_gpr_T1(rB(ctx->opcode)); \
644 gen_op_##name##_64(); \
647 gen_op_store_T0_gpr(rD(ctx->opcode)); \
648 if (unlikely(Rc(ctx->opcode) != 0)) \
652 #define __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
653 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
655 gen_op_load_gpr_T0(rA(ctx->opcode)); \
657 gen_op_##name##_64(); \
660 gen_op_store_T0_gpr(rD(ctx->opcode)); \
661 if (unlikely(Rc(ctx->opcode) != 0)) \
664 #define __GEN_INT_ARITH1_O_64(name, opc1, opc2, opc3, type) \
665 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
667 gen_op_load_gpr_T0(rA(ctx->opcode)); \
669 gen_op_##name##_64(); \
672 gen_op_store_T0_gpr(rD(ctx->opcode)); \
673 if (unlikely(Rc(ctx->opcode) != 0)) \
677 /* Two operands arithmetic functions */
678 #define GEN_INT_ARITH2_64(name, opc1, opc2, opc3, type) \
679 __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000000, type) \
680 __GEN_INT_ARITH2_O_64(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
682 /* Two operands arithmetic functions with no overflow allowed */
683 #define GEN_INT_ARITHN_64(name, opc1, opc2, opc3, type) \
684 __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000400, type)
686 /* One operand arithmetic functions */
687 #define GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
688 __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
689 __GEN_INT_ARITH1_O_64(name##o, opc1, opc2, opc3 | 0x10, type)
691 #define GEN_INT_ARITH2_64 GEN_INT_ARITH2
692 #define GEN_INT_ARITHN_64 GEN_INT_ARITHN
693 #define GEN_INT_ARITH1_64 GEN_INT_ARITH1
696 /* add add. addo addo. */
697 static always_inline void gen_op_addo (void)
703 #if defined(TARGET_PPC64)
704 #define gen_op_add_64 gen_op_add
705 static always_inline void gen_op_addo_64 (void)
709 gen_op_check_addo_64();
712 GEN_INT_ARITH2_64 (add, 0x1F, 0x0A, 0x08, PPC_INTEGER);
713 /* addc addc. addco addco. */
714 static always_inline void gen_op_addc (void)
720 static always_inline void gen_op_addco (void)
727 #if defined(TARGET_PPC64)
728 static always_inline void gen_op_addc_64 (void)
732 gen_op_check_addc_64();
734 static always_inline void gen_op_addco_64 (void)
738 gen_op_check_addc_64();
739 gen_op_check_addo_64();
742 GEN_INT_ARITH2_64 (addc, 0x1F, 0x0A, 0x00, PPC_INTEGER);
743 /* adde adde. addeo addeo. */
744 static always_inline void gen_op_addeo (void)
750 #if defined(TARGET_PPC64)
751 static always_inline void gen_op_addeo_64 (void)
755 gen_op_check_addo_64();
758 GEN_INT_ARITH2_64 (adde, 0x1F, 0x0A, 0x04, PPC_INTEGER);
759 /* addme addme. addmeo addmeo. */
760 static always_inline void gen_op_addme (void)
765 #if defined(TARGET_PPC64)
766 static always_inline void gen_op_addme_64 (void)
772 GEN_INT_ARITH1_64 (addme, 0x1F, 0x0A, 0x07, PPC_INTEGER);
773 /* addze addze. addzeo addzeo. */
774 static always_inline void gen_op_addze (void)
780 static always_inline void gen_op_addzeo (void)
787 #if defined(TARGET_PPC64)
788 static always_inline void gen_op_addze_64 (void)
792 gen_op_check_addc_64();
794 static always_inline void gen_op_addzeo_64 (void)
798 gen_op_check_addc_64();
799 gen_op_check_addo_64();
802 GEN_INT_ARITH1_64 (addze, 0x1F, 0x0A, 0x06, PPC_INTEGER);
803 /* divw divw. divwo divwo. */
804 GEN_INT_ARITH2 (divw, 0x1F, 0x0B, 0x0F, PPC_INTEGER);
805 /* divwu divwu. divwuo divwuo. */
806 GEN_INT_ARITH2 (divwu, 0x1F, 0x0B, 0x0E, PPC_INTEGER);
808 GEN_INT_ARITHN (mulhw, 0x1F, 0x0B, 0x02, PPC_INTEGER);
810 GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00, PPC_INTEGER);
811 /* mullw mullw. mullwo mullwo. */
812 GEN_INT_ARITH2 (mullw, 0x1F, 0x0B, 0x07, PPC_INTEGER);
813 /* neg neg. nego nego. */
814 GEN_INT_ARITH1_64 (neg, 0x1F, 0x08, 0x03, PPC_INTEGER);
815 /* subf subf. subfo subfo. */
816 static always_inline void gen_op_subfo (void)
820 gen_op_check_subfo();
822 #if defined(TARGET_PPC64)
823 #define gen_op_subf_64 gen_op_subf
824 static always_inline void gen_op_subfo_64 (void)
828 gen_op_check_subfo_64();
831 GEN_INT_ARITH2_64 (subf, 0x1F, 0x08, 0x01, PPC_INTEGER);
832 /* subfc subfc. subfco subfco. */
833 static always_inline void gen_op_subfc (void)
836 gen_op_check_subfc();
838 static always_inline void gen_op_subfco (void)
842 gen_op_check_subfc();
843 gen_op_check_subfo();
845 #if defined(TARGET_PPC64)
846 static always_inline void gen_op_subfc_64 (void)
849 gen_op_check_subfc_64();
851 static always_inline void gen_op_subfco_64 (void)
855 gen_op_check_subfc_64();
856 gen_op_check_subfo_64();
859 GEN_INT_ARITH2_64 (subfc, 0x1F, 0x08, 0x00, PPC_INTEGER);
860 /* subfe subfe. subfeo subfeo. */
861 static always_inline void gen_op_subfeo (void)
865 gen_op_check_subfo();
867 #if defined(TARGET_PPC64)
868 #define gen_op_subfe_64 gen_op_subfe
869 static always_inline void gen_op_subfeo_64 (void)
873 gen_op_check_subfo_64();
876 GEN_INT_ARITH2_64 (subfe, 0x1F, 0x08, 0x04, PPC_INTEGER);
877 /* subfme subfme. subfmeo subfmeo. */
878 GEN_INT_ARITH1_64 (subfme, 0x1F, 0x08, 0x07, PPC_INTEGER);
879 /* subfze subfze. subfzeo subfzeo. */
880 GEN_INT_ARITH1_64 (subfze, 0x1F, 0x08, 0x06, PPC_INTEGER);
882 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
884 target_long simm = SIMM(ctx->opcode);
886 if (rA(ctx->opcode) == 0) {
890 gen_op_load_gpr_T0(rA(ctx->opcode));
891 if (likely(simm != 0))
894 gen_op_store_T0_gpr(rD(ctx->opcode));
897 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
899 target_long simm = SIMM(ctx->opcode);
901 gen_op_load_gpr_T0(rA(ctx->opcode));
902 if (likely(simm != 0)) {
905 #if defined(TARGET_PPC64)
907 gen_op_check_addc_64();
912 gen_op_clear_xer_ca();
914 gen_op_store_T0_gpr(rD(ctx->opcode));
917 GEN_HANDLER(addic_, 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
919 target_long simm = SIMM(ctx->opcode);
921 gen_op_load_gpr_T0(rA(ctx->opcode));
922 if (likely(simm != 0)) {
925 #if defined(TARGET_PPC64)
927 gen_op_check_addc_64();
932 gen_op_clear_xer_ca();
934 gen_op_store_T0_gpr(rD(ctx->opcode));
938 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
940 target_long simm = SIMM(ctx->opcode);
942 if (rA(ctx->opcode) == 0) {
944 gen_set_T0(simm << 16);
946 gen_op_load_gpr_T0(rA(ctx->opcode));
947 if (likely(simm != 0))
948 gen_op_addi(simm << 16);
950 gen_op_store_T0_gpr(rD(ctx->opcode));
953 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
955 gen_op_load_gpr_T0(rA(ctx->opcode));
956 gen_op_mulli(SIMM(ctx->opcode));
957 gen_op_store_T0_gpr(rD(ctx->opcode));
960 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
962 gen_op_load_gpr_T0(rA(ctx->opcode));
963 #if defined(TARGET_PPC64)
965 gen_op_subfic_64(SIMM(ctx->opcode));
968 gen_op_subfic(SIMM(ctx->opcode));
969 gen_op_store_T0_gpr(rD(ctx->opcode));
972 #if defined(TARGET_PPC64)
974 GEN_INT_ARITHN (mulhd, 0x1F, 0x09, 0x02, PPC_64B);
976 GEN_INT_ARITHN (mulhdu, 0x1F, 0x09, 0x00, PPC_64B);
977 /* mulld mulld. mulldo mulldo. */
978 GEN_INT_ARITH2 (mulld, 0x1F, 0x09, 0x07, PPC_64B);
979 /* divd divd. divdo divdo. */
980 GEN_INT_ARITH2 (divd, 0x1F, 0x09, 0x0F, PPC_64B);
981 /* divdu divdu. divduo divduo. */
982 GEN_INT_ARITH2 (divdu, 0x1F, 0x09, 0x0E, PPC_64B);
985 /*** Integer comparison ***/
986 #if defined(TARGET_PPC64)
987 #define GEN_CMP(name, opc, type) \
988 GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \
990 gen_op_load_gpr_T0(rA(ctx->opcode)); \
991 gen_op_load_gpr_T1(rB(ctx->opcode)); \
992 if (ctx->sf_mode && (ctx->opcode & 0x00200000)) \
993 gen_op_##name##_64(); \
996 gen_op_store_T0_crf(crfD(ctx->opcode)); \
999 #define GEN_CMP(name, opc, type) \
1000 GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \
1002 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1003 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1005 gen_op_store_T0_crf(crfD(ctx->opcode)); \
1010 GEN_CMP(cmp, 0x00, PPC_INTEGER);
1012 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
1014 gen_op_load_gpr_T0(rA(ctx->opcode));
1015 #if defined(TARGET_PPC64)
1016 if (ctx->sf_mode && (ctx->opcode & 0x00200000))
1017 gen_op_cmpi_64(SIMM(ctx->opcode));
1020 gen_op_cmpi(SIMM(ctx->opcode));
1021 gen_op_store_T0_crf(crfD(ctx->opcode));
1024 GEN_CMP(cmpl, 0x01, PPC_INTEGER);
1026 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
1028 gen_op_load_gpr_T0(rA(ctx->opcode));
1029 #if defined(TARGET_PPC64)
1030 if (ctx->sf_mode && (ctx->opcode & 0x00200000))
1031 gen_op_cmpli_64(UIMM(ctx->opcode));
1034 gen_op_cmpli(UIMM(ctx->opcode));
1035 gen_op_store_T0_crf(crfD(ctx->opcode));
1038 /* isel (PowerPC 2.03 specification) */
1039 GEN_HANDLER(isel, 0x1F, 0x0F, 0x00, 0x00000001, PPC_203)
1041 uint32_t bi = rC(ctx->opcode);
1044 if (rA(ctx->opcode) == 0) {
1047 gen_op_load_gpr_T1(rA(ctx->opcode));
1049 gen_op_load_gpr_T2(rB(ctx->opcode));
1050 mask = 1 << (3 - (bi & 0x03));
1051 gen_op_load_crf_T0(bi >> 2);
1052 gen_op_test_true(mask);
1054 gen_op_store_T0_gpr(rD(ctx->opcode));
1057 /*** Integer logical ***/
1058 #define __GEN_LOGICAL2(name, opc2, opc3, type) \
1059 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, type) \
1061 gen_op_load_gpr_T0(rS(ctx->opcode)); \
1062 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1064 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1065 if (unlikely(Rc(ctx->opcode) != 0)) \
1068 #define GEN_LOGICAL2(name, opc, type) \
1069 __GEN_LOGICAL2(name, 0x1C, opc, type)
1071 #define GEN_LOGICAL1(name, opc, type) \
1072 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
1074 gen_op_load_gpr_T0(rS(ctx->opcode)); \
1076 gen_op_store_T0_gpr(rA(ctx->opcode)); \
1077 if (unlikely(Rc(ctx->opcode) != 0)) \
1082 GEN_LOGICAL2(and, 0x00, PPC_INTEGER);
1084 GEN_LOGICAL2(andc, 0x01, PPC_INTEGER);
1086 GEN_HANDLER(andi_, 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1088 gen_op_load_gpr_T0(rS(ctx->opcode));
1089 gen_op_andi_T0(UIMM(ctx->opcode));
1090 gen_op_store_T0_gpr(rA(ctx->opcode));
1094 GEN_HANDLER(andis_, 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1096 gen_op_load_gpr_T0(rS(ctx->opcode));
1097 gen_op_andi_T0(UIMM(ctx->opcode) << 16);
1098 gen_op_store_T0_gpr(rA(ctx->opcode));
1103 GEN_LOGICAL1(cntlzw, 0x00, PPC_INTEGER);
1105 GEN_LOGICAL2(eqv, 0x08, PPC_INTEGER);
1106 /* extsb & extsb. */
1107 GEN_LOGICAL1(extsb, 0x1D, PPC_INTEGER);
1108 /* extsh & extsh. */
1109 GEN_LOGICAL1(extsh, 0x1C, PPC_INTEGER);
1111 GEN_LOGICAL2(nand, 0x0E, PPC_INTEGER);
1113 GEN_LOGICAL2(nor, 0x03, PPC_INTEGER);
1116 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1120 rs = rS(ctx->opcode);
1121 ra = rA(ctx->opcode);
1122 rb = rB(ctx->opcode);
1123 /* Optimisation for mr. ri case */
1124 if (rs != ra || rs != rb) {
1125 gen_op_load_gpr_T0(rs);
1127 gen_op_load_gpr_T1(rb);
1130 gen_op_store_T0_gpr(ra);
1131 if (unlikely(Rc(ctx->opcode) != 0))
1133 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1134 gen_op_load_gpr_T0(rs);
1136 #if defined(TARGET_PPC64)
1140 /* Set process priority to low */
1141 gen_op_store_pri(2);
1144 /* Set process priority to medium-low */
1145 gen_op_store_pri(3);
1148 /* Set process priority to normal */
1149 gen_op_store_pri(4);
1151 #if !defined(CONFIG_USER_ONLY)
1153 if (ctx->supervisor > 0) {
1154 /* Set process priority to very low */
1155 gen_op_store_pri(1);
1159 if (ctx->supervisor > 0) {
1160 /* Set process priority to medium-hight */
1161 gen_op_store_pri(5);
1165 if (ctx->supervisor > 0) {
1166 /* Set process priority to high */
1167 gen_op_store_pri(6);
1170 #if defined(TARGET_PPC64H)
1172 if (ctx->supervisor > 1) {
1173 /* Set process priority to very high */
1174 gen_op_store_pri(7);
1188 GEN_LOGICAL2(orc, 0x0C, PPC_INTEGER);
1190 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1192 gen_op_load_gpr_T0(rS(ctx->opcode));
1193 /* Optimisation for "set to zero" case */
1194 if (rS(ctx->opcode) != rB(ctx->opcode)) {
1195 gen_op_load_gpr_T1(rB(ctx->opcode));
1200 gen_op_store_T0_gpr(rA(ctx->opcode));
1201 if (unlikely(Rc(ctx->opcode) != 0))
1205 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1207 target_ulong uimm = UIMM(ctx->opcode);
1209 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1211 /* XXX: should handle special NOPs for POWER series */
1214 gen_op_load_gpr_T0(rS(ctx->opcode));
1215 if (likely(uimm != 0))
1217 gen_op_store_T0_gpr(rA(ctx->opcode));
1220 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1222 target_ulong uimm = UIMM(ctx->opcode);
1224 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1228 gen_op_load_gpr_T0(rS(ctx->opcode));
1229 if (likely(uimm != 0))
1230 gen_op_ori(uimm << 16);
1231 gen_op_store_T0_gpr(rA(ctx->opcode));
1234 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1236 target_ulong uimm = UIMM(ctx->opcode);
1238 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1242 gen_op_load_gpr_T0(rS(ctx->opcode));
1243 if (likely(uimm != 0))
1245 gen_op_store_T0_gpr(rA(ctx->opcode));
1249 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1251 target_ulong uimm = UIMM(ctx->opcode);
1253 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1257 gen_op_load_gpr_T0(rS(ctx->opcode));
1258 if (likely(uimm != 0))
1259 gen_op_xori(uimm << 16);
1260 gen_op_store_T0_gpr(rA(ctx->opcode));
1263 /* popcntb : PowerPC 2.03 specification */
1264 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_203)
1266 gen_op_load_gpr_T0(rS(ctx->opcode));
1267 #if defined(TARGET_PPC64)
1269 gen_op_popcntb_64();
1273 gen_op_store_T0_gpr(rA(ctx->opcode));
1276 #if defined(TARGET_PPC64)
1277 /* extsw & extsw. */
1278 GEN_LOGICAL1(extsw, 0x1E, PPC_64B);
1280 GEN_LOGICAL1(cntlzd, 0x01, PPC_64B);
1283 /*** Integer rotate ***/
1284 /* rlwimi & rlwimi. */
1285 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1288 uint32_t mb, me, sh;
1290 mb = MB(ctx->opcode);
1291 me = ME(ctx->opcode);
1292 sh = SH(ctx->opcode);
1293 if (likely(sh == 0)) {
1294 if (likely(mb == 0 && me == 31)) {
1295 gen_op_load_gpr_T0(rS(ctx->opcode));
1297 } else if (likely(mb == 31 && me == 0)) {
1298 gen_op_load_gpr_T0(rA(ctx->opcode));
1301 gen_op_load_gpr_T0(rS(ctx->opcode));
1302 gen_op_load_gpr_T1(rA(ctx->opcode));
1305 gen_op_load_gpr_T0(rS(ctx->opcode));
1306 gen_op_load_gpr_T1(rA(ctx->opcode));
1307 gen_op_rotli32_T0(SH(ctx->opcode));
1309 #if defined(TARGET_PPC64)
1313 mask = MASK(mb, me);
1314 gen_op_andi_T0(mask);
1315 gen_op_andi_T1(~mask);
1318 gen_op_store_T0_gpr(rA(ctx->opcode));
1319 if (unlikely(Rc(ctx->opcode) != 0))
1322 /* rlwinm & rlwinm. */
1323 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1325 uint32_t mb, me, sh;
1327 sh = SH(ctx->opcode);
1328 mb = MB(ctx->opcode);
1329 me = ME(ctx->opcode);
1330 gen_op_load_gpr_T0(rS(ctx->opcode));
1331 if (likely(sh == 0)) {
1334 if (likely(mb == 0)) {
1335 if (likely(me == 31)) {
1336 gen_op_rotli32_T0(sh);
1338 } else if (likely(me == (31 - sh))) {
1342 } else if (likely(me == 31)) {
1343 if (likely(sh == (32 - mb))) {
1348 gen_op_rotli32_T0(sh);
1350 #if defined(TARGET_PPC64)
1354 gen_op_andi_T0(MASK(mb, me));
1356 gen_op_store_T0_gpr(rA(ctx->opcode));
1357 if (unlikely(Rc(ctx->opcode) != 0))
1360 /* rlwnm & rlwnm. */
1361 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1365 mb = MB(ctx->opcode);
1366 me = ME(ctx->opcode);
1367 gen_op_load_gpr_T0(rS(ctx->opcode));
1368 gen_op_load_gpr_T1(rB(ctx->opcode));
1369 gen_op_rotl32_T0_T1();
1370 if (unlikely(mb != 0 || me != 31)) {
1371 #if defined(TARGET_PPC64)
1375 gen_op_andi_T0(MASK(mb, me));
1377 gen_op_store_T0_gpr(rA(ctx->opcode));
1378 if (unlikely(Rc(ctx->opcode) != 0))
1382 #if defined(TARGET_PPC64)
1383 #define GEN_PPC64_R2(name, opc1, opc2) \
1384 GEN_HANDLER(name##0, opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1386 gen_##name(ctx, 0); \
1388 GEN_HANDLER(name##1, opc1, opc2 | 0x10, 0xFF, 0x00000000, PPC_64B) \
1390 gen_##name(ctx, 1); \
1392 #define GEN_PPC64_R4(name, opc1, opc2) \
1393 GEN_HANDLER(name##0, opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1395 gen_##name(ctx, 0, 0); \
1397 GEN_HANDLER(name##1, opc1, opc2 | 0x01, 0xFF, 0x00000000, PPC_64B) \
1399 gen_##name(ctx, 0, 1); \
1401 GEN_HANDLER(name##2, opc1, opc2 | 0x10, 0xFF, 0x00000000, PPC_64B) \
1403 gen_##name(ctx, 1, 0); \
1405 GEN_HANDLER(name##3, opc1, opc2 | 0x11, 0xFF, 0x00000000, PPC_64B) \
1407 gen_##name(ctx, 1, 1); \
1410 static always_inline void gen_andi_T0_64 (DisasContext *ctx, uint64_t mask)
1413 gen_op_andi_T0_64(mask >> 32, mask & 0xFFFFFFFF);
1415 gen_op_andi_T0(mask);
1418 static always_inline void gen_andi_T1_64 (DisasContext *ctx, uint64_t mask)
1421 gen_op_andi_T1_64(mask >> 32, mask & 0xFFFFFFFF);
1423 gen_op_andi_T1(mask);
1426 static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1427 uint32_t me, uint32_t sh)
1429 gen_op_load_gpr_T0(rS(ctx->opcode));
1430 if (likely(sh == 0)) {
1433 if (likely(mb == 0)) {
1434 if (likely(me == 63)) {
1435 gen_op_rotli64_T0(sh);
1437 } else if (likely(me == (63 - sh))) {
1441 } else if (likely(me == 63)) {
1442 if (likely(sh == (64 - mb))) {
1443 gen_op_srli_T0_64(mb);
1447 gen_op_rotli64_T0(sh);
1449 gen_andi_T0_64(ctx, MASK(mb, me));
1451 gen_op_store_T0_gpr(rA(ctx->opcode));
1452 if (unlikely(Rc(ctx->opcode) != 0))
1455 /* rldicl - rldicl. */
1456 static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
1460 sh = SH(ctx->opcode) | (shn << 5);
1461 mb = MB(ctx->opcode) | (mbn << 5);
1462 gen_rldinm(ctx, mb, 63, sh);
1464 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1465 /* rldicr - rldicr. */
1466 static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
1470 sh = SH(ctx->opcode) | (shn << 5);
1471 me = MB(ctx->opcode) | (men << 5);
1472 gen_rldinm(ctx, 0, me, sh);
1474 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1475 /* rldic - rldic. */
1476 static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
1480 sh = SH(ctx->opcode) | (shn << 5);
1481 mb = MB(ctx->opcode) | (mbn << 5);
1482 gen_rldinm(ctx, mb, 63 - sh, sh);
1484 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1486 static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1489 gen_op_load_gpr_T0(rS(ctx->opcode));
1490 gen_op_load_gpr_T1(rB(ctx->opcode));
1491 gen_op_rotl64_T0_T1();
1492 if (unlikely(mb != 0 || me != 63)) {
1493 gen_andi_T0_64(ctx, MASK(mb, me));
1495 gen_op_store_T0_gpr(rA(ctx->opcode));
1496 if (unlikely(Rc(ctx->opcode) != 0))
1500 /* rldcl - rldcl. */
1501 static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
1505 mb = MB(ctx->opcode) | (mbn << 5);
1506 gen_rldnm(ctx, mb, 63);
1508 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1509 /* rldcr - rldcr. */
1510 static always_inline void gen_rldcr (DisasContext *ctx, int men)
1514 me = MB(ctx->opcode) | (men << 5);
1515 gen_rldnm(ctx, 0, me);
1517 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1518 /* rldimi - rldimi. */
1519 static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
1524 sh = SH(ctx->opcode) | (shn << 5);
1525 mb = MB(ctx->opcode) | (mbn << 5);
1526 if (likely(sh == 0)) {
1527 if (likely(mb == 0)) {
1528 gen_op_load_gpr_T0(rS(ctx->opcode));
1530 } else if (likely(mb == 63)) {
1531 gen_op_load_gpr_T0(rA(ctx->opcode));
1534 gen_op_load_gpr_T0(rS(ctx->opcode));
1535 gen_op_load_gpr_T1(rA(ctx->opcode));
1538 gen_op_load_gpr_T0(rS(ctx->opcode));
1539 gen_op_load_gpr_T1(rA(ctx->opcode));
1540 gen_op_rotli64_T0(sh);
1542 mask = MASK(mb, 63 - sh);
1543 gen_andi_T0_64(ctx, mask);
1544 gen_andi_T1_64(ctx, ~mask);
1547 gen_op_store_T0_gpr(rA(ctx->opcode));
1548 if (unlikely(Rc(ctx->opcode) != 0))
1551 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1554 /*** Integer shift ***/
1556 __GEN_LOGICAL2(slw, 0x18, 0x00, PPC_INTEGER);
1558 __GEN_LOGICAL2(sraw, 0x18, 0x18, PPC_INTEGER);
1559 /* srawi & srawi. */
1560 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1563 gen_op_load_gpr_T0(rS(ctx->opcode));
1564 if (SH(ctx->opcode) != 0) {
1565 gen_op_move_T1_T0();
1566 mb = 32 - SH(ctx->opcode);
1568 #if defined(TARGET_PPC64)
1572 gen_op_srawi(SH(ctx->opcode), MASK(mb, me));
1574 gen_op_store_T0_gpr(rA(ctx->opcode));
1575 if (unlikely(Rc(ctx->opcode) != 0))
1579 __GEN_LOGICAL2(srw, 0x18, 0x10, PPC_INTEGER);
1581 #if defined(TARGET_PPC64)
1583 __GEN_LOGICAL2(sld, 0x1B, 0x00, PPC_64B);
1585 __GEN_LOGICAL2(srad, 0x1A, 0x18, PPC_64B);
1586 /* sradi & sradi. */
1587 static always_inline void gen_sradi (DisasContext *ctx, int n)
1592 gen_op_load_gpr_T0(rS(ctx->opcode));
1593 sh = SH(ctx->opcode) + (n << 5);
1595 gen_op_move_T1_T0();
1596 mb = 64 - SH(ctx->opcode);
1598 mask = MASK(mb, me);
1599 gen_op_sradi(sh, mask >> 32, mask);
1601 gen_op_store_T0_gpr(rA(ctx->opcode));
1602 if (unlikely(Rc(ctx->opcode) != 0))
1605 GEN_HANDLER(sradi0, 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
1609 GEN_HANDLER(sradi1, 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
1614 __GEN_LOGICAL2(srd, 0x1B, 0x10, PPC_64B);
1617 /*** Floating-Point arithmetic ***/
1618 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, type) \
1619 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
1621 if (unlikely(!ctx->fpu_enabled)) { \
1622 GEN_EXCP_NO_FP(ctx); \
1625 gen_op_reset_scrfx(); \
1626 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1627 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
1628 gen_op_load_fpr_FT2(rB(ctx->opcode)); \
1633 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1634 if (unlikely(Rc(ctx->opcode) != 0)) \
1638 #define GEN_FLOAT_ACB(name, op2, type) \
1639 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, type); \
1640 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, type);
1642 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat) \
1643 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \
1645 if (unlikely(!ctx->fpu_enabled)) { \
1646 GEN_EXCP_NO_FP(ctx); \
1649 gen_op_reset_scrfx(); \
1650 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1651 gen_op_load_fpr_FT1(rB(ctx->opcode)); \
1656 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1657 if (unlikely(Rc(ctx->opcode) != 0)) \
1660 #define GEN_FLOAT_AB(name, op2, inval) \
1661 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0); \
1662 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1);
1664 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat) \
1665 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \
1667 if (unlikely(!ctx->fpu_enabled)) { \
1668 GEN_EXCP_NO_FP(ctx); \
1671 gen_op_reset_scrfx(); \
1672 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1673 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
1678 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1679 if (unlikely(Rc(ctx->opcode) != 0)) \
1682 #define GEN_FLOAT_AC(name, op2, inval) \
1683 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0); \
1684 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1);
1686 #define GEN_FLOAT_B(name, op2, op3, type) \
1687 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
1689 if (unlikely(!ctx->fpu_enabled)) { \
1690 GEN_EXCP_NO_FP(ctx); \
1693 gen_op_reset_scrfx(); \
1694 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
1696 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1697 if (unlikely(Rc(ctx->opcode) != 0)) \
1701 #define GEN_FLOAT_BS(name, op1, op2, type) \
1702 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
1704 if (unlikely(!ctx->fpu_enabled)) { \
1705 GEN_EXCP_NO_FP(ctx); \
1708 gen_op_reset_scrfx(); \
1709 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
1711 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1712 if (unlikely(Rc(ctx->opcode) != 0)) \
1717 GEN_FLOAT_AB(add, 0x15, 0x000007C0);
1719 GEN_FLOAT_AB(div, 0x12, 0x000007C0);
1721 GEN_FLOAT_AC(mul, 0x19, 0x0000F800);
1724 GEN_FLOAT_BS(re, 0x3F, 0x18, PPC_FLOAT_EXT);
1727 GEN_FLOAT_BS(res, 0x3B, 0x18, PPC_FLOAT_FRES);
1730 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, PPC_FLOAT_FRSQRTE);
1733 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, PPC_FLOAT_FSEL);
1735 GEN_FLOAT_AB(sub, 0x14, 0x000007C0);
1738 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
1740 if (unlikely(!ctx->fpu_enabled)) {
1741 GEN_EXCP_NO_FP(ctx);
1744 gen_op_reset_scrfx();
1745 gen_op_load_fpr_FT0(rB(ctx->opcode));
1747 gen_op_store_FT0_fpr(rD(ctx->opcode));
1748 if (unlikely(Rc(ctx->opcode) != 0))
1752 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
1754 if (unlikely(!ctx->fpu_enabled)) {
1755 GEN_EXCP_NO_FP(ctx);
1758 gen_op_reset_scrfx();
1759 gen_op_load_fpr_FT0(rB(ctx->opcode));
1762 gen_op_store_FT0_fpr(rD(ctx->opcode));
1763 if (unlikely(Rc(ctx->opcode) != 0))
1767 /*** Floating-Point multiply-and-add ***/
1768 /* fmadd - fmadds */
1769 GEN_FLOAT_ACB(madd, 0x1D, PPC_FLOAT);
1770 /* fmsub - fmsubs */
1771 GEN_FLOAT_ACB(msub, 0x1C, PPC_FLOAT);
1772 /* fnmadd - fnmadds */
1773 GEN_FLOAT_ACB(nmadd, 0x1F, PPC_FLOAT);
1774 /* fnmsub - fnmsubs */
1775 GEN_FLOAT_ACB(nmsub, 0x1E, PPC_FLOAT);
1777 /*** Floating-Point round & convert ***/
1779 GEN_FLOAT_B(ctiw, 0x0E, 0x00, PPC_FLOAT);
1781 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, PPC_FLOAT);
1783 GEN_FLOAT_B(rsp, 0x0C, 0x00, PPC_FLOAT);
1784 #if defined(TARGET_PPC64)
1786 GEN_FLOAT_B(cfid, 0x0E, 0x1A, PPC_64B);
1788 GEN_FLOAT_B(ctid, 0x0E, 0x19, PPC_64B);
1790 GEN_FLOAT_B(ctidz, 0x0F, 0x19, PPC_64B);
1794 GEN_FLOAT_B(rin, 0x08, 0x0C, PPC_FLOAT_EXT);
1796 GEN_FLOAT_B(riz, 0x08, 0x0D, PPC_FLOAT_EXT);
1798 GEN_FLOAT_B(rip, 0x08, 0x0E, PPC_FLOAT_EXT);
1800 GEN_FLOAT_B(rim, 0x08, 0x0F, PPC_FLOAT_EXT);
1802 /*** Floating-Point compare ***/
1804 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
1806 if (unlikely(!ctx->fpu_enabled)) {
1807 GEN_EXCP_NO_FP(ctx);
1810 gen_op_reset_scrfx();
1811 gen_op_load_fpr_FT0(rA(ctx->opcode));
1812 gen_op_load_fpr_FT1(rB(ctx->opcode));
1814 gen_op_store_T0_crf(crfD(ctx->opcode));
1818 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
1820 if (unlikely(!ctx->fpu_enabled)) {
1821 GEN_EXCP_NO_FP(ctx);
1824 gen_op_reset_scrfx();
1825 gen_op_load_fpr_FT0(rA(ctx->opcode));
1826 gen_op_load_fpr_FT1(rB(ctx->opcode));
1828 gen_op_store_T0_crf(crfD(ctx->opcode));
1831 /*** Floating-point move ***/
1833 GEN_FLOAT_B(abs, 0x08, 0x08, PPC_FLOAT);
1836 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
1838 if (unlikely(!ctx->fpu_enabled)) {
1839 GEN_EXCP_NO_FP(ctx);
1842 gen_op_reset_scrfx();
1843 gen_op_load_fpr_FT0(rB(ctx->opcode));
1844 gen_op_store_FT0_fpr(rD(ctx->opcode));
1845 if (unlikely(Rc(ctx->opcode) != 0))
1850 GEN_FLOAT_B(nabs, 0x08, 0x04, PPC_FLOAT);
1852 GEN_FLOAT_B(neg, 0x08, 0x01, PPC_FLOAT);
1854 /*** Floating-Point status & ctrl register ***/
1856 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
1858 if (unlikely(!ctx->fpu_enabled)) {
1859 GEN_EXCP_NO_FP(ctx);
1862 gen_op_load_fpscr_T0(crfS(ctx->opcode));
1863 gen_op_store_T0_crf(crfD(ctx->opcode));
1864 gen_op_clear_fpscr(crfS(ctx->opcode));
1868 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
1870 if (unlikely(!ctx->fpu_enabled)) {
1871 GEN_EXCP_NO_FP(ctx);
1874 gen_op_load_fpscr();
1875 gen_op_store_FT0_fpr(rD(ctx->opcode));
1876 if (unlikely(Rc(ctx->opcode) != 0))
1881 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
1885 if (unlikely(!ctx->fpu_enabled)) {
1886 GEN_EXCP_NO_FP(ctx);
1889 crb = crbD(ctx->opcode) >> 2;
1890 gen_op_load_fpscr_T0(crb);
1891 gen_op_andi_T0(~(1 << (crbD(ctx->opcode) & 0x03)));
1892 gen_op_store_T0_fpscr(crb);
1893 if (unlikely(Rc(ctx->opcode) != 0))
1898 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
1902 if (unlikely(!ctx->fpu_enabled)) {
1903 GEN_EXCP_NO_FP(ctx);
1906 crb = crbD(ctx->opcode) >> 2;
1907 gen_op_load_fpscr_T0(crb);
1908 gen_op_ori(1 << (crbD(ctx->opcode) & 0x03));
1909 gen_op_store_T0_fpscr(crb);
1910 if (unlikely(Rc(ctx->opcode) != 0))
1915 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
1917 if (unlikely(!ctx->fpu_enabled)) {
1918 GEN_EXCP_NO_FP(ctx);
1921 gen_op_load_fpr_FT0(rB(ctx->opcode));
1922 gen_op_store_fpscr(FM(ctx->opcode));
1923 if (unlikely(Rc(ctx->opcode) != 0))
1928 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
1930 if (unlikely(!ctx->fpu_enabled)) {
1931 GEN_EXCP_NO_FP(ctx);
1934 gen_op_store_T0_fpscri(crbD(ctx->opcode) >> 2, FPIMM(ctx->opcode));
1935 if (unlikely(Rc(ctx->opcode) != 0))
1939 /*** Addressing modes ***/
1940 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
1941 static always_inline void gen_addr_imm_index (DisasContext *ctx,
1944 target_long simm = SIMM(ctx->opcode);
1947 if (rA(ctx->opcode) == 0) {
1950 gen_op_load_gpr_T0(rA(ctx->opcode));
1951 if (likely(simm != 0))
1954 #ifdef DEBUG_MEMORY_ACCESSES
1955 gen_op_print_mem_EA();
1959 static always_inline void gen_addr_reg_index (DisasContext *ctx)
1961 if (rA(ctx->opcode) == 0) {
1962 gen_op_load_gpr_T0(rB(ctx->opcode));
1964 gen_op_load_gpr_T0(rA(ctx->opcode));
1965 gen_op_load_gpr_T1(rB(ctx->opcode));
1968 #ifdef DEBUG_MEMORY_ACCESSES
1969 gen_op_print_mem_EA();
1973 static always_inline void gen_addr_register (DisasContext *ctx)
1975 if (rA(ctx->opcode) == 0) {
1978 gen_op_load_gpr_T0(rA(ctx->opcode));
1980 #ifdef DEBUG_MEMORY_ACCESSES
1981 gen_op_print_mem_EA();
1985 /*** Integer load ***/
1986 #define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
1987 #if defined(CONFIG_USER_ONLY)
1988 #if defined(TARGET_PPC64)
1989 /* User mode only - 64 bits */
1990 #define OP_LD_TABLE(width) \
1991 static GenOpFunc *gen_op_l##width[] = { \
1992 &gen_op_l##width##_raw, \
1993 &gen_op_l##width##_le_raw, \
1994 &gen_op_l##width##_64_raw, \
1995 &gen_op_l##width##_le_64_raw, \
1997 #define OP_ST_TABLE(width) \
1998 static GenOpFunc *gen_op_st##width[] = { \
1999 &gen_op_st##width##_raw, \
2000 &gen_op_st##width##_le_raw, \
2001 &gen_op_st##width##_64_raw, \
2002 &gen_op_st##width##_le_64_raw, \
2004 /* Byte access routine are endian safe */
2005 #define gen_op_stb_le_64_raw gen_op_stb_64_raw
2006 #define gen_op_lbz_le_64_raw gen_op_lbz_64_raw
2008 /* User mode only - 32 bits */
2009 #define OP_LD_TABLE(width) \
2010 static GenOpFunc *gen_op_l##width[] = { \
2011 &gen_op_l##width##_raw, \
2012 &gen_op_l##width##_le_raw, \
2014 #define OP_ST_TABLE(width) \
2015 static GenOpFunc *gen_op_st##width[] = { \
2016 &gen_op_st##width##_raw, \
2017 &gen_op_st##width##_le_raw, \
2020 /* Byte access routine are endian safe */
2021 #define gen_op_stb_le_raw gen_op_stb_raw
2022 #define gen_op_lbz_le_raw gen_op_lbz_raw
2024 #if defined(TARGET_PPC64)
2025 #if defined(TARGET_PPC64H)
2026 /* Full system - 64 bits with hypervisor mode */
2027 #define OP_LD_TABLE(width) \
2028 static GenOpFunc *gen_op_l##width[] = { \
2029 &gen_op_l##width##_user, \
2030 &gen_op_l##width##_le_user, \
2031 &gen_op_l##width##_64_user, \
2032 &gen_op_l##width##_le_64_user, \
2033 &gen_op_l##width##_kernel, \
2034 &gen_op_l##width##_le_kernel, \
2035 &gen_op_l##width##_64_kernel, \
2036 &gen_op_l##width##_le_64_kernel, \
2037 &gen_op_l##width##_hypv, \
2038 &gen_op_l##width##_le_hypv, \
2039 &gen_op_l##width##_64_hypv, \
2040 &gen_op_l##width##_le_64_hypv, \
2042 #define OP_ST_TABLE(width) \
2043 static GenOpFunc *gen_op_st##width[] = { \
2044 &gen_op_st##width##_user, \
2045 &gen_op_st##width##_le_user, \
2046 &gen_op_st##width##_64_user, \
2047 &gen_op_st##width##_le_64_user, \
2048 &gen_op_st##width##_kernel, \
2049 &gen_op_st##width##_le_kernel, \
2050 &gen_op_st##width##_64_kernel, \
2051 &gen_op_st##width##_le_64_kernel, \
2052 &gen_op_st##width##_hypv, \
2053 &gen_op_st##width##_le_hypv, \
2054 &gen_op_st##width##_64_hypv, \
2055 &gen_op_st##width##_le_64_hypv, \
2057 /* Byte access routine are endian safe */
2058 #define gen_op_stb_le_hypv gen_op_stb_64_hypv
2059 #define gen_op_lbz_le_hypv gen_op_lbz_64_hypv
2060 #define gen_op_stb_le_64_hypv gen_op_stb_64_hypv
2061 #define gen_op_lbz_le_64_hypv gen_op_lbz_64_hypv
2063 /* Full system - 64 bits */
2064 #define OP_LD_TABLE(width) \
2065 static GenOpFunc *gen_op_l##width[] = { \
2066 &gen_op_l##width##_user, \
2067 &gen_op_l##width##_le_user, \
2068 &gen_op_l##width##_64_user, \
2069 &gen_op_l##width##_le_64_user, \
2070 &gen_op_l##width##_kernel, \
2071 &gen_op_l##width##_le_kernel, \
2072 &gen_op_l##width##_64_kernel, \
2073 &gen_op_l##width##_le_64_kernel, \
2075 #define OP_ST_TABLE(width) \
2076 static GenOpFunc *gen_op_st##width[] = { \
2077 &gen_op_st##width##_user, \
2078 &gen_op_st##width##_le_user, \
2079 &gen_op_st##width##_64_user, \
2080 &gen_op_st##width##_le_64_user, \
2081 &gen_op_st##width##_kernel, \
2082 &gen_op_st##width##_le_kernel, \
2083 &gen_op_st##width##_64_kernel, \
2084 &gen_op_st##width##_le_64_kernel, \
2087 /* Byte access routine are endian safe */
2088 #define gen_op_stb_le_64_user gen_op_stb_64_user
2089 #define gen_op_lbz_le_64_user gen_op_lbz_64_user
2090 #define gen_op_stb_le_64_kernel gen_op_stb_64_kernel
2091 #define gen_op_lbz_le_64_kernel gen_op_lbz_64_kernel
2093 /* Full system - 32 bits */
2094 #define OP_LD_TABLE(width) \
2095 static GenOpFunc *gen_op_l##width[] = { \
2096 &gen_op_l##width##_user, \
2097 &gen_op_l##width##_le_user, \
2098 &gen_op_l##width##_kernel, \
2099 &gen_op_l##width##_le_kernel, \
2101 #define OP_ST_TABLE(width) \
2102 static GenOpFunc *gen_op_st##width[] = { \
2103 &gen_op_st##width##_user, \
2104 &gen_op_st##width##_le_user, \
2105 &gen_op_st##width##_kernel, \
2106 &gen_op_st##width##_le_kernel, \
2109 /* Byte access routine are endian safe */
2110 #define gen_op_stb_le_user gen_op_stb_user
2111 #define gen_op_lbz_le_user gen_op_lbz_user
2112 #define gen_op_stb_le_kernel gen_op_stb_kernel
2113 #define gen_op_lbz_le_kernel gen_op_lbz_kernel
2116 #define GEN_LD(width, opc, type) \
2117 GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
2119 gen_addr_imm_index(ctx, 0); \
2120 op_ldst(l##width); \
2121 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2124 #define GEN_LDU(width, opc, type) \
2125 GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2127 if (unlikely(rA(ctx->opcode) == 0 || \
2128 rA(ctx->opcode) == rD(ctx->opcode))) { \
2129 GEN_EXCP_INVAL(ctx); \
2132 if (type == PPC_64B) \
2133 gen_addr_imm_index(ctx, 0x03); \
2135 gen_addr_imm_index(ctx, 0); \
2136 op_ldst(l##width); \
2137 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2138 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2141 #define GEN_LDUX(width, opc2, opc3, type) \
2142 GEN_HANDLER(l##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2144 if (unlikely(rA(ctx->opcode) == 0 || \
2145 rA(ctx->opcode) == rD(ctx->opcode))) { \
2146 GEN_EXCP_INVAL(ctx); \
2149 gen_addr_reg_index(ctx); \
2150 op_ldst(l##width); \
2151 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2152 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2155 #define GEN_LDX(width, opc2, opc3, type) \
2156 GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
2158 gen_addr_reg_index(ctx); \
2159 op_ldst(l##width); \
2160 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2163 #define GEN_LDS(width, op, type) \
2164 OP_LD_TABLE(width); \
2165 GEN_LD(width, op | 0x20, type); \
2166 GEN_LDU(width, op | 0x21, type); \
2167 GEN_LDUX(width, 0x17, op | 0x01, type); \
2168 GEN_LDX(width, 0x17, op | 0x00, type)
2170 /* lbz lbzu lbzux lbzx */
2171 GEN_LDS(bz, 0x02, PPC_INTEGER);
2172 /* lha lhau lhaux lhax */
2173 GEN_LDS(ha, 0x0A, PPC_INTEGER);
2174 /* lhz lhzu lhzux lhzx */
2175 GEN_LDS(hz, 0x08, PPC_INTEGER);
2176 /* lwz lwzu lwzux lwzx */
2177 GEN_LDS(wz, 0x00, PPC_INTEGER);
2178 #if defined(TARGET_PPC64)
2182 GEN_LDUX(wa, 0x15, 0x0B, PPC_64B);
2184 GEN_LDX(wa, 0x15, 0x0A, PPC_64B);
2186 GEN_LDUX(d, 0x15, 0x01, PPC_64B);
2188 GEN_LDX(d, 0x15, 0x00, PPC_64B);
2189 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2191 if (Rc(ctx->opcode)) {
2192 if (unlikely(rA(ctx->opcode) == 0 ||
2193 rA(ctx->opcode) == rD(ctx->opcode))) {
2194 GEN_EXCP_INVAL(ctx);
2198 gen_addr_imm_index(ctx, 0x03);
2199 if (ctx->opcode & 0x02) {
2200 /* lwa (lwau is undefined) */
2206 gen_op_store_T1_gpr(rD(ctx->opcode));
2207 if (Rc(ctx->opcode))
2208 gen_op_store_T0_gpr(rA(ctx->opcode));
2211 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2213 #if defined(CONFIG_USER_ONLY)
2214 GEN_EXCP_PRIVOPC(ctx);
2218 /* Restore CPU state */
2219 if (unlikely(ctx->supervisor == 0)) {
2220 GEN_EXCP_PRIVOPC(ctx);
2223 ra = rA(ctx->opcode);
2224 rd = rD(ctx->opcode);
2225 if (unlikely((rd & 1) || rd == ra)) {
2226 GEN_EXCP_INVAL(ctx);
2229 if (unlikely(ctx->mem_idx & 1)) {
2230 /* Little-endian mode is not handled */
2231 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2234 gen_addr_imm_index(ctx, 0x0F);
2236 gen_op_store_T1_gpr(rd);
2239 gen_op_store_T1_gpr(rd + 1);
2244 /*** Integer store ***/
2245 #define GEN_ST(width, opc, type) \
2246 GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
2248 gen_addr_imm_index(ctx, 0); \
2249 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2250 op_ldst(st##width); \
2253 #define GEN_STU(width, opc, type) \
2254 GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2256 if (unlikely(rA(ctx->opcode) == 0)) { \
2257 GEN_EXCP_INVAL(ctx); \
2260 if (type == PPC_64B) \
2261 gen_addr_imm_index(ctx, 0x03); \
2263 gen_addr_imm_index(ctx, 0); \
2264 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2265 op_ldst(st##width); \
2266 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2269 #define GEN_STUX(width, opc2, opc3, type) \
2270 GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2272 if (unlikely(rA(ctx->opcode) == 0)) { \
2273 GEN_EXCP_INVAL(ctx); \
2276 gen_addr_reg_index(ctx); \
2277 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2278 op_ldst(st##width); \
2279 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2282 #define GEN_STX(width, opc2, opc3, type) \
2283 GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
2285 gen_addr_reg_index(ctx); \
2286 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2287 op_ldst(st##width); \
2290 #define GEN_STS(width, op, type) \
2291 OP_ST_TABLE(width); \
2292 GEN_ST(width, op | 0x20, type); \
2293 GEN_STU(width, op | 0x21, type); \
2294 GEN_STUX(width, 0x17, op | 0x01, type); \
2295 GEN_STX(width, 0x17, op | 0x00, type)
2297 /* stb stbu stbux stbx */
2298 GEN_STS(b, 0x06, PPC_INTEGER);
2299 /* sth sthu sthux sthx */
2300 GEN_STS(h, 0x0C, PPC_INTEGER);
2301 /* stw stwu stwux stwx */
2302 GEN_STS(w, 0x04, PPC_INTEGER);
2303 #if defined(TARGET_PPC64)
2305 GEN_STUX(d, 0x15, 0x05, PPC_64B);
2306 GEN_STX(d, 0x15, 0x04, PPC_64B);
2307 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
2311 rs = rS(ctx->opcode);
2312 if ((ctx->opcode & 0x3) == 0x2) {
2313 #if defined(CONFIG_USER_ONLY)
2314 GEN_EXCP_PRIVOPC(ctx);
2317 if (unlikely(ctx->supervisor == 0)) {
2318 GEN_EXCP_PRIVOPC(ctx);
2321 if (unlikely(rs & 1)) {
2322 GEN_EXCP_INVAL(ctx);
2325 if (unlikely(ctx->mem_idx & 1)) {
2326 /* Little-endian mode is not handled */
2327 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2330 gen_addr_imm_index(ctx, 0x03);
2331 gen_op_load_gpr_T1(rs);
2334 gen_op_load_gpr_T1(rs + 1);
2339 if (Rc(ctx->opcode)) {
2340 if (unlikely(rA(ctx->opcode) == 0)) {
2341 GEN_EXCP_INVAL(ctx);
2345 gen_addr_imm_index(ctx, 0x03);
2346 gen_op_load_gpr_T1(rs);
2348 if (Rc(ctx->opcode))
2349 gen_op_store_T0_gpr(rA(ctx->opcode));
2353 /*** Integer load and store with byte reverse ***/
2356 GEN_LDX(hbr, 0x16, 0x18, PPC_INTEGER);
2359 GEN_LDX(wbr, 0x16, 0x10, PPC_INTEGER);
2362 GEN_STX(hbr, 0x16, 0x1C, PPC_INTEGER);
2365 GEN_STX(wbr, 0x16, 0x14, PPC_INTEGER);
2367 /*** Integer load and store multiple ***/
2368 #define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
2369 #if defined(CONFIG_USER_ONLY)
2370 /* User-mode only */
2371 static GenOpFunc1 *gen_op_lmw[] = {
2374 #if defined(TARGET_PPC64)
2376 &gen_op_lmw_le_64_raw,
2379 static GenOpFunc1 *gen_op_stmw[] = {
2381 &gen_op_stmw_le_raw,
2382 #if defined(TARGET_PPC64)
2383 &gen_op_stmw_64_raw,
2384 &gen_op_stmw_le_64_raw,
2388 #if defined(TARGET_PPC64)
2389 /* Full system - 64 bits mode */
2390 static GenOpFunc1 *gen_op_lmw[] = {
2392 &gen_op_lmw_le_user,
2393 &gen_op_lmw_64_user,
2394 &gen_op_lmw_le_64_user,
2396 &gen_op_lmw_le_kernel,
2397 &gen_op_lmw_64_kernel,
2398 &gen_op_lmw_le_64_kernel,
2399 #if defined(TARGET_PPC64H)
2401 &gen_op_lmw_le_hypv,
2402 &gen_op_lmw_64_hypv,
2403 &gen_op_lmw_le_64_hypv,
2406 static GenOpFunc1 *gen_op_stmw[] = {
2408 &gen_op_stmw_le_user,
2409 &gen_op_stmw_64_user,
2410 &gen_op_stmw_le_64_user,
2411 &gen_op_stmw_kernel,
2412 &gen_op_stmw_le_kernel,
2413 &gen_op_stmw_64_kernel,
2414 &gen_op_stmw_le_64_kernel,
2415 #if defined(TARGET_PPC64H)
2417 &gen_op_stmw_le_hypv,
2418 &gen_op_stmw_64_hypv,
2419 &gen_op_stmw_le_64_hypv,
2423 /* Full system - 32 bits mode */
2424 static GenOpFunc1 *gen_op_lmw[] = {
2426 &gen_op_lmw_le_user,
2428 &gen_op_lmw_le_kernel,
2430 static GenOpFunc1 *gen_op_stmw[] = {
2432 &gen_op_stmw_le_user,
2433 &gen_op_stmw_kernel,
2434 &gen_op_stmw_le_kernel,
2440 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
2442 /* NIP cannot be restored if the memory exception comes from an helper */
2443 gen_update_nip(ctx, ctx->nip - 4);
2444 gen_addr_imm_index(ctx, 0);
2445 op_ldstm(lmw, rD(ctx->opcode));
2449 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
2451 /* NIP cannot be restored if the memory exception comes from an helper */
2452 gen_update_nip(ctx, ctx->nip - 4);
2453 gen_addr_imm_index(ctx, 0);
2454 op_ldstm(stmw, rS(ctx->opcode));
2457 /*** Integer load and store strings ***/
2458 #define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
2459 #define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
2460 #if defined(CONFIG_USER_ONLY)
2461 /* User-mode only */
2462 static GenOpFunc1 *gen_op_lswi[] = {
2464 &gen_op_lswi_le_raw,
2465 #if defined(TARGET_PPC64)
2466 &gen_op_lswi_64_raw,
2467 &gen_op_lswi_le_64_raw,
2470 static GenOpFunc3 *gen_op_lswx[] = {
2472 &gen_op_lswx_le_raw,
2473 #if defined(TARGET_PPC64)
2474 &gen_op_lswx_64_raw,
2475 &gen_op_lswx_le_64_raw,
2478 static GenOpFunc1 *gen_op_stsw[] = {
2480 &gen_op_stsw_le_raw,
2481 #if defined(TARGET_PPC64)
2482 &gen_op_stsw_64_raw,
2483 &gen_op_stsw_le_64_raw,
2487 #if defined(TARGET_PPC64)
2488 /* Full system - 64 bits mode */
2489 static GenOpFunc1 *gen_op_lswi[] = {
2491 &gen_op_lswi_le_user,
2492 &gen_op_lswi_64_user,
2493 &gen_op_lswi_le_64_user,
2494 &gen_op_lswi_kernel,
2495 &gen_op_lswi_le_kernel,
2496 &gen_op_lswi_64_kernel,
2497 &gen_op_lswi_le_64_kernel,
2498 #if defined(TARGET_PPC64H)
2500 &gen_op_lswi_le_hypv,
2501 &gen_op_lswi_64_hypv,
2502 &gen_op_lswi_le_64_hypv,
2505 static GenOpFunc3 *gen_op_lswx[] = {
2507 &gen_op_lswx_le_user,
2508 &gen_op_lswx_64_user,
2509 &gen_op_lswx_le_64_user,
2510 &gen_op_lswx_kernel,
2511 &gen_op_lswx_le_kernel,
2512 &gen_op_lswx_64_kernel,
2513 &gen_op_lswx_le_64_kernel,
2514 #if defined(TARGET_PPC64H)
2516 &gen_op_lswx_le_hypv,
2517 &gen_op_lswx_64_hypv,
2518 &gen_op_lswx_le_64_hypv,
2521 static GenOpFunc1 *gen_op_stsw[] = {
2523 &gen_op_stsw_le_user,
2524 &gen_op_stsw_64_user,
2525 &gen_op_stsw_le_64_user,
2526 &gen_op_stsw_kernel,
2527 &gen_op_stsw_le_kernel,
2528 &gen_op_stsw_64_kernel,
2529 &gen_op_stsw_le_64_kernel,
2530 #if defined(TARGET_PPC64H)
2532 &gen_op_stsw_le_hypv,
2533 &gen_op_stsw_64_hypv,
2534 &gen_op_stsw_le_64_hypv,
2538 /* Full system - 32 bits mode */
2539 static GenOpFunc1 *gen_op_lswi[] = {
2541 &gen_op_lswi_le_user,
2542 &gen_op_lswi_kernel,
2543 &gen_op_lswi_le_kernel,
2545 static GenOpFunc3 *gen_op_lswx[] = {
2547 &gen_op_lswx_le_user,
2548 &gen_op_lswx_kernel,
2549 &gen_op_lswx_le_kernel,
2551 static GenOpFunc1 *gen_op_stsw[] = {
2553 &gen_op_stsw_le_user,
2554 &gen_op_stsw_kernel,
2555 &gen_op_stsw_le_kernel,
2561 /* PowerPC32 specification says we must generate an exception if
2562 * rA is in the range of registers to be loaded.
2563 * In an other hand, IBM says this is valid, but rA won't be loaded.
2564 * For now, I'll follow the spec...
2566 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_INTEGER)
2568 int nb = NB(ctx->opcode);
2569 int start = rD(ctx->opcode);
2570 int ra = rA(ctx->opcode);
2576 if (unlikely(((start + nr) > 32 &&
2577 start <= ra && (start + nr - 32) > ra) ||
2578 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
2579 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
2580 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_LSWX);
2583 /* NIP cannot be restored if the memory exception comes from an helper */
2584 gen_update_nip(ctx, ctx->nip - 4);
2585 gen_addr_register(ctx);
2587 op_ldsts(lswi, start);
2591 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_INTEGER)
2593 int ra = rA(ctx->opcode);
2594 int rb = rB(ctx->opcode);
2596 /* NIP cannot be restored if the memory exception comes from an helper */
2597 gen_update_nip(ctx, ctx->nip - 4);
2598 gen_addr_reg_index(ctx);
2602 gen_op_load_xer_bc();
2603 op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
2607 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_INTEGER)
2609 int nb = NB(ctx->opcode);
2611 /* NIP cannot be restored if the memory exception comes from an helper */
2612 gen_update_nip(ctx, ctx->nip - 4);
2613 gen_addr_register(ctx);
2617 op_ldsts(stsw, rS(ctx->opcode));
2621 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_INTEGER)
2623 /* NIP cannot be restored if the memory exception comes from an helper */
2624 gen_update_nip(ctx, ctx->nip - 4);
2625 gen_addr_reg_index(ctx);
2626 gen_op_load_xer_bc();
2627 op_ldsts(stsw, rS(ctx->opcode));
2630 /*** Memory synchronisation ***/
2632 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
2637 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
2642 #define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
2643 #define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
2644 #if defined(CONFIG_USER_ONLY)
2645 /* User-mode only */
2646 static GenOpFunc *gen_op_lwarx[] = {
2648 &gen_op_lwarx_le_raw,
2649 #if defined(TARGET_PPC64)
2650 &gen_op_lwarx_64_raw,
2651 &gen_op_lwarx_le_64_raw,
2654 static GenOpFunc *gen_op_stwcx[] = {
2656 &gen_op_stwcx_le_raw,
2657 #if defined(TARGET_PPC64)
2658 &gen_op_stwcx_64_raw,
2659 &gen_op_stwcx_le_64_raw,
2663 #if defined(TARGET_PPC64)
2664 /* Full system - 64 bits mode */
2665 static GenOpFunc *gen_op_lwarx[] = {
2667 &gen_op_lwarx_le_user,
2668 &gen_op_lwarx_64_user,
2669 &gen_op_lwarx_le_64_user,
2670 &gen_op_lwarx_kernel,
2671 &gen_op_lwarx_le_kernel,
2672 &gen_op_lwarx_64_kernel,
2673 &gen_op_lwarx_le_64_kernel,
2674 #if defined(TARGET_PPC64H)
2676 &gen_op_lwarx_le_hypv,
2677 &gen_op_lwarx_64_hypv,
2678 &gen_op_lwarx_le_64_hypv,
2681 static GenOpFunc *gen_op_stwcx[] = {
2683 &gen_op_stwcx_le_user,
2684 &gen_op_stwcx_64_user,
2685 &gen_op_stwcx_le_64_user,
2686 &gen_op_stwcx_kernel,
2687 &gen_op_stwcx_le_kernel,
2688 &gen_op_stwcx_64_kernel,
2689 &gen_op_stwcx_le_64_kernel,
2690 #if defined(TARGET_PPC64H)
2692 &gen_op_stwcx_le_hypv,
2693 &gen_op_stwcx_64_hypv,
2694 &gen_op_stwcx_le_64_hypv,
2698 /* Full system - 32 bits mode */
2699 static GenOpFunc *gen_op_lwarx[] = {
2701 &gen_op_lwarx_le_user,
2702 &gen_op_lwarx_kernel,
2703 &gen_op_lwarx_le_kernel,
2705 static GenOpFunc *gen_op_stwcx[] = {
2707 &gen_op_stwcx_le_user,
2708 &gen_op_stwcx_kernel,
2709 &gen_op_stwcx_le_kernel,
2715 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
2717 /* NIP cannot be restored if the memory exception comes from an helper */
2718 gen_update_nip(ctx, ctx->nip - 4);
2719 gen_addr_reg_index(ctx);
2721 gen_op_store_T1_gpr(rD(ctx->opcode));
2725 GEN_HANDLER(stwcx_, 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
2727 /* NIP cannot be restored if the memory exception comes from an helper */
2728 gen_update_nip(ctx, ctx->nip - 4);
2729 gen_addr_reg_index(ctx);
2730 gen_op_load_gpr_T1(rS(ctx->opcode));
2734 #if defined(TARGET_PPC64)
2735 #define op_ldarx() (*gen_op_ldarx[ctx->mem_idx])()
2736 #define op_stdcx() (*gen_op_stdcx[ctx->mem_idx])()
2737 #if defined(CONFIG_USER_ONLY)
2738 /* User-mode only */
2739 static GenOpFunc *gen_op_ldarx[] = {
2741 &gen_op_ldarx_le_raw,
2742 &gen_op_ldarx_64_raw,
2743 &gen_op_ldarx_le_64_raw,
2745 static GenOpFunc *gen_op_stdcx[] = {
2747 &gen_op_stdcx_le_raw,
2748 &gen_op_stdcx_64_raw,
2749 &gen_op_stdcx_le_64_raw,
2753 static GenOpFunc *gen_op_ldarx[] = {
2755 &gen_op_ldarx_le_user,
2756 &gen_op_ldarx_64_user,
2757 &gen_op_ldarx_le_64_user,
2758 &gen_op_ldarx_kernel,
2759 &gen_op_ldarx_le_kernel,
2760 &gen_op_ldarx_64_kernel,
2761 &gen_op_ldarx_le_64_kernel,
2762 #if defined(TARGET_PPC64H)
2764 &gen_op_ldarx_le_hypv,
2765 &gen_op_ldarx_64_hypv,
2766 &gen_op_ldarx_le_64_hypv,
2769 static GenOpFunc *gen_op_stdcx[] = {
2771 &gen_op_stdcx_le_user,
2772 &gen_op_stdcx_64_user,
2773 &gen_op_stdcx_le_64_user,
2774 &gen_op_stdcx_kernel,
2775 &gen_op_stdcx_le_kernel,
2776 &gen_op_stdcx_64_kernel,
2777 &gen_op_stdcx_le_64_kernel,
2778 #if defined(TARGET_PPC64H)
2780 &gen_op_stdcx_le_hypv,
2781 &gen_op_stdcx_64_hypv,
2782 &gen_op_stdcx_le_64_hypv,
2788 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
2790 /* NIP cannot be restored if the memory exception comes from an helper */
2791 gen_update_nip(ctx, ctx->nip - 4);
2792 gen_addr_reg_index(ctx);
2794 gen_op_store_T1_gpr(rD(ctx->opcode));
2798 GEN_HANDLER(stdcx_, 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
2800 /* NIP cannot be restored if the memory exception comes from an helper */
2801 gen_update_nip(ctx, ctx->nip - 4);
2802 gen_addr_reg_index(ctx);
2803 gen_op_load_gpr_T1(rS(ctx->opcode));
2806 #endif /* defined(TARGET_PPC64) */
2809 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
2814 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
2816 /* Stop translation, as the CPU is supposed to sleep from now */
2818 GEN_EXCP(ctx, EXCP_HLT, 1);
2821 /*** Floating-point load ***/
2822 #define GEN_LDF(width, opc, type) \
2823 GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
2825 if (unlikely(!ctx->fpu_enabled)) { \
2826 GEN_EXCP_NO_FP(ctx); \
2829 gen_addr_imm_index(ctx, 0); \
2830 op_ldst(l##width); \
2831 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
2834 #define GEN_LDUF(width, opc, type) \
2835 GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2837 if (unlikely(!ctx->fpu_enabled)) { \
2838 GEN_EXCP_NO_FP(ctx); \
2841 if (unlikely(rA(ctx->opcode) == 0)) { \
2842 GEN_EXCP_INVAL(ctx); \
2845 gen_addr_imm_index(ctx, 0); \
2846 op_ldst(l##width); \
2847 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
2848 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2851 #define GEN_LDUXF(width, opc, type) \
2852 GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
2854 if (unlikely(!ctx->fpu_enabled)) { \
2855 GEN_EXCP_NO_FP(ctx); \
2858 if (unlikely(rA(ctx->opcode) == 0)) { \
2859 GEN_EXCP_INVAL(ctx); \
2862 gen_addr_reg_index(ctx); \
2863 op_ldst(l##width); \
2864 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
2865 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2868 #define GEN_LDXF(width, opc2, opc3, type) \
2869 GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
2871 if (unlikely(!ctx->fpu_enabled)) { \
2872 GEN_EXCP_NO_FP(ctx); \
2875 gen_addr_reg_index(ctx); \
2876 op_ldst(l##width); \
2877 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
2880 #define GEN_LDFS(width, op, type) \
2881 OP_LD_TABLE(width); \
2882 GEN_LDF(width, op | 0x20, type); \
2883 GEN_LDUF(width, op | 0x21, type); \
2884 GEN_LDUXF(width, op | 0x01, type); \
2885 GEN_LDXF(width, 0x17, op | 0x00, type)
2887 /* lfd lfdu lfdux lfdx */
2888 GEN_LDFS(fd, 0x12, PPC_FLOAT);
2889 /* lfs lfsu lfsux lfsx */
2890 GEN_LDFS(fs, 0x10, PPC_FLOAT);
2892 /*** Floating-point store ***/
2893 #define GEN_STF(width, opc, type) \
2894 GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
2896 if (unlikely(!ctx->fpu_enabled)) { \
2897 GEN_EXCP_NO_FP(ctx); \
2900 gen_addr_imm_index(ctx, 0); \
2901 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
2902 op_ldst(st##width); \
2905 #define GEN_STUF(width, opc, type) \
2906 GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2908 if (unlikely(!ctx->fpu_enabled)) { \
2909 GEN_EXCP_NO_FP(ctx); \
2912 if (unlikely(rA(ctx->opcode) == 0)) { \
2913 GEN_EXCP_INVAL(ctx); \
2916 gen_addr_imm_index(ctx, 0); \
2917 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
2918 op_ldst(st##width); \
2919 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2922 #define GEN_STUXF(width, opc, type) \
2923 GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
2925 if (unlikely(!ctx->fpu_enabled)) { \
2926 GEN_EXCP_NO_FP(ctx); \
2929 if (unlikely(rA(ctx->opcode) == 0)) { \
2930 GEN_EXCP_INVAL(ctx); \
2933 gen_addr_reg_index(ctx); \
2934 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
2935 op_ldst(st##width); \
2936 gen_op_store_T0_gpr(rA(ctx->opcode)); \
2939 #define GEN_STXF(width, opc2, opc3, type) \
2940 GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
2942 if (unlikely(!ctx->fpu_enabled)) { \
2943 GEN_EXCP_NO_FP(ctx); \
2946 gen_addr_reg_index(ctx); \
2947 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
2948 op_ldst(st##width); \
2951 #define GEN_STFS(width, op, type) \
2952 OP_ST_TABLE(width); \
2953 GEN_STF(width, op | 0x20, type); \
2954 GEN_STUF(width, op | 0x21, type); \
2955 GEN_STUXF(width, op | 0x01, type); \
2956 GEN_STXF(width, 0x17, op | 0x00, type)
2958 /* stfd stfdu stfdux stfdx */
2959 GEN_STFS(fd, 0x16, PPC_FLOAT);
2960 /* stfs stfsu stfsux stfsx */
2961 GEN_STFS(fs, 0x14, PPC_FLOAT);
2966 GEN_STXF(fiwx, 0x17, 0x1E, PPC_FLOAT_STFIWX);
2969 static always_inline void gen_goto_tb (DisasContext *ctx, int n,
2972 TranslationBlock *tb;
2974 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
2976 gen_op_goto_tb0(TBPARAM(tb));
2978 gen_op_goto_tb1(TBPARAM(tb));
2980 #if defined(TARGET_PPC64)
2986 gen_op_set_T0((long)tb + n);
2987 if (ctx->singlestep_enabled)
2992 #if defined(TARGET_PPC64)
2999 if (ctx->singlestep_enabled)
3005 static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
3007 #if defined(TARGET_PPC64)
3008 if (ctx->sf_mode != 0 && (nip >> 32))
3009 gen_op_setlr_64(ctx->nip >> 32, ctx->nip);
3012 gen_op_setlr(ctx->nip);
3016 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3018 target_ulong li, target;
3020 /* sign extend LI */
3021 #if defined(TARGET_PPC64)
3023 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3026 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
3027 if (likely(AA(ctx->opcode) == 0))
3028 target = ctx->nip + li - 4;
3031 #if defined(TARGET_PPC64)
3033 target = (uint32_t)target;
3035 if (LK(ctx->opcode))
3036 gen_setlr(ctx, ctx->nip);
3037 gen_goto_tb(ctx, 0, target);
3038 ctx->exception = POWERPC_EXCP_BRANCH;
3045 static always_inline void gen_bcond (DisasContext *ctx, int type)
3047 target_ulong target = 0;
3049 uint32_t bo = BO(ctx->opcode);
3050 uint32_t bi = BI(ctx->opcode);
3053 if ((bo & 0x4) == 0)
3057 li = (target_long)((int16_t)(BD(ctx->opcode)));
3058 if (likely(AA(ctx->opcode) == 0)) {
3059 target = ctx->nip + li - 4;
3063 #if defined(TARGET_PPC64)
3065 target = (uint32_t)target;
3069 gen_op_movl_T1_ctr();
3073 gen_op_movl_T1_lr();
3076 if (LK(ctx->opcode))
3077 gen_setlr(ctx, ctx->nip);
3079 /* No CR condition */
3082 #if defined(TARGET_PPC64)
3084 gen_op_test_ctr_64();
3090 #if defined(TARGET_PPC64)
3092 gen_op_test_ctrz_64();
3100 if (type == BCOND_IM) {
3101 gen_goto_tb(ctx, 0, target);
3104 #if defined(TARGET_PPC64)
3116 mask = 1 << (3 - (bi & 0x03));
3117 gen_op_load_crf_T0(bi >> 2);
3121 #if defined(TARGET_PPC64)
3123 gen_op_test_ctr_true_64(mask);
3126 gen_op_test_ctr_true(mask);
3129 #if defined(TARGET_PPC64)
3131 gen_op_test_ctrz_true_64(mask);
3134 gen_op_test_ctrz_true(mask);
3139 gen_op_test_true(mask);
3145 #if defined(TARGET_PPC64)
3147 gen_op_test_ctr_false_64(mask);
3150 gen_op_test_ctr_false(mask);
3153 #if defined(TARGET_PPC64)
3155 gen_op_test_ctrz_false_64(mask);
3158 gen_op_test_ctrz_false(mask);
3163 gen_op_test_false(mask);
3168 if (type == BCOND_IM) {
3169 int l1 = gen_new_label();
3171 gen_goto_tb(ctx, 0, target);
3173 gen_goto_tb(ctx, 1, ctx->nip);
3175 #if defined(TARGET_PPC64)
3177 gen_op_btest_T1_64(ctx->nip >> 32, ctx->nip);
3180 gen_op_btest_T1(ctx->nip);
3183 if (ctx->singlestep_enabled)
3188 ctx->exception = POWERPC_EXCP_BRANCH;
3191 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3193 gen_bcond(ctx, BCOND_IM);
3196 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3198 gen_bcond(ctx, BCOND_CTR);
3201 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3203 gen_bcond(ctx, BCOND_LR);
3206 /*** Condition register logical ***/
3207 #define GEN_CRLOGIC(op, opc) \
3208 GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
3210 gen_op_load_crf_T0(crbA(ctx->opcode) >> 2); \
3211 gen_op_getbit_T0(3 - (crbA(ctx->opcode) & 0x03)); \
3212 gen_op_load_crf_T1(crbB(ctx->opcode) >> 2); \
3213 gen_op_getbit_T1(3 - (crbB(ctx->opcode) & 0x03)); \
3215 gen_op_load_crf_T1(crbD(ctx->opcode) >> 2); \
3216 gen_op_setcrfbit(~(1 << (3 - (crbD(ctx->opcode) & 0x03))), \
3217 3 - (crbD(ctx->opcode) & 0x03)); \
3218 gen_op_store_T1_crf(crbD(ctx->opcode) >> 2); \
3222 GEN_CRLOGIC(and, 0x08);
3224 GEN_CRLOGIC(andc, 0x04);
3226 GEN_CRLOGIC(eqv, 0x09);
3228 GEN_CRLOGIC(nand, 0x07);
3230 GEN_CRLOGIC(nor, 0x01);
3232 GEN_CRLOGIC(or, 0x0E);
3234 GEN_CRLOGIC(orc, 0x0D);
3236 GEN_CRLOGIC(xor, 0x06);
3238 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3240 gen_op_load_crf_T0(crfS(ctx->opcode));
3241 gen_op_store_T0_crf(crfD(ctx->opcode));
3244 /*** System linkage ***/
3245 /* rfi (supervisor only) */
3246 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
3248 #if defined(CONFIG_USER_ONLY)
3249 GEN_EXCP_PRIVOPC(ctx);
3251 /* Restore CPU state */
3252 if (unlikely(!ctx->supervisor)) {
3253 GEN_EXCP_PRIVOPC(ctx);
3261 #if defined(TARGET_PPC64)
3262 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
3264 #if defined(CONFIG_USER_ONLY)
3265 GEN_EXCP_PRIVOPC(ctx);
3267 /* Restore CPU state */
3268 if (unlikely(!ctx->supervisor)) {
3269 GEN_EXCP_PRIVOPC(ctx);
3278 #if defined(TARGET_PPC64H)
3279 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64B)
3281 #if defined(CONFIG_USER_ONLY)
3282 GEN_EXCP_PRIVOPC(ctx);
3284 /* Restore CPU state */
3285 if (unlikely(ctx->supervisor <= 1)) {
3286 GEN_EXCP_PRIVOPC(ctx);
3296 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
3300 lev = (ctx->opcode >> 5) & 0x7F;
3301 #if defined(CONFIG_USER_ONLY)
3302 GEN_EXCP(ctx, POWERPC_EXCP_SYSCALL_USER, lev);
3304 GEN_EXCP(ctx, POWERPC_EXCP_SYSCALL, lev);
3310 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
3312 gen_op_load_gpr_T0(rA(ctx->opcode));
3313 gen_op_load_gpr_T1(rB(ctx->opcode));
3314 /* Update the nip since this might generate a trap exception */
3315 gen_update_nip(ctx, ctx->nip);
3316 gen_op_tw(TO(ctx->opcode));
3320 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3322 gen_op_load_gpr_T0(rA(ctx->opcode));
3323 gen_set_T1(SIMM(ctx->opcode));
3324 /* Update the nip since this might generate a trap exception */
3325 gen_update_nip(ctx, ctx->nip);
3326 gen_op_tw(TO(ctx->opcode));
3329 #if defined(TARGET_PPC64)
3331 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3333 gen_op_load_gpr_T0(rA(ctx->opcode));
3334 gen_op_load_gpr_T1(rB(ctx->opcode));
3335 /* Update the nip since this might generate a trap exception */
3336 gen_update_nip(ctx, ctx->nip);
3337 gen_op_td(TO(ctx->opcode));
3341 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3343 gen_op_load_gpr_T0(rA(ctx->opcode));
3344 gen_set_T1(SIMM(ctx->opcode));
3345 /* Update the nip since this might generate a trap exception */
3346 gen_update_nip(ctx, ctx->nip);
3347 gen_op_td(TO(ctx->opcode));
3351 /*** Processor control ***/
3353 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3355 gen_op_load_xer_cr();
3356 gen_op_store_T0_crf(crfD(ctx->opcode));
3357 gen_op_clear_xer_ov();
3358 gen_op_clear_xer_ca();
3362 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
3366 if (likely(ctx->opcode & 0x00100000)) {
3367 crm = CRM(ctx->opcode);
3368 if (likely((crm ^ (crm - 1)) == 0)) {
3370 gen_op_load_cro(7 - crn);
3375 gen_op_store_T0_gpr(rD(ctx->opcode));
3379 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3381 #if defined(CONFIG_USER_ONLY)
3382 GEN_EXCP_PRIVREG(ctx);
3384 if (unlikely(!ctx->supervisor)) {
3385 GEN_EXCP_PRIVREG(ctx);
3389 gen_op_store_T0_gpr(rD(ctx->opcode));
3394 #define SPR_NOACCESS ((void *)(-1))
3396 static void spr_noaccess (void *opaque, int sprn)
3398 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3399 printf("ERROR: try to access SPR %d !\n", sprn);
3401 #define SPR_NOACCESS (&spr_noaccess)
3405 static always_inline void gen_op_mfspr (DisasContext *ctx)
3407 void (*read_cb)(void *opaque, int sprn);
3408 uint32_t sprn = SPR(ctx->opcode);
3410 #if !defined(CONFIG_USER_ONLY)
3411 #if defined(TARGET_PPC64H)
3412 if (ctx->supervisor == 2)
3413 read_cb = ctx->spr_cb[sprn].hea_read;
3416 if (ctx->supervisor)
3417 read_cb = ctx->spr_cb[sprn].oea_read;
3420 read_cb = ctx->spr_cb[sprn].uea_read;
3421 if (likely(read_cb != NULL)) {
3422 if (likely(read_cb != SPR_NOACCESS)) {
3423 (*read_cb)(ctx, sprn);
3424 gen_op_store_T0_gpr(rD(ctx->opcode));
3426 /* Privilege exception */
3427 if (loglevel != 0) {
3428 fprintf(logfile, "Trying to read privileged spr %d %03x\n",
3431 printf("Trying to read privileged spr %d %03x\n", sprn, sprn);
3432 GEN_EXCP_PRIVREG(ctx);
3436 if (loglevel != 0) {
3437 fprintf(logfile, "Trying to read invalid spr %d %03x\n",
3440 printf("Trying to read invalid spr %d %03x\n", sprn, sprn);
3441 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3442 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
3446 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
3452 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3458 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
3462 gen_op_load_gpr_T0(rS(ctx->opcode));
3463 crm = CRM(ctx->opcode);
3464 if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
3466 gen_op_srli_T0(crn * 4);
3467 gen_op_andi_T0(0xF);
3468 gen_op_store_cro(7 - crn);
3470 gen_op_store_cr(crm);
3475 #if defined(TARGET_PPC64)
3476 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
3478 #if defined(CONFIG_USER_ONLY)
3479 GEN_EXCP_PRIVREG(ctx);
3481 if (unlikely(!ctx->supervisor)) {
3482 GEN_EXCP_PRIVREG(ctx);
3485 gen_op_load_gpr_T0(rS(ctx->opcode));
3486 if (ctx->opcode & 0x00010000) {
3487 /* Special form that does not need any synchronisation */
3488 gen_op_update_riee();
3490 /* XXX: we need to update nip before the store
3491 * if we enter power saving mode, we will exit the loop
3492 * directly from ppc_store_msr
3494 gen_update_nip(ctx, ctx->nip);
3496 /* Must stop the translation as machine state (may have) changed */
3497 /* Note that mtmsr is not always defined as context-synchronizing */
3498 ctx->exception = POWERPC_EXCP_STOP;
3504 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3506 #if defined(CONFIG_USER_ONLY)
3507 GEN_EXCP_PRIVREG(ctx);
3509 if (unlikely(!ctx->supervisor)) {
3510 GEN_EXCP_PRIVREG(ctx);
3513 gen_op_load_gpr_T0(rS(ctx->opcode));
3514 if (ctx->opcode & 0x00010000) {
3515 /* Special form that does not need any synchronisation */
3516 gen_op_update_riee();
3518 /* XXX: we need to update nip before the store
3519 * if we enter power saving mode, we will exit the loop
3520 * directly from ppc_store_msr
3522 gen_update_nip(ctx, ctx->nip);
3523 #if defined(TARGET_PPC64)
3525 gen_op_store_msr_32();
3529 /* Must stop the translation as machine state (may have) changed */
3530 /* Note that mtmsrd is not always defined as context-synchronizing */
3531 ctx->exception = POWERPC_EXCP_STOP;
3537 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
3539 void (*write_cb)(void *opaque, int sprn);
3540 uint32_t sprn = SPR(ctx->opcode);
3542 #if !defined(CONFIG_USER_ONLY)
3543 #if defined(TARGET_PPC64H)
3544 if (ctx->supervisor == 2)
3545 write_cb = ctx->spr_cb[sprn].hea_write;
3548 if (ctx->supervisor)
3549 write_cb = ctx->spr_cb[sprn].oea_write;
3552 write_cb = ctx->spr_cb[sprn].uea_write;
3553 if (likely(write_cb != NULL)) {
3554 if (likely(write_cb != SPR_NOACCESS)) {
3555 gen_op_load_gpr_T0(rS(ctx->opcode));
3556 (*write_cb)(ctx, sprn);
3558 /* Privilege exception */
3559 if (loglevel != 0) {
3560 fprintf(logfile, "Trying to write privileged spr %d %03x\n",
3563 printf("Trying to write privileged spr %d %03x\n", sprn, sprn);
3564 GEN_EXCP_PRIVREG(ctx);
3568 if (loglevel != 0) {
3569 fprintf(logfile, "Trying to write invalid spr %d %03x\n",
3572 printf("Trying to write invalid spr %d %03x\n", sprn, sprn);
3573 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3574 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
3578 /*** Cache management ***/
3579 /* For now, all those will be implemented as nop:
3580 * this is valid, regarding the PowerPC specs...
3581 * We just have to flush tb while invalidating instruction cache lines...
3584 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
3586 gen_addr_reg_index(ctx);
3590 /* dcbi (Supervisor only) */
3591 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
3593 #if defined(CONFIG_USER_ONLY)
3594 GEN_EXCP_PRIVOPC(ctx);
3596 if (unlikely(!ctx->supervisor)) {
3597 GEN_EXCP_PRIVOPC(ctx);
3600 gen_addr_reg_index(ctx);
3601 /* XXX: specification says this should be treated as a store by the MMU */
3608 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
3610 /* XXX: specification say this is treated as a load by the MMU */
3611 gen_addr_reg_index(ctx);
3616 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
3618 /* interpreted as no-op */
3619 /* XXX: specification say this is treated as a load by the MMU
3620 * but does not generate any exception
3625 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
3627 /* interpreted as no-op */
3628 /* XXX: specification say this is treated as a load by the MMU
3629 * but does not generate any exception
3634 #define op_dcbz(n) (*gen_op_dcbz[n][ctx->mem_idx])()
3635 #if defined(CONFIG_USER_ONLY)
3636 /* User-mode only */
3637 static GenOpFunc *gen_op_dcbz[4][4] = {
3639 &gen_op_dcbz_l32_raw,
3640 &gen_op_dcbz_l32_raw,
3641 #if defined(TARGET_PPC64)
3642 &gen_op_dcbz_l32_64_raw,
3643 &gen_op_dcbz_l32_64_raw,
3647 &gen_op_dcbz_l64_raw,
3648 &gen_op_dcbz_l64_raw,
3649 #if defined(TARGET_PPC64)
3650 &gen_op_dcbz_l64_64_raw,
3651 &gen_op_dcbz_l64_64_raw,
3655 &gen_op_dcbz_l128_raw,
3656 &gen_op_dcbz_l128_raw,
3657 #if defined(TARGET_PPC64)
3658 &gen_op_dcbz_l128_64_raw,
3659 &gen_op_dcbz_l128_64_raw,
3665 #if defined(TARGET_PPC64)
3666 &gen_op_dcbz_64_raw,
3667 &gen_op_dcbz_64_raw,
3672 #if defined(TARGET_PPC64)
3673 /* Full system - 64 bits mode */
3674 static GenOpFunc *gen_op_dcbz[4][12] = {
3676 &gen_op_dcbz_l32_user,
3677 &gen_op_dcbz_l32_user,
3678 &gen_op_dcbz_l32_64_user,
3679 &gen_op_dcbz_l32_64_user,
3680 &gen_op_dcbz_l32_kernel,
3681 &gen_op_dcbz_l32_kernel,
3682 &gen_op_dcbz_l32_64_kernel,
3683 &gen_op_dcbz_l32_64_kernel,
3684 #if defined(TARGET_PPC64H)
3685 &gen_op_dcbz_l32_hypv,
3686 &gen_op_dcbz_l32_hypv,
3687 &gen_op_dcbz_l32_64_hypv,
3688 &gen_op_dcbz_l32_64_hypv,
3692 &gen_op_dcbz_l64_user,
3693 &gen_op_dcbz_l64_user,
3694 &gen_op_dcbz_l64_64_user,
3695 &gen_op_dcbz_l64_64_user,
3696 &gen_op_dcbz_l64_kernel,
3697 &gen_op_dcbz_l64_kernel,
3698 &gen_op_dcbz_l64_64_kernel,
3699 &gen_op_dcbz_l64_64_kernel,
3700 #if defined(TARGET_PPC64H)
3701 &gen_op_dcbz_l64_hypv,
3702 &gen_op_dcbz_l64_hypv,
3703 &gen_op_dcbz_l64_64_hypv,
3704 &gen_op_dcbz_l64_64_hypv,
3708 &gen_op_dcbz_l128_user,
3709 &gen_op_dcbz_l128_user,
3710 &gen_op_dcbz_l128_64_user,
3711 &gen_op_dcbz_l128_64_user,
3712 &gen_op_dcbz_l128_kernel,
3713 &gen_op_dcbz_l128_kernel,
3714 &gen_op_dcbz_l128_64_kernel,
3715 &gen_op_dcbz_l128_64_kernel,
3716 #if defined(TARGET_PPC64H)
3717 &gen_op_dcbz_l128_hypv,
3718 &gen_op_dcbz_l128_hypv,
3719 &gen_op_dcbz_l128_64_hypv,
3720 &gen_op_dcbz_l128_64_hypv,
3726 &gen_op_dcbz_64_user,
3727 &gen_op_dcbz_64_user,
3728 &gen_op_dcbz_kernel,
3729 &gen_op_dcbz_kernel,
3730 &gen_op_dcbz_64_kernel,
3731 &gen_op_dcbz_64_kernel,
3732 #if defined(TARGET_PPC64H)
3735 &gen_op_dcbz_64_hypv,
3736 &gen_op_dcbz_64_hypv,
3741 /* Full system - 32 bits mode */
3742 static GenOpFunc *gen_op_dcbz[4][4] = {
3744 &gen_op_dcbz_l32_user,
3745 &gen_op_dcbz_l32_user,
3746 &gen_op_dcbz_l32_kernel,
3747 &gen_op_dcbz_l32_kernel,
3750 &gen_op_dcbz_l64_user,
3751 &gen_op_dcbz_l64_user,
3752 &gen_op_dcbz_l64_kernel,
3753 &gen_op_dcbz_l64_kernel,
3756 &gen_op_dcbz_l128_user,
3757 &gen_op_dcbz_l128_user,
3758 &gen_op_dcbz_l128_kernel,
3759 &gen_op_dcbz_l128_kernel,
3764 &gen_op_dcbz_kernel,
3765 &gen_op_dcbz_kernel,
3771 static always_inline void handler_dcbz (DisasContext *ctx,
3772 int dcache_line_size)
3776 switch (dcache_line_size) {
3793 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
3795 gen_addr_reg_index(ctx);
3796 handler_dcbz(ctx, ctx->dcache_line_size);
3797 gen_op_check_reservation();
3800 GEN_HANDLER(dcbz_970, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
3802 gen_addr_reg_index(ctx);
3803 if (ctx->opcode & 0x00200000)
3804 handler_dcbz(ctx, ctx->dcache_line_size);
3806 handler_dcbz(ctx, -1);
3807 gen_op_check_reservation();
3811 #define op_icbi() (*gen_op_icbi[ctx->mem_idx])()
3812 #if defined(CONFIG_USER_ONLY)
3813 /* User-mode only */
3814 static GenOpFunc *gen_op_icbi[] = {
3817 #if defined(TARGET_PPC64)
3818 &gen_op_icbi_64_raw,
3819 &gen_op_icbi_64_raw,
3823 /* Full system - 64 bits mode */
3824 #if defined(TARGET_PPC64)
3825 static GenOpFunc *gen_op_icbi[] = {
3828 &gen_op_icbi_64_user,
3829 &gen_op_icbi_64_user,
3830 &gen_op_icbi_kernel,
3831 &gen_op_icbi_kernel,
3832 &gen_op_icbi_64_kernel,
3833 &gen_op_icbi_64_kernel,
3834 #if defined(TARGET_PPC64H)
3837 &gen_op_icbi_64_hypv,
3838 &gen_op_icbi_64_hypv,
3842 /* Full system - 32 bits mode */
3843 static GenOpFunc *gen_op_icbi[] = {
3846 &gen_op_icbi_kernel,
3847 &gen_op_icbi_kernel,
3852 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE)
3854 /* NIP cannot be restored if the memory exception comes from an helper */
3855 gen_update_nip(ctx, ctx->nip - 4);
3856 gen_addr_reg_index(ctx);
3862 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
3864 /* interpreted as no-op */
3865 /* XXX: specification say this is treated as a store by the MMU
3866 * but does not generate any exception
3870 /*** Segment register manipulation ***/
3871 /* Supervisor only: */
3873 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
3875 #if defined(CONFIG_USER_ONLY)
3876 GEN_EXCP_PRIVREG(ctx);
3878 if (unlikely(!ctx->supervisor)) {
3879 GEN_EXCP_PRIVREG(ctx);
3882 gen_op_set_T1(SR(ctx->opcode));
3884 gen_op_store_T0_gpr(rD(ctx->opcode));
3889 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
3891 #if defined(CONFIG_USER_ONLY)
3892 GEN_EXCP_PRIVREG(ctx);
3894 if (unlikely(!ctx->supervisor)) {
3895 GEN_EXCP_PRIVREG(ctx);
3898 gen_op_load_gpr_T1(rB(ctx->opcode));
3901 gen_op_store_T0_gpr(rD(ctx->opcode));
3906 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
3908 #if defined(CONFIG_USER_ONLY)
3909 GEN_EXCP_PRIVREG(ctx);
3911 if (unlikely(!ctx->supervisor)) {
3912 GEN_EXCP_PRIVREG(ctx);
3915 gen_op_load_gpr_T0(rS(ctx->opcode));
3916 gen_op_set_T1(SR(ctx->opcode));
3922 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
3924 #if defined(CONFIG_USER_ONLY)
3925 GEN_EXCP_PRIVREG(ctx);
3927 if (unlikely(!ctx->supervisor)) {
3928 GEN_EXCP_PRIVREG(ctx);
3931 gen_op_load_gpr_T0(rS(ctx->opcode));
3932 gen_op_load_gpr_T1(rB(ctx->opcode));
3938 #if defined(TARGET_PPC64)
3939 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
3941 GEN_HANDLER(mfsr_64b, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
3943 #if defined(CONFIG_USER_ONLY)
3944 GEN_EXCP_PRIVREG(ctx);
3946 if (unlikely(!ctx->supervisor)) {
3947 GEN_EXCP_PRIVREG(ctx);
3950 gen_op_set_T1(SR(ctx->opcode));
3952 gen_op_store_T0_gpr(rD(ctx->opcode));
3957 GEN_HANDLER(mfsrin_64b, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT_64B)
3959 #if defined(CONFIG_USER_ONLY)
3960 GEN_EXCP_PRIVREG(ctx);
3962 if (unlikely(!ctx->supervisor)) {
3963 GEN_EXCP_PRIVREG(ctx);
3966 gen_op_load_gpr_T1(rB(ctx->opcode));
3969 gen_op_store_T0_gpr(rD(ctx->opcode));
3974 GEN_HANDLER(mtsr_64b, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
3976 #if defined(CONFIG_USER_ONLY)
3977 GEN_EXCP_PRIVREG(ctx);
3979 if (unlikely(!ctx->supervisor)) {
3980 GEN_EXCP_PRIVREG(ctx);
3983 gen_op_load_gpr_T0(rS(ctx->opcode));
3984 gen_op_set_T1(SR(ctx->opcode));
3990 GEN_HANDLER(mtsrin_64b, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT_64B)
3992 #if defined(CONFIG_USER_ONLY)
3993 GEN_EXCP_PRIVREG(ctx);
3995 if (unlikely(!ctx->supervisor)) {
3996 GEN_EXCP_PRIVREG(ctx);
3999 gen_op_load_gpr_T0(rS(ctx->opcode));
4000 gen_op_load_gpr_T1(rB(ctx->opcode));
4005 #endif /* defined(TARGET_PPC64) */
4007 /*** Lookaside buffer management ***/
4008 /* Optional & supervisor only: */
4010 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
4012 #if defined(CONFIG_USER_ONLY)
4013 GEN_EXCP_PRIVOPC(ctx);
4015 if (unlikely(!ctx->supervisor)) {
4017 fprintf(logfile, "%s: ! supervisor\n", __func__);
4018 GEN_EXCP_PRIVOPC(ctx);
4026 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
4028 #if defined(CONFIG_USER_ONLY)
4029 GEN_EXCP_PRIVOPC(ctx);
4031 if (unlikely(!ctx->supervisor)) {
4032 GEN_EXCP_PRIVOPC(ctx);
4035 gen_op_load_gpr_T0(rB(ctx->opcode));
4036 #if defined(TARGET_PPC64)
4046 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
4048 #if defined(CONFIG_USER_ONLY)
4049 GEN_EXCP_PRIVOPC(ctx);
4051 if (unlikely(!ctx->supervisor)) {
4052 GEN_EXCP_PRIVOPC(ctx);
4055 /* This has no effect: it should ensure that all previous
4056 * tlbie have completed
4062 #if defined(TARGET_PPC64)
4064 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4066 #if defined(CONFIG_USER_ONLY)
4067 GEN_EXCP_PRIVOPC(ctx);
4069 if (unlikely(!ctx->supervisor)) {
4071 fprintf(logfile, "%s: ! supervisor\n", __func__);
4072 GEN_EXCP_PRIVOPC(ctx);
4080 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4082 #if defined(CONFIG_USER_ONLY)
4083 GEN_EXCP_PRIVOPC(ctx);
4085 if (unlikely(!ctx->supervisor)) {
4086 GEN_EXCP_PRIVOPC(ctx);
4089 gen_op_load_gpr_T0(rB(ctx->opcode));
4095 /*** External control ***/
4097 #define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
4098 #define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
4099 #if defined(CONFIG_USER_ONLY)
4100 /* User-mode only */
4101 static GenOpFunc *gen_op_eciwx[] = {
4103 &gen_op_eciwx_le_raw,
4104 #if defined(TARGET_PPC64)
4105 &gen_op_eciwx_64_raw,
4106 &gen_op_eciwx_le_64_raw,
4109 static GenOpFunc *gen_op_ecowx[] = {
4111 &gen_op_ecowx_le_raw,
4112 #if defined(TARGET_PPC64)
4113 &gen_op_ecowx_64_raw,
4114 &gen_op_ecowx_le_64_raw,
4118 #if defined(TARGET_PPC64)
4119 /* Full system - 64 bits mode */
4120 static GenOpFunc *gen_op_eciwx[] = {
4122 &gen_op_eciwx_le_user,
4123 &gen_op_eciwx_64_user,
4124 &gen_op_eciwx_le_64_user,
4125 &gen_op_eciwx_kernel,
4126 &gen_op_eciwx_le_kernel,
4127 &gen_op_eciwx_64_kernel,
4128 &gen_op_eciwx_le_64_kernel,
4129 #if defined(TARGET_PPC64H)
4131 &gen_op_eciwx_le_hypv,
4132 &gen_op_eciwx_64_hypv,
4133 &gen_op_eciwx_le_64_hypv,
4136 static GenOpFunc *gen_op_ecowx[] = {
4138 &gen_op_ecowx_le_user,
4139 &gen_op_ecowx_64_user,
4140 &gen_op_ecowx_le_64_user,
4141 &gen_op_ecowx_kernel,
4142 &gen_op_ecowx_le_kernel,
4143 &gen_op_ecowx_64_kernel,
4144 &gen_op_ecowx_le_64_kernel,
4145 #if defined(TARGET_PPC64H)
4147 &gen_op_ecowx_le_hypv,
4148 &gen_op_ecowx_64_hypv,
4149 &gen_op_ecowx_le_64_hypv,
4153 /* Full system - 32 bits mode */
4154 static GenOpFunc *gen_op_eciwx[] = {
4156 &gen_op_eciwx_le_user,
4157 &gen_op_eciwx_kernel,
4158 &gen_op_eciwx_le_kernel,
4160 static GenOpFunc *gen_op_ecowx[] = {
4162 &gen_op_ecowx_le_user,
4163 &gen_op_ecowx_kernel,
4164 &gen_op_ecowx_le_kernel,
4170 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4172 /* Should check EAR[E] & alignment ! */
4173 gen_addr_reg_index(ctx);
4175 gen_op_store_T0_gpr(rD(ctx->opcode));
4179 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4181 /* Should check EAR[E] & alignment ! */
4182 gen_addr_reg_index(ctx);
4183 gen_op_load_gpr_T1(rS(ctx->opcode));
4187 /* PowerPC 601 specific instructions */
4189 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
4191 gen_op_load_gpr_T0(rA(ctx->opcode));
4193 gen_op_store_T0_gpr(rD(ctx->opcode));
4194 if (unlikely(Rc(ctx->opcode) != 0))
4199 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
4201 gen_op_load_gpr_T0(rA(ctx->opcode));
4202 gen_op_POWER_abso();
4203 gen_op_store_T0_gpr(rD(ctx->opcode));
4204 if (unlikely(Rc(ctx->opcode) != 0))
4209 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
4211 gen_op_load_gpr_T0(rA(ctx->opcode));
4212 gen_op_POWER_clcs();
4213 gen_op_store_T0_gpr(rD(ctx->opcode));
4217 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
4219 gen_op_load_gpr_T0(rA(ctx->opcode));
4220 gen_op_load_gpr_T1(rB(ctx->opcode));
4222 gen_op_store_T0_gpr(rD(ctx->opcode));
4223 if (unlikely(Rc(ctx->opcode) != 0))
4228 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
4230 gen_op_load_gpr_T0(rA(ctx->opcode));
4231 gen_op_load_gpr_T1(rB(ctx->opcode));
4232 gen_op_POWER_divo();
4233 gen_op_store_T0_gpr(rD(ctx->opcode));
4234 if (unlikely(Rc(ctx->opcode) != 0))
4239 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
4241 gen_op_load_gpr_T0(rA(ctx->opcode));
4242 gen_op_load_gpr_T1(rB(ctx->opcode));
4243 gen_op_POWER_divs();
4244 gen_op_store_T0_gpr(rD(ctx->opcode));
4245 if (unlikely(Rc(ctx->opcode) != 0))
4249 /* divso - divso. */
4250 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
4252 gen_op_load_gpr_T0(rA(ctx->opcode));
4253 gen_op_load_gpr_T1(rB(ctx->opcode));
4254 gen_op_POWER_divso();
4255 gen_op_store_T0_gpr(rD(ctx->opcode));
4256 if (unlikely(Rc(ctx->opcode) != 0))
4261 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
4263 gen_op_load_gpr_T0(rA(ctx->opcode));
4264 gen_op_load_gpr_T1(rB(ctx->opcode));
4266 gen_op_store_T0_gpr(rD(ctx->opcode));
4267 if (unlikely(Rc(ctx->opcode) != 0))
4272 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
4274 gen_op_load_gpr_T0(rA(ctx->opcode));
4275 gen_op_load_gpr_T1(rB(ctx->opcode));
4276 gen_op_POWER_dozo();
4277 gen_op_store_T0_gpr(rD(ctx->opcode));
4278 if (unlikely(Rc(ctx->opcode) != 0))
4283 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4285 gen_op_load_gpr_T0(rA(ctx->opcode));
4286 gen_op_set_T1(SIMM(ctx->opcode));
4288 gen_op_store_T0_gpr(rD(ctx->opcode));
4291 /* As lscbx load from memory byte after byte, it's always endian safe */
4292 #define op_POWER_lscbx(start, ra, rb) \
4293 (*gen_op_POWER_lscbx[ctx->mem_idx])(start, ra, rb)
4294 #if defined(CONFIG_USER_ONLY)
4295 static GenOpFunc3 *gen_op_POWER_lscbx[] = {
4296 &gen_op_POWER_lscbx_raw,
4297 &gen_op_POWER_lscbx_raw,
4300 static GenOpFunc3 *gen_op_POWER_lscbx[] = {
4301 &gen_op_POWER_lscbx_user,
4302 &gen_op_POWER_lscbx_user,
4303 &gen_op_POWER_lscbx_kernel,
4304 &gen_op_POWER_lscbx_kernel,
4308 /* lscbx - lscbx. */
4309 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4311 int ra = rA(ctx->opcode);
4312 int rb = rB(ctx->opcode);
4314 gen_addr_reg_index(ctx);
4318 /* NIP cannot be restored if the memory exception comes from an helper */
4319 gen_update_nip(ctx, ctx->nip - 4);
4320 gen_op_load_xer_bc();
4321 gen_op_load_xer_cmp();
4322 op_POWER_lscbx(rD(ctx->opcode), ra, rb);
4323 gen_op_store_xer_bc();
4324 if (unlikely(Rc(ctx->opcode) != 0))
4328 /* maskg - maskg. */
4329 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4331 gen_op_load_gpr_T0(rS(ctx->opcode));
4332 gen_op_load_gpr_T1(rB(ctx->opcode));
4333 gen_op_POWER_maskg();
4334 gen_op_store_T0_gpr(rA(ctx->opcode));
4335 if (unlikely(Rc(ctx->opcode) != 0))
4339 /* maskir - maskir. */
4340 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4342 gen_op_load_gpr_T0(rA(ctx->opcode));
4343 gen_op_load_gpr_T1(rS(ctx->opcode));
4344 gen_op_load_gpr_T2(rB(ctx->opcode));
4345 gen_op_POWER_maskir();
4346 gen_op_store_T0_gpr(rA(ctx->opcode));
4347 if (unlikely(Rc(ctx->opcode) != 0))
4352 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4354 gen_op_load_gpr_T0(rA(ctx->opcode));
4355 gen_op_load_gpr_T1(rB(ctx->opcode));
4357 gen_op_store_T0_gpr(rD(ctx->opcode));
4358 if (unlikely(Rc(ctx->opcode) != 0))
4363 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4365 gen_op_load_gpr_T0(rA(ctx->opcode));
4366 gen_op_load_gpr_T1(rB(ctx->opcode));
4367 gen_op_POWER_mulo();
4368 gen_op_store_T0_gpr(rD(ctx->opcode));
4369 if (unlikely(Rc(ctx->opcode) != 0))
4374 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4376 gen_op_load_gpr_T0(rA(ctx->opcode));
4377 gen_op_POWER_nabs();
4378 gen_op_store_T0_gpr(rD(ctx->opcode));
4379 if (unlikely(Rc(ctx->opcode) != 0))
4383 /* nabso - nabso. */
4384 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4386 gen_op_load_gpr_T0(rA(ctx->opcode));
4387 gen_op_POWER_nabso();
4388 gen_op_store_T0_gpr(rD(ctx->opcode));
4389 if (unlikely(Rc(ctx->opcode) != 0))
4394 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4398 mb = MB(ctx->opcode);
4399 me = ME(ctx->opcode);
4400 gen_op_load_gpr_T0(rS(ctx->opcode));
4401 gen_op_load_gpr_T1(rA(ctx->opcode));
4402 gen_op_load_gpr_T2(rB(ctx->opcode));
4403 gen_op_POWER_rlmi(MASK(mb, me), ~MASK(mb, me));
4404 gen_op_store_T0_gpr(rA(ctx->opcode));
4405 if (unlikely(Rc(ctx->opcode) != 0))
4410 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4412 gen_op_load_gpr_T0(rS(ctx->opcode));
4413 gen_op_load_gpr_T1(rA(ctx->opcode));
4414 gen_op_load_gpr_T2(rB(ctx->opcode));
4415 gen_op_POWER_rrib();
4416 gen_op_store_T0_gpr(rA(ctx->opcode));
4417 if (unlikely(Rc(ctx->opcode) != 0))
4422 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4424 gen_op_load_gpr_T0(rS(ctx->opcode));
4425 gen_op_load_gpr_T1(rB(ctx->opcode));
4427 gen_op_store_T0_gpr(rA(ctx->opcode));
4428 if (unlikely(Rc(ctx->opcode) != 0))
4433 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4435 gen_op_load_gpr_T0(rS(ctx->opcode));
4436 gen_op_load_gpr_T1(rB(ctx->opcode));
4437 gen_op_POWER_sleq();
4438 gen_op_store_T0_gpr(rA(ctx->opcode));
4439 if (unlikely(Rc(ctx->opcode) != 0))
4444 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4446 gen_op_load_gpr_T0(rS(ctx->opcode));
4447 gen_op_set_T1(SH(ctx->opcode));
4449 gen_op_store_T0_gpr(rA(ctx->opcode));
4450 if (unlikely(Rc(ctx->opcode) != 0))
4454 /* slliq - slliq. */
4455 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4457 gen_op_load_gpr_T0(rS(ctx->opcode));
4458 gen_op_set_T1(SH(ctx->opcode));
4459 gen_op_POWER_sleq();
4460 gen_op_store_T0_gpr(rA(ctx->opcode));
4461 if (unlikely(Rc(ctx->opcode) != 0))
4466 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4468 gen_op_load_gpr_T0(rS(ctx->opcode));
4469 gen_op_load_gpr_T1(rB(ctx->opcode));
4470 gen_op_POWER_sllq();
4471 gen_op_store_T0_gpr(rA(ctx->opcode));
4472 if (unlikely(Rc(ctx->opcode) != 0))
4477 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4479 gen_op_load_gpr_T0(rS(ctx->opcode));
4480 gen_op_load_gpr_T1(rB(ctx->opcode));
4482 gen_op_store_T0_gpr(rA(ctx->opcode));
4483 if (unlikely(Rc(ctx->opcode) != 0))
4487 /* sraiq - sraiq. */
4488 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4490 gen_op_load_gpr_T0(rS(ctx->opcode));
4491 gen_op_set_T1(SH(ctx->opcode));
4492 gen_op_POWER_sraq();
4493 gen_op_store_T0_gpr(rA(ctx->opcode));
4494 if (unlikely(Rc(ctx->opcode) != 0))
4499 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4501 gen_op_load_gpr_T0(rS(ctx->opcode));
4502 gen_op_load_gpr_T1(rB(ctx->opcode));
4503 gen_op_POWER_sraq();
4504 gen_op_store_T0_gpr(rA(ctx->opcode));
4505 if (unlikely(Rc(ctx->opcode) != 0))
4510 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4512 gen_op_load_gpr_T0(rS(ctx->opcode));
4513 gen_op_load_gpr_T1(rB(ctx->opcode));
4515 gen_op_store_T0_gpr(rA(ctx->opcode));
4516 if (unlikely(Rc(ctx->opcode) != 0))
4521 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4523 gen_op_load_gpr_T0(rS(ctx->opcode));
4524 gen_op_load_gpr_T1(rB(ctx->opcode));
4525 gen_op_POWER_srea();
4526 gen_op_store_T0_gpr(rA(ctx->opcode));
4527 if (unlikely(Rc(ctx->opcode) != 0))
4532 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
4534 gen_op_load_gpr_T0(rS(ctx->opcode));
4535 gen_op_load_gpr_T1(rB(ctx->opcode));
4536 gen_op_POWER_sreq();
4537 gen_op_store_T0_gpr(rA(ctx->opcode));
4538 if (unlikely(Rc(ctx->opcode) != 0))
4543 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
4545 gen_op_load_gpr_T0(rS(ctx->opcode));
4546 gen_op_set_T1(SH(ctx->opcode));
4548 gen_op_store_T0_gpr(rA(ctx->opcode));
4549 if (unlikely(Rc(ctx->opcode) != 0))
4554 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
4556 gen_op_load_gpr_T0(rS(ctx->opcode));
4557 gen_op_load_gpr_T1(rB(ctx->opcode));
4558 gen_op_set_T1(SH(ctx->opcode));
4559 gen_op_POWER_srlq();
4560 gen_op_store_T0_gpr(rA(ctx->opcode));
4561 if (unlikely(Rc(ctx->opcode) != 0))
4566 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
4568 gen_op_load_gpr_T0(rS(ctx->opcode));
4569 gen_op_load_gpr_T1(rB(ctx->opcode));
4570 gen_op_POWER_srlq();
4571 gen_op_store_T0_gpr(rA(ctx->opcode));
4572 if (unlikely(Rc(ctx->opcode) != 0))
4577 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
4579 gen_op_load_gpr_T0(rS(ctx->opcode));
4580 gen_op_load_gpr_T1(rB(ctx->opcode));
4582 gen_op_store_T0_gpr(rA(ctx->opcode));
4583 if (unlikely(Rc(ctx->opcode) != 0))
4587 /* PowerPC 602 specific instructions */
4589 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
4592 GEN_EXCP_INVAL(ctx);
4596 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
4599 GEN_EXCP_INVAL(ctx);
4603 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
4605 #if defined(CONFIG_USER_ONLY)
4606 GEN_EXCP_PRIVOPC(ctx);
4608 if (unlikely(!ctx->supervisor)) {
4609 GEN_EXCP_PRIVOPC(ctx);
4612 gen_op_load_gpr_T0(rA(ctx->opcode));
4614 gen_op_store_T0_gpr(rD(ctx->opcode));
4618 /* 602 - 603 - G2 TLB management */
4620 GEN_HANDLER(tlbld_6xx, 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
4622 #if defined(CONFIG_USER_ONLY)
4623 GEN_EXCP_PRIVOPC(ctx);
4625 if (unlikely(!ctx->supervisor)) {
4626 GEN_EXCP_PRIVOPC(ctx);
4629 gen_op_load_gpr_T0(rB(ctx->opcode));
4635 GEN_HANDLER(tlbli_6xx, 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
4637 #if defined(CONFIG_USER_ONLY)
4638 GEN_EXCP_PRIVOPC(ctx);
4640 if (unlikely(!ctx->supervisor)) {
4641 GEN_EXCP_PRIVOPC(ctx);
4644 gen_op_load_gpr_T0(rB(ctx->opcode));
4649 /* 74xx TLB management */
4651 GEN_HANDLER(tlbld_74xx, 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
4653 #if defined(CONFIG_USER_ONLY)
4654 GEN_EXCP_PRIVOPC(ctx);
4656 if (unlikely(!ctx->supervisor)) {
4657 GEN_EXCP_PRIVOPC(ctx);
4660 gen_op_load_gpr_T0(rB(ctx->opcode));
4661 gen_op_74xx_tlbld();
4666 GEN_HANDLER(tlbli_74xx, 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
4668 #if defined(CONFIG_USER_ONLY)
4669 GEN_EXCP_PRIVOPC(ctx);
4671 if (unlikely(!ctx->supervisor)) {
4672 GEN_EXCP_PRIVOPC(ctx);
4675 gen_op_load_gpr_T0(rB(ctx->opcode));
4676 gen_op_74xx_tlbli();
4680 /* POWER instructions not in PowerPC 601 */
4682 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
4684 /* Cache line flush: implemented as no-op */
4688 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
4690 /* Cache line invalidate: privileged and treated as no-op */
4691 #if defined(CONFIG_USER_ONLY)
4692 GEN_EXCP_PRIVOPC(ctx);
4694 if (unlikely(!ctx->supervisor)) {
4695 GEN_EXCP_PRIVOPC(ctx);
4702 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
4704 /* Data cache line store: treated as no-op */
4707 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
4709 #if defined(CONFIG_USER_ONLY)
4710 GEN_EXCP_PRIVOPC(ctx);
4712 if (unlikely(!ctx->supervisor)) {
4713 GEN_EXCP_PRIVOPC(ctx);
4716 int ra = rA(ctx->opcode);
4717 int rd = rD(ctx->opcode);
4719 gen_addr_reg_index(ctx);
4720 gen_op_POWER_mfsri();
4721 gen_op_store_T0_gpr(rd);
4722 if (ra != 0 && ra != rd)
4723 gen_op_store_T1_gpr(ra);
4727 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
4729 #if defined(CONFIG_USER_ONLY)
4730 GEN_EXCP_PRIVOPC(ctx);
4732 if (unlikely(!ctx->supervisor)) {
4733 GEN_EXCP_PRIVOPC(ctx);
4736 gen_addr_reg_index(ctx);
4738 gen_op_store_T0_gpr(rD(ctx->opcode));
4742 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
4744 #if defined(CONFIG_USER_ONLY)
4745 GEN_EXCP_PRIVOPC(ctx);
4747 if (unlikely(!ctx->supervisor)) {
4748 GEN_EXCP_PRIVOPC(ctx);
4751 gen_op_POWER_rfsvc();
4756 /* svc is not implemented for now */
4758 /* POWER2 specific instructions */
4759 /* Quad manipulation (load/store two floats at a time) */
4760 #define op_POWER2_lfq() (*gen_op_POWER2_lfq[ctx->mem_idx])()
4761 #define op_POWER2_stfq() (*gen_op_POWER2_stfq[ctx->mem_idx])()
4762 #if defined(CONFIG_USER_ONLY)
4763 static GenOpFunc *gen_op_POWER2_lfq[] = {
4764 &gen_op_POWER2_lfq_le_raw,
4765 &gen_op_POWER2_lfq_raw,
4767 static GenOpFunc *gen_op_POWER2_stfq[] = {
4768 &gen_op_POWER2_stfq_le_raw,
4769 &gen_op_POWER2_stfq_raw,
4772 static GenOpFunc *gen_op_POWER2_lfq[] = {
4773 &gen_op_POWER2_lfq_le_user,
4774 &gen_op_POWER2_lfq_user,
4775 &gen_op_POWER2_lfq_le_kernel,
4776 &gen_op_POWER2_lfq_kernel,
4778 static GenOpFunc *gen_op_POWER2_stfq[] = {
4779 &gen_op_POWER2_stfq_le_user,
4780 &gen_op_POWER2_stfq_user,
4781 &gen_op_POWER2_stfq_le_kernel,
4782 &gen_op_POWER2_stfq_kernel,
4787 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4789 /* NIP cannot be restored if the memory exception comes from an helper */
4790 gen_update_nip(ctx, ctx->nip - 4);
4791 gen_addr_imm_index(ctx, 0);
4793 gen_op_store_FT0_fpr(rD(ctx->opcode));
4794 gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4798 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4800 int ra = rA(ctx->opcode);
4802 /* NIP cannot be restored if the memory exception comes from an helper */
4803 gen_update_nip(ctx, ctx->nip - 4);
4804 gen_addr_imm_index(ctx, 0);
4806 gen_op_store_FT0_fpr(rD(ctx->opcode));
4807 gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4809 gen_op_store_T0_gpr(ra);
4813 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
4815 int ra = rA(ctx->opcode);
4817 /* NIP cannot be restored if the memory exception comes from an helper */
4818 gen_update_nip(ctx, ctx->nip - 4);
4819 gen_addr_reg_index(ctx);
4821 gen_op_store_FT0_fpr(rD(ctx->opcode));
4822 gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4824 gen_op_store_T0_gpr(ra);
4828 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
4830 /* NIP cannot be restored if the memory exception comes from an helper */
4831 gen_update_nip(ctx, ctx->nip - 4);
4832 gen_addr_reg_index(ctx);
4834 gen_op_store_FT0_fpr(rD(ctx->opcode));
4835 gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4839 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4841 /* NIP cannot be restored if the memory exception comes from an helper */
4842 gen_update_nip(ctx, ctx->nip - 4);
4843 gen_addr_imm_index(ctx, 0);
4844 gen_op_load_fpr_FT0(rS(ctx->opcode));
4845 gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
4850 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4852 int ra = rA(ctx->opcode);
4854 /* NIP cannot be restored if the memory exception comes from an helper */
4855 gen_update_nip(ctx, ctx->nip - 4);
4856 gen_addr_imm_index(ctx, 0);
4857 gen_op_load_fpr_FT0(rS(ctx->opcode));
4858 gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
4861 gen_op_store_T0_gpr(ra);
4865 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
4867 int ra = rA(ctx->opcode);
4869 /* NIP cannot be restored if the memory exception comes from an helper */
4870 gen_update_nip(ctx, ctx->nip - 4);
4871 gen_addr_reg_index(ctx);
4872 gen_op_load_fpr_FT0(rS(ctx->opcode));
4873 gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
4876 gen_op_store_T0_gpr(ra);
4880 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
4882 /* NIP cannot be restored if the memory exception comes from an helper */
4883 gen_update_nip(ctx, ctx->nip - 4);
4884 gen_addr_reg_index(ctx);
4885 gen_op_load_fpr_FT0(rS(ctx->opcode));
4886 gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
4890 /* BookE specific instructions */
4891 /* XXX: not implemented on 440 ? */
4892 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_BOOKE_EXT)
4895 GEN_EXCP_INVAL(ctx);
4898 /* XXX: not implemented on 440 ? */
4899 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_BOOKE_EXT)
4901 #if defined(CONFIG_USER_ONLY)
4902 GEN_EXCP_PRIVOPC(ctx);
4904 if (unlikely(!ctx->supervisor)) {
4905 GEN_EXCP_PRIVOPC(ctx);
4908 gen_addr_reg_index(ctx);
4909 /* Use the same micro-ops as for tlbie */
4910 #if defined(TARGET_PPC64)
4919 /* All 405 MAC instructions are translated here */
4920 static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
4922 int ra, int rb, int rt, int Rc)
4924 gen_op_load_gpr_T0(ra);
4925 gen_op_load_gpr_T1(rb);
4926 switch (opc3 & 0x0D) {
4928 /* macchw - macchw. - macchwo - macchwo. */
4929 /* macchws - macchws. - macchwso - macchwso. */
4930 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
4931 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
4932 /* mulchw - mulchw. */
4933 gen_op_405_mulchw();
4936 /* macchwu - macchwu. - macchwuo - macchwuo. */
4937 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
4938 /* mulchwu - mulchwu. */
4939 gen_op_405_mulchwu();
4942 /* machhw - machhw. - machhwo - machhwo. */
4943 /* machhws - machhws. - machhwso - machhwso. */
4944 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
4945 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
4946 /* mulhhw - mulhhw. */
4947 gen_op_405_mulhhw();
4950 /* machhwu - machhwu. - machhwuo - machhwuo. */
4951 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
4952 /* mulhhwu - mulhhwu. */
4953 gen_op_405_mulhhwu();
4956 /* maclhw - maclhw. - maclhwo - maclhwo. */
4957 /* maclhws - maclhws. - maclhwso - maclhwso. */
4958 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
4959 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
4960 /* mullhw - mullhw. */
4961 gen_op_405_mullhw();
4964 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
4965 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
4966 /* mullhwu - mullhwu. */
4967 gen_op_405_mullhwu();
4971 /* nmultiply-and-accumulate (0x0E) */
4975 /* (n)multiply-and-accumulate (0x0C - 0x0E) */
4976 gen_op_load_gpr_T2(rt);
4977 gen_op_move_T1_T0();
4978 gen_op_405_add_T0_T2();
4981 /* Check overflow */
4983 gen_op_405_check_ov();
4985 gen_op_405_check_ovu();
4990 gen_op_405_check_sat();
4992 gen_op_405_check_satu();
4994 gen_op_store_T0_gpr(rt);
4995 if (unlikely(Rc) != 0) {
5001 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5002 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
5004 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5005 rD(ctx->opcode), Rc(ctx->opcode)); \
5008 /* macchw - macchw. */
5009 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5010 /* macchwo - macchwo. */
5011 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5012 /* macchws - macchws. */
5013 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5014 /* macchwso - macchwso. */
5015 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5016 /* macchwsu - macchwsu. */
5017 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5018 /* macchwsuo - macchwsuo. */
5019 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5020 /* macchwu - macchwu. */
5021 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5022 /* macchwuo - macchwuo. */
5023 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5024 /* machhw - machhw. */
5025 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5026 /* machhwo - machhwo. */
5027 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5028 /* machhws - machhws. */
5029 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5030 /* machhwso - machhwso. */
5031 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5032 /* machhwsu - machhwsu. */
5033 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5034 /* machhwsuo - machhwsuo. */
5035 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5036 /* machhwu - machhwu. */
5037 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5038 /* machhwuo - machhwuo. */
5039 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5040 /* maclhw - maclhw. */
5041 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5042 /* maclhwo - maclhwo. */
5043 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5044 /* maclhws - maclhws. */
5045 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5046 /* maclhwso - maclhwso. */
5047 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5048 /* maclhwu - maclhwu. */
5049 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5050 /* maclhwuo - maclhwuo. */
5051 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5052 /* maclhwsu - maclhwsu. */
5053 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5054 /* maclhwsuo - maclhwsuo. */
5055 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5056 /* nmacchw - nmacchw. */
5057 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5058 /* nmacchwo - nmacchwo. */
5059 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5060 /* nmacchws - nmacchws. */
5061 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5062 /* nmacchwso - nmacchwso. */
5063 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5064 /* nmachhw - nmachhw. */
5065 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5066 /* nmachhwo - nmachhwo. */
5067 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5068 /* nmachhws - nmachhws. */
5069 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5070 /* nmachhwso - nmachhwso. */
5071 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5072 /* nmaclhw - nmaclhw. */
5073 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5074 /* nmaclhwo - nmaclhwo. */
5075 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5076 /* nmaclhws - nmaclhws. */
5077 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5078 /* nmaclhwso - nmaclhwso. */
5079 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5081 /* mulchw - mulchw. */
5082 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5083 /* mulchwu - mulchwu. */
5084 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5085 /* mulhhw - mulhhw. */
5086 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5087 /* mulhhwu - mulhhwu. */
5088 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5089 /* mullhw - mullhw. */
5090 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5091 /* mullhwu - mullhwu. */
5092 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5095 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_EMB_COMMON)
5097 #if defined(CONFIG_USER_ONLY)
5098 GEN_EXCP_PRIVREG(ctx);
5100 uint32_t dcrn = SPR(ctx->opcode);
5102 if (unlikely(!ctx->supervisor)) {
5103 GEN_EXCP_PRIVREG(ctx);
5106 gen_op_set_T0(dcrn);
5108 gen_op_store_T0_gpr(rD(ctx->opcode));
5113 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_EMB_COMMON)
5115 #if defined(CONFIG_USER_ONLY)
5116 GEN_EXCP_PRIVREG(ctx);
5118 uint32_t dcrn = SPR(ctx->opcode);
5120 if (unlikely(!ctx->supervisor)) {
5121 GEN_EXCP_PRIVREG(ctx);
5124 gen_op_set_T0(dcrn);
5125 gen_op_load_gpr_T1(rS(ctx->opcode));
5131 /* XXX: not implemented on 440 ? */
5132 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_BOOKE_EXT)
5134 #if defined(CONFIG_USER_ONLY)
5135 GEN_EXCP_PRIVREG(ctx);
5137 if (unlikely(!ctx->supervisor)) {
5138 GEN_EXCP_PRIVREG(ctx);
5141 gen_op_load_gpr_T0(rA(ctx->opcode));
5143 gen_op_store_T0_gpr(rD(ctx->opcode));
5144 /* Note: Rc update flag set leads to undefined state of Rc0 */
5149 /* XXX: not implemented on 440 ? */
5150 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_BOOKE_EXT)
5152 #if defined(CONFIG_USER_ONLY)
5153 GEN_EXCP_PRIVREG(ctx);
5155 if (unlikely(!ctx->supervisor)) {
5156 GEN_EXCP_PRIVREG(ctx);
5159 gen_op_load_gpr_T0(rA(ctx->opcode));
5160 gen_op_load_gpr_T1(rS(ctx->opcode));
5162 /* Note: Rc update flag set leads to undefined state of Rc0 */
5166 /* mfdcrux (PPC 460) : user-mode access to DCR */
5167 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
5169 gen_op_load_gpr_T0(rA(ctx->opcode));
5171 gen_op_store_T0_gpr(rD(ctx->opcode));
5172 /* Note: Rc update flag set leads to undefined state of Rc0 */
5175 /* mtdcrux (PPC 460) : user-mode access to DCR */
5176 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
5178 gen_op_load_gpr_T0(rA(ctx->opcode));
5179 gen_op_load_gpr_T1(rS(ctx->opcode));
5181 /* Note: Rc update flag set leads to undefined state of Rc0 */
5185 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
5187 #if defined(CONFIG_USER_ONLY)
5188 GEN_EXCP_PRIVOPC(ctx);
5190 if (unlikely(!ctx->supervisor)) {
5191 GEN_EXCP_PRIVOPC(ctx);
5194 /* interpreted as no-op */
5199 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
5201 #if defined(CONFIG_USER_ONLY)
5202 GEN_EXCP_PRIVOPC(ctx);
5204 if (unlikely(!ctx->supervisor)) {
5205 GEN_EXCP_PRIVOPC(ctx);
5208 gen_addr_reg_index(ctx);
5210 gen_op_store_T0_gpr(rD(ctx->opcode));
5215 GEN_HANDLER(icbt_40x, 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
5217 /* interpreted as no-op */
5218 /* XXX: specification say this is treated as a load by the MMU
5219 * but does not generate any exception
5224 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
5226 #if defined(CONFIG_USER_ONLY)
5227 GEN_EXCP_PRIVOPC(ctx);
5229 if (unlikely(!ctx->supervisor)) {
5230 GEN_EXCP_PRIVOPC(ctx);
5233 /* interpreted as no-op */
5238 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
5240 #if defined(CONFIG_USER_ONLY)
5241 GEN_EXCP_PRIVOPC(ctx);
5243 if (unlikely(!ctx->supervisor)) {
5244 GEN_EXCP_PRIVOPC(ctx);
5247 /* interpreted as no-op */
5251 /* rfci (supervisor only) */
5252 GEN_HANDLER(rfci_40x, 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
5254 #if defined(CONFIG_USER_ONLY)
5255 GEN_EXCP_PRIVOPC(ctx);
5257 if (unlikely(!ctx->supervisor)) {
5258 GEN_EXCP_PRIVOPC(ctx);
5261 /* Restore CPU state */
5267 GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
5269 #if defined(CONFIG_USER_ONLY)
5270 GEN_EXCP_PRIVOPC(ctx);
5272 if (unlikely(!ctx->supervisor)) {
5273 GEN_EXCP_PRIVOPC(ctx);
5276 /* Restore CPU state */
5282 /* BookE specific */
5283 /* XXX: not implemented on 440 ? */
5284 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_BOOKE_EXT)
5286 #if defined(CONFIG_USER_ONLY)
5287 GEN_EXCP_PRIVOPC(ctx);
5289 if (unlikely(!ctx->supervisor)) {
5290 GEN_EXCP_PRIVOPC(ctx);
5293 /* Restore CPU state */
5299 /* XXX: not implemented on 440 ? */
5300 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
5302 #if defined(CONFIG_USER_ONLY)
5303 GEN_EXCP_PRIVOPC(ctx);
5305 if (unlikely(!ctx->supervisor)) {
5306 GEN_EXCP_PRIVOPC(ctx);
5309 /* Restore CPU state */
5315 /* TLB management - PowerPC 405 implementation */
5317 GEN_HANDLER(tlbre_40x, 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
5319 #if defined(CONFIG_USER_ONLY)
5320 GEN_EXCP_PRIVOPC(ctx);
5322 if (unlikely(!ctx->supervisor)) {
5323 GEN_EXCP_PRIVOPC(ctx);
5326 switch (rB(ctx->opcode)) {
5328 gen_op_load_gpr_T0(rA(ctx->opcode));
5329 gen_op_4xx_tlbre_hi();
5330 gen_op_store_T0_gpr(rD(ctx->opcode));
5333 gen_op_load_gpr_T0(rA(ctx->opcode));
5334 gen_op_4xx_tlbre_lo();
5335 gen_op_store_T0_gpr(rD(ctx->opcode));
5338 GEN_EXCP_INVAL(ctx);
5344 /* tlbsx - tlbsx. */
5345 GEN_HANDLER(tlbsx_40x, 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
5347 #if defined(CONFIG_USER_ONLY)
5348 GEN_EXCP_PRIVOPC(ctx);
5350 if (unlikely(!ctx->supervisor)) {
5351 GEN_EXCP_PRIVOPC(ctx);
5354 gen_addr_reg_index(ctx);
5356 if (Rc(ctx->opcode))
5357 gen_op_4xx_tlbsx_check();
5358 gen_op_store_T0_gpr(rD(ctx->opcode));
5363 GEN_HANDLER(tlbwe_40x, 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
5365 #if defined(CONFIG_USER_ONLY)
5366 GEN_EXCP_PRIVOPC(ctx);
5368 if (unlikely(!ctx->supervisor)) {
5369 GEN_EXCP_PRIVOPC(ctx);
5372 switch (rB(ctx->opcode)) {
5374 gen_op_load_gpr_T0(rA(ctx->opcode));
5375 gen_op_load_gpr_T1(rS(ctx->opcode));
5376 gen_op_4xx_tlbwe_hi();
5379 gen_op_load_gpr_T0(rA(ctx->opcode));
5380 gen_op_load_gpr_T1(rS(ctx->opcode));
5381 gen_op_4xx_tlbwe_lo();
5384 GEN_EXCP_INVAL(ctx);
5390 /* TLB management - PowerPC 440 implementation */
5392 GEN_HANDLER(tlbre_440, 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5394 #if defined(CONFIG_USER_ONLY)
5395 GEN_EXCP_PRIVOPC(ctx);
5397 if (unlikely(!ctx->supervisor)) {
5398 GEN_EXCP_PRIVOPC(ctx);
5401 switch (rB(ctx->opcode)) {
5405 gen_op_load_gpr_T0(rA(ctx->opcode));
5406 gen_op_440_tlbre(rB(ctx->opcode));
5407 gen_op_store_T0_gpr(rD(ctx->opcode));
5410 GEN_EXCP_INVAL(ctx);
5416 /* tlbsx - tlbsx. */
5417 GEN_HANDLER(tlbsx_440, 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5419 #if defined(CONFIG_USER_ONLY)
5420 GEN_EXCP_PRIVOPC(ctx);
5422 if (unlikely(!ctx->supervisor)) {
5423 GEN_EXCP_PRIVOPC(ctx);
5426 gen_addr_reg_index(ctx);
5428 if (Rc(ctx->opcode))
5429 gen_op_4xx_tlbsx_check();
5430 gen_op_store_T0_gpr(rD(ctx->opcode));
5435 GEN_HANDLER(tlbwe_440, 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5437 #if defined(CONFIG_USER_ONLY)
5438 GEN_EXCP_PRIVOPC(ctx);
5440 if (unlikely(!ctx->supervisor)) {
5441 GEN_EXCP_PRIVOPC(ctx);
5444 switch (rB(ctx->opcode)) {
5448 gen_op_load_gpr_T0(rA(ctx->opcode));
5449 gen_op_load_gpr_T1(rS(ctx->opcode));
5450 gen_op_440_tlbwe(rB(ctx->opcode));
5453 GEN_EXCP_INVAL(ctx);
5460 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_EMB_COMMON)
5462 #if defined(CONFIG_USER_ONLY)
5463 GEN_EXCP_PRIVOPC(ctx);
5465 if (unlikely(!ctx->supervisor)) {
5466 GEN_EXCP_PRIVOPC(ctx);
5469 gen_op_load_gpr_T0(rD(ctx->opcode));
5471 /* Stop translation to have a chance to raise an exception
5472 * if we just set msr_ee to 1
5479 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_EMB_COMMON)
5481 #if defined(CONFIG_USER_ONLY)
5482 GEN_EXCP_PRIVOPC(ctx);
5484 if (unlikely(!ctx->supervisor)) {
5485 GEN_EXCP_PRIVOPC(ctx);
5488 gen_op_set_T0(ctx->opcode & 0x00010000);
5490 /* Stop translation to have a chance to raise an exception
5491 * if we just set msr_ee to 1
5497 /* PowerPC 440 specific instructions */
5499 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
5501 gen_op_load_gpr_T0(rS(ctx->opcode));
5502 gen_op_load_gpr_T1(rB(ctx->opcode));
5504 gen_op_store_T0_gpr(rA(ctx->opcode));
5505 gen_op_store_xer_bc();
5506 if (Rc(ctx->opcode)) {
5507 gen_op_440_dlmzb_update_Rc();
5508 gen_op_store_T0_crf(0);
5512 /* mbar replaces eieio on 440 */
5513 GEN_HANDLER(mbar, 0x1F, 0x16, 0x13, 0x001FF801, PPC_BOOKE)
5515 /* interpreted as no-op */
5518 /* msync replaces sync on 440 */
5519 GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
5521 /* interpreted as no-op */
5525 GEN_HANDLER(icbt_440, 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
5527 /* interpreted as no-op */
5528 /* XXX: specification say this is treated as a load by the MMU
5529 * but does not generate any exception
5533 #if defined(TARGET_PPCEMB)
5534 /*** SPE extension ***/
5536 /* Register moves */
5537 GEN32(gen_op_load_gpr64_T0, gen_op_load_gpr64_T0_gpr);
5538 GEN32(gen_op_load_gpr64_T1, gen_op_load_gpr64_T1_gpr);
5540 GEN32(gen_op_load_gpr64_T2, gen_op_load_gpr64_T2_gpr);
5543 GEN32(gen_op_store_T0_gpr64, gen_op_store_T0_gpr64_gpr);
5544 GEN32(gen_op_store_T1_gpr64, gen_op_store_T1_gpr64_gpr);
5546 GEN32(gen_op_store_T2_gpr64, gen_op_store_T2_gpr64_gpr);
5549 #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
5550 GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
5552 if (Rc(ctx->opcode)) \
5558 /* Handler for undefined SPE opcodes */
5559 static always_inline void gen_speundef (DisasContext *ctx)
5561 GEN_EXCP_INVAL(ctx);
5564 /* SPE load and stores */
5565 static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, int sh)
5567 target_long simm = rB(ctx->opcode);
5569 if (rA(ctx->opcode) == 0) {
5570 gen_set_T0(simm << sh);
5572 gen_op_load_gpr_T0(rA(ctx->opcode));
5573 if (likely(simm != 0))
5574 gen_op_addi(simm << sh);
5578 #define op_spe_ldst(name) (*gen_op_##name[ctx->mem_idx])()
5579 #if defined(CONFIG_USER_ONLY)
5580 #if defined(TARGET_PPC64)
5581 /* User-mode only - 64 bits mode */
5582 #define OP_SPE_LD_TABLE(name) \
5583 static GenOpFunc *gen_op_spe_l##name[] = { \
5584 &gen_op_spe_l##name##_raw, \
5585 &gen_op_spe_l##name##_le_raw, \
5586 &gen_op_spe_l##name##_64_raw, \
5587 &gen_op_spe_l##name##_le_64_raw, \
5589 #define OP_SPE_ST_TABLE(name) \
5590 static GenOpFunc *gen_op_spe_st##name[] = { \
5591 &gen_op_spe_st##name##_raw, \
5592 &gen_op_spe_st##name##_le_raw, \
5593 &gen_op_spe_st##name##_64_raw, \
5594 &gen_op_spe_st##name##_le_64_raw, \
5596 #else /* defined(TARGET_PPC64) */
5597 /* User-mode only - 32 bits mode */
5598 #define OP_SPE_LD_TABLE(name) \
5599 static GenOpFunc *gen_op_spe_l##name[] = { \
5600 &gen_op_spe_l##name##_raw, \
5601 &gen_op_spe_l##name##_le_raw, \
5603 #define OP_SPE_ST_TABLE(name) \
5604 static GenOpFunc *gen_op_spe_st##name[] = { \
5605 &gen_op_spe_st##name##_raw, \
5606 &gen_op_spe_st##name##_le_raw, \
5608 #endif /* defined(TARGET_PPC64) */
5609 #else /* defined(CONFIG_USER_ONLY) */
5610 #if defined(TARGET_PPC64H)
5611 /* Full system with hypervisor mode */
5612 #define OP_SPE_LD_TABLE(name) \
5613 static GenOpFunc *gen_op_spe_l##name[] = { \
5614 &gen_op_spe_l##name##_user, \
5615 &gen_op_spe_l##name##_le_user, \
5616 &gen_op_spe_l##name##_64_user, \
5617 &gen_op_spe_l##name##_le_64_user, \
5618 &gen_op_spe_l##name##_kernel, \
5619 &gen_op_spe_l##name##_le_kernel, \
5620 &gen_op_spe_l##name##_64_kernel, \
5621 &gen_op_spe_l##name##_le_64_kernel, \
5622 &gen_op_spe_l##name##_hypv, \
5623 &gen_op_spe_l##name##_le_hypv, \
5624 &gen_op_spe_l##name##_64_hypv, \
5625 &gen_op_spe_l##name##_le_64_hypv, \
5627 #define OP_SPE_ST_TABLE(name) \
5628 static GenOpFunc *gen_op_spe_st##name[] = { \
5629 &gen_op_spe_st##name##_user, \
5630 &gen_op_spe_st##name##_le_user, \
5631 &gen_op_spe_st##name##_64_user, \
5632 &gen_op_spe_st##name##_le_64_user, \
5633 &gen_op_spe_st##name##_kernel, \
5634 &gen_op_spe_st##name##_le_kernel, \
5635 &gen_op_spe_st##name##_64_kernel, \
5636 &gen_op_spe_st##name##_le_64_kernel, \
5637 &gen_op_spe_st##name##_hypv, \
5638 &gen_op_spe_st##name##_le_hypv, \
5639 &gen_op_spe_st##name##_64_hypv, \
5640 &gen_op_spe_st##name##_le_64_hypv, \
5642 #elif defined(TARGET_PPC64)
5643 /* Full system - 64 bits mode */
5644 #define OP_SPE_LD_TABLE(name) \
5645 static GenOpFunc *gen_op_spe_l##name[] = { \
5646 &gen_op_spe_l##name##_user, \
5647 &gen_op_spe_l##name##_le_user, \
5648 &gen_op_spe_l##name##_64_user, \
5649 &gen_op_spe_l##name##_le_64_user, \
5650 &gen_op_spe_l##name##_kernel, \
5651 &gen_op_spe_l##name##_le_kernel, \
5652 &gen_op_spe_l##name##_64_kernel, \
5653 &gen_op_spe_l##name##_le_64_kernel, \
5655 #define OP_SPE_ST_TABLE(name) \
5656 static GenOpFunc *gen_op_spe_st##name[] = { \
5657 &gen_op_spe_st##name##_user, \
5658 &gen_op_spe_st##name##_le_user, \
5659 &gen_op_spe_st##name##_64_user, \
5660 &gen_op_spe_st##name##_le_64_user, \
5661 &gen_op_spe_st##name##_kernel, \
5662 &gen_op_spe_st##name##_le_kernel, \
5663 &gen_op_spe_st##name##_64_kernel, \
5664 &gen_op_spe_st##name##_le_64_kernel, \
5666 #else /* defined(TARGET_PPC64) */
5667 /* Full system - 32 bits mode */
5668 #define OP_SPE_LD_TABLE(name) \
5669 static GenOpFunc *gen_op_spe_l##name[] = { \
5670 &gen_op_spe_l##name##_user, \
5671 &gen_op_spe_l##name##_le_user, \
5672 &gen_op_spe_l##name##_kernel, \
5673 &gen_op_spe_l##name##_le_kernel, \
5675 #define OP_SPE_ST_TABLE(name) \
5676 static GenOpFunc *gen_op_spe_st##name[] = { \
5677 &gen_op_spe_st##name##_user, \
5678 &gen_op_spe_st##name##_le_user, \
5679 &gen_op_spe_st##name##_kernel, \
5680 &gen_op_spe_st##name##_le_kernel, \
5682 #endif /* defined(TARGET_PPC64) */
5683 #endif /* defined(CONFIG_USER_ONLY) */
5685 #define GEN_SPE_LD(name, sh) \
5686 static always_inline void gen_evl##name (DisasContext *ctx) \
5688 if (unlikely(!ctx->spe_enabled)) { \
5689 GEN_EXCP_NO_AP(ctx); \
5692 gen_addr_spe_imm_index(ctx, sh); \
5693 op_spe_ldst(spe_l##name); \
5694 gen_op_store_T1_gpr64(rD(ctx->opcode)); \
5697 #define GEN_SPE_LDX(name) \
5698 static always_inline void gen_evl##name##x (DisasContext *ctx) \
5700 if (unlikely(!ctx->spe_enabled)) { \
5701 GEN_EXCP_NO_AP(ctx); \
5704 gen_addr_reg_index(ctx); \
5705 op_spe_ldst(spe_l##name); \
5706 gen_op_store_T1_gpr64(rD(ctx->opcode)); \
5709 #define GEN_SPEOP_LD(name, sh) \
5710 OP_SPE_LD_TABLE(name); \
5711 GEN_SPE_LD(name, sh); \
5714 #define GEN_SPE_ST(name, sh) \
5715 static always_inline void gen_evst##name (DisasContext *ctx) \
5717 if (unlikely(!ctx->spe_enabled)) { \
5718 GEN_EXCP_NO_AP(ctx); \
5721 gen_addr_spe_imm_index(ctx, sh); \
5722 gen_op_load_gpr64_T1(rS(ctx->opcode)); \
5723 op_spe_ldst(spe_st##name); \
5726 #define GEN_SPE_STX(name) \
5727 static always_inline void gen_evst##name##x (DisasContext *ctx) \
5729 if (unlikely(!ctx->spe_enabled)) { \
5730 GEN_EXCP_NO_AP(ctx); \
5733 gen_addr_reg_index(ctx); \
5734 gen_op_load_gpr64_T1(rS(ctx->opcode)); \
5735 op_spe_ldst(spe_st##name); \
5738 #define GEN_SPEOP_ST(name, sh) \
5739 OP_SPE_ST_TABLE(name); \
5740 GEN_SPE_ST(name, sh); \
5743 #define GEN_SPEOP_LDST(name, sh) \
5744 GEN_SPEOP_LD(name, sh); \
5745 GEN_SPEOP_ST(name, sh)
5747 /* SPE arithmetic and logic */
5748 #define GEN_SPEOP_ARITH2(name) \
5749 static always_inline void gen_##name (DisasContext *ctx) \
5751 if (unlikely(!ctx->spe_enabled)) { \
5752 GEN_EXCP_NO_AP(ctx); \
5755 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
5756 gen_op_load_gpr64_T1(rB(ctx->opcode)); \
5758 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
5761 #define GEN_SPEOP_ARITH1(name) \
5762 static always_inline void gen_##name (DisasContext *ctx) \
5764 if (unlikely(!ctx->spe_enabled)) { \
5765 GEN_EXCP_NO_AP(ctx); \
5768 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
5770 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
5773 #define GEN_SPEOP_COMP(name) \
5774 static always_inline void gen_##name (DisasContext *ctx) \
5776 if (unlikely(!ctx->spe_enabled)) { \
5777 GEN_EXCP_NO_AP(ctx); \
5780 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
5781 gen_op_load_gpr64_T1(rB(ctx->opcode)); \
5783 gen_op_store_T0_crf(crfD(ctx->opcode)); \
5787 GEN_SPEOP_ARITH2(evand);
5788 GEN_SPEOP_ARITH2(evandc);
5789 GEN_SPEOP_ARITH2(evxor);
5790 GEN_SPEOP_ARITH2(evor);
5791 GEN_SPEOP_ARITH2(evnor);
5792 GEN_SPEOP_ARITH2(eveqv);
5793 GEN_SPEOP_ARITH2(evorc);
5794 GEN_SPEOP_ARITH2(evnand);
5795 GEN_SPEOP_ARITH2(evsrwu);
5796 GEN_SPEOP_ARITH2(evsrws);
5797 GEN_SPEOP_ARITH2(evslw);
5798 GEN_SPEOP_ARITH2(evrlw);
5799 GEN_SPEOP_ARITH2(evmergehi);
5800 GEN_SPEOP_ARITH2(evmergelo);
5801 GEN_SPEOP_ARITH2(evmergehilo);
5802 GEN_SPEOP_ARITH2(evmergelohi);
5805 GEN_SPEOP_ARITH2(evaddw);
5806 GEN_SPEOP_ARITH2(evsubfw);
5807 GEN_SPEOP_ARITH1(evabs);
5808 GEN_SPEOP_ARITH1(evneg);
5809 GEN_SPEOP_ARITH1(evextsb);
5810 GEN_SPEOP_ARITH1(evextsh);
5811 GEN_SPEOP_ARITH1(evrndw);
5812 GEN_SPEOP_ARITH1(evcntlzw);
5813 GEN_SPEOP_ARITH1(evcntlsw);
5814 static always_inline void gen_brinc (DisasContext *ctx)
5816 /* Note: brinc is usable even if SPE is disabled */
5817 gen_op_load_gpr64_T0(rA(ctx->opcode));
5818 gen_op_load_gpr64_T1(rB(ctx->opcode));
5820 gen_op_store_T0_gpr64(rD(ctx->opcode));
5823 #define GEN_SPEOP_ARITH_IMM2(name) \
5824 static always_inline void gen_##name##i (DisasContext *ctx) \
5826 if (unlikely(!ctx->spe_enabled)) { \
5827 GEN_EXCP_NO_AP(ctx); \
5830 gen_op_load_gpr64_T0(rB(ctx->opcode)); \
5831 gen_op_splatwi_T1_64(rA(ctx->opcode)); \
5833 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
5836 #define GEN_SPEOP_LOGIC_IMM2(name) \
5837 static always_inline void gen_##name##i (DisasContext *ctx) \
5839 if (unlikely(!ctx->spe_enabled)) { \
5840 GEN_EXCP_NO_AP(ctx); \
5843 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
5844 gen_op_splatwi_T1_64(rB(ctx->opcode)); \
5846 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
5849 GEN_SPEOP_ARITH_IMM2(evaddw);
5850 #define gen_evaddiw gen_evaddwi
5851 GEN_SPEOP_ARITH_IMM2(evsubfw);
5852 #define gen_evsubifw gen_evsubfwi
5853 GEN_SPEOP_LOGIC_IMM2(evslw);
5854 GEN_SPEOP_LOGIC_IMM2(evsrwu);
5855 #define gen_evsrwis gen_evsrwsi
5856 GEN_SPEOP_LOGIC_IMM2(evsrws);
5857 #define gen_evsrwiu gen_evsrwui
5858 GEN_SPEOP_LOGIC_IMM2(evrlw);
5860 static always_inline void gen_evsplati (DisasContext *ctx)
5862 int32_t imm = (int32_t)(rA(ctx->opcode) << 27) >> 27;
5864 gen_op_splatwi_T0_64(imm);
5865 gen_op_store_T0_gpr64(rD(ctx->opcode));
5868 static always_inline void gen_evsplatfi (DisasContext *ctx)
5870 uint32_t imm = rA(ctx->opcode) << 27;
5872 gen_op_splatwi_T0_64(imm);
5873 gen_op_store_T0_gpr64(rD(ctx->opcode));
5877 GEN_SPEOP_COMP(evcmpgtu);
5878 GEN_SPEOP_COMP(evcmpgts);
5879 GEN_SPEOP_COMP(evcmpltu);
5880 GEN_SPEOP_COMP(evcmplts);
5881 GEN_SPEOP_COMP(evcmpeq);
5883 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
5884 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
5885 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
5886 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
5887 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
5888 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
5889 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
5890 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
5891 GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
5892 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
5893 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
5894 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
5895 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
5896 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
5897 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
5898 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
5899 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
5900 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
5901 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
5902 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
5903 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
5904 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
5905 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
5906 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
5907 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
5909 static always_inline void gen_evsel (DisasContext *ctx)
5911 if (unlikely(!ctx->spe_enabled)) {
5912 GEN_EXCP_NO_AP(ctx);
5915 gen_op_load_crf_T0(ctx->opcode & 0x7);
5916 gen_op_load_gpr64_T0(rA(ctx->opcode));
5917 gen_op_load_gpr64_T1(rB(ctx->opcode));
5919 gen_op_store_T0_gpr64(rD(ctx->opcode));
5922 GEN_HANDLER(evsel0, 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
5926 GEN_HANDLER(evsel1, 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
5930 GEN_HANDLER(evsel2, 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
5934 GEN_HANDLER(evsel3, 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
5939 /* Load and stores */
5940 #if defined(TARGET_PPC64)
5941 /* In that case, we already have 64 bits load & stores
5942 * so, spe_ldd is equivalent to ld and spe_std is equivalent to std
5944 #if defined(CONFIG_USER_ONLY)
5945 #define gen_op_spe_ldd_raw gen_op_ld_raw
5946 #define gen_op_spe_ldd_64_raw gen_op_ld_64_raw
5947 #define gen_op_spe_ldd_le_raw gen_op_ld_le_raw
5948 #define gen_op_spe_ldd_le_64_raw gen_op_ld_le_64_raw
5949 #define gen_op_spe_stdd_raw gen_op_ld_raw
5950 #define gen_op_spe_stdd_64_raw gen_op_std_64_raw
5951 #define gen_op_spe_stdd_le_raw gen_op_std_le_raw
5952 #define gen_op_spe_stdd_le_64_raw gen_op_std_le_64_raw
5953 #else /* defined(CONFIG_USER_ONLY) */
5954 #define gen_op_spe_ldd_kernel gen_op_ld_kernel
5955 #define gen_op_spe_ldd_64_kernel gen_op_ld_64_kernel
5956 #define gen_op_spe_ldd_le_kernel gen_op_ld_kernel
5957 #define gen_op_spe_ldd_le_64_kernel gen_op_ld_64_kernel
5958 #define gen_op_spe_ldd_user gen_op_ld_user
5959 #define gen_op_spe_ldd_64_user gen_op_ld_64_user
5960 #define gen_op_spe_ldd_le_user gen_op_ld_le_user
5961 #define gen_op_spe_ldd_le_64_user gen_op_ld_le_64_user
5962 #define gen_op_spe_stdd_kernel gen_op_std_kernel
5963 #define gen_op_spe_stdd_64_kernel gen_op_std_64_kernel
5964 #define gen_op_spe_stdd_le_kernel gen_op_std_kernel
5965 #define gen_op_spe_stdd_le_64_kernel gen_op_std_64_kernel
5966 #define gen_op_spe_stdd_user gen_op_std_user
5967 #define gen_op_spe_stdd_64_user gen_op_std_64_user
5968 #define gen_op_spe_stdd_le_user gen_op_std_le_user
5969 #define gen_op_spe_stdd_le_64_user gen_op_std_le_64_user
5970 #endif /* defined(CONFIG_USER_ONLY) */
5971 #endif /* defined(TARGET_PPC64) */
5972 GEN_SPEOP_LDST(dd, 3);
5973 GEN_SPEOP_LDST(dw, 3);
5974 GEN_SPEOP_LDST(dh, 3);
5975 GEN_SPEOP_LDST(whe, 2);
5976 GEN_SPEOP_LD(whou, 2);
5977 GEN_SPEOP_LD(whos, 2);
5978 GEN_SPEOP_ST(who, 2);
5980 #if defined(TARGET_PPC64)
5981 /* In that case, spe_stwwo is equivalent to stw */
5982 #if defined(CONFIG_USER_ONLY)
5983 #define gen_op_spe_stwwo_raw gen_op_stw_raw
5984 #define gen_op_spe_stwwo_le_raw gen_op_stw_le_raw
5985 #define gen_op_spe_stwwo_64_raw gen_op_stw_64_raw
5986 #define gen_op_spe_stwwo_le_64_raw gen_op_stw_le_64_raw
5988 #define gen_op_spe_stwwo_user gen_op_stw_user
5989 #define gen_op_spe_stwwo_le_user gen_op_stw_le_user
5990 #define gen_op_spe_stwwo_64_user gen_op_stw_64_user
5991 #define gen_op_spe_stwwo_le_64_user gen_op_stw_le_64_user
5992 #define gen_op_spe_stwwo_kernel gen_op_stw_kernel
5993 #define gen_op_spe_stwwo_le_kernel gen_op_stw_le_kernel
5994 #define gen_op_spe_stwwo_64_kernel gen_op_stw_64_kernel
5995 #define gen_op_spe_stwwo_le_64_kernel gen_op_stw_le_64_kernel
5998 #define _GEN_OP_SPE_STWWE(suffix) \
5999 static always_inline void gen_op_spe_stwwe_##suffix (void) \
6001 gen_op_srli32_T1_64(); \
6002 gen_op_spe_stwwo_##suffix(); \
6004 #define _GEN_OP_SPE_STWWE_LE(suffix) \
6005 static always_inline void gen_op_spe_stwwe_le_##suffix (void) \
6007 gen_op_srli32_T1_64(); \
6008 gen_op_spe_stwwo_le_##suffix(); \
6010 #if defined(TARGET_PPC64)
6011 #define GEN_OP_SPE_STWWE(suffix) \
6012 _GEN_OP_SPE_STWWE(suffix); \
6013 _GEN_OP_SPE_STWWE_LE(suffix); \
6014 static always_inline void gen_op_spe_stwwe_64_##suffix (void) \
6016 gen_op_srli32_T1_64(); \
6017 gen_op_spe_stwwo_64_##suffix(); \
6019 static always_inline void gen_op_spe_stwwe_le_64_##suffix (void) \
6021 gen_op_srli32_T1_64(); \
6022 gen_op_spe_stwwo_le_64_##suffix(); \
6025 #define GEN_OP_SPE_STWWE(suffix) \
6026 _GEN_OP_SPE_STWWE(suffix); \
6027 _GEN_OP_SPE_STWWE_LE(suffix)
6029 #if defined(CONFIG_USER_ONLY)
6030 GEN_OP_SPE_STWWE(raw);
6031 #else /* defined(CONFIG_USER_ONLY) */
6032 GEN_OP_SPE_STWWE(kernel);
6033 GEN_OP_SPE_STWWE(user);
6034 #endif /* defined(CONFIG_USER_ONLY) */
6035 GEN_SPEOP_ST(wwe, 2);
6036 GEN_SPEOP_ST(wwo, 2);
6038 #define GEN_SPE_LDSPLAT(name, op, suffix) \
6039 static always_inline void gen_op_spe_l##name##_##suffix (void) \
6041 gen_op_##op##_##suffix(); \
6042 gen_op_splatw_T1_64(); \
6045 #define GEN_OP_SPE_LHE(suffix) \
6046 static always_inline void gen_op_spe_lhe_##suffix (void) \
6048 gen_op_spe_lh_##suffix(); \
6049 gen_op_sli16_T1_64(); \
6052 #define GEN_OP_SPE_LHX(suffix) \
6053 static always_inline void gen_op_spe_lhx_##suffix (void) \
6055 gen_op_spe_lh_##suffix(); \
6056 gen_op_extsh_T1_64(); \
6059 #if defined(CONFIG_USER_ONLY)
6060 GEN_OP_SPE_LHE(raw);
6061 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, raw);
6062 GEN_OP_SPE_LHE(le_raw);
6063 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_raw);
6064 GEN_SPE_LDSPLAT(hhousplat, spe_lh, raw);
6065 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_raw);
6066 GEN_OP_SPE_LHX(raw);
6067 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, raw);
6068 GEN_OP_SPE_LHX(le_raw);
6069 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_raw);
6070 #if defined(TARGET_PPC64)
6071 GEN_OP_SPE_LHE(64_raw);
6072 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_raw);
6073 GEN_OP_SPE_LHE(le_64_raw);
6074 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_raw);
6075 GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_raw);
6076 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_raw);
6077 GEN_OP_SPE_LHX(64_raw);
6078 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_raw);
6079 GEN_OP_SPE_LHX(le_64_raw);
6080 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_raw);
6083 GEN_OP_SPE_LHE(kernel);
6084 GEN_OP_SPE_LHE(user);
6085 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, kernel);
6086 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, user);
6087 GEN_OP_SPE_LHE(le_kernel);
6088 GEN_OP_SPE_LHE(le_user);
6089 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_kernel);
6090 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_user);
6091 GEN_SPE_LDSPLAT(hhousplat, spe_lh, kernel);
6092 GEN_SPE_LDSPLAT(hhousplat, spe_lh, user);
6093 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_kernel);
6094 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_user);
6095 GEN_OP_SPE_LHX(kernel);
6096 GEN_OP_SPE_LHX(user);
6097 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, kernel);
6098 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, user);
6099 GEN_OP_SPE_LHX(le_kernel);
6100 GEN_OP_SPE_LHX(le_user);
6101 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_kernel);
6102 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_user);
6103 #if defined(TARGET_PPC64)
6104 GEN_OP_SPE_LHE(64_kernel);
6105 GEN_OP_SPE_LHE(64_user);
6106 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_kernel);
6107 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_user);
6108 GEN_OP_SPE_LHE(le_64_kernel);
6109 GEN_OP_SPE_LHE(le_64_user);
6110 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_kernel);
6111 GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_user);
6112 GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_kernel);
6113 GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_user);
6114 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_kernel);
6115 GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_user);
6116 GEN_OP_SPE_LHX(64_kernel);
6117 GEN_OP_SPE_LHX(64_user);
6118 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_kernel);
6119 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_user);
6120 GEN_OP_SPE_LHX(le_64_kernel);
6121 GEN_OP_SPE_LHX(le_64_user);
6122 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_kernel);
6123 GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_user);
6126 GEN_SPEOP_LD(hhesplat, 1);
6127 GEN_SPEOP_LD(hhousplat, 1);
6128 GEN_SPEOP_LD(hhossplat, 1);
6129 GEN_SPEOP_LD(wwsplat, 2);
6130 GEN_SPEOP_LD(whsplat, 2);
6132 GEN_SPE(evlddx, evldd, 0x00, 0x0C, 0x00000000, PPC_SPE); //
6133 GEN_SPE(evldwx, evldw, 0x01, 0x0C, 0x00000000, PPC_SPE); //
6134 GEN_SPE(evldhx, evldh, 0x02, 0x0C, 0x00000000, PPC_SPE); //
6135 GEN_SPE(evlhhesplatx, evlhhesplat, 0x04, 0x0C, 0x00000000, PPC_SPE); //
6136 GEN_SPE(evlhhousplatx, evlhhousplat, 0x06, 0x0C, 0x00000000, PPC_SPE); //
6137 GEN_SPE(evlhhossplatx, evlhhossplat, 0x07, 0x0C, 0x00000000, PPC_SPE); //
6138 GEN_SPE(evlwhex, evlwhe, 0x08, 0x0C, 0x00000000, PPC_SPE); //
6139 GEN_SPE(evlwhoux, evlwhou, 0x0A, 0x0C, 0x00000000, PPC_SPE); //
6140 GEN_SPE(evlwhosx, evlwhos, 0x0B, 0x0C, 0x00000000, PPC_SPE); //
6141 GEN_SPE(evlwwsplatx, evlwwsplat, 0x0C, 0x0C, 0x00000000, PPC_SPE); //
6142 GEN_SPE(evlwhsplatx, evlwhsplat, 0x0E, 0x0C, 0x00000000, PPC_SPE); //
6143 GEN_SPE(evstddx, evstdd, 0x10, 0x0C, 0x00000000, PPC_SPE); //
6144 GEN_SPE(evstdwx, evstdw, 0x11, 0x0C, 0x00000000, PPC_SPE); //
6145 GEN_SPE(evstdhx, evstdh, 0x12, 0x0C, 0x00000000, PPC_SPE); //
6146 GEN_SPE(evstwhex, evstwhe, 0x18, 0x0C, 0x00000000, PPC_SPE); //
6147 GEN_SPE(evstwhox, evstwho, 0x1A, 0x0C, 0x00000000, PPC_SPE); //
6148 GEN_SPE(evstwwex, evstwwe, 0x1C, 0x0C, 0x00000000, PPC_SPE); //
6149 GEN_SPE(evstwwox, evstwwo, 0x1E, 0x0C, 0x00000000, PPC_SPE); //
6151 /* Multiply and add - TODO */
6153 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
6154 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
6155 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
6156 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
6157 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
6158 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
6159 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
6160 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
6161 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
6162 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
6163 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
6164 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
6166 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
6167 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
6168 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
6169 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
6170 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
6171 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
6172 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
6173 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
6174 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
6175 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
6176 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
6177 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
6178 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
6179 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
6181 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
6182 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
6183 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
6184 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
6185 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
6186 GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
6188 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
6189 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
6190 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
6191 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
6192 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
6193 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
6194 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
6195 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
6196 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
6197 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
6198 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
6199 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
6201 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
6202 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
6203 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
6204 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
6205 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
6207 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
6208 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
6209 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
6210 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
6211 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
6212 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
6213 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
6214 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
6215 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
6216 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
6217 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
6218 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
6220 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
6221 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
6222 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
6223 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
6224 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
6227 /*** SPE floating-point extension ***/
6228 #define GEN_SPEFPUOP_CONV(name) \
6229 static always_inline void gen_##name (DisasContext *ctx) \
6231 gen_op_load_gpr64_T0(rB(ctx->opcode)); \
6233 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
6236 /* Single precision floating-point vectors operations */
6238 GEN_SPEOP_ARITH2(evfsadd);
6239 GEN_SPEOP_ARITH2(evfssub);
6240 GEN_SPEOP_ARITH2(evfsmul);
6241 GEN_SPEOP_ARITH2(evfsdiv);
6242 GEN_SPEOP_ARITH1(evfsabs);
6243 GEN_SPEOP_ARITH1(evfsnabs);
6244 GEN_SPEOP_ARITH1(evfsneg);
6246 GEN_SPEFPUOP_CONV(evfscfui);
6247 GEN_SPEFPUOP_CONV(evfscfsi);
6248 GEN_SPEFPUOP_CONV(evfscfuf);
6249 GEN_SPEFPUOP_CONV(evfscfsf);
6250 GEN_SPEFPUOP_CONV(evfsctui);
6251 GEN_SPEFPUOP_CONV(evfsctsi);
6252 GEN_SPEFPUOP_CONV(evfsctuf);
6253 GEN_SPEFPUOP_CONV(evfsctsf);
6254 GEN_SPEFPUOP_CONV(evfsctuiz);
6255 GEN_SPEFPUOP_CONV(evfsctsiz);
6257 GEN_SPEOP_COMP(evfscmpgt);
6258 GEN_SPEOP_COMP(evfscmplt);
6259 GEN_SPEOP_COMP(evfscmpeq);
6260 GEN_SPEOP_COMP(evfststgt);
6261 GEN_SPEOP_COMP(evfststlt);
6262 GEN_SPEOP_COMP(evfststeq);
6264 /* Opcodes definitions */
6265 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
6266 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPEFPU); //
6267 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPEFPU); //
6268 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPEFPU); //
6269 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPEFPU); //
6270 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPEFPU); //
6271 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPEFPU); //
6272 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPEFPU); //
6273 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPEFPU); //
6274 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPEFPU); //
6275 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPEFPU); //
6276 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPEFPU); //
6277 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPEFPU); //
6278 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPEFPU); //
6280 /* Single precision floating-point operations */
6282 GEN_SPEOP_ARITH2(efsadd);
6283 GEN_SPEOP_ARITH2(efssub);
6284 GEN_SPEOP_ARITH2(efsmul);
6285 GEN_SPEOP_ARITH2(efsdiv);
6286 GEN_SPEOP_ARITH1(efsabs);
6287 GEN_SPEOP_ARITH1(efsnabs);
6288 GEN_SPEOP_ARITH1(efsneg);
6290 GEN_SPEFPUOP_CONV(efscfui);
6291 GEN_SPEFPUOP_CONV(efscfsi);
6292 GEN_SPEFPUOP_CONV(efscfuf);
6293 GEN_SPEFPUOP_CONV(efscfsf);
6294 GEN_SPEFPUOP_CONV(efsctui);
6295 GEN_SPEFPUOP_CONV(efsctsi);
6296 GEN_SPEFPUOP_CONV(efsctuf);
6297 GEN_SPEFPUOP_CONV(efsctsf);
6298 GEN_SPEFPUOP_CONV(efsctuiz);
6299 GEN_SPEFPUOP_CONV(efsctsiz);
6300 GEN_SPEFPUOP_CONV(efscfd);
6302 GEN_SPEOP_COMP(efscmpgt);
6303 GEN_SPEOP_COMP(efscmplt);
6304 GEN_SPEOP_COMP(efscmpeq);
6305 GEN_SPEOP_COMP(efststgt);
6306 GEN_SPEOP_COMP(efststlt);
6307 GEN_SPEOP_COMP(efststeq);
6309 /* Opcodes definitions */
6310 GEN_SPE(efsadd, efssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
6311 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU); //
6312 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU); //
6313 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPEFPU); //
6314 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPEFPU); //
6315 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPEFPU); //
6316 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPEFPU); //
6317 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPEFPU); //
6318 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPEFPU); //
6319 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPEFPU); //
6320 GEN_SPE(efsctuiz, efsctsiz, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU); //
6321 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPEFPU); //
6322 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPEFPU); //
6324 /* Double precision floating-point operations */
6326 GEN_SPEOP_ARITH2(efdadd);
6327 GEN_SPEOP_ARITH2(efdsub);
6328 GEN_SPEOP_ARITH2(efdmul);
6329 GEN_SPEOP_ARITH2(efddiv);
6330 GEN_SPEOP_ARITH1(efdabs);
6331 GEN_SPEOP_ARITH1(efdnabs);
6332 GEN_SPEOP_ARITH1(efdneg);
6335 GEN_SPEFPUOP_CONV(efdcfui);
6336 GEN_SPEFPUOP_CONV(efdcfsi);
6337 GEN_SPEFPUOP_CONV(efdcfuf);
6338 GEN_SPEFPUOP_CONV(efdcfsf);
6339 GEN_SPEFPUOP_CONV(efdctui);
6340 GEN_SPEFPUOP_CONV(efdctsi);
6341 GEN_SPEFPUOP_CONV(efdctuf);
6342 GEN_SPEFPUOP_CONV(efdctsf);
6343 GEN_SPEFPUOP_CONV(efdctuiz);
6344 GEN_SPEFPUOP_CONV(efdctsiz);
6345 GEN_SPEFPUOP_CONV(efdcfs);
6346 GEN_SPEFPUOP_CONV(efdcfuid);
6347 GEN_SPEFPUOP_CONV(efdcfsid);
6348 GEN_SPEFPUOP_CONV(efdctuidz);
6349 GEN_SPEFPUOP_CONV(efdctsidz);
6351 GEN_SPEOP_COMP(efdcmpgt);
6352 GEN_SPEOP_COMP(efdcmplt);
6353 GEN_SPEOP_COMP(efdcmpeq);
6354 GEN_SPEOP_COMP(efdtstgt);
6355 GEN_SPEOP_COMP(efdtstlt);
6356 GEN_SPEOP_COMP(efdtsteq);
6358 /* Opcodes definitions */
6359 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPEFPU); //
6360 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPEFPU); //
6361 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPEFPU); //
6362 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPEFPU); //
6363 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPEFPU); //
6364 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPEFPU); //
6365 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPEFPU); //
6366 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPEFPU); //
6367 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPEFPU); //
6368 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPEFPU); //
6369 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPEFPU); //
6370 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPEFPU); //
6371 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPEFPU); //
6372 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU); //
6373 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU); //
6374 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU); //
6377 /* End opcode list */
6378 GEN_OPCODE_MARK(end);
6380 #include "translate_init.c"
6382 /*****************************************************************************/
6383 /* Misc PowerPC helpers */
6384 static always_inline uint32_t load_xer (CPUState *env)
6386 return (xer_so << XER_SO) |
6387 (xer_ov << XER_OV) |
6388 (xer_ca << XER_CA) |
6389 (xer_bc << XER_BC) |
6390 (xer_cmp << XER_CMP);
6393 void cpu_dump_state (CPUState *env, FILE *f,
6394 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
6397 #if defined(TARGET_PPC64) || 1
6409 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX "\n",
6410 env->nip, env->lr, env->ctr);
6411 cpu_fprintf(f, "MSR " REGX FILL " XER %08x "
6412 #if !defined(NO_TIMER_DUMP)
6414 #if !defined(CONFIG_USER_ONLY)
6419 do_load_msr(env), load_xer(env)
6420 #if !defined(NO_TIMER_DUMP)
6421 , cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
6422 #if !defined(CONFIG_USER_ONLY)
6423 , cpu_ppc_load_decr(env)
6427 for (i = 0; i < 32; i++) {
6428 if ((i & (RGPL - 1)) == 0)
6429 cpu_fprintf(f, "GPR%02d", i);
6430 cpu_fprintf(f, " " REGX, (target_ulong)env->gpr[i]);
6431 if ((i & (RGPL - 1)) == (RGPL - 1))
6432 cpu_fprintf(f, "\n");
6434 cpu_fprintf(f, "CR ");
6435 for (i = 0; i < 8; i++)
6436 cpu_fprintf(f, "%01x", env->crf[i]);
6437 cpu_fprintf(f, " [");
6438 for (i = 0; i < 8; i++) {
6440 if (env->crf[i] & 0x08)
6442 else if (env->crf[i] & 0x04)
6444 else if (env->crf[i] & 0x02)
6446 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
6448 cpu_fprintf(f, " ] " FILL "RES " REGX "\n", env->reserve);
6449 for (i = 0; i < 32; i++) {
6450 if ((i & (RFPL - 1)) == 0)
6451 cpu_fprintf(f, "FPR%02d", i);
6452 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
6453 if ((i & (RFPL - 1)) == (RFPL - 1))
6454 cpu_fprintf(f, "\n");
6456 #if !defined(CONFIG_USER_ONLY)
6457 cpu_fprintf(f, "SRR0 " REGX " SRR1 " REGX " " FILL FILL FILL
6459 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
6467 void cpu_dump_statistics (CPUState *env, FILE*f,
6468 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
6471 #if defined(DO_PPC_STATISTICS)
6472 opc_handler_t **t1, **t2, **t3, *handler;
6476 for (op1 = 0; op1 < 64; op1++) {
6478 if (is_indirect_opcode(handler)) {
6479 t2 = ind_table(handler);
6480 for (op2 = 0; op2 < 32; op2++) {
6482 if (is_indirect_opcode(handler)) {
6483 t3 = ind_table(handler);
6484 for (op3 = 0; op3 < 32; op3++) {
6486 if (handler->count == 0)
6488 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
6490 op1, op2, op3, op1, (op3 << 5) | op2,
6492 handler->count, handler->count);
6495 if (handler->count == 0)
6497 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
6499 op1, op2, op1, op2, handler->oname,
6500 handler->count, handler->count);
6504 if (handler->count == 0)
6506 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
6507 op1, op1, handler->oname,
6508 handler->count, handler->count);
6514 /*****************************************************************************/
6515 static always_inline int gen_intermediate_code_internal (CPUState *env,
6516 TranslationBlock *tb,
6519 DisasContext ctx, *ctxp = &ctx;
6520 opc_handler_t **table, *handler;
6521 target_ulong pc_start;
6522 uint16_t *gen_opc_end;
6524 int single_step, branch_step;
6528 gen_opc_ptr = gen_opc_buf;
6529 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
6530 gen_opparam_ptr = gen_opparam_buf;
6534 ctx.exception = POWERPC_EXCP_NONE;
6535 ctx.spr_cb = env->spr_cb;
6536 #if defined(CONFIG_USER_ONLY)
6539 #if defined(TARGET_PPC64H)
6540 if (msr_pr == 0 && msr_hv == 1)
6544 supervisor = 1 - msr_pr;
6545 ctx.supervisor = supervisor;
6547 #if defined(TARGET_PPC64)
6548 ctx.sf_mode = msr_sf;
6549 ctx.mem_idx = (supervisor << 2) | (msr_sf << 1) | msr_le;
6551 ctx.mem_idx = (supervisor << 1) | msr_le;
6553 ctx.dcache_line_size = env->dcache_line_size;
6554 ctx.fpu_enabled = msr_fp;
6555 #if defined(TARGET_PPCEMB)
6556 if (env->flags & POWERPC_FLAG_SPE)
6557 ctx.spe_enabled = msr_spe;
6559 ctx.spe_enabled = 0;
6561 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
6565 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
6569 ctx.singlestep_enabled = env->singlestep_enabled || single_step == 1;;
6570 #if defined (DO_SINGLE_STEP) && 0
6571 /* Single step trace mode */
6574 /* Set env in case of segfault during code fetch */
6575 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
6576 if (unlikely(env->nb_breakpoints > 0)) {
6577 for (j = 0; j < env->nb_breakpoints; j++) {
6578 if (env->breakpoints[j] == ctx.nip) {
6579 gen_update_nip(&ctx, ctx.nip);
6585 if (unlikely(search_pc)) {
6586 j = gen_opc_ptr - gen_opc_buf;
6590 gen_opc_instr_start[lj++] = 0;
6591 gen_opc_pc[lj] = ctx.nip;
6592 gen_opc_instr_start[lj] = 1;
6595 #if defined PPC_DEBUG_DISAS
6596 if (loglevel & CPU_LOG_TB_IN_ASM) {
6597 fprintf(logfile, "----------------\n");
6598 fprintf(logfile, "nip=" ADDRX " super=%d ir=%d\n",
6599 ctx.nip, 1 - msr_pr, msr_ir);
6602 ctx.opcode = ldl_code(ctx.nip);
6604 ctx.opcode = ((ctx.opcode & 0xFF000000) >> 24) |
6605 ((ctx.opcode & 0x00FF0000) >> 8) |
6606 ((ctx.opcode & 0x0000FF00) << 8) |
6607 ((ctx.opcode & 0x000000FF) << 24);
6609 #if defined PPC_DEBUG_DISAS
6610 if (loglevel & CPU_LOG_TB_IN_ASM) {
6611 fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n",
6612 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
6613 opc3(ctx.opcode), msr_le ? "little" : "big");
6617 table = env->opcodes;
6618 handler = table[opc1(ctx.opcode)];
6619 if (is_indirect_opcode(handler)) {
6620 table = ind_table(handler);
6621 handler = table[opc2(ctx.opcode)];
6622 if (is_indirect_opcode(handler)) {
6623 table = ind_table(handler);
6624 handler = table[opc3(ctx.opcode)];
6627 /* Is opcode *REALLY* valid ? */
6628 if (unlikely(handler->handler == &gen_invalid)) {
6629 if (loglevel != 0) {
6630 fprintf(logfile, "invalid/unsupported opcode: "
6631 "%02x - %02x - %02x (%08x) 0x" ADDRX " %d\n",
6632 opc1(ctx.opcode), opc2(ctx.opcode),
6633 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, msr_ir);
6635 printf("invalid/unsupported opcode: "
6636 "%02x - %02x - %02x (%08x) 0x" ADDRX " %d\n",
6637 opc1(ctx.opcode), opc2(ctx.opcode),
6638 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, msr_ir);
6641 if (unlikely((ctx.opcode & handler->inval) != 0)) {
6642 if (loglevel != 0) {
6643 fprintf(logfile, "invalid bits: %08x for opcode: "
6644 "%02x - %02x - %02x (%08x) 0x" ADDRX "\n",
6645 ctx.opcode & handler->inval, opc1(ctx.opcode),
6646 opc2(ctx.opcode), opc3(ctx.opcode),
6647 ctx.opcode, ctx.nip - 4);
6649 printf("invalid bits: %08x for opcode: "
6650 "%02x - %02x - %02x (%08x) 0x" ADDRX "\n",
6651 ctx.opcode & handler->inval, opc1(ctx.opcode),
6652 opc2(ctx.opcode), opc3(ctx.opcode),
6653 ctx.opcode, ctx.nip - 4);
6655 GEN_EXCP_INVAL(ctxp);
6659 (*(handler->handler))(&ctx);
6660 #if defined(DO_PPC_STATISTICS)
6663 /* Check trace mode exceptions */
6664 if (unlikely(branch_step != 0 &&
6665 ctx.exception == POWERPC_EXCP_BRANCH)) {
6666 GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0);
6667 } else if (unlikely(single_step != 0 &&
6668 (ctx.nip <= 0x100 || ctx.nip > 0xF00 ||
6669 (ctx.nip & 0xFC) != 0x04) &&
6670 #if defined(CONFIG_USER_ONLY)
6671 ctx.exception != POWERPC_EXCP_SYSCALL_USER &&
6673 ctx.exception != POWERPC_EXCP_SYSCALL &&
6675 ctx.exception != POWERPC_EXCP_TRAP)) {
6676 GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0);
6677 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
6678 (env->singlestep_enabled))) {
6679 /* if we reach a page boundary or are single stepping, stop
6684 #if defined (DO_SINGLE_STEP)
6688 if (ctx.exception == POWERPC_EXCP_NONE) {
6689 gen_goto_tb(&ctx, 0, ctx.nip);
6690 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
6692 /* Generate the return instruction */
6695 *gen_opc_ptr = INDEX_op_end;
6696 if (unlikely(search_pc)) {
6697 j = gen_opc_ptr - gen_opc_buf;
6700 gen_opc_instr_start[lj++] = 0;
6702 tb->size = ctx.nip - pc_start;
6704 #if defined(DEBUG_DISAS)
6705 if (loglevel & CPU_LOG_TB_CPU) {
6706 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
6707 cpu_dump_state(env, logfile, fprintf, 0);
6709 if (loglevel & CPU_LOG_TB_IN_ASM) {
6711 flags = env->bfd_mach;
6712 flags |= msr_le << 16;
6713 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
6714 target_disas(logfile, pc_start, ctx.nip - pc_start, flags);
6715 fprintf(logfile, "\n");
6717 if (loglevel & CPU_LOG_TB_OP) {
6718 fprintf(logfile, "OP:\n");
6719 dump_ops(gen_opc_buf, gen_opparam_buf);
6720 fprintf(logfile, "\n");
6726 int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
6728 return gen_intermediate_code_internal(env, tb, 0);
6731 int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
6733 return gen_intermediate_code_internal(env, tb, 1);