4 * Copyright (c) 2005 Samuel Tardieu
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30 #include "hw/sh_intc.h"
32 #if defined(CONFIG_USER_ONLY)
34 void do_interrupt (CPUState *env)
36 env->exception_index = -1;
39 int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
40 int mmu_idx, int is_softmmu)
43 env->exception_index = 0;
47 env->exception_index = 0x0a0;
51 env->exception_index = 0x0c0;
57 target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
62 #else /* !CONFIG_USER_ONLY */
65 #define MMU_ITLB_MISS (-1)
66 #define MMU_ITLB_MULTIPLE (-2)
67 #define MMU_ITLB_VIOLATION (-3)
68 #define MMU_DTLB_MISS_READ (-4)
69 #define MMU_DTLB_MISS_WRITE (-5)
70 #define MMU_DTLB_INITIAL_WRITE (-6)
71 #define MMU_DTLB_VIOLATION_READ (-7)
72 #define MMU_DTLB_VIOLATION_WRITE (-8)
73 #define MMU_DTLB_MULTIPLE (-9)
74 #define MMU_DTLB_MISS (-10)
76 void do_interrupt(CPUState * env)
78 int do_irq = env->interrupt_request & CPU_INTERRUPT_HARD;
79 int do_exp, irq_vector = env->exception_index;
81 /* prioritize exceptions over interrupts */
83 do_exp = env->exception_index != -1;
84 do_irq = do_irq && (env->exception_index == -1);
86 if (env->sr & SR_BL) {
87 if (do_exp && env->exception_index != 0x1e0) {
88 env->exception_index = 0x000; /* masked exception -> reset */
90 if (do_irq && !env->intr_at_halt) {
93 env->intr_at_halt = 0;
97 irq_vector = sh_intc_get_pending_vector(env->intc_handle,
98 (env->sr >> 4) & 0xf);
99 if (irq_vector == -1) {
104 if (loglevel & CPU_LOG_INT) {
106 switch (env->exception_index) {
108 expname = "addr_error";
111 expname = "tlb_miss";
114 expname = "tlb_violation";
117 expname = "illegal_instruction";
120 expname = "slot_illegal_instruction";
123 expname = "fpu_disable";
126 expname = "slot_fpu";
129 expname = "data_write";
132 expname = "dtlb_miss_write";
135 expname = "dtlb_violation_write";
138 expname = "fpu_exception";
141 expname = "initial_page_write";
147 expname = do_irq ? "interrupt" : "???";
150 fprintf(logfile, "exception 0x%03x [%s] raised\n",
151 irq_vector, expname);
152 cpu_dump_state(env, logfile, fprintf, 0);
157 env->sgr = env->gregs[15];
158 env->sr |= SR_BL | SR_MD | SR_RB;
160 if (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
161 /* Branch instruction should be executed again before delay slot. */
163 /* Clear flags for exception/interrupt routine. */
164 env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL | DELAY_SLOT_TRUE);
166 if (env->flags & DELAY_SLOT_CLEARME)
170 env->expevt = env->exception_index;
171 switch (env->exception_index) {
176 env->sr |= 0xf << 4; /* IMASK */
177 env->pc = 0xa0000000;
181 env->pc = env->vbr + 0x400;
184 env->spc += 2; /* special case for TRAPA */
187 env->pc = env->vbr + 0x100;
194 env->intevt = irq_vector;
195 env->pc = env->vbr + 0x600;
200 static void update_itlb_use(CPUState * env, int itlbnb)
202 uint8_t or_mask = 0, and_mask = (uint8_t) - 1;
221 env->mmucr &= (and_mask << 24) | 0x00ffffff;
222 env->mmucr |= (or_mask << 24);
225 static int itlb_replacement(CPUState * env)
227 if ((env->mmucr & 0xe0000000) == 0xe0000000)
229 if ((env->mmucr & 0x98000000) == 0x18000000)
231 if ((env->mmucr & 0x54000000) == 0x04000000)
233 if ((env->mmucr & 0x2c000000) == 0x00000000)
238 /* Find the corresponding entry in the right TLB
239 Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
241 static int find_tlb_entry(CPUState * env, target_ulong address,
242 tlb_t * entries, uint8_t nbtlb, int use_asid)
244 int match = MMU_DTLB_MISS;
249 asid = env->pteh & 0xff;
251 for (i = 0; i < nbtlb; i++) {
253 continue; /* Invalid entry */
254 if (use_asid && entries[i].asid != asid && !entries[i].sh)
255 continue; /* Bad ASID */
257 switch (entries[i].sz) {
259 size = 1024; /* 1kB */
262 size = 4 * 1024; /* 4kB */
265 size = 64 * 1024; /* 64kB */
268 size = 1024 * 1024; /* 1MB */
274 start = (entries[i].vpn << 10) & ~(entries[i].size - 1);
275 end = start + entries[i].size - 1;
276 if (address >= start && address <= end) { /* Match */
277 if (match != MMU_DTLB_MISS)
278 return MMU_DTLB_MULTIPLE; /* Multiple match */
285 static int same_tlb_entry_exists(const tlb_t * haystack, uint8_t nbtlb,
286 const tlb_t * needle)
289 for (i = 0; i < nbtlb; i++)
290 if (!memcmp(&haystack[i], needle, sizeof(tlb_t)))
295 static void increment_urc(CPUState * env)
300 urb = ((env->mmucr) >> 18) & 0x3f;
301 urc = ((env->mmucr) >> 10) & 0x3f;
303 if (urc == urb || urc == UTLB_SIZE - 1)
305 env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10);
308 /* Find itlb entry - update itlb from utlb if necessary and asked for
309 Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
310 Update the itlb from utlb if update is not 0
312 int find_itlb_entry(CPUState * env, target_ulong address,
313 int use_asid, int update)
317 e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid);
318 if (e == MMU_DTLB_MULTIPLE)
319 e = MMU_ITLB_MULTIPLE;
320 else if (e == MMU_DTLB_MISS && update) {
321 e = find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
323 n = itlb_replacement(env);
324 env->itlb[n] = env->utlb[e];
326 } else if (e == MMU_DTLB_MISS)
328 } else if (e == MMU_DTLB_MISS)
331 update_itlb_use(env, e);
336 Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
337 int find_utlb_entry(CPUState * env, target_ulong address, int use_asid)
339 /* per utlb access */
343 return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
346 /* Match address against MMU
347 Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE,
348 MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ,
349 MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS,
350 MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION
352 static int get_mmu_address(CPUState * env, target_ulong * physical,
353 int *prot, target_ulong address,
354 int rw, int access_type)
356 int use_asid, is_code, n;
357 tlb_t *matching = NULL;
359 use_asid = (env->mmucr & MMUCR_SV) == 0 && (env->sr & SR_MD) == 0;
360 is_code = env->pc == address; /* Hack */
362 /* Use a hack to find if this is an instruction or data access */
363 if (env->pc == address && !(rw & PAGE_WRITE)) {
364 n = find_itlb_entry(env, address, use_asid, 1);
366 matching = &env->itlb[n];
367 if ((env->sr & SR_MD) & !(matching->pr & 2))
368 n = MMU_ITLB_VIOLATION;
373 n = find_utlb_entry(env, address, use_asid);
375 matching = &env->utlb[n];
376 switch ((matching->pr << 1) | ((env->sr & SR_MD) ? 1 : 0)) {
379 n = (rw & PAGE_WRITE) ? MMU_DTLB_VIOLATION_WRITE :
380 MMU_DTLB_VIOLATION_READ;
386 n = MMU_DTLB_VIOLATION_WRITE;
393 *prot = rw & (PAGE_READ | PAGE_WRITE);
396 } else if (n == MMU_DTLB_MISS) {
397 n = (rw & PAGE_WRITE) ? MMU_DTLB_MISS_WRITE :
402 *physical = ((matching->ppn << 10) & ~(matching->size - 1)) |
403 (address & (matching->size - 1));
404 if ((rw & PAGE_WRITE) & !matching->d)
405 n = MMU_DTLB_INITIAL_WRITE;
412 int get_physical_address(CPUState * env, target_ulong * physical,
413 int *prot, target_ulong address,
414 int rw, int access_type)
416 /* P1, P2 and P4 areas do not use translation */
417 if ((address >= 0x80000000 && address < 0xc0000000) ||
418 address >= 0xe0000000) {
419 if (!(env->sr & SR_MD)
420 && (address < 0xe0000000 || address > 0xe4000000)) {
421 /* Unauthorized access in user mode (only store queues are available) */
422 fprintf(stderr, "Unauthorized access\n");
423 return (rw & PAGE_WRITE) ? MMU_DTLB_MISS_WRITE :
426 if (address >= 0x80000000 && address < 0xc0000000) {
427 /* Mask upper 3 bits for P1 and P2 areas */
428 *physical = address & 0x1fffffff;
429 } else if (address >= 0xfc000000) {
431 * Mask upper 3 bits for control registers in P4 area,
432 * to unify access to control registers via P0-P3 area.
433 * The addresses for cache store queue, TLB address array
436 *physical = address & 0x1fffffff;
438 /* access to cache store queue, or TLB address array. */
441 *prot = PAGE_READ | PAGE_WRITE;
445 /* If MMU is disabled, return the corresponding physical page */
446 if (!env->mmucr & MMUCR_AT) {
447 *physical = address & 0x1FFFFFFF;
448 *prot = PAGE_READ | PAGE_WRITE;
452 /* We need to resort to the MMU */
453 return get_mmu_address(env, physical, prot, address, rw, access_type);
456 int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
457 int mmu_idx, int is_softmmu)
459 target_ulong physical, page_offset, page_size;
460 int prot, ret, access_type;
469 case 2: /* READ_ACCESS_TYPE == 2 defined in softmmu_template.h */
479 fprintf(stderr, "%s pc %08x ad %08x rw %d mmu_idx %d smmu %d\n",
480 __func__, env->pc, address, rw, mmu_idx, is_softmmu);
483 access_type = ACCESS_INT;
485 get_physical_address(env, &physical, &prot, address, rw,
492 case MMU_DTLB_MISS_READ:
493 env->exception_index = 0x040;
495 case MMU_DTLB_MULTIPLE:
496 case MMU_ITLB_MULTIPLE:
497 env->exception_index = 0x140;
499 case MMU_ITLB_VIOLATION:
500 env->exception_index = 0x0a0;
502 case MMU_DTLB_MISS_WRITE:
503 env->exception_index = 0x060;
505 case MMU_DTLB_INITIAL_WRITE:
506 env->exception_index = 0x080;
508 case MMU_DTLB_VIOLATION_READ:
509 env->exception_index = 0x0a0;
511 case MMU_DTLB_VIOLATION_WRITE:
512 env->exception_index = 0x0c0;
520 page_size = TARGET_PAGE_SIZE;
522 (address - (address & TARGET_PAGE_MASK)) & ~(page_size - 1);
523 address = (address & TARGET_PAGE_MASK) + page_offset;
524 physical = (physical & TARGET_PAGE_MASK) + page_offset;
526 return tlb_set_page(env, address, physical, prot, mmu_idx, is_softmmu);
529 target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
531 target_ulong physical;
534 get_physical_address(env, &physical, &prot, addr, PAGE_READ, 0);
538 void cpu_load_tlb(CPUState * env)
540 int n = cpu_mmucr_urc(env->mmucr);
541 tlb_t * entry = &env->utlb[n];
543 /* Take values into cpu status from registers. */
544 entry->asid = (uint8_t)cpu_pteh_asid(env->pteh);
545 entry->vpn = cpu_pteh_vpn(env->pteh);
546 entry->v = (uint8_t)cpu_ptel_v(env->ptel);
547 entry->ppn = cpu_ptel_ppn(env->ptel);
548 entry->sz = (uint8_t)cpu_ptel_sz(env->ptel);
551 entry->size = 1024; /* 1K */
554 entry->size = 1024 * 4; /* 4K */
557 entry->size = 1024 * 64; /* 64K */
560 entry->size = 1024 * 1024; /* 1M */
566 entry->sh = (uint8_t)cpu_ptel_sh(env->ptel);
567 entry->c = (uint8_t)cpu_ptel_c(env->ptel);
568 entry->pr = (uint8_t)cpu_ptel_pr(env->ptel);
569 entry->d = (uint8_t)cpu_ptel_d(env->ptel);
570 entry->wt = (uint8_t)cpu_ptel_wt(env->ptel);
571 entry->sa = (uint8_t)cpu_ptea_sa(env->ptea);
572 entry->tc = (uint8_t)cpu_ptea_tc(env->ptea);
575 void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
578 int associate = addr & 0x0000080;
579 uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
580 uint8_t d = (uint8_t)((mem_value & 0x00000200) >> 9);
581 uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
582 uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
586 tlb_t * utlb_match_entry = NULL;
587 int needs_tlb_flush = 0;
590 for (i = 0; i < UTLB_SIZE; i++) {
591 tlb_t * entry = &s->utlb[i];
595 if (entry->vpn == vpn && entry->asid == asid) {
596 if (utlb_match_entry) {
597 /* Multiple TLB Exception */
598 s->exception_index = 0x140;
606 utlb_match_entry = entry;
608 increment_urc(s); /* per utlb access */
612 for (i = 0; i < ITLB_SIZE; i++) {
613 tlb_t * entry = &s->itlb[i];
614 if (entry->vpn == vpn && entry->asid == asid) {
617 if (utlb_match_entry)
618 *entry = *utlb_match_entry;
626 tlb_flush_page(s, vpn << 10);
629 int index = (addr & 0x00003f00) >> 8;
630 tlb_t * entry = &s->utlb[index];
632 /* Overwriting valid entry in utlb. */
633 target_ulong address = entry->vpn << 10;
634 if (!same_tlb_entry_exists(s->itlb, ITLB_SIZE, entry)) {
635 tlb_flush_page(s, address);