git.maemo.org Git - qemu/blob - target-sh4/translate.c

   1 /*
   2  *  SH4 translation
   3  *
   4  *  Copyright (c) 2005 Samuel Tardieu
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include <stdarg.h>
  21 #include <stdlib.h>
  22 #include <stdio.h>
  23 #include <string.h>
  24 #include <inttypes.h>
  25 #include <assert.h>
  26
  27 #define DEBUG_DISAS
  28 #define SH4_DEBUG_DISAS
  29 //#define SH4_SINGLE_STEP
  30
  31 #include "cpu.h"
  32 #include "exec-all.h"
  33 #include "disas.h"
  34 #include "helper.h"
  35 #include "tcg-op.h"
  36 #include "qemu-common.h"
  37
  38 typedef struct DisasContext {
  39     struct TranslationBlock *tb;
  40     target_ulong pc;
  41     uint32_t sr;
  42     uint32_t fpscr;
  43     uint16_t opcode;
  44     uint32_t flags;
  45     int bstate;
  46     int memidx;
  47     uint32_t delayed_pc;
  48     int singlestep_enabled;
  49 } DisasContext;
  50
  51 #if defined(CONFIG_USER_ONLY)
  52 #define IS_USER(ctx) 1
  53 #else
  54 #define IS_USER(ctx) (!(ctx->sr & SR_MD))
  55 #endif
  56
  57 enum {
  58     BS_NONE     = 0, /* We go out of the TB without reaching a branch or an
  59                       * exception condition
  60                       */
  61     BS_STOP     = 1, /* We want to stop translation for any reason */
  62     BS_BRANCH   = 2, /* We reached a branch condition     */
  63     BS_EXCP     = 3, /* We reached an exception condition */
  64 };
  65
  66 /* global register indexes */
  67 static TCGv cpu_env;
  68 static TCGv cpu_gregs[24];
  69 static TCGv cpu_pc, cpu_sr, cpu_ssr, cpu_spc, cpu_gbr;
  70 static TCGv cpu_vbr, cpu_sgr, cpu_dbr, cpu_mach, cpu_macl;
  71 static TCGv cpu_pr, cpu_fpscr, cpu_fpul, cpu_flags;
  72
  73 /* internal register indexes */
  74 static TCGv cpu_flags, cpu_delayed_pc;
  75
  76 #include "gen-icount.h"
  77
  78 static void sh4_translate_init(void)
  79 {
  80     int i;
  81     static int done_init = 0;
  82     static const char * const gregnames[24] = {
  83         "R0_BANK0", "R1_BANK0", "R2_BANK0", "R3_BANK0",
  84         "R4_BANK0", "R5_BANK0", "R6_BANK0", "R7_BANK0",
  85         "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15",
  86         "R0_BANK1", "R1_BANK1", "R2_BANK1", "R3_BANK1",
  87         "R4_BANK1", "R5_BANK1", "R6_BANK1", "R7_BANK1"
  88     };
  89
  90     if (done_init)
  91         return;
  92
  93     cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
  94
  95     for (i = 0; i < 24; i++)
  96         cpu_gregs[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
  97                                           offsetof(CPUState, gregs[i]),
  98                                           gregnames[i]);
  99
 100     cpu_pc = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
 101                                 offsetof(CPUState, pc), "PC");
 102     cpu_sr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
 103                                 offsetof(CPUState, sr), "SR");
 104     cpu_ssr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
 105                                  offsetof(CPUState, ssr), "SSR");
 106     cpu_spc = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
 107                                  offsetof(CPUState, spc), "SPC");
 108     cpu_gbr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
 109                                  offsetof(CPUState, gbr), "GBR");
 110     cpu_vbr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
 111                                  offsetof(CPUState, vbr), "VBR");
 112     cpu_sgr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
 113                                  offsetof(CPUState, sgr), "SGR");
 114     cpu_dbr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
 115                                  offsetof(CPUState, dbr), "DBR");
 116     cpu_mach = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
 117                                   offsetof(CPUState, mach), "MACH");
 118     cpu_macl = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
 119                                   offsetof(CPUState, macl), "MACL");
 120     cpu_pr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
 121                                 offsetof(CPUState, pr), "PR");
 122     cpu_fpscr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
 123                                    offsetof(CPUState, fpscr), "FPSCR");
 124     cpu_fpul = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
 125                                   offsetof(CPUState, fpul), "FPUL");
 126
 127     cpu_flags = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
 128                                    offsetof(CPUState, flags), "_flags_");
 129     cpu_delayed_pc = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
 130                                         offsetof(CPUState, delayed_pc),
 131                                         "_delayed_pc_");
 132
 133     /* register helpers */
 134 #undef DEF_HELPER
 135 #define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
 136 #include "helper.h"
 137
 138     done_init = 1;
 139 }
 140
 141 void cpu_dump_state(CPUState * env, FILE * f,
 142                     int (*cpu_fprintf) (FILE * f, const char *fmt, ...),
 143                     int flags)
 144 {
 145     int i;
 146     cpu_fprintf(f, "pc=0x%08x sr=0x%08x pr=0x%08x fpscr=0x%08x\n",
 147                 env->pc, env->sr, env->pr, env->fpscr);
 148     cpu_fprintf(f, "spc=0x%08x ssr=0x%08x gbr=0x%08x vbr=0x%08x\n",
 149                 env->spc, env->ssr, env->gbr, env->vbr);
 150     cpu_fprintf(f, "sgr=0x%08x dbr=0x%08x delayed_pc=0x%08x fpul=0x%08x\n",
 151                 env->sgr, env->dbr, env->delayed_pc, env->fpul);
 152     for (i = 0; i < 24; i += 4) {
 153         cpu_fprintf(f, "r%d=0x%08x r%d=0x%08x r%d=0x%08x r%d=0x%08x\n",
 154                     i, env->gregs[i], i + 1, env->gregs[i + 1],
 155                     i + 2, env->gregs[i + 2], i + 3, env->gregs[i + 3]);
 156     }
 157     if (env->flags & DELAY_SLOT) {
 158         cpu_fprintf(f, "in delay slot (delayed_pc=0x%08x)\n",
 159                     env->delayed_pc);
 160     } else if (env->flags & DELAY_SLOT_CONDITIONAL) {
 161         cpu_fprintf(f, "in conditional delay slot (delayed_pc=0x%08x)\n",
 162                     env->delayed_pc);
 163     }
 164 }
 165
 166 void cpu_sh4_reset(CPUSH4State * env)
 167 {
 168 #if defined(CONFIG_USER_ONLY)
 169     env->sr = SR_FD;            /* FD - kernel does lazy fpu context switch */
 170 #else
 171     env->sr = 0x700000F0;       /* MD, RB, BL, I3-I0 */
 172 #endif
 173     env->vbr = 0;
 174     env->pc = 0xA0000000;
 175 #if defined(CONFIG_USER_ONLY)
 176     env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */
 177     set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */
 178 #else
 179     env->fpscr = 0x00040001; /* CPU reset value according to SH4 manual */
 180     set_float_rounding_mode(float_round_to_zero, &env->fp_status);
 181 #endif
 182     env->mmucr = 0;
 183 }
 184
 185 typedef struct {
 186     const char *name;
 187     int id;
 188     uint32_t pvr;
 189     uint32_t prr;
 190     uint32_t cvr;
 191 } sh4_def_t;
 192
 193 static sh4_def_t sh4_defs[] = {
 194     {
 195         .name = "SH7750R",
 196         .id = SH_CPU_SH7750R,
 197         .pvr = 0x00050000,
 198         .prr = 0x00000100,
 199         .cvr = 0x00110000,
 200     }, {
 201         .name = "SH7751R",
 202         .id = SH_CPU_SH7751R,
 203         .pvr = 0x04050005,
 204         .prr = 0x00000113,
 205         .cvr = 0x00110000,      /* Neutered caches, should be 0x20480000 */
 206     },
 207 };
 208
 209 static const sh4_def_t *cpu_sh4_find_by_name(const char *name)
 210 {
 211     int i;
 212
 213     if (strcasecmp(name, "any") == 0)
 214         return &sh4_defs[0];
 215
 216     for (i = 0; i < sizeof(sh4_defs) / sizeof(*sh4_defs); i++)
 217         if (strcasecmp(name, sh4_defs[i].name) == 0)
 218             return &sh4_defs[i];
 219
 220     return NULL;
 221 }
 222
 223 void sh4_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
 224 {
 225     int i;
 226
 227     for (i = 0; i < sizeof(sh4_defs) / sizeof(*sh4_defs); i++)
 228         (*cpu_fprintf)(f, "%s\n", sh4_defs[i].name);
 229 }
 230
 231 static void cpu_sh4_register(CPUSH4State *env, const sh4_def_t *def)
 232 {
 233     env->pvr = def->pvr;
 234     env->prr = def->prr;
 235     env->cvr = def->cvr;
 236     env->id = def->id;
 237 }
 238
 239 CPUSH4State *cpu_sh4_init(const char *cpu_model)
 240 {
 241     CPUSH4State *env;
 242     const sh4_def_t *def;
 243
 244     def = cpu_sh4_find_by_name(cpu_model);
 245     if (!def)
 246         return NULL;
 247     env = qemu_mallocz(sizeof(CPUSH4State));
 248     if (!env)
 249         return NULL;
 250     cpu_exec_init(env);
 251     sh4_translate_init();
 252     env->cpu_model_str = cpu_model;
 253     cpu_sh4_reset(env);
 254     cpu_sh4_register(env, def);
 255     tlb_flush(env, 1);
 256     return env;
 257 }
 258
 259 static void gen_goto_tb(DisasContext * ctx, int n, target_ulong dest)
 260 {
 261     TranslationBlock *tb;
 262     tb = ctx->tb;
 263
 264     if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
 265         !ctx->singlestep_enabled) {
 266         /* Use a direct jump if in same page and singlestep not enabled */
 267         tcg_gen_goto_tb(n);
 268         tcg_gen_movi_i32(cpu_pc, dest);
 269         tcg_gen_exit_tb((long) tb + n);
 270     } else {
 271         tcg_gen_movi_i32(cpu_pc, dest);
 272         if (ctx->singlestep_enabled)
 273             tcg_gen_helper_0_0(helper_debug);
 274         tcg_gen_exit_tb(0);
 275     }
 276 }
 277
 278 static void gen_jump(DisasContext * ctx)
 279 {
 280     if (ctx->delayed_pc == (uint32_t) - 1) {
 281         /* Target is not statically known, it comes necessarily from a
 282            delayed jump as immediate jump are conditinal jumps */
 283         tcg_gen_mov_i32(cpu_pc, cpu_delayed_pc);
 284         if (ctx->singlestep_enabled)
 285             tcg_gen_helper_0_0(helper_debug);
 286         tcg_gen_exit_tb(0);
 287     } else {
 288         gen_goto_tb(ctx, 0, ctx->delayed_pc);
 289     }
 290 }
 291
 292 static inline void gen_branch_slot(uint32_t delayed_pc, int t)
 293 {
 294     TCGv sr;
 295     int label = gen_new_label();
 296     tcg_gen_movi_i32(cpu_delayed_pc, delayed_pc);
 297     sr = tcg_temp_new(TCG_TYPE_I32);
 298     tcg_gen_andi_i32(sr, cpu_sr, SR_T);
 299     tcg_gen_brcondi_i32(TCG_COND_NE, sr, t ? SR_T : 0, label);
 300     tcg_gen_ori_i32(cpu_flags, cpu_flags, DELAY_SLOT_TRUE);
 301     gen_set_label(label);
 302 }
 303
 304 /* Immediate conditional jump (bt or bf) */
 305 static void gen_conditional_jump(DisasContext * ctx,
 306                                  target_ulong ift, target_ulong ifnott)
 307 {
 308     int l1;
 309     TCGv sr;
 310
 311     l1 = gen_new_label();
 312     sr = tcg_temp_new(TCG_TYPE_I32);
 313     tcg_gen_andi_i32(sr, cpu_sr, SR_T);
 314     tcg_gen_brcondi_i32(TCG_COND_EQ, sr, SR_T, l1);
 315     gen_goto_tb(ctx, 0, ifnott);
 316     gen_set_label(l1);
 317     gen_goto_tb(ctx, 1, ift);
 318 }
 319
 320 /* Delayed conditional jump (bt or bf) */
 321 static void gen_delayed_conditional_jump(DisasContext * ctx)
 322 {
 323     int l1;
 324     TCGv ds;
 325
 326     l1 = gen_new_label();
 327     ds = tcg_temp_new(TCG_TYPE_I32);
 328     tcg_gen_andi_i32(ds, cpu_flags, DELAY_SLOT_TRUE);
 329     tcg_gen_brcondi_i32(TCG_COND_EQ, ds, DELAY_SLOT_TRUE, l1);
 330     gen_goto_tb(ctx, 1, ctx->pc + 2);
 331     gen_set_label(l1);
 332     tcg_gen_andi_i32(cpu_flags, cpu_flags, ~DELAY_SLOT_TRUE);
 333     gen_jump(ctx);
 334 }
 335
 336 static inline void gen_set_t(void)
 337 {
 338     tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_T);
 339 }
 340
 341 static inline void gen_clr_t(void)
 342 {
 343     tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
 344 }
 345
 346 static inline void gen_cmp(int cond, TCGv t0, TCGv t1)
 347 {
 348     int label1 = gen_new_label();
 349     int label2 = gen_new_label();
 350     tcg_gen_brcond_i32(cond, t1, t0, label1);
 351     gen_clr_t();
 352     tcg_gen_br(label2);
 353     gen_set_label(label1);
 354     gen_set_t();
 355     gen_set_label(label2);
 356 }
 357
 358 static inline void gen_cmp_imm(int cond, TCGv t0, int32_t imm)
 359 {
 360     int label1 = gen_new_label();
 361     int label2 = gen_new_label();
 362     tcg_gen_brcondi_i32(cond, t0, imm, label1);
 363     gen_clr_t();
 364     tcg_gen_br(label2);
 365     gen_set_label(label1);
 366     gen_set_t();
 367     gen_set_label(label2);
 368 }
 369
 370 static inline void gen_store_flags(uint32_t flags)
 371 {
 372     tcg_gen_andi_i32(cpu_flags, cpu_flags, DELAY_SLOT_TRUE);
 373     tcg_gen_ori_i32(cpu_flags, cpu_flags, flags);
 374 }
 375
 376 static inline void gen_copy_bit_i32(TCGv t0, int p0, TCGv t1, int p1)
 377 {
 378     TCGv tmp = tcg_temp_new(TCG_TYPE_I32);
 379
 380     p0 &= 0x1f;
 381     p1 &= 0x1f;
 382
 383     tcg_gen_andi_i32(tmp, t1, (1 << p1));
 384     tcg_gen_andi_i32(t0, t0, ~(1 << p0));
 385     if (p0 < p1)
 386         tcg_gen_shri_i32(tmp, tmp, p1 - p0);
 387     else if (p0 > p1)
 388         tcg_gen_shli_i32(tmp, tmp, p0 - p1);
 389     tcg_gen_or_i32(t0, t0, tmp);
 390
 391     tcg_temp_free(tmp);
 392 }
 393
 394
 395 static inline void gen_load_fpr32(TCGv t, int reg)
 396 {
 397     tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, fregs[reg]));
 398 }
 399
 400 static inline void gen_load_fpr64(TCGv t, int reg)
 401 {
 402     TCGv tmp1 = tcg_temp_new(TCG_TYPE_I32);
 403     TCGv tmp2 = tcg_temp_new(TCG_TYPE_I32);
 404
 405     tcg_gen_ld_i32(tmp1, cpu_env, offsetof(CPUState, fregs[reg]));
 406     tcg_gen_ld_i32(tmp2, cpu_env, offsetof(CPUState, fregs[reg + 1]));
 407     tcg_gen_concat_i32_i64(t, tmp2, tmp1);
 408     tcg_temp_free(tmp1);
 409     tcg_temp_free(tmp2);
 410 }
 411
 412 static inline void gen_store_fpr32(TCGv t, int reg)
 413 {
 414     tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, fregs[reg]));
 415 }
 416
 417 static inline void gen_store_fpr64 (TCGv t, int reg)
 418 {
 419     TCGv tmp = tcg_temp_new(TCG_TYPE_I32);
 420
 421     tcg_gen_trunc_i64_i32(tmp, t);
 422     tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, fregs[reg + 1]));
 423     tcg_gen_shri_i64(t, t, 32);
 424     tcg_gen_trunc_i64_i32(tmp, t);
 425     tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, fregs[reg]));
 426     tcg_temp_free(tmp);
 427 }
 428
 429 #define B3_0 (ctx->opcode & 0xf)
 430 #define B6_4 ((ctx->opcode >> 4) & 0x7)
 431 #define B7_4 ((ctx->opcode >> 4) & 0xf)
 432 #define B7_0 (ctx->opcode & 0xff)
 433 #define B7_0s ((int32_t) (int8_t) (ctx->opcode & 0xff))
 434 #define B11_0s (ctx->opcode & 0x800 ? 0xfffff000 | (ctx->opcode & 0xfff) : \
 435   (ctx->opcode & 0xfff))
 436 #define B11_8 ((ctx->opcode >> 8) & 0xf)
 437 #define B15_12 ((ctx->opcode >> 12) & 0xf)
 438
 439 #define REG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB) ? \
 440                 (cpu_gregs[x + 16]) : (cpu_gregs[x]))
 441
 442 #define ALTREG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) != (SR_MD | SR_RB) \
 443                 ? (cpu_gregs[x + 16]) : (cpu_gregs[x]))
 444
 445 #define FREG(x) (ctx->fpscr & FPSCR_FR ? (x) ^ 0x10 : (x))
 446 #define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe))
 447 #define XREG(x) (ctx->fpscr & FPSCR_FR ? XHACK(x) ^ 0x10 : XHACK(x))
 448 #define DREG(x) FREG(x) /* Assumes lsb of (x) is always 0 */
 449
 450 #define CHECK_NOT_DELAY_SLOT \
 451   if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) \
 452   {tcg_gen_helper_0_0(helper_raise_slot_illegal_instruction); ctx->bstate = BS_EXCP; \
 453    return;}
 454
 455 #define CHECK_PRIVILEGED                                      \
 456   if (IS_USER(ctx)) {                                         \
 457       tcg_gen_helper_0_0(helper_raise_illegal_instruction);   \
 458       ctx->bstate = BS_EXCP;                                  \
 459       return;                                                 \
 460   }
 461
 462 void _decode_opc(DisasContext * ctx)
 463 {
 464 #if 0
 465     fprintf(stderr, "Translating opcode 0x%04x\n", ctx->opcode);
 466 #endif
 467     switch (ctx->opcode) {
 468     case 0x0019:                /* div0u */
 469         tcg_gen_andi_i32(cpu_sr, cpu_sr, ~(SR_M | SR_Q | SR_T));
 470         return;
 471     case 0x000b:                /* rts */
 472         CHECK_NOT_DELAY_SLOT
 473         tcg_gen_mov_i32(cpu_delayed_pc, cpu_pr);
 474         ctx->flags |= DELAY_SLOT;
 475         ctx->delayed_pc = (uint32_t) - 1;
 476         return;
 477     case 0x0028:                /* clrmac */
 478         tcg_gen_movi_i32(cpu_mach, 0);
 479         tcg_gen_movi_i32(cpu_macl, 0);
 480         return;
 481     case 0x0048:                /* clrs */
 482         tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_S);
 483         return;
 484     case 0x0008:                /* clrt */
 485         gen_clr_t();
 486         return;
 487     case 0x0038:                /* ldtlb */
 488         CHECK_PRIVILEGED
 489         tcg_gen_helper_0_0(helper_ldtlb);
 490         return;
 491     case 0x002b:                /* rte */
 492         CHECK_PRIVILEGED
 493         CHECK_NOT_DELAY_SLOT
 494         tcg_gen_mov_i32(cpu_sr, cpu_ssr);
 495         tcg_gen_mov_i32(cpu_delayed_pc, cpu_spc);
 496         ctx->flags |= DELAY_SLOT;
 497         ctx->delayed_pc = (uint32_t) - 1;
 498         return;
 499     case 0x0058:                /* sets */
 500         tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_S);
 501         return;
 502     case 0x0018:                /* sett */
 503         gen_set_t();
 504         return;
 505     case 0xfbfd:                /* frchg */
 506         tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_FR);
 507         ctx->bstate = BS_STOP;
 508         return;
 509     case 0xf3fd:                /* fschg */
 510         tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_SZ);
 511         ctx->bstate = BS_STOP;
 512         return;
 513     case 0x0009:                /* nop */
 514         return;
 515     case 0x001b:                /* sleep */
 516         CHECK_PRIVILEGED
 517         tcg_gen_helper_0_1(helper_sleep, tcg_const_i32(ctx->pc + 2));
 518         return;
 519     }
 520
 521     switch (ctx->opcode & 0xf000) {
 522     case 0x1000:                /* mov.l Rm,@(disp,Rn) */
 523         {
 524             TCGv addr = tcg_temp_new(TCG_TYPE_I32);
 525             tcg_gen_addi_i32(addr, REG(B11_8), B3_0 * 4);
 526             tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx);
 527             tcg_temp_free(addr);
 528         }
 529         return;
 530     case 0x5000:                /* mov.l @(disp,Rm),Rn */
 531         {
 532             TCGv addr = tcg_temp_new(TCG_TYPE_I32);
 533             tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 4);
 534             tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx);
 535             tcg_temp_free(addr);
 536         }
 537         return;
 538     case 0xe000:                /* mov #imm,Rn */
 539         tcg_gen_movi_i32(REG(B11_8), B7_0s);
 540         return;
 541     case 0x9000:                /* mov.w @(disp,PC),Rn */
 542         {
 543             TCGv addr = tcg_const_i32(ctx->pc + 4 + B7_0 * 2);
 544             tcg_gen_qemu_ld16s(REG(B11_8), addr, ctx->memidx);
 545             tcg_temp_free(addr);
 546         }
 547         return;
 548     case 0xd000:                /* mov.l @(disp,PC),Rn */
 549         {
 550             TCGv addr = tcg_const_i32((ctx->pc + 4 + B7_0 * 4) & ~3);
 551             tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx);
 552             tcg_temp_free(addr);
 553         }
 554         return;
 555     case 0x7000:                /* add #imm,Rn */
 556         tcg_gen_addi_i32(REG(B11_8), REG(B11_8), B7_0s);
 557         return;
 558     case 0xa000:                /* bra disp */
 559         CHECK_NOT_DELAY_SLOT
 560         ctx->delayed_pc = ctx->pc + 4 + B11_0s * 2;
 561         tcg_gen_movi_i32(cpu_delayed_pc, ctx->delayed_pc);
 562         ctx->flags |= DELAY_SLOT;
 563         return;
 564     case 0xb000:                /* bsr disp */
 565         CHECK_NOT_DELAY_SLOT
 566         tcg_gen_movi_i32(cpu_pr, ctx->pc + 4);
 567         ctx->delayed_pc = ctx->pc + 4 + B11_0s * 2;
 568         tcg_gen_movi_i32(cpu_delayed_pc, ctx->delayed_pc);
 569         ctx->flags |= DELAY_SLOT;
 570         return;
 571     }
 572
 573     switch (ctx->opcode & 0xf00f) {
 574     case 0x6003:                /* mov Rm,Rn */
 575         tcg_gen_mov_i32(REG(B11_8), REG(B7_4));
 576         return;
 577     case 0x2000:                /* mov.b Rm,@Rn */
 578         tcg_gen_qemu_st8(REG(B7_4), REG(B11_8), ctx->memidx);
 579         return;
 580     case 0x2001:                /* mov.w Rm,@Rn */
 581         tcg_gen_qemu_st16(REG(B7_4), REG(B11_8), ctx->memidx);
 582         return;
 583     case 0x2002:                /* mov.l Rm,@Rn */
 584         tcg_gen_qemu_st32(REG(B7_4), REG(B11_8), ctx->memidx);
 585         return;
 586     case 0x6000:                /* mov.b @Rm,Rn */
 587         tcg_gen_qemu_ld8s(REG(B11_8), REG(B7_4), ctx->memidx);
 588         return;
 589     case 0x6001:                /* mov.w @Rm,Rn */
 590         tcg_gen_qemu_ld16s(REG(B11_8), REG(B7_4), ctx->memidx);
 591         return;
 592     case 0x6002:                /* mov.l @Rm,Rn */
 593         tcg_gen_qemu_ld32s(REG(B11_8), REG(B7_4), ctx->memidx);
 594         return;
 595     case 0x2004:                /* mov.b Rm,@-Rn */
 596         {
 597             TCGv addr = tcg_temp_new(TCG_TYPE_I32);
 598             tcg_gen_subi_i32(addr, REG(B11_8), 1);
 599             tcg_gen_qemu_st8(REG(B7_4), addr, ctx->memidx);     /* might cause re-execution */
 600             tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 1);        /* modify register status */
 601             tcg_temp_free(addr);
 602         }
 603         return;
 604     case 0x2005:                /* mov.w Rm,@-Rn */
 605         {
 606             TCGv addr = tcg_temp_new(TCG_TYPE_I32);
 607             tcg_gen_subi_i32(addr, REG(B11_8), 2);
 608             tcg_gen_qemu_st16(REG(B7_4), addr, ctx->memidx);
 609             tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 2);
 610             tcg_temp_free(addr);
 611         }
 612         return;
 613     case 0x2006:                /* mov.l Rm,@-Rn */
 614         {
 615             TCGv addr = tcg_temp_new(TCG_TYPE_I32);
 616             tcg_gen_subi_i32(addr, REG(B11_8), 4);
 617             tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx);
 618             tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
 619         }
 620         return;
 621     case 0x6004:                /* mov.b @Rm+,Rn */
 622         tcg_gen_qemu_ld8s(REG(B11_8), REG(B7_4), ctx->memidx);
 623         if ( B11_8 != B7_4 )
 624                 tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 1);
 625         return;
 626     case 0x6005:                /* mov.w @Rm+,Rn */
 627         tcg_gen_qemu_ld16s(REG(B11_8), REG(B7_4), ctx->memidx);
 628         if ( B11_8 != B7_4 )
 629                 tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2);
 630         return;
 631     case 0x6006:                /* mov.l @Rm+,Rn */
 632         tcg_gen_qemu_ld32s(REG(B11_8), REG(B7_4), ctx->memidx);
 633         if ( B11_8 != B7_4 )
 634                 tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
 635         return;
 636     case 0x0004:                /* mov.b Rm,@(R0,Rn) */
 637         {
 638             TCGv addr = tcg_temp_new(TCG_TYPE_I32);
 639             tcg_gen_add_i32(addr, REG(B11_8), REG(0));
 640             tcg_gen_qemu_st8(REG(B7_4), addr, ctx->memidx);
 641             tcg_temp_free(addr);
 642         }
 643         return;
 644     case 0x0005:                /* mov.w Rm,@(R0,Rn) */
 645         {
 646             TCGv addr = tcg_temp_new(TCG_TYPE_I32);
 647             tcg_gen_add_i32(addr, REG(B11_8), REG(0));
 648             tcg_gen_qemu_st16(REG(B7_4), addr, ctx->memidx);
 649             tcg_temp_free(addr);
 650         }
 651         return;
 652     case 0x0006:                /* mov.l Rm,@(R0,Rn) */
 653         {
 654             TCGv addr = tcg_temp_new(TCG_TYPE_I32);
 655             tcg_gen_add_i32(addr, REG(B11_8), REG(0));
 656             tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx);
 657             tcg_temp_free(addr);
 658         }
 659         return;
 660     case 0x000c:                /* mov.b @(R0,Rm),Rn */
 661         {
 662             TCGv addr = tcg_temp_new(TCG_TYPE_I32);
 663             tcg_gen_add_i32(addr, REG(B7_4), REG(0));
 664             tcg_gen_qemu_ld8s(REG(B11_8), addr, ctx->memidx);
 665             tcg_temp_free(addr);
 666         }
 667         return;
 668     case 0x000d:                /* mov.w @(R0,Rm),Rn */
 669         {
 670             TCGv addr = tcg_temp_new(TCG_TYPE_I32);
 671             tcg_gen_add_i32(addr, REG(B7_4), REG(0));
 672             tcg_gen_qemu_ld16s(REG(B11_8), addr, ctx->memidx);
 673             tcg_temp_free(addr);
 674         }
 675         return;
 676     case 0x000e:                /* mov.l @(R0,Rm),Rn */
 677         {
 678             TCGv addr = tcg_temp_new(TCG_TYPE_I32);
 679             tcg_gen_add_i32(addr, REG(B7_4), REG(0));
 680             tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx);
 681             tcg_temp_free(addr);
 682         }
 683         return;
 684     case 0x6008:                /* swap.b Rm,Rn */
 685         {
 686             TCGv highw, high, low;
 687             highw = tcg_temp_new(TCG_TYPE_I32);
 688             tcg_gen_andi_i32(highw, REG(B7_4), 0xffff0000);
 689             high = tcg_temp_new(TCG_TYPE_I32);
 690             tcg_gen_ext8u_i32(high, REG(B7_4));
 691             tcg_gen_shli_i32(high, high, 8);
 692             low = tcg_temp_new(TCG_TYPE_I32);
 693             tcg_gen_shri_i32(low, REG(B7_4), 8);
 694             tcg_gen_ext8u_i32(low, low);
 695             tcg_gen_or_i32(REG(B11_8), high, low);
 696             tcg_gen_or_i32(REG(B11_8), REG(B11_8), highw);
 697             tcg_temp_free(low);
 698             tcg_temp_free(high);
 699         }
 700         return;
 701     case 0x6009:                /* swap.w Rm,Rn */
 702         {
 703             TCGv high, low;
 704             high = tcg_temp_new(TCG_TYPE_I32);
 705             tcg_gen_ext16u_i32(high, REG(B7_4));
 706             tcg_gen_shli_i32(high, high, 16);
 707             low = tcg_temp_new(TCG_TYPE_I32);
 708             tcg_gen_shri_i32(low, REG(B7_4), 16);
 709             tcg_gen_ext16u_i32(low, low);
 710             tcg_gen_or_i32(REG(B11_8), high, low);
 711             tcg_temp_free(low);
 712             tcg_temp_free(high);
 713         }
 714         return;
 715     case 0x200d:                /* xtrct Rm,Rn */
 716         {
 717             TCGv high, low;
 718             high = tcg_temp_new(TCG_TYPE_I32);
 719             tcg_gen_ext16u_i32(high, REG(B7_4));
 720             tcg_gen_shli_i32(high, high, 16);
 721             low = tcg_temp_new(TCG_TYPE_I32);
 722             tcg_gen_shri_i32(low, REG(B11_8), 16);
 723             tcg_gen_ext16u_i32(low, low);
 724             tcg_gen_or_i32(REG(B11_8), high, low);
 725             tcg_temp_free(low);
 726             tcg_temp_free(high);
 727         }
 728         return;
 729     case 0x300c:                /* add Rm,Rn */
 730         tcg_gen_add_i32(REG(B11_8), REG(B11_8), REG(B7_4));
 731         return;
 732     case 0x300e:                /* addc Rm,Rn */
 733         tcg_gen_helper_1_2(helper_addc, REG(B11_8), REG(B7_4), REG(B11_8));
 734         return;
 735     case 0x300f:                /* addv Rm,Rn */
 736         tcg_gen_helper_1_2(helper_addv, REG(B11_8), REG(B7_4), REG(B11_8));
 737         return;
 738     case 0x2009:                /* and Rm,Rn */
 739         tcg_gen_and_i32(REG(B11_8), REG(B11_8), REG(B7_4));
 740         return;
 741     case 0x3000:                /* cmp/eq Rm,Rn */
 742         gen_cmp(TCG_COND_EQ, REG(B7_4), REG(B11_8));
 743         return;
 744     case 0x3003:                /* cmp/ge Rm,Rn */
 745         gen_cmp(TCG_COND_GE, REG(B7_4), REG(B11_8));
 746         return;
 747     case 0x3007:                /* cmp/gt Rm,Rn */
 748         gen_cmp(TCG_COND_GT, REG(B7_4), REG(B11_8));
 749         return;
 750     case 0x3006:                /* cmp/hi Rm,Rn */
 751         gen_cmp(TCG_COND_GTU, REG(B7_4), REG(B11_8));
 752         return;
 753     case 0x3002:                /* cmp/hs Rm,Rn */
 754         gen_cmp(TCG_COND_GEU, REG(B7_4), REG(B11_8));
 755         return;
 756     case 0x200c:                /* cmp/str Rm,Rn */
 757         {
 758             int label1 = gen_new_label();
 759             int label2 = gen_new_label();
 760             TCGv cmp1 = tcg_temp_local_new(TCG_TYPE_I32);
 761             TCGv cmp2 = tcg_temp_local_new(TCG_TYPE_I32);
 762             tcg_gen_xor_i32(cmp1, REG(B7_4), REG(B11_8));
 763             tcg_gen_andi_i32(cmp2, cmp1, 0xff000000);
 764             tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);
 765             tcg_gen_andi_i32(cmp2, cmp1, 0x00ff0000);
 766             tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);
 767             tcg_gen_andi_i32(cmp2, cmp1, 0x0000ff00);
 768             tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);
 769             tcg_gen_andi_i32(cmp2, cmp1, 0x000000ff);
 770             tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);
 771             tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
 772             tcg_gen_br(label2);
 773             gen_set_label(label1);
 774             tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_T);
 775             gen_set_label(label2);
 776             tcg_temp_free(cmp2);
 777             tcg_temp_free(cmp1);
 778         }
 779         return;
 780     case 0x2007:                /* div0s Rm,Rn */
 781         {
 782             gen_copy_bit_i32(cpu_sr, 8, REG(B11_8), 31);        /* SR_Q */
 783             gen_copy_bit_i32(cpu_sr, 9, REG(B7_4), 31);         /* SR_M */
 784             TCGv val = tcg_temp_new(TCG_TYPE_I32);
 785             tcg_gen_xor_i32(val, REG(B7_4), REG(B11_8));
 786             gen_copy_bit_i32(cpu_sr, 0, val, 31);               /* SR_T */
 787             tcg_temp_free(val);
 788         }
 789         return;
 790     case 0x3004:                /* div1 Rm,Rn */
 791         tcg_gen_helper_1_2(helper_div1, REG(B11_8), REG(B7_4), REG(B11_8));
 792         return;
 793     case 0x300d:                /* dmuls.l Rm,Rn */
 794         {
 795             TCGv tmp1 = tcg_temp_new(TCG_TYPE_I64);
 796             TCGv tmp2 = tcg_temp_new(TCG_TYPE_I64);
 797
 798             tcg_gen_ext_i32_i64(tmp1, REG(B7_4));
 799             tcg_gen_ext_i32_i64(tmp2, REG(B11_8));
 800             tcg_gen_mul_i64(tmp1, tmp1, tmp2);
 801             tcg_gen_trunc_i64_i32(cpu_macl, tmp1);
 802             tcg_gen_shri_i64(tmp1, tmp1, 32);
 803             tcg_gen_trunc_i64_i32(cpu_mach, tmp1);
 804
 805             tcg_temp_free(tmp2);
 806             tcg_temp_free(tmp1);
 807         }
 808         return;
 809     case 0x3005:                /* dmulu.l Rm,Rn */
 810         {
 811             TCGv tmp1 = tcg_temp_new(TCG_TYPE_I64);
 812             TCGv tmp2 = tcg_temp_new(TCG_TYPE_I64);
 813
 814             tcg_gen_extu_i32_i64(tmp1, REG(B7_4));
 815             tcg_gen_extu_i32_i64(tmp2, REG(B11_8));
 816             tcg_gen_mul_i64(tmp1, tmp1, tmp2);
 817             tcg_gen_trunc_i64_i32(cpu_macl, tmp1);
 818             tcg_gen_shri_i64(tmp1, tmp1, 32);
 819             tcg_gen_trunc_i64_i32(cpu_mach, tmp1);
 820
 821             tcg_temp_free(tmp2);
 822             tcg_temp_free(tmp1);
 823         }
 824         return;
 825     case 0x600e:                /* exts.b Rm,Rn */
 826         tcg_gen_ext8s_i32(REG(B11_8), REG(B7_4));
 827         return;
 828     case 0x600f:                /* exts.w Rm,Rn */
 829         tcg_gen_ext16s_i32(REG(B11_8), REG(B7_4));
 830         return;
 831     case 0x600c:                /* extu.b Rm,Rn */
 832         tcg_gen_ext8u_i32(REG(B11_8), REG(B7_4));
 833         return;
 834     case 0x600d:                /* extu.w Rm,Rn */
 835         tcg_gen_ext16u_i32(REG(B11_8), REG(B7_4));
 836         return;
 837     case 0x000f:                /* mac.l @Rm+,@Rn+ */
 838         {
 839             TCGv arg0, arg1;
 840             arg0 = tcg_temp_new(TCG_TYPE_I32);
 841             tcg_gen_qemu_ld32s(arg0, REG(B7_4), ctx->memidx);
 842             arg1 = tcg_temp_new(TCG_TYPE_I32);
 843             tcg_gen_qemu_ld32s(arg1, REG(B11_8), ctx->memidx);
 844             tcg_gen_helper_0_2(helper_macl, arg0, arg1);
 845             tcg_temp_free(arg1);
 846             tcg_temp_free(arg0);
 847             tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
 848             tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
 849         }
 850         return;
 851     case 0x400f:                /* mac.w @Rm+,@Rn+ */
 852         {
 853             TCGv arg0, arg1;
 854             arg0 = tcg_temp_new(TCG_TYPE_I32);
 855             tcg_gen_qemu_ld32s(arg0, REG(B7_4), ctx->memidx);
 856             arg1 = tcg_temp_new(TCG_TYPE_I32);
 857             tcg_gen_qemu_ld32s(arg1, REG(B11_8), ctx->memidx);
 858             tcg_gen_helper_0_2(helper_macw, arg0, arg1);
 859             tcg_temp_free(arg1);
 860             tcg_temp_free(arg0);
 861             tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 2);
 862             tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2);
 863         }
 864         return;
 865     case 0x0007:                /* mul.l Rm,Rn */
 866         tcg_gen_mul_i32(cpu_macl, REG(B7_4), REG(B11_8));
 867         return;
 868     case 0x200f:                /* muls.w Rm,Rn */
 869         {
 870             TCGv arg0, arg1;
 871             arg0 = tcg_temp_new(TCG_TYPE_I32);
 872             tcg_gen_ext16s_i32(arg0, REG(B7_4));
 873             arg1 = tcg_temp_new(TCG_TYPE_I32);
 874             tcg_gen_ext16s_i32(arg1, REG(B11_8));
 875             tcg_gen_mul_i32(cpu_macl, arg0, arg1);
 876             tcg_temp_free(arg1);
 877             tcg_temp_free(arg0);
 878         }
 879         return;
 880     case 0x200e:                /* mulu.w Rm,Rn */
 881         {
 882             TCGv arg0, arg1;
 883             arg0 = tcg_temp_new(TCG_TYPE_I32);
 884             tcg_gen_ext16u_i32(arg0, REG(B7_4));
 885             arg1 = tcg_temp_new(TCG_TYPE_I32);
 886             tcg_gen_ext16u_i32(arg1, REG(B11_8));
 887             tcg_gen_mul_i32(cpu_macl, arg0, arg1);
 888             tcg_temp_free(arg1);
 889             tcg_temp_free(arg0);
 890         }
 891         return;
 892     case 0x600b:                /* neg Rm,Rn */
 893         tcg_gen_neg_i32(REG(B11_8), REG(B7_4));
 894         return;
 895     case 0x600a:                /* negc Rm,Rn */
 896         tcg_gen_helper_1_1(helper_negc, REG(B11_8), REG(B7_4));
 897         return;
 898     case 0x6007:                /* not Rm,Rn */
 899         tcg_gen_not_i32(REG(B11_8), REG(B7_4));
 900         return;
 901     case 0x200b:                /* or Rm,Rn */
 902         tcg_gen_or_i32(REG(B11_8), REG(B11_8), REG(B7_4));
 903         return;
 904     case 0x400c:                /* shad Rm,Rn */
 905         {
 906             int label1 = gen_new_label();
 907             int label2 = gen_new_label();
 908             int label3 = gen_new_label();
 909             int label4 = gen_new_label();
 910             TCGv shift = tcg_temp_local_new(TCG_TYPE_I32);
 911             tcg_gen_brcondi_i32(TCG_COND_LT, REG(B7_4), 0, label1);
 912             /* Rm positive, shift to the left */
 913             tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
 914             tcg_gen_shl_i32(REG(B11_8), REG(B11_8), shift);
 915             tcg_gen_br(label4);
 916             /* Rm negative, shift to the right */
 917             gen_set_label(label1);
 918             tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
 919             tcg_gen_brcondi_i32(TCG_COND_EQ, shift, 0, label2);
 920             tcg_gen_not_i32(shift, REG(B7_4));
 921             tcg_gen_andi_i32(shift, shift, 0x1f);
 922             tcg_gen_addi_i32(shift, shift, 1);
 923             tcg_gen_sar_i32(REG(B11_8), REG(B11_8), shift);
 924             tcg_gen_br(label4);
 925             /* Rm = -32 */
 926             gen_set_label(label2);
 927             tcg_gen_brcondi_i32(TCG_COND_LT, REG(B11_8), 0, label3);
 928             tcg_gen_movi_i32(REG(B11_8), 0);
 929             tcg_gen_br(label4);
 930             gen_set_label(label3);
 931             tcg_gen_movi_i32(REG(B11_8), 0xffffffff);
 932             gen_set_label(label4);
 933             tcg_temp_free(shift);
 934         }
 935         return;
 936     case 0x400d:                /* shld Rm,Rn */
 937         {
 938             int label1 = gen_new_label();
 939             int label2 = gen_new_label();
 940             int label3 = gen_new_label();
 941             TCGv shift = tcg_temp_local_new(TCG_TYPE_I32);
 942             tcg_gen_brcondi_i32(TCG_COND_LT, REG(B7_4), 0, label1);
 943             /* Rm positive, shift to the left */
 944             tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
 945             tcg_gen_shl_i32(REG(B11_8), REG(B11_8), shift);
 946             tcg_gen_br(label3);
 947             /* Rm negative, shift to the right */
 948             gen_set_label(label1);
 949             tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
 950             tcg_gen_brcondi_i32(TCG_COND_EQ, shift, 0, label2);
 951             tcg_gen_not_i32(shift, REG(B7_4));
 952             tcg_gen_andi_i32(shift, shift, 0x1f);
 953             tcg_gen_addi_i32(shift, shift, 1);
 954             tcg_gen_shr_i32(REG(B11_8), REG(B11_8), shift);
 955             tcg_gen_br(label3);
 956             /* Rm = -32 */
 957             gen_set_label(label2);
 958             tcg_gen_movi_i32(REG(B11_8), 0);
 959             gen_set_label(label3);
 960             tcg_temp_free(shift);
 961         }
 962         return;
 963     case 0x3008:                /* sub Rm,Rn */
 964         tcg_gen_sub_i32(REG(B11_8), REG(B11_8), REG(B7_4));
 965         return;
 966     case 0x300a:                /* subc Rm,Rn */
 967         tcg_gen_helper_1_2(helper_subc, REG(B11_8), REG(B7_4), REG(B11_8));
 968         return;
 969     case 0x300b:                /* subv Rm,Rn */
 970         tcg_gen_helper_1_2(helper_subv, REG(B11_8), REG(B7_4), REG(B11_8));
 971         return;
 972     case 0x2008:                /* tst Rm,Rn */
 973         {
 974             TCGv val = tcg_temp_new(TCG_TYPE_I32);
 975             tcg_gen_and_i32(val, REG(B7_4), REG(B11_8));
 976             gen_cmp_imm(TCG_COND_EQ, val, 0);
 977             tcg_temp_free(val);
 978         }
 979         return;
 980     case 0x200a:                /* xor Rm,Rn */
 981         tcg_gen_xor_i32(REG(B11_8), REG(B11_8), REG(B7_4));
 982         return;
 983     case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */
 984         if (ctx->fpscr & FPSCR_SZ) {
 985             TCGv fp = tcg_temp_new(TCG_TYPE_I64);
 986             gen_load_fpr64(fp, XREG(B7_4));
 987             gen_store_fpr64(fp, XREG(B11_8));
 988             tcg_temp_free(fp);
 989         } else {
 990             TCGv fp = tcg_temp_new(TCG_TYPE_I32);
 991             gen_load_fpr32(fp, FREG(B7_4));
 992             gen_store_fpr32(fp, FREG(B11_8));
 993             tcg_temp_free(fp);
 994         }
 995         return;
 996     case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
 997         if (ctx->fpscr & FPSCR_SZ) {
 998             TCGv fp = tcg_temp_new(TCG_TYPE_I64);
 999             gen_load_fpr64(fp, XREG(B7_4));
1000             tcg_gen_qemu_st64(fp, REG(B11_8), ctx->memidx);
1001             tcg_temp_free(fp);
1002         } else {
1003             TCGv fp = tcg_temp_new(TCG_TYPE_I32);
1004             gen_load_fpr32(fp, FREG(B7_4));
1005             tcg_gen_qemu_st32(fp, REG(B11_8), ctx->memidx);
1006             tcg_temp_free(fp);
1007         }
1008         return;
1009     case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
1010         if (ctx->fpscr & FPSCR_SZ) {
1011             TCGv fp = tcg_temp_new(TCG_TYPE_I64);
1012             tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx);
1013             gen_store_fpr64(fp, XREG(B11_8));
1014             tcg_temp_free(fp);
1015         } else {
1016             TCGv fp = tcg_temp_new(TCG_TYPE_I32);
1017             tcg_gen_qemu_ld32u(fp, REG(B7_4), ctx->memidx);
1018             gen_store_fpr32(fp, FREG(B11_8));
1019             tcg_temp_free(fp);
1020         }
1021         return;
1022     case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
1023         if (ctx->fpscr & FPSCR_SZ) {
1024             TCGv fp = tcg_temp_new(TCG_TYPE_I64);
1025             tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx);
1026             gen_store_fpr64(fp, XREG(B11_8));
1027             tcg_temp_free(fp);
1028             tcg_gen_addi_i32(REG(B7_4),REG(B7_4), 8);
1029         } else {
1030             TCGv fp = tcg_temp_new(TCG_TYPE_I32);
1031             tcg_gen_qemu_ld32u(fp, REG(B7_4), ctx->memidx);
1032             gen_store_fpr32(fp, FREG(B11_8));
1033             tcg_temp_free(fp);
1034             tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
1035         }
1036         return;
1037     case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */
1038         if (ctx->fpscr & FPSCR_SZ) {
1039             TCGv addr, fp;
1040             addr = tcg_temp_new(TCG_TYPE_I32);
1041             tcg_gen_subi_i32(addr, REG(B11_8), 8);
1042             fp = tcg_temp_new(TCG_TYPE_I64);
1043             gen_load_fpr64(fp, XREG(B7_4));
1044             tcg_gen_qemu_st64(fp, addr, ctx->memidx);
1045             tcg_temp_free(fp);
1046             tcg_temp_free(addr);
1047             tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 8);
1048         } else {
1049             TCGv addr, fp;
1050             addr = tcg_temp_new(TCG_TYPE_I32);
1051             tcg_gen_subi_i32(addr, REG(B11_8), 4);
1052             fp = tcg_temp_new(TCG_TYPE_I32);
1053             gen_load_fpr32(fp, FREG(B7_4));
1054             tcg_gen_qemu_st32(fp, addr, ctx->memidx);
1055             tcg_temp_free(fp);
1056             tcg_temp_free(addr);
1057             tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
1058         }
1059         return;
1060     case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */
1061         {
1062             TCGv addr = tcg_temp_new(TCG_TYPE_I32);
1063             tcg_gen_add_i32(addr, REG(B7_4), REG(0));
1064             if (ctx->fpscr & FPSCR_SZ) {
1065                 TCGv fp = tcg_temp_new(TCG_TYPE_I64);
1066                 tcg_gen_qemu_ld64(fp, addr, ctx->memidx);
1067                 gen_store_fpr64(fp, XREG(B11_8));
1068                 tcg_temp_free(fp);
1069             } else {
1070                 TCGv fp = tcg_temp_new(TCG_TYPE_I32);
1071                 tcg_gen_qemu_ld32u(fp, addr, ctx->memidx);
1072                 gen_store_fpr32(fp, FREG(B11_8));
1073                 tcg_temp_free(fp);
1074             }
1075             tcg_temp_free(addr);
1076         }
1077         return;
1078     case 0xf007: /* fmov {F,D,X}Rn,@(R0,Rn) - FPSCR: Nothing */
1079         {
1080             TCGv addr = tcg_temp_new(TCG_TYPE_I32);
1081             tcg_gen_add_i32(addr, REG(B11_8), REG(0));
1082             if (ctx->fpscr & FPSCR_SZ) {
1083                 TCGv fp = tcg_temp_new(TCG_TYPE_I64);
1084                 gen_load_fpr64(fp, XREG(B7_4));
1085                 tcg_gen_qemu_st64(fp, addr, ctx->memidx);
1086                 tcg_temp_free(fp);
1087             } else {
1088                 TCGv fp = tcg_temp_new(TCG_TYPE_I32);
1089                 gen_load_fpr32(fp, FREG(B7_4));
1090                 tcg_gen_qemu_st32(fp, addr, ctx->memidx);
1091                 tcg_temp_free(fp);
1092             }
1093             tcg_temp_free(addr);
1094         }
1095         return;
1096     case 0xf000: /* fadd Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
1097     case 0xf001: /* fsub Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
1098     case 0xf002: /* fmul Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
1099     case 0xf003: /* fdiv Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
1100     case 0xf004: /* fcmp/eq Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
1101     case 0xf005: /* fcmp/gt Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
1102         {
1103             TCGv fp0, fp1;
1104
1105             if (ctx->fpscr & FPSCR_PR) {
1106                 if (ctx->opcode & 0x0110)
1107                     break; /* illegal instruction */
1108                 fp0 = tcg_temp_new(TCG_TYPE_I64);
1109                 fp1 = tcg_temp_new(TCG_TYPE_I64);
1110                 gen_load_fpr64(fp0, DREG(B11_8));
1111                 gen_load_fpr64(fp1, DREG(B7_4));
1112             }
1113             else {
1114                 fp0 = tcg_temp_new(TCG_TYPE_I32);
1115                 fp1 = tcg_temp_new(TCG_TYPE_I32);
1116                 gen_load_fpr32(fp0, FREG(B11_8));
1117                 gen_load_fpr32(fp1, FREG(B7_4));
1118             }
1119
1120             switch (ctx->opcode & 0xf00f) {
1121             case 0xf000:                /* fadd Rm,Rn */
1122                 if (ctx->fpscr & FPSCR_PR)
1123                     tcg_gen_helper_1_2(helper_fadd_DT, fp0, fp0, fp1);
1124                 else
1125                     tcg_gen_helper_1_2(helper_fadd_FT, fp0, fp0, fp1);
1126                 break;
1127             case 0xf001:                /* fsub Rm,Rn */
1128                 if (ctx->fpscr & FPSCR_PR)
1129                     tcg_gen_helper_1_2(helper_fsub_DT, fp0, fp0, fp1);
1130                 else
1131                     tcg_gen_helper_1_2(helper_fsub_FT, fp0, fp0, fp1);
1132                 break;
1133             case 0xf002:                /* fmul Rm,Rn */
1134                 if (ctx->fpscr & FPSCR_PR)
1135                     tcg_gen_helper_1_2(helper_fmul_DT, fp0, fp0, fp1);
1136                 else
1137                     tcg_gen_helper_1_2(helper_fmul_FT, fp0, fp0, fp1);
1138                 break;
1139             case 0xf003:                /* fdiv Rm,Rn */
1140                 if (ctx->fpscr & FPSCR_PR)
1141                     tcg_gen_helper_1_2(helper_fdiv_DT, fp0, fp0, fp1);
1142                 else
1143                     tcg_gen_helper_1_2(helper_fdiv_FT, fp0, fp0, fp1);
1144                 break;
1145             case 0xf004:                /* fcmp/eq Rm,Rn */
1146                 if (ctx->fpscr & FPSCR_PR)
1147                     tcg_gen_helper_0_2(helper_fcmp_eq_DT, fp0, fp1);
1148                 else
1149                     tcg_gen_helper_0_2(helper_fcmp_eq_FT, fp0, fp1);
1150                 return;
1151             case 0xf005:                /* fcmp/gt Rm,Rn */
1152                 if (ctx->fpscr & FPSCR_PR)
1153                     tcg_gen_helper_0_2(helper_fcmp_gt_DT, fp0, fp1);
1154                 else
1155                     tcg_gen_helper_0_2(helper_fcmp_gt_FT, fp0, fp1);
1156                 return;
1157             }
1158
1159             if (ctx->fpscr & FPSCR_PR) {
1160                 gen_store_fpr64(fp0, DREG(B11_8));
1161             }
1162             else {
1163                 gen_store_fpr32(fp0, FREG(B11_8));
1164             }
1165             tcg_temp_free(fp1);
1166             tcg_temp_free(fp0);
1167         }
1168         return;
1169     }
1170
1171     switch (ctx->opcode & 0xff00) {
1172     case 0xc900:                /* and #imm,R0 */
1173         tcg_gen_andi_i32(REG(0), REG(0), B7_0);
1174         return;
1175     case 0xcd00:                /* and.b #imm,@(R0,GBR) */
1176         {
1177             TCGv addr, val;
1178             addr = tcg_temp_new(TCG_TYPE_I32);
1179             tcg_gen_add_i32(addr, REG(0), cpu_gbr);
1180             val = tcg_temp_new(TCG_TYPE_I32);
1181             tcg_gen_qemu_ld8u(val, addr, ctx->memidx);
1182             tcg_gen_andi_i32(val, val, B7_0);
1183             tcg_gen_qemu_st8(val, addr, ctx->memidx);
1184             tcg_temp_free(val);
1185             tcg_temp_free(addr);
1186         }
1187         return;
1188     case 0x8b00:                /* bf label */
1189         CHECK_NOT_DELAY_SLOT
1190             gen_conditional_jump(ctx, ctx->pc + 2,
1191                                  ctx->pc + 4 + B7_0s * 2);
1192         ctx->bstate = BS_BRANCH;
1193         return;
1194     case 0x8f00:                /* bf/s label */
1195         CHECK_NOT_DELAY_SLOT
1196         gen_branch_slot(ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2, 0);
1197         ctx->flags |= DELAY_SLOT_CONDITIONAL;
1198         return;
1199     case 0x8900:                /* bt label */
1200         CHECK_NOT_DELAY_SLOT
1201             gen_conditional_jump(ctx, ctx->pc + 4 + B7_0s * 2,
1202                                  ctx->pc + 2);
1203         ctx->bstate = BS_BRANCH;
1204         return;
1205     case 0x8d00:                /* bt/s label */
1206         CHECK_NOT_DELAY_SLOT
1207         gen_branch_slot(ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2, 1);
1208         ctx->flags |= DELAY_SLOT_CONDITIONAL;
1209         return;
1210     case 0x8800:                /* cmp/eq #imm,R0 */
1211         gen_cmp_imm(TCG_COND_EQ, REG(0), B7_0s);
1212         return;
1213     case 0xc400:                /* mov.b @(disp,GBR),R0 */
1214         {
1215             TCGv addr = tcg_temp_new(TCG_TYPE_I32);
1216             tcg_gen_addi_i32(addr, cpu_gbr, B7_0);
1217             tcg_gen_qemu_ld8s(REG(0), addr, ctx->memidx);
1218             tcg_temp_free(addr);
1219         }
1220         return;
1221     case 0xc500:                /* mov.w @(disp,GBR),R0 */
1222         {
1223             TCGv addr = tcg_temp_new(TCG_TYPE_I32);
1224             tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 2);
1225             tcg_gen_qemu_ld16s(REG(0), addr, ctx->memidx);
1226             tcg_temp_free(addr);
1227         }
1228         return;
1229     case 0xc600:                /* mov.l @(disp,GBR),R0 */
1230         {
1231             TCGv addr = tcg_temp_new(TCG_TYPE_I32);
1232             tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 4);
1233             tcg_gen_qemu_ld32s(REG(0), addr, ctx->memidx);
1234             tcg_temp_free(addr);
1235         }
1236         return;
1237     case 0xc000:                /* mov.b R0,@(disp,GBR) */
1238         {
1239             TCGv addr = tcg_temp_new(TCG_TYPE_I32);
1240             tcg_gen_addi_i32(addr, cpu_gbr, B7_0);
1241             tcg_gen_qemu_st8(REG(0), addr, ctx->memidx);
1242             tcg_temp_free(addr);
1243         }
1244         return;
1245     case 0xc100:                /* mov.w R0,@(disp,GBR) */
1246         {
1247             TCGv addr = tcg_temp_new(TCG_TYPE_I32);
1248             tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 2);
1249             tcg_gen_qemu_st16(REG(0), addr, ctx->memidx);
1250             tcg_temp_free(addr);
1251         }
1252         return;
1253     case 0xc200:                /* mov.l R0,@(disp,GBR) */
1254         {
1255             TCGv addr = tcg_temp_new(TCG_TYPE_I32);
1256             tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 4);
1257             tcg_gen_qemu_st32(REG(0), addr, ctx->memidx);
1258             tcg_temp_free(addr);
1259         }
1260         return;
1261     case 0x8000:                /* mov.b R0,@(disp,Rn) */
1262         {
1263             TCGv addr = tcg_temp_new(TCG_TYPE_I32);
1264             tcg_gen_addi_i32(addr, REG(B7_4), B3_0);
1265             tcg_gen_qemu_st8(REG(0), addr, ctx->memidx);
1266             tcg_temp_free(addr);
1267         }
1268         return;
1269     case 0x8100:                /* mov.w R0,@(disp,Rn) */
1270         {
1271             TCGv addr = tcg_temp_new(TCG_TYPE_I32);
1272             tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2);
1273             tcg_gen_qemu_st16(REG(0), addr, ctx->memidx);
1274             tcg_temp_free(addr);
1275         }
1276         return;
1277     case 0x8400:                /* mov.b @(disp,Rn),R0 */
1278         {
1279             TCGv addr = tcg_temp_new(TCG_TYPE_I32);
1280             tcg_gen_addi_i32(addr, REG(B7_4), B3_0);
1281             tcg_gen_qemu_ld8s(REG(0), addr, ctx->memidx);
1282             tcg_temp_free(addr);
1283         }
1284         return;
1285     case 0x8500:                /* mov.w @(disp,Rn),R0 */
1286         {
1287             TCGv addr = tcg_temp_new(TCG_TYPE_I32);
1288             tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2);
1289             tcg_gen_qemu_ld16s(REG(0), addr, ctx->memidx);
1290             tcg_temp_free(addr);
1291         }
1292         return;
1293     case 0xc700:                /* mova @(disp,PC),R0 */
1294         tcg_gen_movi_i32(REG(0), ((ctx->pc & 0xfffffffc) + 4 + B7_0 * 4) & ~3);
1295         return;
1296     case 0xcb00:                /* or #imm,R0 */
1297         tcg_gen_ori_i32(REG(0), REG(0), B7_0);
1298         return;
1299     case 0xcf00:                /* or.b #imm,@(R0,GBR) */
1300         {
1301             TCGv addr, val;
1302             addr = tcg_temp_new(TCG_TYPE_I32);
1303             tcg_gen_add_i32(addr, REG(0), cpu_gbr);
1304             val = tcg_temp_new(TCG_TYPE_I32);
1305             tcg_gen_qemu_ld8u(val, addr, ctx->memidx);
1306             tcg_gen_ori_i32(val, val, B7_0);
1307             tcg_gen_qemu_st8(val, addr, ctx->memidx);
1308             tcg_temp_free(val);
1309             tcg_temp_free(addr);
1310         }
1311         return;
1312     case 0xc300:                /* trapa #imm */
1313         {
1314             TCGv imm;
1315             CHECK_NOT_DELAY_SLOT
1316             tcg_gen_movi_i32(cpu_pc, ctx->pc);
1317             imm = tcg_const_i32(B7_0);
1318             tcg_gen_helper_0_1(helper_trapa, imm);
1319             tcg_temp_free(imm);
1320             ctx->bstate = BS_BRANCH;
1321         }
1322         return;
1323     case 0xc800:                /* tst #imm,R0 */
1324         {
1325             TCGv val = tcg_temp_new(TCG_TYPE_I32);
1326             tcg_gen_andi_i32(val, REG(0), B7_0);
1327             gen_cmp_imm(TCG_COND_EQ, val, 0);
1328             tcg_temp_free(val);
1329         }
1330         return;
1331     case 0xcc00:                /* tst.b #imm,@(R0,GBR) */
1332         {
1333             TCGv val = tcg_temp_new(TCG_TYPE_I32);
1334             tcg_gen_add_i32(val, REG(0), cpu_gbr);
1335             tcg_gen_qemu_ld8u(val, val, ctx->memidx);
1336             tcg_gen_andi_i32(val, val, B7_0);
1337             gen_cmp_imm(TCG_COND_EQ, val, 0);
1338             tcg_temp_free(val);
1339         }
1340         return;
1341     case 0xca00:                /* xor #imm,R0 */
1342         tcg_gen_xori_i32(REG(0), REG(0), B7_0);
1343         return;
1344     case 0xce00:                /* xor.b #imm,@(R0,GBR) */
1345         {
1346             TCGv addr, val;
1347             addr = tcg_temp_new(TCG_TYPE_I32);
1348             tcg_gen_add_i32(addr, REG(0), cpu_gbr);
1349             val = tcg_temp_new(TCG_TYPE_I32);
1350             tcg_gen_qemu_ld8u(val, addr, ctx->memidx);
1351             tcg_gen_xori_i32(val, val, B7_0);
1352             tcg_gen_qemu_st8(val, addr, ctx->memidx);
1353             tcg_temp_free(val);
1354             tcg_temp_free(addr);
1355         }
1356         return;
1357     }
1358
1359     switch (ctx->opcode & 0xf08f) {
1360     case 0x408e:                /* ldc Rm,Rn_BANK */
1361         CHECK_PRIVILEGED
1362         tcg_gen_mov_i32(ALTREG(B6_4), REG(B11_8));
1363         return;
1364     case 0x4087:                /* ldc.l @Rm+,Rn_BANK */
1365         CHECK_PRIVILEGED
1366         tcg_gen_qemu_ld32s(ALTREG(B6_4), REG(B11_8), ctx->memidx);
1367         tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
1368         return;
1369     case 0x0082:                /* stc Rm_BANK,Rn */
1370         CHECK_PRIVILEGED
1371         tcg_gen_mov_i32(REG(B11_8), ALTREG(B6_4));
1372         return;
1373     case 0x4083:                /* stc.l Rm_BANK,@-Rn */
1374         CHECK_PRIVILEGED
1375         {
1376             TCGv addr = tcg_temp_new(TCG_TYPE_I32);
1377             tcg_gen_subi_i32(addr, REG(B11_8), 4);
1378             tcg_gen_qemu_st32(ALTREG(B6_4), addr, ctx->memidx);
1379             tcg_temp_free(addr);
1380             tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
1381         }
1382         return;
1383     }
1384
1385     switch (ctx->opcode & 0xf0ff) {
1386     case 0x0023:                /* braf Rn */
1387         CHECK_NOT_DELAY_SLOT
1388         tcg_gen_addi_i32(cpu_delayed_pc, REG(B11_8), ctx->pc + 4);
1389         ctx->flags |= DELAY_SLOT;
1390         ctx->delayed_pc = (uint32_t) - 1;
1391         return;
1392     case 0x0003:                /* bsrf Rn */
1393         CHECK_NOT_DELAY_SLOT
1394         tcg_gen_movi_i32(cpu_pr, ctx->pc + 4);
1395         tcg_gen_add_i32(cpu_delayed_pc, REG(B11_8), cpu_pr);
1396         ctx->flags |= DELAY_SLOT;
1397         ctx->delayed_pc = (uint32_t) - 1;
1398         return;
1399     case 0x4015:                /* cmp/pl Rn */
1400         gen_cmp_imm(TCG_COND_GT, REG(B11_8), 0);
1401         return;
1402     case 0x4011:                /* cmp/pz Rn */
1403         gen_cmp_imm(TCG_COND_GE, REG(B11_8), 0);
1404         return;
1405     case 0x4010:                /* dt Rn */
1406         tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 1);
1407         gen_cmp_imm(TCG_COND_EQ, REG(B11_8), 0);
1408         return;
1409     case 0x402b:                /* jmp @Rn */
1410         CHECK_NOT_DELAY_SLOT
1411         tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8));
1412         ctx->flags |= DELAY_SLOT;
1413         ctx->delayed_pc = (uint32_t) - 1;
1414         return;
1415     case 0x400b:                /* jsr @Rn */
1416         CHECK_NOT_DELAY_SLOT
1417         tcg_gen_movi_i32(cpu_pr, ctx->pc + 4);
1418         tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8));
1419         ctx->flags |= DELAY_SLOT;
1420         ctx->delayed_pc = (uint32_t) - 1;
1421         return;
1422     case 0x400e:                /* ldc Rm,SR */
1423         CHECK_PRIVILEGED
1424         tcg_gen_andi_i32(cpu_sr, REG(B11_8), 0x700083f3);
1425         ctx->bstate = BS_STOP;
1426         return;
1427     case 0x4007:                /* ldc.l @Rm+,SR */
1428         CHECK_PRIVILEGED
1429         {
1430             TCGv val = tcg_temp_new(TCG_TYPE_I32);
1431             tcg_gen_qemu_ld32s(val, REG(B11_8), ctx->memidx);
1432             tcg_gen_andi_i32(cpu_sr, val, 0x700083f3);
1433             tcg_temp_free(val);
1434             tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
1435             ctx->bstate = BS_STOP;
1436         }
1437         return;
1438     case 0x0002:                /* stc SR,Rn */
1439         CHECK_PRIVILEGED
1440         tcg_gen_mov_i32(REG(B11_8), cpu_sr);
1441         return;
1442     case 0x4003:                /* stc SR,@-Rn */
1443         CHECK_PRIVILEGED
1444         {
1445             TCGv addr = tcg_temp_new(TCG_TYPE_I32);
1446             tcg_gen_subi_i32(addr, REG(B11_8), 4);
1447             tcg_gen_qemu_st32(cpu_sr, addr, ctx->memidx);
1448             tcg_temp_free(addr);
1449             tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
1450         }
1451         return;
1452 #define LDST(reg,ldnum,ldpnum,stnum,stpnum,prechk)              \
1453   case ldnum:                                                   \
1454     prechk                                                      \
1455     tcg_gen_mov_i32 (cpu_##reg, REG(B11_8));                    \
1456     return;                                                     \
1457   case ldpnum:                                                  \
1458     prechk                                                      \
1459     tcg_gen_qemu_ld32s (cpu_##reg, REG(B11_8), ctx->memidx);    \
1460     tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);                \
1461     return;                                                     \
1462   case stnum:                                                   \
1463     prechk                                                      \
1464     tcg_gen_mov_i32 (REG(B11_8), cpu_##reg);                    \
1465     return;                                                     \
1466   case stpnum:                                                  \
1467     prechk                                                      \
1468     {                                                           \
1469         TCGv addr = tcg_temp_new(TCG_TYPE_I32);                 \
1470         tcg_gen_subi_i32(addr, REG(B11_8), 4);                  \
1471         tcg_gen_qemu_st32 (cpu_##reg, addr, ctx->memidx);       \
1472         tcg_temp_free(addr);                                    \
1473         tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);            \
1474     }                                                           \
1475     return;
1476         LDST(gbr,  0x401e, 0x4017, 0x0012, 0x4013, {})
1477         LDST(vbr,  0x402e, 0x4027, 0x0022, 0x4023, CHECK_PRIVILEGED)
1478         LDST(ssr,  0x403e, 0x4037, 0x0032, 0x4033, CHECK_PRIVILEGED)
1479         LDST(spc,  0x404e, 0x4047, 0x0042, 0x4043, CHECK_PRIVILEGED)
1480         LDST(dbr,  0x40fa, 0x40f6, 0x00fa, 0x40f2, CHECK_PRIVILEGED)
1481         LDST(mach, 0x400a, 0x4006, 0x000a, 0x4002, {})
1482         LDST(macl, 0x401a, 0x4016, 0x001a, 0x4012, {})
1483         LDST(pr,   0x402a, 0x4026, 0x002a, 0x4022, {})
1484         LDST(fpul, 0x405a, 0x4056, 0x005a, 0x4052, {})
1485     case 0x406a:                /* lds Rm,FPSCR */
1486         tcg_gen_helper_0_1(helper_ld_fpscr, REG(B11_8));
1487         ctx->bstate = BS_STOP;
1488         return;
1489     case 0x4066:                /* lds.l @Rm+,FPSCR */
1490         {
1491             TCGv addr = tcg_temp_new(TCG_TYPE_I32);
1492             tcg_gen_qemu_ld32s(addr, REG(B11_8), ctx->memidx);
1493             tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
1494             tcg_gen_helper_0_1(helper_ld_fpscr, addr);
1495             tcg_temp_free(addr);
1496             ctx->bstate = BS_STOP;
1497         }
1498         return;
1499     case 0x006a:                /* sts FPSCR,Rn */
1500         tcg_gen_andi_i32(REG(B11_8), cpu_fpscr, 0x003fffff);
1501         return;
1502     case 0x4062:                /* sts FPSCR,@-Rn */
1503         {
1504             TCGv addr, val;
1505             val = tcg_temp_new(TCG_TYPE_I32);
1506             tcg_gen_andi_i32(val, cpu_fpscr, 0x003fffff);
1507             addr = tcg_temp_new(TCG_TYPE_I32);
1508             tcg_gen_subi_i32(addr, REG(B11_8), 4);
1509             tcg_gen_qemu_st32(val, addr, ctx->memidx);
1510             tcg_temp_free(addr);
1511             tcg_temp_free(val);
1512             tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
1513         }
1514         return;
1515     case 0x00c3:                /* movca.l R0,@Rm */
1516         tcg_gen_qemu_st32(REG(0), REG(B11_8), ctx->memidx);
1517         return;
1518     case 0x0029:                /* movt Rn */
1519         tcg_gen_andi_i32(REG(B11_8), cpu_sr, SR_T);
1520         return;
1521     case 0x0093:                /* ocbi @Rn */
1522         {
1523             TCGv dummy = tcg_temp_new(TCG_TYPE_I32);
1524             tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx);
1525             tcg_temp_free(dummy);
1526         }
1527         return;
1528     case 0x00a3:                /* ocbp @Rn */
1529         {
1530             TCGv dummy = tcg_temp_new(TCG_TYPE_I32);
1531             tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx);
1532             tcg_temp_free(dummy);
1533         }
1534         return;
1535     case 0x00b3:                /* ocbwb @Rn */
1536         {
1537             TCGv dummy = tcg_temp_new(TCG_TYPE_I32);
1538             tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx);
1539             tcg_temp_free(dummy);
1540         }
1541         return;
1542     case 0x0083:                /* pref @Rn */
1543         return;
1544     case 0x4024:                /* rotcl Rn */
1545         {
1546             TCGv tmp = tcg_temp_new(TCG_TYPE_I32);
1547             tcg_gen_mov_i32(tmp, cpu_sr);
1548             gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31);
1549             tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1);
1550             gen_copy_bit_i32(REG(B11_8), 0, tmp, 0);
1551             tcg_temp_free(tmp);
1552         }
1553         return;
1554     case 0x4025:                /* rotcr Rn */
1555         {
1556             TCGv tmp = tcg_temp_new(TCG_TYPE_I32);
1557             tcg_gen_mov_i32(tmp, cpu_sr);
1558             gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0);
1559             tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1);
1560             gen_copy_bit_i32(REG(B11_8), 31, tmp, 0);
1561             tcg_temp_free(tmp);
1562         }
1563         return;
1564     case 0x4004:                /* rotl Rn */
1565         gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31);
1566         tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1);
1567         gen_copy_bit_i32(REG(B11_8), 0, cpu_sr, 0);
1568         return;
1569     case 0x4005:                /* rotr Rn */
1570         gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0);
1571         tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1);
1572         gen_copy_bit_i32(REG(B11_8), 31, cpu_sr, 0);
1573         return;
1574     case 0x4000:                /* shll Rn */
1575     case 0x4020:                /* shal Rn */
1576         gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31);
1577         tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1);
1578         return;
1579     case 0x4021:                /* shar Rn */
1580         gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0);
1581         tcg_gen_sari_i32(REG(B11_8), REG(B11_8), 1);
1582         return;
1583     case 0x4001:                /* shlr Rn */
1584         gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0);
1585         tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1);
1586         return;
1587     case 0x4008:                /* shll2 Rn */
1588         tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 2);
1589         return;
1590     case 0x4018:                /* shll8 Rn */
1591         tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 8);
1592         return;
1593     case 0x4028:                /* shll16 Rn */
1594         tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 16);
1595         return;
1596     case 0x4009:                /* shlr2 Rn */
1597         tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 2);
1598         return;
1599     case 0x4019:                /* shlr8 Rn */
1600         tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 8);
1601         return;
1602     case 0x4029:                /* shlr16 Rn */
1603         tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 16);
1604         return;
1605     case 0x401b:                /* tas.b @Rn */
1606         {
1607             TCGv addr, val;
1608             addr = tcg_temp_local_new(TCG_TYPE_I32);
1609             tcg_gen_mov_i32(addr, REG(B11_8));
1610             val = tcg_temp_local_new(TCG_TYPE_I32);
1611             tcg_gen_qemu_ld8u(val, addr, ctx->memidx);
1612             gen_cmp_imm(TCG_COND_EQ, val, 0);
1613             tcg_gen_ori_i32(val, val, 0x80);
1614             tcg_gen_qemu_st8(val, addr, ctx->memidx);
1615             tcg_temp_free(val);
1616             tcg_temp_free(addr);
1617         }
1618         return;
1619     case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */
1620         {
1621             TCGv fp = tcg_temp_new(TCG_TYPE_I32);
1622             tcg_gen_mov_i32(fp, cpu_fpul);
1623             gen_store_fpr32(fp, FREG(B11_8));
1624             tcg_temp_free(fp);
1625         }
1626         return;
1627     case 0xf01d: /* flds FRm,FPUL - FPSCR: Nothing */
1628         {
1629             TCGv fp = tcg_temp_new(TCG_TYPE_I32);
1630             gen_load_fpr32(fp, FREG(B11_8));
1631             tcg_gen_mov_i32(cpu_fpul, fp);
1632             tcg_temp_free(fp);
1633         }
1634         return;
1635     case 0xf02d: /* float FPUL,FRn/DRn - FPSCR: R[PR,Enable.I]/W[Cause,Flag] */
1636         if (ctx->fpscr & FPSCR_PR) {
1637             TCGv fp;
1638             if (ctx->opcode & 0x0100)
1639                 break; /* illegal instruction */
1640             fp = tcg_temp_new(TCG_TYPE_I64);
1641             tcg_gen_helper_1_1(helper_float_DT, fp, cpu_fpul);
1642             gen_store_fpr64(fp, DREG(B11_8));
1643             tcg_temp_free(fp);
1644         }
1645         else {
1646             TCGv fp = tcg_temp_new(TCG_TYPE_I32);
1647             tcg_gen_helper_1_1(helper_float_FT, fp, cpu_fpul);
1648             gen_store_fpr32(fp, FREG(B11_8));
1649             tcg_temp_free(fp);
1650         }
1651         return;
1652     case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
1653         if (ctx->fpscr & FPSCR_PR) {
1654             TCGv fp;
1655             if (ctx->opcode & 0x0100)
1656                 break; /* illegal instruction */
1657             fp = tcg_temp_new(TCG_TYPE_I64);
1658             gen_load_fpr64(fp, DREG(B11_8));
1659             tcg_gen_helper_1_1(helper_ftrc_DT, cpu_fpul, fp);
1660             tcg_temp_free(fp);
1661         }
1662         else {
1663             TCGv fp = tcg_temp_new(TCG_TYPE_I32);
1664             gen_load_fpr32(fp, FREG(B11_8));
1665             tcg_gen_helper_1_1(helper_ftrc_FT, cpu_fpul, fp);
1666             tcg_temp_free(fp);
1667         }
1668         return;
1669     case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */
1670         {
1671             TCGv fp = tcg_temp_new(TCG_TYPE_I32);
1672             gen_load_fpr32(fp, FREG(B11_8));
1673             tcg_gen_helper_1_1(helper_fneg_T, fp, fp);
1674             gen_store_fpr32(fp, FREG(B11_8));
1675             tcg_temp_free(fp);
1676         }
1677         return;
1678     case 0xf05d: /* fabs FRn/DRn */
1679         if (ctx->fpscr & FPSCR_PR) {
1680             if (ctx->opcode & 0x0100)
1681                 break; /* illegal instruction */
1682             TCGv fp = tcg_temp_new(TCG_TYPE_I64);
1683             gen_load_fpr64(fp, DREG(B11_8));
1684             tcg_gen_helper_1_1(helper_fabs_DT, fp, fp);
1685             gen_store_fpr64(fp, DREG(B11_8));
1686             tcg_temp_free(fp);
1687         } else {
1688             TCGv fp = tcg_temp_new(TCG_TYPE_I32);
1689             gen_load_fpr32(fp, FREG(B11_8));
1690             tcg_gen_helper_1_1(helper_fabs_FT, fp, fp);
1691             gen_store_fpr32(fp, FREG(B11_8));
1692             tcg_temp_free(fp);
1693         }
1694         return;
1695     case 0xf06d: /* fsqrt FRn */
1696         if (ctx->fpscr & FPSCR_PR) {
1697             if (ctx->opcode & 0x0100)
1698                 break; /* illegal instruction */
1699             TCGv fp = tcg_temp_new(TCG_TYPE_I64);
1700             gen_load_fpr64(fp, DREG(B11_8));
1701             tcg_gen_helper_1_1(helper_fsqrt_DT, fp, fp);
1702             gen_store_fpr64(fp, DREG(B11_8));
1703             tcg_temp_free(fp);
1704         } else {
1705             TCGv fp = tcg_temp_new(TCG_TYPE_I32);
1706             gen_load_fpr32(fp, FREG(B11_8));
1707             tcg_gen_helper_1_1(helper_fsqrt_FT, fp, fp);
1708             gen_store_fpr32(fp, FREG(B11_8));
1709             tcg_temp_free(fp);
1710         }
1711         return;
1712     case 0xf07d: /* fsrra FRn */
1713         break;
1714     case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */
1715         if (!(ctx->fpscr & FPSCR_PR)) {
1716             TCGv val = tcg_const_i32(0);
1717             gen_load_fpr32(val, FREG(B11_8));
1718             tcg_temp_free(val);
1719             return;
1720         }
1721         break;
1722     case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */
1723         if (!(ctx->fpscr & FPSCR_PR)) {
1724             TCGv val = tcg_const_i32(0x3f800000);
1725             gen_load_fpr32(val, FREG(B11_8));
1726             tcg_temp_free(val);
1727             return;
1728         }
1729         break;
1730     case 0xf0ad: /* fcnvsd FPUL,DRn */
1731         {
1732             TCGv fp = tcg_temp_new(TCG_TYPE_I64);
1733             tcg_gen_helper_1_1(helper_fcnvsd_FT_DT, fp, cpu_fpul);
1734             gen_store_fpr64(fp, DREG(B11_8));
1735             tcg_temp_free(fp);
1736         }
1737         return;
1738     case 0xf0bd: /* fcnvds DRn,FPUL */
1739         {
1740             TCGv fp = tcg_temp_new(TCG_TYPE_I64);
1741             gen_load_fpr64(fp, DREG(B11_8));
1742             tcg_gen_helper_1_1(helper_fcnvds_DT_FT, cpu_fpul, fp);
1743             tcg_temp_free(fp);
1744         }
1745         return;
1746     }
1747
1748     fprintf(stderr, "unknown instruction 0x%04x at pc 0x%08x\n",
1749             ctx->opcode, ctx->pc);
1750     tcg_gen_helper_0_0(helper_raise_illegal_instruction);
1751     ctx->bstate = BS_EXCP;
1752 }
1753
1754 void decode_opc(DisasContext * ctx)
1755 {
1756     uint32_t old_flags = ctx->flags;
1757
1758     _decode_opc(ctx);
1759
1760     if (old_flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
1761         if (ctx->flags & DELAY_SLOT_CLEARME) {
1762             gen_store_flags(0);
1763         } else {
1764             /* go out of the delay slot */
1765             uint32_t new_flags = ctx->flags;
1766             new_flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL);
1767             gen_store_flags(new_flags);
1768         }
1769         ctx->flags = 0;
1770         ctx->bstate = BS_BRANCH;
1771         if (old_flags & DELAY_SLOT_CONDITIONAL) {
1772             gen_delayed_conditional_jump(ctx);
1773         } else if (old_flags & DELAY_SLOT) {
1774             gen_jump(ctx);
1775         }
1776
1777     }
1778
1779     /* go into a delay slot */
1780     if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL))
1781         gen_store_flags(ctx->flags);
1782 }
1783
1784 static inline void
1785 gen_intermediate_code_internal(CPUState * env, TranslationBlock * tb,
1786                                int search_pc)
1787 {
1788     DisasContext ctx;
1789     target_ulong pc_start;
1790     static uint16_t *gen_opc_end;
1791     int i, ii;
1792     int num_insns;
1793     int max_insns;
1794
1795     pc_start = tb->pc;
1796     gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
1797     ctx.pc = pc_start;
1798     ctx.flags = (uint32_t)tb->flags;
1799     ctx.bstate = BS_NONE;
1800     ctx.sr = env->sr;
1801     ctx.fpscr = env->fpscr;
1802     ctx.memidx = (env->sr & SR_MD) ? 1 : 0;
1803     /* We don't know if the delayed pc came from a dynamic or static branch,
1804        so assume it is a dynamic branch.  */
1805     ctx.delayed_pc = -1; /* use delayed pc from env pointer */
1806     ctx.tb = tb;
1807     ctx.singlestep_enabled = env->singlestep_enabled;
1808
1809 #ifdef DEBUG_DISAS
1810     if (loglevel & CPU_LOG_TB_CPU) {
1811         fprintf(logfile,
1812                 "------------------------------------------------\n");
1813         cpu_dump_state(env, logfile, fprintf, 0);
1814     }
1815 #endif
1816
1817     ii = -1;
1818     num_insns = 0;
1819     max_insns = tb->cflags & CF_COUNT_MASK;
1820     if (max_insns == 0)
1821         max_insns = CF_COUNT_MASK;
1822     gen_icount_start();
1823     while (ctx.bstate == BS_NONE && gen_opc_ptr < gen_opc_end) {
1824         if (env->nb_breakpoints > 0) {
1825             for (i = 0; i < env->nb_breakpoints; i++) {
1826                 if (ctx.pc == env->breakpoints[i]) {
1827                     /* We have hit a breakpoint - make sure PC is up-to-date */
1828                     tcg_gen_movi_i32(cpu_pc, ctx.pc);
1829                     tcg_gen_helper_0_0(helper_debug);
1830                     ctx.bstate = BS_EXCP;
1831                     break;
1832                 }
1833             }
1834         }
1835         if (search_pc) {
1836             i = gen_opc_ptr - gen_opc_buf;
1837             if (ii < i) {
1838                 ii++;
1839                 while (ii < i)
1840                     gen_opc_instr_start[ii++] = 0;
1841             }
1842             gen_opc_pc[ii] = ctx.pc;
1843             gen_opc_hflags[ii] = ctx.flags;
1844             gen_opc_instr_start[ii] = 1;
1845             gen_opc_icount[ii] = num_insns;
1846         }
1847         if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
1848             gen_io_start();
1849 #if 0
1850         fprintf(stderr, "Loading opcode at address 0x%08x\n", ctx.pc);
1851         fflush(stderr);
1852 #endif
1853         ctx.opcode = lduw_code(ctx.pc);
1854         decode_opc(&ctx);
1855         num_insns++;
1856         ctx.pc += 2;
1857         if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0)
1858             break;
1859         if (env->singlestep_enabled)
1860             break;
1861         if (num_insns >= max_insns)
1862             break;
1863 #ifdef SH4_SINGLE_STEP
1864         break;
1865 #endif
1866     }
1867     if (tb->cflags & CF_LAST_IO)
1868         gen_io_end();
1869     if (env->singlestep_enabled) {
1870         tcg_gen_movi_i32(cpu_pc, ctx.pc);
1871         tcg_gen_helper_0_0(helper_debug);
1872     } else {
1873         switch (ctx.bstate) {
1874         case BS_STOP:
1875             /* gen_op_interrupt_restart(); */
1876             /* fall through */
1877         case BS_NONE:
1878             if (ctx.flags) {
1879                 gen_store_flags(ctx.flags | DELAY_SLOT_CLEARME);
1880             }
1881             gen_goto_tb(&ctx, 0, ctx.pc);
1882             break;
1883         case BS_EXCP:
1884             /* gen_op_interrupt_restart(); */
1885             tcg_gen_exit_tb(0);
1886             break;
1887         case BS_BRANCH:
1888         default:
1889             break;
1890         }
1891     }
1892
1893     gen_icount_end(tb, num_insns);
1894     *gen_opc_ptr = INDEX_op_end;
1895     if (search_pc) {
1896         i = gen_opc_ptr - gen_opc_buf;
1897         ii++;
1898         while (ii <= i)
1899             gen_opc_instr_start[ii++] = 0;
1900     } else {
1901         tb->size = ctx.pc - pc_start;
1902         tb->icount = num_insns;
1903     }
1904
1905 #ifdef DEBUG_DISAS
1906 #ifdef SH4_DEBUG_DISAS
1907     if (loglevel & CPU_LOG_TB_IN_ASM)
1908         fprintf(logfile, "\n");
1909 #endif
1910     if (loglevel & CPU_LOG_TB_IN_ASM) {
1911         fprintf(logfile, "IN:\n");      /* , lookup_symbol(pc_start)); */
1912         target_disas(logfile, pc_start, ctx.pc - pc_start, 0);
1913         fprintf(logfile, "\n");
1914     }
1915 #endif
1916 }
1917
1918 void gen_intermediate_code(CPUState * env, struct TranslationBlock *tb)
1919 {
1920     gen_intermediate_code_internal(env, tb, 0);
1921 }
1922
1923 void gen_intermediate_code_pc(CPUState * env, struct TranslationBlock *tb)
1924 {
1925     gen_intermediate_code_internal(env, tb, 1);
1926 }
1927
1928 void gen_pc_load(CPUState *env, TranslationBlock *tb,
1929                 unsigned long searched_pc, int pc_pos, void *puc)
1930 {
1931     env->pc = gen_opc_pc[pc_pos];
1932     env->flags = gen_opc_hflags[pc_pos];
1933 }