git.maemo.org Git - qemu/blob - target-sh4/translate.c

   1 /*
   2  *  SH4 translation
   3  *
   4  *  Copyright (c) 2005 Samuel Tardieu
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
  19  */
  20 #include <stdarg.h>
  21 #include <stdlib.h>
  22 #include <stdio.h>
  23 #include <string.h>
  24 #include <inttypes.h>
  25 #include <assert.h>
  26
  27 #define DEBUG_DISAS
  28 #define SH4_DEBUG_DISAS
  29 //#define SH4_SINGLE_STEP
  30
  31 #include "cpu.h"
  32 #include "exec-all.h"
  33 #include "disas.h"
  34 #include "tcg-op.h"
  35 #include "qemu-common.h"
  36
  37 #include "helper.h"
  38 #define GEN_HELPER 1
  39 #include "helper.h"
  40
  41 typedef struct DisasContext {
  42     struct TranslationBlock *tb;
  43     target_ulong pc;
  44     uint32_t sr;
  45     uint32_t fpscr;
  46     uint16_t opcode;
  47     uint32_t flags;
  48     int bstate;
  49     int memidx;
  50     uint32_t delayed_pc;
  51     int singlestep_enabled;
  52     uint32_t features;
  53 } DisasContext;
  54
  55 #if defined(CONFIG_USER_ONLY)
  56 #define IS_USER(ctx) 1
  57 #else
  58 #define IS_USER(ctx) (!(ctx->sr & SR_MD))
  59 #endif
  60
  61 enum {
  62     BS_NONE     = 0, /* We go out of the TB without reaching a branch or an
  63                       * exception condition
  64                       */
  65     BS_STOP     = 1, /* We want to stop translation for any reason */
  66     BS_BRANCH   = 2, /* We reached a branch condition     */
  67     BS_EXCP     = 3, /* We reached an exception condition */
  68 };
  69
  70 /* global register indexes */
  71 static TCGv_ptr cpu_env;
  72 static TCGv cpu_gregs[24];
  73 static TCGv cpu_pc, cpu_sr, cpu_ssr, cpu_spc, cpu_gbr;
  74 static TCGv cpu_vbr, cpu_sgr, cpu_dbr, cpu_mach, cpu_macl;
  75 static TCGv cpu_pr, cpu_fpscr, cpu_fpul;
  76 static TCGv cpu_fregs[32];
  77
  78 /* internal register indexes */
  79 static TCGv cpu_flags, cpu_delayed_pc;
  80
  81 #include "gen-icount.h"
  82
  83 static void sh4_translate_init(void)
  84 {
  85     int i;
  86     static int done_init = 0;
  87     static const char * const gregnames[24] = {
  88         "R0_BANK0", "R1_BANK0", "R2_BANK0", "R3_BANK0",
  89         "R4_BANK0", "R5_BANK0", "R6_BANK0", "R7_BANK0",
  90         "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15",
  91         "R0_BANK1", "R1_BANK1", "R2_BANK1", "R3_BANK1",
  92         "R4_BANK1", "R5_BANK1", "R6_BANK1", "R7_BANK1"
  93     };
  94     static const char * const fregnames[32] = {
  95          "FPR0_BANK0",  "FPR1_BANK0",  "FPR2_BANK0",  "FPR3_BANK0",
  96          "FPR4_BANK0",  "FPR5_BANK0",  "FPR6_BANK0",  "FPR7_BANK0",
  97          "FPR8_BANK0",  "FPR9_BANK0", "FPR10_BANK0", "FPR11_BANK0",
  98         "FPR12_BANK0", "FPR13_BANK0", "FPR14_BANK0", "FPR15_BANK0",
  99          "FPR0_BANK1",  "FPR1_BANK1",  "FPR2_BANK1",  "FPR3_BANK1",
 100          "FPR4_BANK1",  "FPR5_BANK1",  "FPR6_BANK1",  "FPR7_BANK1",
 101          "FPR8_BANK1",  "FPR9_BANK1", "FPR10_BANK1", "FPR11_BANK1",
 102         "FPR12_BANK1", "FPR13_BANK1", "FPR14_BANK1", "FPR15_BANK1",
 103     };
 104
 105     if (done_init)
 106         return;
 107
 108     cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
 109
 110     for (i = 0; i < 24; i++)
 111         cpu_gregs[i] = tcg_global_mem_new_i32(TCG_AREG0,
 112                                               offsetof(CPUState, gregs[i]),
 113                                               gregnames[i]);
 114
 115     cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
 116                                     offsetof(CPUState, pc), "PC");
 117     cpu_sr = tcg_global_mem_new_i32(TCG_AREG0,
 118                                     offsetof(CPUState, sr), "SR");
 119     cpu_ssr = tcg_global_mem_new_i32(TCG_AREG0,
 120                                      offsetof(CPUState, ssr), "SSR");
 121     cpu_spc = tcg_global_mem_new_i32(TCG_AREG0,
 122                                      offsetof(CPUState, spc), "SPC");
 123     cpu_gbr = tcg_global_mem_new_i32(TCG_AREG0,
 124                                      offsetof(CPUState, gbr), "GBR");
 125     cpu_vbr = tcg_global_mem_new_i32(TCG_AREG0,
 126                                      offsetof(CPUState, vbr), "VBR");
 127     cpu_sgr = tcg_global_mem_new_i32(TCG_AREG0,
 128                                      offsetof(CPUState, sgr), "SGR");
 129     cpu_dbr = tcg_global_mem_new_i32(TCG_AREG0,
 130                                      offsetof(CPUState, dbr), "DBR");
 131     cpu_mach = tcg_global_mem_new_i32(TCG_AREG0,
 132                                       offsetof(CPUState, mach), "MACH");
 133     cpu_macl = tcg_global_mem_new_i32(TCG_AREG0,
 134                                       offsetof(CPUState, macl), "MACL");
 135     cpu_pr = tcg_global_mem_new_i32(TCG_AREG0,
 136                                     offsetof(CPUState, pr), "PR");
 137     cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
 138                                        offsetof(CPUState, fpscr), "FPSCR");
 139     cpu_fpul = tcg_global_mem_new_i32(TCG_AREG0,
 140                                       offsetof(CPUState, fpul), "FPUL");
 141
 142     cpu_flags = tcg_global_mem_new_i32(TCG_AREG0,
 143                                        offsetof(CPUState, flags), "_flags_");
 144     cpu_delayed_pc = tcg_global_mem_new_i32(TCG_AREG0,
 145                                             offsetof(CPUState, delayed_pc),
 146                                             "_delayed_pc_");
 147
 148     for (i = 0; i < 32; i++)
 149         cpu_fregs[i] = tcg_global_mem_new_i32(TCG_AREG0,
 150                                               offsetof(CPUState, fregs[i]),
 151                                               fregnames[i]);
 152
 153     /* register helpers */
 154 #define GEN_HELPER 2
 155 #include "helper.h"
 156
 157     done_init = 1;
 158 }
 159
 160 void cpu_dump_state(CPUState * env, FILE * f,
 161                     int (*cpu_fprintf) (FILE * f, const char *fmt, ...),
 162                     int flags)
 163 {
 164     int i;
 165     cpu_fprintf(f, "pc=0x%08x sr=0x%08x pr=0x%08x fpscr=0x%08x\n",
 166                 env->pc, env->sr, env->pr, env->fpscr);
 167     cpu_fprintf(f, "spc=0x%08x ssr=0x%08x gbr=0x%08x vbr=0x%08x\n",
 168                 env->spc, env->ssr, env->gbr, env->vbr);
 169     cpu_fprintf(f, "sgr=0x%08x dbr=0x%08x delayed_pc=0x%08x fpul=0x%08x\n",
 170                 env->sgr, env->dbr, env->delayed_pc, env->fpul);
 171     for (i = 0; i < 24; i += 4) {
 172         cpu_fprintf(f, "r%d=0x%08x r%d=0x%08x r%d=0x%08x r%d=0x%08x\n",
 173                     i, env->gregs[i], i + 1, env->gregs[i + 1],
 174                     i + 2, env->gregs[i + 2], i + 3, env->gregs[i + 3]);
 175     }
 176     if (env->flags & DELAY_SLOT) {
 177         cpu_fprintf(f, "in delay slot (delayed_pc=0x%08x)\n",
 178                     env->delayed_pc);
 179     } else if (env->flags & DELAY_SLOT_CONDITIONAL) {
 180         cpu_fprintf(f, "in conditional delay slot (delayed_pc=0x%08x)\n",
 181                     env->delayed_pc);
 182     }
 183 }
 184
 185 static void cpu_sh4_reset(CPUSH4State * env)
 186 {
 187     if (qemu_loglevel_mask(CPU_LOG_RESET)) {
 188         qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
 189         log_cpu_state(env, 0);
 190     }
 191
 192 #if defined(CONFIG_USER_ONLY)
 193     env->sr = 0;
 194 #else
 195     env->sr = SR_MD | SR_RB | SR_BL | SR_I3 | SR_I2 | SR_I1 | SR_I0;
 196 #endif
 197     env->vbr = 0;
 198     env->pc = 0xA0000000;
 199 #if defined(CONFIG_USER_ONLY)
 200     env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */
 201     set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */
 202 #else
 203     env->fpscr = 0x00040001; /* CPU reset value according to SH4 manual */
 204     set_float_rounding_mode(float_round_to_zero, &env->fp_status);
 205 #endif
 206     env->mmucr = 0;
 207 }
 208
 209 typedef struct {
 210     const char *name;
 211     int id;
 212     uint32_t pvr;
 213     uint32_t prr;
 214     uint32_t cvr;
 215     uint32_t features;
 216 } sh4_def_t;
 217
 218 static sh4_def_t sh4_defs[] = {
 219     {
 220         .name = "SH7750R",
 221         .id = SH_CPU_SH7750R,
 222         .pvr = 0x00050000,
 223         .prr = 0x00000100,
 224         .cvr = 0x00110000,
 225     }, {
 226         .name = "SH7751R",
 227         .id = SH_CPU_SH7751R,
 228         .pvr = 0x04050005,
 229         .prr = 0x00000113,
 230         .cvr = 0x00110000,      /* Neutered caches, should be 0x20480000 */
 231     }, {
 232         .name = "SH7785",
 233         .id = SH_CPU_SH7785,
 234         .pvr = 0x10300700,
 235         .prr = 0x00000200,
 236         .cvr = 0x71440211,
 237         .features = SH_FEATURE_SH4A,
 238      },
 239 };
 240
 241 static const sh4_def_t *cpu_sh4_find_by_name(const char *name)
 242 {
 243     int i;
 244
 245     if (strcasecmp(name, "any") == 0)
 246         return &sh4_defs[0];
 247
 248     for (i = 0; i < ARRAY_SIZE(sh4_defs); i++)
 249         if (strcasecmp(name, sh4_defs[i].name) == 0)
 250             return &sh4_defs[i];
 251
 252     return NULL;
 253 }
 254
 255 void sh4_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
 256 {
 257     int i;
 258
 259     for (i = 0; i < ARRAY_SIZE(sh4_defs); i++)
 260         (*cpu_fprintf)(f, "%s\n", sh4_defs[i].name);
 261 }
 262
 263 static void cpu_sh4_register(CPUSH4State *env, const sh4_def_t *def)
 264 {
 265     env->pvr = def->pvr;
 266     env->prr = def->prr;
 267     env->cvr = def->cvr;
 268     env->id = def->id;
 269 }
 270
 271 CPUSH4State *cpu_sh4_init(const char *cpu_model)
 272 {
 273     CPUSH4State *env;
 274     const sh4_def_t *def;
 275
 276     def = cpu_sh4_find_by_name(cpu_model);
 277     if (!def)
 278         return NULL;
 279     env = qemu_mallocz(sizeof(CPUSH4State));
 280     env->features = def->features;
 281     cpu_exec_init(env);
 282     sh4_translate_init();
 283     env->cpu_model_str = cpu_model;
 284     cpu_sh4_reset(env);
 285     cpu_sh4_register(env, def);
 286     tlb_flush(env, 1);
 287     return env;
 288 }
 289
 290 static void gen_goto_tb(DisasContext * ctx, int n, target_ulong dest)
 291 {
 292     TranslationBlock *tb;
 293     tb = ctx->tb;
 294
 295     if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
 296         !ctx->singlestep_enabled) {
 297         /* Use a direct jump if in same page and singlestep not enabled */
 298         tcg_gen_goto_tb(n);
 299         tcg_gen_movi_i32(cpu_pc, dest);
 300         tcg_gen_exit_tb((long) tb + n);
 301     } else {
 302         tcg_gen_movi_i32(cpu_pc, dest);
 303         if (ctx->singlestep_enabled)
 304             gen_helper_debug();
 305         tcg_gen_exit_tb(0);
 306     }
 307 }
 308
 309 static void gen_jump(DisasContext * ctx)
 310 {
 311     if (ctx->delayed_pc == (uint32_t) - 1) {
 312         /* Target is not statically known, it comes necessarily from a
 313            delayed jump as immediate jump are conditinal jumps */
 314         tcg_gen_mov_i32(cpu_pc, cpu_delayed_pc);
 315         if (ctx->singlestep_enabled)
 316             gen_helper_debug();
 317         tcg_gen_exit_tb(0);
 318     } else {
 319         gen_goto_tb(ctx, 0, ctx->delayed_pc);
 320     }
 321 }
 322
 323 static inline void gen_branch_slot(uint32_t delayed_pc, int t)
 324 {
 325     TCGv sr;
 326     int label = gen_new_label();
 327     tcg_gen_movi_i32(cpu_delayed_pc, delayed_pc);
 328     sr = tcg_temp_new();
 329     tcg_gen_andi_i32(sr, cpu_sr, SR_T);
 330     tcg_gen_brcondi_i32(TCG_COND_NE, sr, t ? SR_T : 0, label);
 331     tcg_gen_ori_i32(cpu_flags, cpu_flags, DELAY_SLOT_TRUE);
 332     gen_set_label(label);
 333 }
 334
 335 /* Immediate conditional jump (bt or bf) */
 336 static void gen_conditional_jump(DisasContext * ctx,
 337                                  target_ulong ift, target_ulong ifnott)
 338 {
 339     int l1;
 340     TCGv sr;
 341
 342     l1 = gen_new_label();
 343     sr = tcg_temp_new();
 344     tcg_gen_andi_i32(sr, cpu_sr, SR_T);
 345     tcg_gen_brcondi_i32(TCG_COND_EQ, sr, SR_T, l1);
 346     gen_goto_tb(ctx, 0, ifnott);
 347     gen_set_label(l1);
 348     gen_goto_tb(ctx, 1, ift);
 349 }
 350
 351 /* Delayed conditional jump (bt or bf) */
 352 static void gen_delayed_conditional_jump(DisasContext * ctx)
 353 {
 354     int l1;
 355     TCGv ds;
 356
 357     l1 = gen_new_label();
 358     ds = tcg_temp_new();
 359     tcg_gen_andi_i32(ds, cpu_flags, DELAY_SLOT_TRUE);
 360     tcg_gen_brcondi_i32(TCG_COND_EQ, ds, DELAY_SLOT_TRUE, l1);
 361     gen_goto_tb(ctx, 1, ctx->pc + 2);
 362     gen_set_label(l1);
 363     tcg_gen_andi_i32(cpu_flags, cpu_flags, ~DELAY_SLOT_TRUE);
 364     gen_jump(ctx);
 365 }
 366
 367 static inline void gen_set_t(void)
 368 {
 369     tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_T);
 370 }
 371
 372 static inline void gen_clr_t(void)
 373 {
 374     tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
 375 }
 376
 377 static inline void gen_cmp(int cond, TCGv t0, TCGv t1)
 378 {
 379     int label1 = gen_new_label();
 380     int label2 = gen_new_label();
 381     tcg_gen_brcond_i32(cond, t1, t0, label1);
 382     gen_clr_t();
 383     tcg_gen_br(label2);
 384     gen_set_label(label1);
 385     gen_set_t();
 386     gen_set_label(label2);
 387 }
 388
 389 static inline void gen_cmp_imm(int cond, TCGv t0, int32_t imm)
 390 {
 391     int label1 = gen_new_label();
 392     int label2 = gen_new_label();
 393     tcg_gen_brcondi_i32(cond, t0, imm, label1);
 394     gen_clr_t();
 395     tcg_gen_br(label2);
 396     gen_set_label(label1);
 397     gen_set_t();
 398     gen_set_label(label2);
 399 }
 400
 401 static inline void gen_store_flags(uint32_t flags)
 402 {
 403     tcg_gen_andi_i32(cpu_flags, cpu_flags, DELAY_SLOT_TRUE);
 404     tcg_gen_ori_i32(cpu_flags, cpu_flags, flags);
 405 }
 406
 407 static inline void gen_copy_bit_i32(TCGv t0, int p0, TCGv t1, int p1)
 408 {
 409     TCGv tmp = tcg_temp_new();
 410
 411     p0 &= 0x1f;
 412     p1 &= 0x1f;
 413
 414     tcg_gen_andi_i32(tmp, t1, (1 << p1));
 415     tcg_gen_andi_i32(t0, t0, ~(1 << p0));
 416     if (p0 < p1)
 417         tcg_gen_shri_i32(tmp, tmp, p1 - p0);
 418     else if (p0 > p1)
 419         tcg_gen_shli_i32(tmp, tmp, p0 - p1);
 420     tcg_gen_or_i32(t0, t0, tmp);
 421
 422     tcg_temp_free(tmp);
 423 }
 424
 425 static inline void gen_load_fpr64(TCGv_i64 t, int reg)
 426 {
 427     tcg_gen_concat_i32_i64(t, cpu_fregs[reg + 1], cpu_fregs[reg]);
 428 }
 429
 430 static inline void gen_store_fpr64 (TCGv_i64 t, int reg)
 431 {
 432     TCGv_i32 tmp = tcg_temp_new_i32();
 433     tcg_gen_trunc_i64_i32(tmp, t);
 434     tcg_gen_mov_i32(cpu_fregs[reg + 1], tmp);
 435     tcg_gen_shri_i64(t, t, 32);
 436     tcg_gen_trunc_i64_i32(tmp, t);
 437     tcg_gen_mov_i32(cpu_fregs[reg], tmp);
 438     tcg_temp_free_i32(tmp);
 439 }
 440
 441 #define B3_0 (ctx->opcode & 0xf)
 442 #define B6_4 ((ctx->opcode >> 4) & 0x7)
 443 #define B7_4 ((ctx->opcode >> 4) & 0xf)
 444 #define B7_0 (ctx->opcode & 0xff)
 445 #define B7_0s ((int32_t) (int8_t) (ctx->opcode & 0xff))
 446 #define B11_0s (ctx->opcode & 0x800 ? 0xfffff000 | (ctx->opcode & 0xfff) : \
 447   (ctx->opcode & 0xfff))
 448 #define B11_8 ((ctx->opcode >> 8) & 0xf)
 449 #define B15_12 ((ctx->opcode >> 12) & 0xf)
 450
 451 #define REG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB) ? \
 452                 (cpu_gregs[x + 16]) : (cpu_gregs[x]))
 453
 454 #define ALTREG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) != (SR_MD | SR_RB) \
 455                 ? (cpu_gregs[x + 16]) : (cpu_gregs[x]))
 456
 457 #define FREG(x) (ctx->fpscr & FPSCR_FR ? (x) ^ 0x10 : (x))
 458 #define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe))
 459 #define XREG(x) (ctx->fpscr & FPSCR_FR ? XHACK(x) ^ 0x10 : XHACK(x))
 460 #define DREG(x) FREG(x) /* Assumes lsb of (x) is always 0 */
 461
 462 #define CHECK_NOT_DELAY_SLOT \
 463   if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL))     \
 464   {                                                           \
 465       tcg_gen_movi_i32(cpu_pc, ctx->pc-2);                    \
 466       gen_helper_raise_slot_illegal_instruction();            \
 467       ctx->bstate = BS_EXCP;                                  \
 468       return;                                                 \
 469   }
 470
 471 #define CHECK_PRIVILEGED                                      \
 472   if (IS_USER(ctx)) {                                         \
 473       tcg_gen_movi_i32(cpu_pc, ctx->pc);                      \
 474       gen_helper_raise_illegal_instruction();                 \
 475       ctx->bstate = BS_EXCP;                                  \
 476       return;                                                 \
 477   }
 478
 479 #define CHECK_FPU_ENABLED                                       \
 480   if (ctx->flags & SR_FD) {                                     \
 481       if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) { \
 482           tcg_gen_movi_i32(cpu_pc, ctx->pc-2);                  \
 483           gen_helper_raise_slot_fpu_disable();                  \
 484       } else {                                                  \
 485           tcg_gen_movi_i32(cpu_pc, ctx->pc);                    \
 486           gen_helper_raise_fpu_disable();                       \
 487       }                                                         \
 488       ctx->bstate = BS_EXCP;                                    \
 489       return;                                                   \
 490   }
 491
 492 static void _decode_opc(DisasContext * ctx)
 493 {
 494 #if 0
 495     fprintf(stderr, "Translating opcode 0x%04x\n", ctx->opcode);
 496 #endif
 497
 498     switch (ctx->opcode) {
 499     case 0x0019:                /* div0u */
 500         tcg_gen_andi_i32(cpu_sr, cpu_sr, ~(SR_M | SR_Q | SR_T));
 501         return;
 502     case 0x000b:                /* rts */
 503         CHECK_NOT_DELAY_SLOT
 504         tcg_gen_mov_i32(cpu_delayed_pc, cpu_pr);
 505         ctx->flags |= DELAY_SLOT;
 506         ctx->delayed_pc = (uint32_t) - 1;
 507         return;
 508     case 0x0028:                /* clrmac */
 509         tcg_gen_movi_i32(cpu_mach, 0);
 510         tcg_gen_movi_i32(cpu_macl, 0);
 511         return;
 512     case 0x0048:                /* clrs */
 513         tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_S);
 514         return;
 515     case 0x0008:                /* clrt */
 516         gen_clr_t();
 517         return;
 518     case 0x0038:                /* ldtlb */
 519         CHECK_PRIVILEGED
 520         gen_helper_ldtlb();
 521         return;
 522     case 0x002b:                /* rte */
 523         CHECK_PRIVILEGED
 524         CHECK_NOT_DELAY_SLOT
 525         tcg_gen_mov_i32(cpu_sr, cpu_ssr);
 526         tcg_gen_mov_i32(cpu_delayed_pc, cpu_spc);
 527         ctx->flags |= DELAY_SLOT;
 528         ctx->delayed_pc = (uint32_t) - 1;
 529         return;
 530     case 0x0058:                /* sets */
 531         tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_S);
 532         return;
 533     case 0x0018:                /* sett */
 534         gen_set_t();
 535         return;
 536     case 0xfbfd:                /* frchg */
 537         tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_FR);
 538         ctx->bstate = BS_STOP;
 539         return;
 540     case 0xf3fd:                /* fschg */
 541         tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_SZ);
 542         ctx->bstate = BS_STOP;
 543         return;
 544     case 0x0009:                /* nop */
 545         return;
 546     case 0x001b:                /* sleep */
 547         CHECK_PRIVILEGED
 548         gen_helper_sleep(tcg_const_i32(ctx->pc + 2));
 549         return;
 550     }
 551
 552     switch (ctx->opcode & 0xf000) {
 553     case 0x1000:                /* mov.l Rm,@(disp,Rn) */
 554         {
 555             TCGv addr = tcg_temp_new();
 556             tcg_gen_addi_i32(addr, REG(B11_8), B3_0 * 4);
 557             tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx);
 558             tcg_temp_free(addr);
 559         }
 560         return;
 561     case 0x5000:                /* mov.l @(disp,Rm),Rn */
 562         {
 563             TCGv addr = tcg_temp_new();
 564             tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 4);
 565             tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx);
 566             tcg_temp_free(addr);
 567         }
 568         return;
 569     case 0xe000:                /* mov #imm,Rn */
 570         tcg_gen_movi_i32(REG(B11_8), B7_0s);
 571         return;
 572     case 0x9000:                /* mov.w @(disp,PC),Rn */
 573         {
 574             TCGv addr = tcg_const_i32(ctx->pc + 4 + B7_0 * 2);
 575             tcg_gen_qemu_ld16s(REG(B11_8), addr, ctx->memidx);
 576             tcg_temp_free(addr);
 577         }
 578         return;
 579     case 0xd000:                /* mov.l @(disp,PC),Rn */
 580         {
 581             TCGv addr = tcg_const_i32((ctx->pc + 4 + B7_0 * 4) & ~3);
 582             tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx);
 583             tcg_temp_free(addr);
 584         }
 585         return;
 586     case 0x7000:                /* add #imm,Rn */
 587         tcg_gen_addi_i32(REG(B11_8), REG(B11_8), B7_0s);
 588         return;
 589     case 0xa000:                /* bra disp */
 590         CHECK_NOT_DELAY_SLOT
 591         ctx->delayed_pc = ctx->pc + 4 + B11_0s * 2;
 592         tcg_gen_movi_i32(cpu_delayed_pc, ctx->delayed_pc);
 593         ctx->flags |= DELAY_SLOT;
 594         return;
 595     case 0xb000:                /* bsr disp */
 596         CHECK_NOT_DELAY_SLOT
 597         tcg_gen_movi_i32(cpu_pr, ctx->pc + 4);
 598         ctx->delayed_pc = ctx->pc + 4 + B11_0s * 2;
 599         tcg_gen_movi_i32(cpu_delayed_pc, ctx->delayed_pc);
 600         ctx->flags |= DELAY_SLOT;
 601         return;
 602     }
 603
 604     switch (ctx->opcode & 0xf00f) {
 605     case 0x6003:                /* mov Rm,Rn */
 606         tcg_gen_mov_i32(REG(B11_8), REG(B7_4));
 607         return;
 608     case 0x2000:                /* mov.b Rm,@Rn */
 609         tcg_gen_qemu_st8(REG(B7_4), REG(B11_8), ctx->memidx);
 610         return;
 611     case 0x2001:                /* mov.w Rm,@Rn */
 612         tcg_gen_qemu_st16(REG(B7_4), REG(B11_8), ctx->memidx);
 613         return;
 614     case 0x2002:                /* mov.l Rm,@Rn */
 615         tcg_gen_qemu_st32(REG(B7_4), REG(B11_8), ctx->memidx);
 616         return;
 617     case 0x6000:                /* mov.b @Rm,Rn */
 618         tcg_gen_qemu_ld8s(REG(B11_8), REG(B7_4), ctx->memidx);
 619         return;
 620     case 0x6001:                /* mov.w @Rm,Rn */
 621         tcg_gen_qemu_ld16s(REG(B11_8), REG(B7_4), ctx->memidx);
 622         return;
 623     case 0x6002:                /* mov.l @Rm,Rn */
 624         tcg_gen_qemu_ld32s(REG(B11_8), REG(B7_4), ctx->memidx);
 625         return;
 626     case 0x2004:                /* mov.b Rm,@-Rn */
 627         {
 628             TCGv addr = tcg_temp_new();
 629             tcg_gen_subi_i32(addr, REG(B11_8), 1);
 630             tcg_gen_qemu_st8(REG(B7_4), addr, ctx->memidx);     /* might cause re-execution */
 631             tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 1);        /* modify register status */
 632             tcg_temp_free(addr);
 633         }
 634         return;
 635     case 0x2005:                /* mov.w Rm,@-Rn */
 636         {
 637             TCGv addr = tcg_temp_new();
 638             tcg_gen_subi_i32(addr, REG(B11_8), 2);
 639             tcg_gen_qemu_st16(REG(B7_4), addr, ctx->memidx);
 640             tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 2);
 641             tcg_temp_free(addr);
 642         }
 643         return;
 644     case 0x2006:                /* mov.l Rm,@-Rn */
 645         {
 646             TCGv addr = tcg_temp_new();
 647             tcg_gen_subi_i32(addr, REG(B11_8), 4);
 648             tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx);
 649             tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
 650         }
 651         return;
 652     case 0x6004:                /* mov.b @Rm+,Rn */
 653         tcg_gen_qemu_ld8s(REG(B11_8), REG(B7_4), ctx->memidx);
 654         if ( B11_8 != B7_4 )
 655                 tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 1);
 656         return;
 657     case 0x6005:                /* mov.w @Rm+,Rn */
 658         tcg_gen_qemu_ld16s(REG(B11_8), REG(B7_4), ctx->memidx);
 659         if ( B11_8 != B7_4 )
 660                 tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2);
 661         return;
 662     case 0x6006:                /* mov.l @Rm+,Rn */
 663         tcg_gen_qemu_ld32s(REG(B11_8), REG(B7_4), ctx->memidx);
 664         if ( B11_8 != B7_4 )
 665                 tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
 666         return;
 667     case 0x0004:                /* mov.b Rm,@(R0,Rn) */
 668         {
 669             TCGv addr = tcg_temp_new();
 670             tcg_gen_add_i32(addr, REG(B11_8), REG(0));
 671             tcg_gen_qemu_st8(REG(B7_4), addr, ctx->memidx);
 672             tcg_temp_free(addr);
 673         }
 674         return;
 675     case 0x0005:                /* mov.w Rm,@(R0,Rn) */
 676         {
 677             TCGv addr = tcg_temp_new();
 678             tcg_gen_add_i32(addr, REG(B11_8), REG(0));
 679             tcg_gen_qemu_st16(REG(B7_4), addr, ctx->memidx);
 680             tcg_temp_free(addr);
 681         }
 682         return;
 683     case 0x0006:                /* mov.l Rm,@(R0,Rn) */
 684         {
 685             TCGv addr = tcg_temp_new();
 686             tcg_gen_add_i32(addr, REG(B11_8), REG(0));
 687             tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx);
 688             tcg_temp_free(addr);
 689         }
 690         return;
 691     case 0x000c:                /* mov.b @(R0,Rm),Rn */
 692         {
 693             TCGv addr = tcg_temp_new();
 694             tcg_gen_add_i32(addr, REG(B7_4), REG(0));
 695             tcg_gen_qemu_ld8s(REG(B11_8), addr, ctx->memidx);
 696             tcg_temp_free(addr);
 697         }
 698         return;
 699     case 0x000d:                /* mov.w @(R0,Rm),Rn */
 700         {
 701             TCGv addr = tcg_temp_new();
 702             tcg_gen_add_i32(addr, REG(B7_4), REG(0));
 703             tcg_gen_qemu_ld16s(REG(B11_8), addr, ctx->memidx);
 704             tcg_temp_free(addr);
 705         }
 706         return;
 707     case 0x000e:                /* mov.l @(R0,Rm),Rn */
 708         {
 709             TCGv addr = tcg_temp_new();
 710             tcg_gen_add_i32(addr, REG(B7_4), REG(0));
 711             tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx);
 712             tcg_temp_free(addr);
 713         }
 714         return;
 715     case 0x6008:                /* swap.b Rm,Rn */
 716         {
 717             TCGv highw, high, low;
 718             highw = tcg_temp_new();
 719             tcg_gen_andi_i32(highw, REG(B7_4), 0xffff0000);
 720             high = tcg_temp_new();
 721             tcg_gen_ext8u_i32(high, REG(B7_4));
 722             tcg_gen_shli_i32(high, high, 8);
 723             low = tcg_temp_new();
 724             tcg_gen_shri_i32(low, REG(B7_4), 8);
 725             tcg_gen_ext8u_i32(low, low);
 726             tcg_gen_or_i32(REG(B11_8), high, low);
 727             tcg_gen_or_i32(REG(B11_8), REG(B11_8), highw);
 728             tcg_temp_free(low);
 729             tcg_temp_free(high);
 730         }
 731         return;
 732     case 0x6009:                /* swap.w Rm,Rn */
 733         {
 734             TCGv high, low;
 735             high = tcg_temp_new();
 736             tcg_gen_ext16u_i32(high, REG(B7_4));
 737             tcg_gen_shli_i32(high, high, 16);
 738             low = tcg_temp_new();
 739             tcg_gen_shri_i32(low, REG(B7_4), 16);
 740             tcg_gen_ext16u_i32(low, low);
 741             tcg_gen_or_i32(REG(B11_8), high, low);
 742             tcg_temp_free(low);
 743             tcg_temp_free(high);
 744         }
 745         return;
 746     case 0x200d:                /* xtrct Rm,Rn */
 747         {
 748             TCGv high, low;
 749             high = tcg_temp_new();
 750             tcg_gen_ext16u_i32(high, REG(B7_4));
 751             tcg_gen_shli_i32(high, high, 16);
 752             low = tcg_temp_new();
 753             tcg_gen_shri_i32(low, REG(B11_8), 16);
 754             tcg_gen_ext16u_i32(low, low);
 755             tcg_gen_or_i32(REG(B11_8), high, low);
 756             tcg_temp_free(low);
 757             tcg_temp_free(high);
 758         }
 759         return;
 760     case 0x300c:                /* add Rm,Rn */
 761         tcg_gen_add_i32(REG(B11_8), REG(B11_8), REG(B7_4));
 762         return;
 763     case 0x300e:                /* addc Rm,Rn */
 764         gen_helper_addc(REG(B11_8), REG(B7_4), REG(B11_8));
 765         return;
 766     case 0x300f:                /* addv Rm,Rn */
 767         gen_helper_addv(REG(B11_8), REG(B7_4), REG(B11_8));
 768         return;
 769     case 0x2009:                /* and Rm,Rn */
 770         tcg_gen_and_i32(REG(B11_8), REG(B11_8), REG(B7_4));
 771         return;
 772     case 0x3000:                /* cmp/eq Rm,Rn */
 773         gen_cmp(TCG_COND_EQ, REG(B7_4), REG(B11_8));
 774         return;
 775     case 0x3003:                /* cmp/ge Rm,Rn */
 776         gen_cmp(TCG_COND_GE, REG(B7_4), REG(B11_8));
 777         return;
 778     case 0x3007:                /* cmp/gt Rm,Rn */
 779         gen_cmp(TCG_COND_GT, REG(B7_4), REG(B11_8));
 780         return;
 781     case 0x3006:                /* cmp/hi Rm,Rn */
 782         gen_cmp(TCG_COND_GTU, REG(B7_4), REG(B11_8));
 783         return;
 784     case 0x3002:                /* cmp/hs Rm,Rn */
 785         gen_cmp(TCG_COND_GEU, REG(B7_4), REG(B11_8));
 786         return;
 787     case 0x200c:                /* cmp/str Rm,Rn */
 788         {
 789             int label1 = gen_new_label();
 790             int label2 = gen_new_label();
 791             TCGv cmp1 = tcg_temp_local_new();
 792             TCGv cmp2 = tcg_temp_local_new();
 793             tcg_gen_xor_i32(cmp1, REG(B7_4), REG(B11_8));
 794             tcg_gen_andi_i32(cmp2, cmp1, 0xff000000);
 795             tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);
 796             tcg_gen_andi_i32(cmp2, cmp1, 0x00ff0000);
 797             tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);
 798             tcg_gen_andi_i32(cmp2, cmp1, 0x0000ff00);
 799             tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);
 800             tcg_gen_andi_i32(cmp2, cmp1, 0x000000ff);
 801             tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);
 802             tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
 803             tcg_gen_br(label2);
 804             gen_set_label(label1);
 805             tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_T);
 806             gen_set_label(label2);
 807             tcg_temp_free(cmp2);
 808             tcg_temp_free(cmp1);
 809         }
 810         return;
 811     case 0x2007:                /* div0s Rm,Rn */
 812         {
 813             gen_copy_bit_i32(cpu_sr, 8, REG(B11_8), 31);        /* SR_Q */
 814             gen_copy_bit_i32(cpu_sr, 9, REG(B7_4), 31);         /* SR_M */
 815             TCGv val = tcg_temp_new();
 816             tcg_gen_xor_i32(val, REG(B7_4), REG(B11_8));
 817             gen_copy_bit_i32(cpu_sr, 0, val, 31);               /* SR_T */
 818             tcg_temp_free(val);
 819         }
 820         return;
 821     case 0x3004:                /* div1 Rm,Rn */
 822         gen_helper_div1(REG(B11_8), REG(B7_4), REG(B11_8));
 823         return;
 824     case 0x300d:                /* dmuls.l Rm,Rn */
 825         {
 826             TCGv_i64 tmp1 = tcg_temp_new_i64();
 827             TCGv_i64 tmp2 = tcg_temp_new_i64();
 828
 829             tcg_gen_ext_i32_i64(tmp1, REG(B7_4));
 830             tcg_gen_ext_i32_i64(tmp2, REG(B11_8));
 831             tcg_gen_mul_i64(tmp1, tmp1, tmp2);
 832             tcg_gen_trunc_i64_i32(cpu_macl, tmp1);
 833             tcg_gen_shri_i64(tmp1, tmp1, 32);
 834             tcg_gen_trunc_i64_i32(cpu_mach, tmp1);
 835
 836             tcg_temp_free_i64(tmp2);
 837             tcg_temp_free_i64(tmp1);
 838         }
 839         return;
 840     case 0x3005:                /* dmulu.l Rm,Rn */
 841         {
 842             TCGv_i64 tmp1 = tcg_temp_new_i64();
 843             TCGv_i64 tmp2 = tcg_temp_new_i64();
 844
 845             tcg_gen_extu_i32_i64(tmp1, REG(B7_4));
 846             tcg_gen_extu_i32_i64(tmp2, REG(B11_8));
 847             tcg_gen_mul_i64(tmp1, tmp1, tmp2);
 848             tcg_gen_trunc_i64_i32(cpu_macl, tmp1);
 849             tcg_gen_shri_i64(tmp1, tmp1, 32);
 850             tcg_gen_trunc_i64_i32(cpu_mach, tmp1);
 851
 852             tcg_temp_free_i64(tmp2);
 853             tcg_temp_free_i64(tmp1);
 854         }
 855         return;
 856     case 0x600e:                /* exts.b Rm,Rn */
 857         tcg_gen_ext8s_i32(REG(B11_8), REG(B7_4));
 858         return;
 859     case 0x600f:                /* exts.w Rm,Rn */
 860         tcg_gen_ext16s_i32(REG(B11_8), REG(B7_4));
 861         return;
 862     case 0x600c:                /* extu.b Rm,Rn */
 863         tcg_gen_ext8u_i32(REG(B11_8), REG(B7_4));
 864         return;
 865     case 0x600d:                /* extu.w Rm,Rn */
 866         tcg_gen_ext16u_i32(REG(B11_8), REG(B7_4));
 867         return;
 868     case 0x000f:                /* mac.l @Rm+,@Rn+ */
 869         {
 870             TCGv arg0, arg1;
 871             arg0 = tcg_temp_new();
 872             tcg_gen_qemu_ld32s(arg0, REG(B7_4), ctx->memidx);
 873             arg1 = tcg_temp_new();
 874             tcg_gen_qemu_ld32s(arg1, REG(B11_8), ctx->memidx);
 875             gen_helper_macl(arg0, arg1);
 876             tcg_temp_free(arg1);
 877             tcg_temp_free(arg0);
 878             tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
 879             tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
 880         }
 881         return;
 882     case 0x400f:                /* mac.w @Rm+,@Rn+ */
 883         {
 884             TCGv arg0, arg1;
 885             arg0 = tcg_temp_new();
 886             tcg_gen_qemu_ld32s(arg0, REG(B7_4), ctx->memidx);
 887             arg1 = tcg_temp_new();
 888             tcg_gen_qemu_ld32s(arg1, REG(B11_8), ctx->memidx);
 889             gen_helper_macw(arg0, arg1);
 890             tcg_temp_free(arg1);
 891             tcg_temp_free(arg0);
 892             tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 2);
 893             tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2);
 894         }
 895         return;
 896     case 0x0007:                /* mul.l Rm,Rn */
 897         tcg_gen_mul_i32(cpu_macl, REG(B7_4), REG(B11_8));
 898         return;
 899     case 0x200f:                /* muls.w Rm,Rn */
 900         {
 901             TCGv arg0, arg1;
 902             arg0 = tcg_temp_new();
 903             tcg_gen_ext16s_i32(arg0, REG(B7_4));
 904             arg1 = tcg_temp_new();
 905             tcg_gen_ext16s_i32(arg1, REG(B11_8));
 906             tcg_gen_mul_i32(cpu_macl, arg0, arg1);
 907             tcg_temp_free(arg1);
 908             tcg_temp_free(arg0);
 909         }
 910         return;
 911     case 0x200e:                /* mulu.w Rm,Rn */
 912         {
 913             TCGv arg0, arg1;
 914             arg0 = tcg_temp_new();
 915             tcg_gen_ext16u_i32(arg0, REG(B7_4));
 916             arg1 = tcg_temp_new();
 917             tcg_gen_ext16u_i32(arg1, REG(B11_8));
 918             tcg_gen_mul_i32(cpu_macl, arg0, arg1);
 919             tcg_temp_free(arg1);
 920             tcg_temp_free(arg0);
 921         }
 922         return;
 923     case 0x600b:                /* neg Rm,Rn */
 924         tcg_gen_neg_i32(REG(B11_8), REG(B7_4));
 925         return;
 926     case 0x600a:                /* negc Rm,Rn */
 927         gen_helper_negc(REG(B11_8), REG(B7_4));
 928         return;
 929     case 0x6007:                /* not Rm,Rn */
 930         tcg_gen_not_i32(REG(B11_8), REG(B7_4));
 931         return;
 932     case 0x200b:                /* or Rm,Rn */
 933         tcg_gen_or_i32(REG(B11_8), REG(B11_8), REG(B7_4));
 934         return;
 935     case 0x400c:                /* shad Rm,Rn */
 936         {
 937             int label1 = gen_new_label();
 938             int label2 = gen_new_label();
 939             int label3 = gen_new_label();
 940             int label4 = gen_new_label();
 941             TCGv shift = tcg_temp_local_new();
 942             tcg_gen_brcondi_i32(TCG_COND_LT, REG(B7_4), 0, label1);
 943             /* Rm positive, shift to the left */
 944             tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
 945             tcg_gen_shl_i32(REG(B11_8), REG(B11_8), shift);
 946             tcg_gen_br(label4);
 947             /* Rm negative, shift to the right */
 948             gen_set_label(label1);
 949             tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
 950             tcg_gen_brcondi_i32(TCG_COND_EQ, shift, 0, label2);
 951             tcg_gen_not_i32(shift, REG(B7_4));
 952             tcg_gen_andi_i32(shift, shift, 0x1f);
 953             tcg_gen_addi_i32(shift, shift, 1);
 954             tcg_gen_sar_i32(REG(B11_8), REG(B11_8), shift);
 955             tcg_gen_br(label4);
 956             /* Rm = -32 */
 957             gen_set_label(label2);
 958             tcg_gen_brcondi_i32(TCG_COND_LT, REG(B11_8), 0, label3);
 959             tcg_gen_movi_i32(REG(B11_8), 0);
 960             tcg_gen_br(label4);
 961             gen_set_label(label3);
 962             tcg_gen_movi_i32(REG(B11_8), 0xffffffff);
 963             gen_set_label(label4);
 964             tcg_temp_free(shift);
 965         }
 966         return;
 967     case 0x400d:                /* shld Rm,Rn */
 968         {
 969             int label1 = gen_new_label();
 970             int label2 = gen_new_label();
 971             int label3 = gen_new_label();
 972             TCGv shift = tcg_temp_local_new();
 973             tcg_gen_brcondi_i32(TCG_COND_LT, REG(B7_4), 0, label1);
 974             /* Rm positive, shift to the left */
 975             tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
 976             tcg_gen_shl_i32(REG(B11_8), REG(B11_8), shift);
 977             tcg_gen_br(label3);
 978             /* Rm negative, shift to the right */
 979             gen_set_label(label1);
 980             tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
 981             tcg_gen_brcondi_i32(TCG_COND_EQ, shift, 0, label2);
 982             tcg_gen_not_i32(shift, REG(B7_4));
 983             tcg_gen_andi_i32(shift, shift, 0x1f);
 984             tcg_gen_addi_i32(shift, shift, 1);
 985             tcg_gen_shr_i32(REG(B11_8), REG(B11_8), shift);
 986             tcg_gen_br(label3);
 987             /* Rm = -32 */
 988             gen_set_label(label2);
 989             tcg_gen_movi_i32(REG(B11_8), 0);
 990             gen_set_label(label3);
 991             tcg_temp_free(shift);
 992         }
 993         return;
 994     case 0x3008:                /* sub Rm,Rn */
 995         tcg_gen_sub_i32(REG(B11_8), REG(B11_8), REG(B7_4));
 996         return;
 997     case 0x300a:                /* subc Rm,Rn */
 998         gen_helper_subc(REG(B11_8), REG(B7_4), REG(B11_8));
 999         return;
1000     case 0x300b:                /* subv Rm,Rn */
1001         gen_helper_subv(REG(B11_8), REG(B7_4), REG(B11_8));
1002         return;
1003     case 0x2008:                /* tst Rm,Rn */
1004         {
1005             TCGv val = tcg_temp_new();
1006             tcg_gen_and_i32(val, REG(B7_4), REG(B11_8));
1007             gen_cmp_imm(TCG_COND_EQ, val, 0);
1008             tcg_temp_free(val);
1009         }
1010         return;
1011     case 0x200a:                /* xor Rm,Rn */
1012         tcg_gen_xor_i32(REG(B11_8), REG(B11_8), REG(B7_4));
1013         return;
1014     case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */
1015         CHECK_FPU_ENABLED
1016         if (ctx->fpscr & FPSCR_SZ) {
1017             TCGv_i64 fp = tcg_temp_new_i64();
1018             gen_load_fpr64(fp, XREG(B7_4));
1019             gen_store_fpr64(fp, XREG(B11_8));
1020             tcg_temp_free_i64(fp);
1021         } else {
1022             tcg_gen_mov_i32(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
1023         }
1024         return;
1025     case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
1026         CHECK_FPU_ENABLED
1027         if (ctx->fpscr & FPSCR_SZ) {
1028             TCGv addr_hi = tcg_temp_new();
1029             int fr = XREG(B7_4);
1030             tcg_gen_addi_i32(addr_hi, REG(B11_8), 4);
1031             tcg_gen_qemu_st32(cpu_fregs[fr  ], REG(B11_8), ctx->memidx);
1032             tcg_gen_qemu_st32(cpu_fregs[fr+1], addr_hi,    ctx->memidx);
1033             tcg_temp_free(addr_hi);
1034         } else {
1035             tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], REG(B11_8), ctx->memidx);
1036         }
1037         return;
1038     case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
1039         CHECK_FPU_ENABLED
1040         if (ctx->fpscr & FPSCR_SZ) {
1041             TCGv addr_hi = tcg_temp_new();
1042             int fr = XREG(B11_8);
1043             tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
1044             tcg_gen_qemu_ld32u(cpu_fregs[fr  ], REG(B7_4), ctx->memidx);
1045             tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr_hi,   ctx->memidx);
1046             tcg_temp_free(addr_hi);
1047         } else {
1048             tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx);
1049         }
1050         return;
1051     case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
1052         CHECK_FPU_ENABLED
1053         if (ctx->fpscr & FPSCR_SZ) {
1054             TCGv addr_hi = tcg_temp_new();
1055             int fr = XREG(B11_8);
1056             tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
1057             tcg_gen_qemu_ld32u(cpu_fregs[fr  ], REG(B7_4), ctx->memidx);
1058             tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr_hi,   ctx->memidx);
1059             tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 8);
1060             tcg_temp_free(addr_hi);
1061         } else {
1062             tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx);
1063             tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
1064         }
1065         return;
1066     case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */
1067         CHECK_FPU_ENABLED
1068         if (ctx->fpscr & FPSCR_SZ) {
1069             TCGv addr = tcg_temp_new_i32();
1070             int fr = XREG(B7_4);
1071             tcg_gen_subi_i32(addr, REG(B11_8), 4);
1072             tcg_gen_qemu_st32(cpu_fregs[fr+1], addr, ctx->memidx);
1073             tcg_gen_subi_i32(addr, REG(B11_8), 8);
1074             tcg_gen_qemu_st32(cpu_fregs[fr  ], addr, ctx->memidx);
1075             tcg_gen_mov_i32(REG(B11_8), addr);
1076             tcg_temp_free(addr);
1077         } else {
1078             TCGv addr;
1079             addr = tcg_temp_new_i32();
1080             tcg_gen_subi_i32(addr, REG(B11_8), 4);
1081             tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx);
1082             tcg_temp_free(addr);
1083             tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
1084         }
1085         return;
1086     case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */
1087         CHECK_FPU_ENABLED
1088         {
1089             TCGv addr = tcg_temp_new_i32();
1090             tcg_gen_add_i32(addr, REG(B7_4), REG(0));
1091             if (ctx->fpscr & FPSCR_SZ) {
1092                 int fr = XREG(B11_8);
1093                 tcg_gen_qemu_ld32u(cpu_fregs[fr  ], addr, ctx->memidx);
1094                 tcg_gen_addi_i32(addr, addr, 4);
1095                 tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx);
1096             } else {
1097                 tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], addr, ctx->memidx);
1098             }
1099             tcg_temp_free(addr);
1100         }
1101         return;
1102     case 0xf007: /* fmov {F,D,X}Rn,@(R0,Rn) - FPSCR: Nothing */
1103         CHECK_FPU_ENABLED
1104         {
1105             TCGv addr = tcg_temp_new();
1106             tcg_gen_add_i32(addr, REG(B11_8), REG(0));
1107             if (ctx->fpscr & FPSCR_SZ) {
1108                 int fr = XREG(B7_4);
1109                 tcg_gen_qemu_ld32u(cpu_fregs[fr  ], addr, ctx->memidx);
1110                 tcg_gen_addi_i32(addr, addr, 4);
1111                 tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx);
1112             } else {
1113                 tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx);
1114             }
1115             tcg_temp_free(addr);
1116         }
1117         return;
1118     case 0xf000: /* fadd Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
1119     case 0xf001: /* fsub Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
1120     case 0xf002: /* fmul Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
1121     case 0xf003: /* fdiv Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
1122     case 0xf004: /* fcmp/eq Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
1123     case 0xf005: /* fcmp/gt Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
1124         {
1125             CHECK_FPU_ENABLED
1126             if (ctx->fpscr & FPSCR_PR) {
1127                 TCGv_i64 fp0, fp1;
1128
1129                 if (ctx->opcode & 0x0110)
1130                     break; /* illegal instruction */
1131                 fp0 = tcg_temp_new_i64();
1132                 fp1 = tcg_temp_new_i64();
1133                 gen_load_fpr64(fp0, DREG(B11_8));
1134                 gen_load_fpr64(fp1, DREG(B7_4));
1135                 switch (ctx->opcode & 0xf00f) {
1136                 case 0xf000:            /* fadd Rm,Rn */
1137                     gen_helper_fadd_DT(fp0, fp0, fp1);
1138                     break;
1139                 case 0xf001:            /* fsub Rm,Rn */
1140                     gen_helper_fsub_DT(fp0, fp0, fp1);
1141                     break;
1142                 case 0xf002:            /* fmul Rm,Rn */
1143                     gen_helper_fmul_DT(fp0, fp0, fp1);
1144                     break;
1145                 case 0xf003:            /* fdiv Rm,Rn */
1146                     gen_helper_fdiv_DT(fp0, fp0, fp1);
1147                     break;
1148                 case 0xf004:            /* fcmp/eq Rm,Rn */
1149                     gen_helper_fcmp_eq_DT(fp0, fp1);
1150                     return;
1151                 case 0xf005:            /* fcmp/gt Rm,Rn */
1152                     gen_helper_fcmp_gt_DT(fp0, fp1);
1153                     return;
1154                 }
1155                 gen_store_fpr64(fp0, DREG(B11_8));
1156                 tcg_temp_free_i64(fp0);
1157                 tcg_temp_free_i64(fp1);
1158             } else {
1159                 switch (ctx->opcode & 0xf00f) {
1160                 case 0xf000:            /* fadd Rm,Rn */
1161                     gen_helper_fadd_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
1162                     break;
1163                 case 0xf001:            /* fsub Rm,Rn */
1164                     gen_helper_fsub_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
1165                     break;
1166                 case 0xf002:            /* fmul Rm,Rn */
1167                     gen_helper_fmul_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
1168                     break;
1169                 case 0xf003:            /* fdiv Rm,Rn */
1170                     gen_helper_fdiv_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
1171                     break;
1172                 case 0xf004:            /* fcmp/eq Rm,Rn */
1173                     gen_helper_fcmp_eq_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
1174                     return;
1175                 case 0xf005:            /* fcmp/gt Rm,Rn */
1176                     gen_helper_fcmp_gt_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
1177                     return;
1178                 }
1179             }
1180         }
1181         return;
1182     case 0xf00e: /* fmac FR0,RM,Rn */
1183         {
1184             CHECK_FPU_ENABLED
1185             if (ctx->fpscr & FPSCR_PR) {
1186                 break; /* illegal instruction */
1187             } else {
1188                 gen_helper_fmac_FT(cpu_fregs[FREG(B11_8)],
1189                                    cpu_fregs[FREG(0)], cpu_fregs[FREG(B7_4)], cpu_fregs[FREG(B11_8)]);
1190                 return;
1191             }
1192         }
1193     }
1194
1195     switch (ctx->opcode & 0xff00) {
1196     case 0xc900:                /* and #imm,R0 */
1197         tcg_gen_andi_i32(REG(0), REG(0), B7_0);
1198         return;
1199     case 0xcd00:                /* and.b #imm,@(R0,GBR) */
1200         {
1201             TCGv addr, val;
1202             addr = tcg_temp_new();
1203             tcg_gen_add_i32(addr, REG(0), cpu_gbr);
1204             val = tcg_temp_new();
1205             tcg_gen_qemu_ld8u(val, addr, ctx->memidx);
1206             tcg_gen_andi_i32(val, val, B7_0);
1207             tcg_gen_qemu_st8(val, addr, ctx->memidx);
1208             tcg_temp_free(val);
1209             tcg_temp_free(addr);
1210         }
1211         return;
1212     case 0x8b00:                /* bf label */
1213         CHECK_NOT_DELAY_SLOT
1214             gen_conditional_jump(ctx, ctx->pc + 2,
1215                                  ctx->pc + 4 + B7_0s * 2);
1216         ctx->bstate = BS_BRANCH;
1217         return;
1218     case 0x8f00:                /* bf/s label */
1219         CHECK_NOT_DELAY_SLOT
1220         gen_branch_slot(ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2, 0);
1221         ctx->flags |= DELAY_SLOT_CONDITIONAL;
1222         return;
1223     case 0x8900:                /* bt label */
1224         CHECK_NOT_DELAY_SLOT
1225             gen_conditional_jump(ctx, ctx->pc + 4 + B7_0s * 2,
1226                                  ctx->pc + 2);
1227         ctx->bstate = BS_BRANCH;
1228         return;
1229     case 0x8d00:                /* bt/s label */
1230         CHECK_NOT_DELAY_SLOT
1231         gen_branch_slot(ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2, 1);
1232         ctx->flags |= DELAY_SLOT_CONDITIONAL;
1233         return;
1234     case 0x8800:                /* cmp/eq #imm,R0 */
1235         gen_cmp_imm(TCG_COND_EQ, REG(0), B7_0s);
1236         return;
1237     case 0xc400:                /* mov.b @(disp,GBR),R0 */
1238         {
1239             TCGv addr = tcg_temp_new();
1240             tcg_gen_addi_i32(addr, cpu_gbr, B7_0);
1241             tcg_gen_qemu_ld8s(REG(0), addr, ctx->memidx);
1242             tcg_temp_free(addr);
1243         }
1244         return;
1245     case 0xc500:                /* mov.w @(disp,GBR),R0 */
1246         {
1247             TCGv addr = tcg_temp_new();
1248             tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 2);
1249             tcg_gen_qemu_ld16s(REG(0), addr, ctx->memidx);
1250             tcg_temp_free(addr);
1251         }
1252         return;
1253     case 0xc600:                /* mov.l @(disp,GBR),R0 */
1254         {
1255             TCGv addr = tcg_temp_new();
1256             tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 4);
1257             tcg_gen_qemu_ld32s(REG(0), addr, ctx->memidx);
1258             tcg_temp_free(addr);
1259         }
1260         return;
1261     case 0xc000:                /* mov.b R0,@(disp,GBR) */
1262         {
1263             TCGv addr = tcg_temp_new();
1264             tcg_gen_addi_i32(addr, cpu_gbr, B7_0);
1265             tcg_gen_qemu_st8(REG(0), addr, ctx->memidx);
1266             tcg_temp_free(addr);
1267         }
1268         return;
1269     case 0xc100:                /* mov.w R0,@(disp,GBR) */
1270         {
1271             TCGv addr = tcg_temp_new();
1272             tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 2);
1273             tcg_gen_qemu_st16(REG(0), addr, ctx->memidx);
1274             tcg_temp_free(addr);
1275         }
1276         return;
1277     case 0xc200:                /* mov.l R0,@(disp,GBR) */
1278         {
1279             TCGv addr = tcg_temp_new();
1280             tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 4);
1281             tcg_gen_qemu_st32(REG(0), addr, ctx->memidx);
1282             tcg_temp_free(addr);
1283         }
1284         return;
1285     case 0x8000:                /* mov.b R0,@(disp,Rn) */
1286         {
1287             TCGv addr = tcg_temp_new();
1288             tcg_gen_addi_i32(addr, REG(B7_4), B3_0);
1289             tcg_gen_qemu_st8(REG(0), addr, ctx->memidx);
1290             tcg_temp_free(addr);
1291         }
1292         return;
1293     case 0x8100:                /* mov.w R0,@(disp,Rn) */
1294         {
1295             TCGv addr = tcg_temp_new();
1296             tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2);
1297             tcg_gen_qemu_st16(REG(0), addr, ctx->memidx);
1298             tcg_temp_free(addr);
1299         }
1300         return;
1301     case 0x8400:                /* mov.b @(disp,Rn),R0 */
1302         {
1303             TCGv addr = tcg_temp_new();
1304             tcg_gen_addi_i32(addr, REG(B7_4), B3_0);
1305             tcg_gen_qemu_ld8s(REG(0), addr, ctx->memidx);
1306             tcg_temp_free(addr);
1307         }
1308         return;
1309     case 0x8500:                /* mov.w @(disp,Rn),R0 */
1310         {
1311             TCGv addr = tcg_temp_new();
1312             tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2);
1313             tcg_gen_qemu_ld16s(REG(0), addr, ctx->memidx);
1314             tcg_temp_free(addr);
1315         }
1316         return;
1317     case 0xc700:                /* mova @(disp,PC),R0 */
1318         tcg_gen_movi_i32(REG(0), ((ctx->pc & 0xfffffffc) + 4 + B7_0 * 4) & ~3);
1319         return;
1320     case 0xcb00:                /* or #imm,R0 */
1321         tcg_gen_ori_i32(REG(0), REG(0), B7_0);
1322         return;
1323     case 0xcf00:                /* or.b #imm,@(R0,GBR) */
1324         {
1325             TCGv addr, val;
1326             addr = tcg_temp_new();
1327             tcg_gen_add_i32(addr, REG(0), cpu_gbr);
1328             val = tcg_temp_new();
1329             tcg_gen_qemu_ld8u(val, addr, ctx->memidx);
1330             tcg_gen_ori_i32(val, val, B7_0);
1331             tcg_gen_qemu_st8(val, addr, ctx->memidx);
1332             tcg_temp_free(val);
1333             tcg_temp_free(addr);
1334         }
1335         return;
1336     case 0xc300:                /* trapa #imm */
1337         {
1338             TCGv imm;
1339             CHECK_NOT_DELAY_SLOT
1340             tcg_gen_movi_i32(cpu_pc, ctx->pc);
1341             imm = tcg_const_i32(B7_0);
1342             gen_helper_trapa(imm);
1343             tcg_temp_free(imm);
1344             ctx->bstate = BS_BRANCH;
1345         }
1346         return;
1347     case 0xc800:                /* tst #imm,R0 */
1348         {
1349             TCGv val = tcg_temp_new();
1350             tcg_gen_andi_i32(val, REG(0), B7_0);
1351             gen_cmp_imm(TCG_COND_EQ, val, 0);
1352             tcg_temp_free(val);
1353         }
1354         return;
1355     case 0xcc00:                /* tst.b #imm,@(R0,GBR) */
1356         {
1357             TCGv val = tcg_temp_new();
1358             tcg_gen_add_i32(val, REG(0), cpu_gbr);
1359             tcg_gen_qemu_ld8u(val, val, ctx->memidx);
1360             tcg_gen_andi_i32(val, val, B7_0);
1361             gen_cmp_imm(TCG_COND_EQ, val, 0);
1362             tcg_temp_free(val);
1363         }
1364         return;
1365     case 0xca00:                /* xor #imm,R0 */
1366         tcg_gen_xori_i32(REG(0), REG(0), B7_0);
1367         return;
1368     case 0xce00:                /* xor.b #imm,@(R0,GBR) */
1369         {
1370             TCGv addr, val;
1371             addr = tcg_temp_new();
1372             tcg_gen_add_i32(addr, REG(0), cpu_gbr);
1373             val = tcg_temp_new();
1374             tcg_gen_qemu_ld8u(val, addr, ctx->memidx);
1375             tcg_gen_xori_i32(val, val, B7_0);
1376             tcg_gen_qemu_st8(val, addr, ctx->memidx);
1377             tcg_temp_free(val);
1378             tcg_temp_free(addr);
1379         }
1380         return;
1381     }
1382
1383     switch (ctx->opcode & 0xf08f) {
1384     case 0x408e:                /* ldc Rm,Rn_BANK */
1385         CHECK_PRIVILEGED
1386         tcg_gen_mov_i32(ALTREG(B6_4), REG(B11_8));
1387         return;
1388     case 0x4087:                /* ldc.l @Rm+,Rn_BANK */
1389         CHECK_PRIVILEGED
1390         tcg_gen_qemu_ld32s(ALTREG(B6_4), REG(B11_8), ctx->memidx);
1391         tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
1392         return;
1393     case 0x0082:                /* stc Rm_BANK,Rn */
1394         CHECK_PRIVILEGED
1395         tcg_gen_mov_i32(REG(B11_8), ALTREG(B6_4));
1396         return;
1397     case 0x4083:                /* stc.l Rm_BANK,@-Rn */
1398         CHECK_PRIVILEGED
1399         {
1400             TCGv addr = tcg_temp_new();
1401             tcg_gen_subi_i32(addr, REG(B11_8), 4);
1402             tcg_gen_qemu_st32(ALTREG(B6_4), addr, ctx->memidx);
1403             tcg_temp_free(addr);
1404             tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
1405         }
1406         return;
1407     }
1408
1409     switch (ctx->opcode & 0xf0ff) {
1410     case 0x0023:                /* braf Rn */
1411         CHECK_NOT_DELAY_SLOT
1412         tcg_gen_addi_i32(cpu_delayed_pc, REG(B11_8), ctx->pc + 4);
1413         ctx->flags |= DELAY_SLOT;
1414         ctx->delayed_pc = (uint32_t) - 1;
1415         return;
1416     case 0x0003:                /* bsrf Rn */
1417         CHECK_NOT_DELAY_SLOT
1418         tcg_gen_movi_i32(cpu_pr, ctx->pc + 4);
1419         tcg_gen_add_i32(cpu_delayed_pc, REG(B11_8), cpu_pr);
1420         ctx->flags |= DELAY_SLOT;
1421         ctx->delayed_pc = (uint32_t) - 1;
1422         return;
1423     case 0x4015:                /* cmp/pl Rn */
1424         gen_cmp_imm(TCG_COND_GT, REG(B11_8), 0);
1425         return;
1426     case 0x4011:                /* cmp/pz Rn */
1427         gen_cmp_imm(TCG_COND_GE, REG(B11_8), 0);
1428         return;
1429     case 0x4010:                /* dt Rn */
1430         tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 1);
1431         gen_cmp_imm(TCG_COND_EQ, REG(B11_8), 0);
1432         return;
1433     case 0x402b:                /* jmp @Rn */
1434         CHECK_NOT_DELAY_SLOT
1435         tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8));
1436         ctx->flags |= DELAY_SLOT;
1437         ctx->delayed_pc = (uint32_t) - 1;
1438         return;
1439     case 0x400b:                /* jsr @Rn */
1440         CHECK_NOT_DELAY_SLOT
1441         tcg_gen_movi_i32(cpu_pr, ctx->pc + 4);
1442         tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8));
1443         ctx->flags |= DELAY_SLOT;
1444         ctx->delayed_pc = (uint32_t) - 1;
1445         return;
1446     case 0x400e:                /* ldc Rm,SR */
1447         CHECK_PRIVILEGED
1448         tcg_gen_andi_i32(cpu_sr, REG(B11_8), 0x700083f3);
1449         ctx->bstate = BS_STOP;
1450         return;
1451     case 0x4007:                /* ldc.l @Rm+,SR */
1452         CHECK_PRIVILEGED
1453         {
1454             TCGv val = tcg_temp_new();
1455             tcg_gen_qemu_ld32s(val, REG(B11_8), ctx->memidx);
1456             tcg_gen_andi_i32(cpu_sr, val, 0x700083f3);
1457             tcg_temp_free(val);
1458             tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
1459             ctx->bstate = BS_STOP;
1460         }
1461         return;
1462     case 0x0002:                /* stc SR,Rn */
1463         CHECK_PRIVILEGED
1464         tcg_gen_mov_i32(REG(B11_8), cpu_sr);
1465         return;
1466     case 0x4003:                /* stc SR,@-Rn */
1467         CHECK_PRIVILEGED
1468         {
1469             TCGv addr = tcg_temp_new();
1470             tcg_gen_subi_i32(addr, REG(B11_8), 4);
1471             tcg_gen_qemu_st32(cpu_sr, addr, ctx->memidx);
1472             tcg_temp_free(addr);
1473             tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
1474         }
1475         return;
1476 #define LDST(reg,ldnum,ldpnum,stnum,stpnum,prechk)              \
1477   case ldnum:                                                   \
1478     prechk                                                      \
1479     tcg_gen_mov_i32 (cpu_##reg, REG(B11_8));                    \
1480     return;                                                     \
1481   case ldpnum:                                                  \
1482     prechk                                                      \
1483     tcg_gen_qemu_ld32s (cpu_##reg, REG(B11_8), ctx->memidx);    \
1484     tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);                \
1485     return;                                                     \
1486   case stnum:                                                   \
1487     prechk                                                      \
1488     tcg_gen_mov_i32 (REG(B11_8), cpu_##reg);                    \
1489     return;                                                     \
1490   case stpnum:                                                  \
1491     prechk                                                      \
1492     {                                                           \
1493         TCGv addr = tcg_temp_new();                     \
1494         tcg_gen_subi_i32(addr, REG(B11_8), 4);                  \
1495         tcg_gen_qemu_st32 (cpu_##reg, addr, ctx->memidx);       \
1496         tcg_temp_free(addr);                                    \
1497         tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);            \
1498     }                                                           \
1499     return;
1500         LDST(gbr,  0x401e, 0x4017, 0x0012, 0x4013, {})
1501         LDST(vbr,  0x402e, 0x4027, 0x0022, 0x4023, CHECK_PRIVILEGED)
1502         LDST(ssr,  0x403e, 0x4037, 0x0032, 0x4033, CHECK_PRIVILEGED)
1503         LDST(spc,  0x404e, 0x4047, 0x0042, 0x4043, CHECK_PRIVILEGED)
1504         LDST(dbr,  0x40fa, 0x40f6, 0x00fa, 0x40f2, CHECK_PRIVILEGED)
1505         LDST(mach, 0x400a, 0x4006, 0x000a, 0x4002, {})
1506         LDST(macl, 0x401a, 0x4016, 0x001a, 0x4012, {})
1507         LDST(pr,   0x402a, 0x4026, 0x002a, 0x4022, {})
1508         LDST(fpul, 0x405a, 0x4056, 0x005a, 0x4052, {CHECK_FPU_ENABLED})
1509     case 0x406a:                /* lds Rm,FPSCR */
1510         CHECK_FPU_ENABLED
1511         gen_helper_ld_fpscr(REG(B11_8));
1512         ctx->bstate = BS_STOP;
1513         return;
1514     case 0x4066:                /* lds.l @Rm+,FPSCR */
1515         CHECK_FPU_ENABLED
1516         {
1517             TCGv addr = tcg_temp_new();
1518             tcg_gen_qemu_ld32s(addr, REG(B11_8), ctx->memidx);
1519             tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
1520             gen_helper_ld_fpscr(addr);
1521             tcg_temp_free(addr);
1522             ctx->bstate = BS_STOP;
1523         }
1524         return;
1525     case 0x006a:                /* sts FPSCR,Rn */
1526         CHECK_FPU_ENABLED
1527         tcg_gen_andi_i32(REG(B11_8), cpu_fpscr, 0x003fffff);
1528         return;
1529     case 0x4062:                /* sts FPSCR,@-Rn */
1530         CHECK_FPU_ENABLED
1531         {
1532             TCGv addr, val;
1533             val = tcg_temp_new();
1534             tcg_gen_andi_i32(val, cpu_fpscr, 0x003fffff);
1535             addr = tcg_temp_new();
1536             tcg_gen_subi_i32(addr, REG(B11_8), 4);
1537             tcg_gen_qemu_st32(val, addr, ctx->memidx);
1538             tcg_temp_free(addr);
1539             tcg_temp_free(val);
1540             tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
1541         }
1542         return;
1543     case 0x00c3:                /* movca.l R0,@Rm */
1544         tcg_gen_qemu_st32(REG(0), REG(B11_8), ctx->memidx);
1545         return;
1546     case 0x40a9:
1547         /* MOVUA.L @Rm,R0 (Rm) -> R0
1548            Load non-boundary-aligned data */
1549         tcg_gen_qemu_ld32u(REG(0), REG(B11_8), ctx->memidx);
1550         return;
1551     case 0x40e9:
1552         /* MOVUA.L @Rm+,R0   (Rm) -> R0, Rm + 4 -> Rm
1553            Load non-boundary-aligned data */
1554         tcg_gen_qemu_ld32u(REG(0), REG(B11_8), ctx->memidx);
1555         tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
1556         return;
1557     case 0x0029:                /* movt Rn */
1558         tcg_gen_andi_i32(REG(B11_8), cpu_sr, SR_T);
1559         return;
1560     case 0x0093:                /* ocbi @Rn */
1561         {
1562             TCGv dummy = tcg_temp_new();
1563             tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx);
1564             tcg_temp_free(dummy);
1565         }
1566         return;
1567     case 0x00a3:                /* ocbp @Rn */
1568         {
1569             TCGv dummy = tcg_temp_new();
1570             tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx);
1571             tcg_temp_free(dummy);
1572         }
1573         return;
1574     case 0x00b3:                /* ocbwb @Rn */
1575         {
1576             TCGv dummy = tcg_temp_new();
1577             tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx);
1578             tcg_temp_free(dummy);
1579         }
1580         return;
1581     case 0x0083:                /* pref @Rn */
1582         return;
1583     case 0x00d3:                /* prefi @Rn */
1584         if (ctx->features & SH_FEATURE_SH4A)
1585             return;
1586         else
1587             break;
1588     case 0x00e3:                /* icbi @Rn */
1589         if (ctx->features & SH_FEATURE_SH4A)
1590             return;
1591         else
1592             break;
1593     case 0x00ab:                /* synco */
1594         if (ctx->features & SH_FEATURE_SH4A)
1595             return;
1596         else
1597             break;
1598     case 0x4024:                /* rotcl Rn */
1599         {
1600             TCGv tmp = tcg_temp_new();
1601             tcg_gen_mov_i32(tmp, cpu_sr);
1602             gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31);
1603             tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1);
1604             gen_copy_bit_i32(REG(B11_8), 0, tmp, 0);
1605             tcg_temp_free(tmp);
1606         }
1607         return;
1608     case 0x4025:                /* rotcr Rn */
1609         {
1610             TCGv tmp = tcg_temp_new();
1611             tcg_gen_mov_i32(tmp, cpu_sr);
1612             gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0);
1613             tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1);
1614             gen_copy_bit_i32(REG(B11_8), 31, tmp, 0);
1615             tcg_temp_free(tmp);
1616         }
1617         return;
1618     case 0x4004:                /* rotl Rn */
1619         gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31);
1620         tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1);
1621         gen_copy_bit_i32(REG(B11_8), 0, cpu_sr, 0);
1622         return;
1623     case 0x4005:                /* rotr Rn */
1624         gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0);
1625         tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1);
1626         gen_copy_bit_i32(REG(B11_8), 31, cpu_sr, 0);
1627         return;
1628     case 0x4000:                /* shll Rn */
1629     case 0x4020:                /* shal Rn */
1630         gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31);
1631         tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1);
1632         return;
1633     case 0x4021:                /* shar Rn */
1634         gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0);
1635         tcg_gen_sari_i32(REG(B11_8), REG(B11_8), 1);
1636         return;
1637     case 0x4001:                /* shlr Rn */
1638         gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0);
1639         tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1);
1640         return;
1641     case 0x4008:                /* shll2 Rn */
1642         tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 2);
1643         return;
1644     case 0x4018:                /* shll8 Rn */
1645         tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 8);
1646         return;
1647     case 0x4028:                /* shll16 Rn */
1648         tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 16);
1649         return;
1650     case 0x4009:                /* shlr2 Rn */
1651         tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 2);
1652         return;
1653     case 0x4019:                /* shlr8 Rn */
1654         tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 8);
1655         return;
1656     case 0x4029:                /* shlr16 Rn */
1657         tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 16);
1658         return;
1659     case 0x401b:                /* tas.b @Rn */
1660         {
1661             TCGv addr, val;
1662             addr = tcg_temp_local_new();
1663             tcg_gen_mov_i32(addr, REG(B11_8));
1664             val = tcg_temp_local_new();
1665             tcg_gen_qemu_ld8u(val, addr, ctx->memidx);
1666             gen_cmp_imm(TCG_COND_EQ, val, 0);
1667             tcg_gen_ori_i32(val, val, 0x80);
1668             tcg_gen_qemu_st8(val, addr, ctx->memidx);
1669             tcg_temp_free(val);
1670             tcg_temp_free(addr);
1671         }
1672         return;
1673     case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */
1674         CHECK_FPU_ENABLED
1675         tcg_gen_mov_i32(cpu_fregs[FREG(B11_8)], cpu_fpul);
1676         return;
1677     case 0xf01d: /* flds FRm,FPUL - FPSCR: Nothing */
1678         CHECK_FPU_ENABLED
1679         tcg_gen_mov_i32(cpu_fpul, cpu_fregs[FREG(B11_8)]);
1680         return;
1681     case 0xf02d: /* float FPUL,FRn/DRn - FPSCR: R[PR,Enable.I]/W[Cause,Flag] */
1682         CHECK_FPU_ENABLED
1683         if (ctx->fpscr & FPSCR_PR) {
1684             TCGv_i64 fp;
1685             if (ctx->opcode & 0x0100)
1686                 break; /* illegal instruction */
1687             fp = tcg_temp_new_i64();
1688             gen_helper_float_DT(fp, cpu_fpul);
1689             gen_store_fpr64(fp, DREG(B11_8));
1690             tcg_temp_free_i64(fp);
1691         }
1692         else {
1693             gen_helper_float_FT(cpu_fregs[FREG(B11_8)], cpu_fpul);
1694         }
1695         return;
1696     case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
1697         CHECK_FPU_ENABLED
1698         if (ctx->fpscr & FPSCR_PR) {
1699             TCGv_i64 fp;
1700             if (ctx->opcode & 0x0100)
1701                 break; /* illegal instruction */
1702             fp = tcg_temp_new_i64();
1703             gen_load_fpr64(fp, DREG(B11_8));
1704             gen_helper_ftrc_DT(cpu_fpul, fp);
1705             tcg_temp_free_i64(fp);
1706         }
1707         else {
1708             gen_helper_ftrc_FT(cpu_fpul, cpu_fregs[FREG(B11_8)]);
1709         }
1710         return;
1711     case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */
1712         CHECK_FPU_ENABLED
1713         {
1714             gen_helper_fneg_T(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]);
1715         }
1716         return;
1717     case 0xf05d: /* fabs FRn/DRn */
1718         CHECK_FPU_ENABLED
1719         if (ctx->fpscr & FPSCR_PR) {
1720             if (ctx->opcode & 0x0100)
1721                 break; /* illegal instruction */
1722             TCGv_i64 fp = tcg_temp_new_i64();
1723             gen_load_fpr64(fp, DREG(B11_8));
1724             gen_helper_fabs_DT(fp, fp);
1725             gen_store_fpr64(fp, DREG(B11_8));
1726             tcg_temp_free_i64(fp);
1727         } else {
1728             gen_helper_fabs_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]);
1729         }
1730         return;
1731     case 0xf06d: /* fsqrt FRn */
1732         CHECK_FPU_ENABLED
1733         if (ctx->fpscr & FPSCR_PR) {
1734             if (ctx->opcode & 0x0100)
1735                 break; /* illegal instruction */
1736             TCGv_i64 fp = tcg_temp_new_i64();
1737             gen_load_fpr64(fp, DREG(B11_8));
1738             gen_helper_fsqrt_DT(fp, fp);
1739             gen_store_fpr64(fp, DREG(B11_8));
1740             tcg_temp_free_i64(fp);
1741         } else {
1742             gen_helper_fsqrt_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]);
1743         }
1744         return;
1745     case 0xf07d: /* fsrra FRn */
1746         CHECK_FPU_ENABLED
1747         break;
1748     case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */
1749         CHECK_FPU_ENABLED
1750         if (!(ctx->fpscr & FPSCR_PR)) {
1751             tcg_gen_movi_i32(cpu_fregs[FREG(B11_8)], 0);
1752         }
1753         return;
1754     case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */
1755         CHECK_FPU_ENABLED
1756         if (!(ctx->fpscr & FPSCR_PR)) {
1757             tcg_gen_movi_i32(cpu_fregs[FREG(B11_8)], 0x3f800000);
1758         }
1759         return;
1760     case 0xf0ad: /* fcnvsd FPUL,DRn */
1761         CHECK_FPU_ENABLED
1762         {
1763             TCGv_i64 fp = tcg_temp_new_i64();
1764             gen_helper_fcnvsd_FT_DT(fp, cpu_fpul);
1765             gen_store_fpr64(fp, DREG(B11_8));
1766             tcg_temp_free_i64(fp);
1767         }
1768         return;
1769     case 0xf0bd: /* fcnvds DRn,FPUL */
1770         CHECK_FPU_ENABLED
1771         {
1772             TCGv_i64 fp = tcg_temp_new_i64();
1773             gen_load_fpr64(fp, DREG(B11_8));
1774             gen_helper_fcnvds_DT_FT(cpu_fpul, fp);
1775             tcg_temp_free_i64(fp);
1776         }
1777         return;
1778     }
1779 #if 0
1780     fprintf(stderr, "unknown instruction 0x%04x at pc 0x%08x\n",
1781             ctx->opcode, ctx->pc);
1782     fflush(stderr);
1783 #endif
1784     gen_helper_raise_illegal_instruction();
1785     ctx->bstate = BS_EXCP;
1786 }
1787
1788 static void decode_opc(DisasContext * ctx)
1789 {
1790     uint32_t old_flags = ctx->flags;
1791
1792     _decode_opc(ctx);
1793
1794     if (old_flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
1795         if (ctx->flags & DELAY_SLOT_CLEARME) {
1796             gen_store_flags(0);
1797         } else {
1798             /* go out of the delay slot */
1799             uint32_t new_flags = ctx->flags;
1800             new_flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL);
1801             gen_store_flags(new_flags);
1802         }
1803         ctx->flags = 0;
1804         ctx->bstate = BS_BRANCH;
1805         if (old_flags & DELAY_SLOT_CONDITIONAL) {
1806             gen_delayed_conditional_jump(ctx);
1807         } else if (old_flags & DELAY_SLOT) {
1808             gen_jump(ctx);
1809         }
1810
1811     }
1812
1813     /* go into a delay slot */
1814     if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL))
1815         gen_store_flags(ctx->flags);
1816 }
1817
1818 static inline void
1819 gen_intermediate_code_internal(CPUState * env, TranslationBlock * tb,
1820                                int search_pc)
1821 {
1822     DisasContext ctx;
1823     target_ulong pc_start;
1824     static uint16_t *gen_opc_end;
1825     CPUBreakpoint *bp;
1826     int i, ii;
1827     int num_insns;
1828     int max_insns;
1829
1830     pc_start = tb->pc;
1831     gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
1832     ctx.pc = pc_start;
1833     ctx.flags = (uint32_t)tb->flags;
1834     ctx.bstate = BS_NONE;
1835     ctx.sr = env->sr;
1836     ctx.fpscr = env->fpscr;
1837     ctx.memidx = (env->sr & SR_MD) ? 1 : 0;
1838     /* We don't know if the delayed pc came from a dynamic or static branch,
1839        so assume it is a dynamic branch.  */
1840     ctx.delayed_pc = -1; /* use delayed pc from env pointer */
1841     ctx.tb = tb;
1842     ctx.singlestep_enabled = env->singlestep_enabled;
1843     ctx.features = env->features;
1844
1845 #ifdef DEBUG_DISAS
1846     qemu_log_mask(CPU_LOG_TB_CPU,
1847                  "------------------------------------------------\n");
1848     log_cpu_state_mask(CPU_LOG_TB_CPU, env, 0);
1849 #endif
1850
1851     ii = -1;
1852     num_insns = 0;
1853     max_insns = tb->cflags & CF_COUNT_MASK;
1854     if (max_insns == 0)
1855         max_insns = CF_COUNT_MASK;
1856     gen_icount_start();
1857     while (ctx.bstate == BS_NONE && gen_opc_ptr < gen_opc_end) {
1858         if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
1859             TAILQ_FOREACH(bp, &env->breakpoints, entry) {
1860                 if (ctx.pc == bp->pc) {
1861                     /* We have hit a breakpoint - make sure PC is up-to-date */
1862                     tcg_gen_movi_i32(cpu_pc, ctx.pc);
1863                     gen_helper_debug();
1864                     ctx.bstate = BS_EXCP;
1865                     break;
1866                 }
1867             }
1868         }
1869         if (search_pc) {
1870             i = gen_opc_ptr - gen_opc_buf;
1871             if (ii < i) {
1872                 ii++;
1873                 while (ii < i)
1874                     gen_opc_instr_start[ii++] = 0;
1875             }
1876             gen_opc_pc[ii] = ctx.pc;
1877             gen_opc_hflags[ii] = ctx.flags;
1878             gen_opc_instr_start[ii] = 1;
1879             gen_opc_icount[ii] = num_insns;
1880         }
1881         if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
1882             gen_io_start();
1883 #if 0
1884         fprintf(stderr, "Loading opcode at address 0x%08x\n", ctx.pc);
1885         fflush(stderr);
1886 #endif
1887         ctx.opcode = lduw_code(ctx.pc);
1888         decode_opc(&ctx);
1889         num_insns++;
1890         ctx.pc += 2;
1891         if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0)
1892             break;
1893         if (env->singlestep_enabled)
1894             break;
1895         if (num_insns >= max_insns)
1896             break;
1897 #ifdef SH4_SINGLE_STEP
1898         break;
1899 #endif
1900     }
1901     if (tb->cflags & CF_LAST_IO)
1902         gen_io_end();
1903     if (env->singlestep_enabled) {
1904         tcg_gen_movi_i32(cpu_pc, ctx.pc);
1905         gen_helper_debug();
1906     } else {
1907         switch (ctx.bstate) {
1908         case BS_STOP:
1909             /* gen_op_interrupt_restart(); */
1910             /* fall through */
1911         case BS_NONE:
1912             if (ctx.flags) {
1913                 gen_store_flags(ctx.flags | DELAY_SLOT_CLEARME);
1914             }
1915             gen_goto_tb(&ctx, 0, ctx.pc);
1916             break;
1917         case BS_EXCP:
1918             /* gen_op_interrupt_restart(); */
1919             tcg_gen_exit_tb(0);
1920             break;
1921         case BS_BRANCH:
1922         default:
1923             break;
1924         }
1925     }
1926
1927     gen_icount_end(tb, num_insns);
1928     *gen_opc_ptr = INDEX_op_end;
1929     if (search_pc) {
1930         i = gen_opc_ptr - gen_opc_buf;
1931         ii++;
1932         while (ii <= i)
1933             gen_opc_instr_start[ii++] = 0;
1934     } else {
1935         tb->size = ctx.pc - pc_start;
1936         tb->icount = num_insns;
1937     }
1938
1939 #ifdef DEBUG_DISAS
1940 #ifdef SH4_DEBUG_DISAS
1941     qemu_log_mask(CPU_LOG_TB_IN_ASM, "\n");
1942 #endif
1943     if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1944         qemu_log("IN:\n");      /* , lookup_symbol(pc_start)); */
1945         log_target_disas(pc_start, ctx.pc - pc_start, 0);
1946         qemu_log("\n");
1947     }
1948 #endif
1949 }
1950
1951 void gen_intermediate_code(CPUState * env, struct TranslationBlock *tb)
1952 {
1953     gen_intermediate_code_internal(env, tb, 0);
1954 }
1955
1956 void gen_intermediate_code_pc(CPUState * env, struct TranslationBlock *tb)
1957 {
1958     gen_intermediate_code_internal(env, tb, 1);
1959 }
1960
1961 void gen_pc_load(CPUState *env, TranslationBlock *tb,
1962                 unsigned long searched_pc, int pc_pos, void *puc)
1963 {
1964     env->pc = gen_opc_pc[pc_pos];
1965     env->flags = gen_opc_hflags[pc_pos];
1966 }