git.maemo.org Git - qemu/blob - target-sh4/translate.c

   1 /*
   2  *  SH4 translation
   3  *
   4  *  Copyright (c) 2005 Samuel Tardieu
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include <stdarg.h>
  21 #include <stdlib.h>
  22 #include <stdio.h>
  23 #include <string.h>
  24 #include <inttypes.h>
  25 #include <assert.h>
  26
  27 #define DEBUG_DISAS
  28 #define SH4_DEBUG_DISAS
  29 //#define SH4_SINGLE_STEP
  30
  31 #include "cpu.h"
  32 #include "exec-all.h"
  33 #include "disas.h"
  34 #include "tcg-op.h"
  35 #include "qemu-common.h"
  36
  37 #include "helper.h"
  38 #define GEN_HELPER 1
  39 #include "helper.h"
  40
  41 typedef struct DisasContext {
  42     struct TranslationBlock *tb;
  43     target_ulong pc;
  44     uint32_t sr;
  45     uint32_t fpscr;
  46     uint16_t opcode;
  47     uint32_t flags;
  48     int bstate;
  49     int memidx;
  50     uint32_t delayed_pc;
  51     int singlestep_enabled;
  52 } DisasContext;
  53
  54 #if defined(CONFIG_USER_ONLY)
  55 #define IS_USER(ctx) 1
  56 #else
  57 #define IS_USER(ctx) (!(ctx->sr & SR_MD))
  58 #endif
  59
  60 enum {
  61     BS_NONE     = 0, /* We go out of the TB without reaching a branch or an
  62                       * exception condition
  63                       */
  64     BS_STOP     = 1, /* We want to stop translation for any reason */
  65     BS_BRANCH   = 2, /* We reached a branch condition     */
  66     BS_EXCP     = 3, /* We reached an exception condition */
  67 };
  68
  69 /* global register indexes */
  70 static TCGv_ptr cpu_env;
  71 static TCGv cpu_gregs[24];
  72 static TCGv cpu_pc, cpu_sr, cpu_ssr, cpu_spc, cpu_gbr;
  73 static TCGv cpu_vbr, cpu_sgr, cpu_dbr, cpu_mach, cpu_macl;
  74 static TCGv cpu_pr, cpu_fpscr, cpu_fpul, cpu_flags;
  75
  76 /* internal register indexes */
  77 static TCGv cpu_flags, cpu_delayed_pc;
  78
  79 #include "gen-icount.h"
  80
  81 static void sh4_translate_init(void)
  82 {
  83     int i;
  84     static int done_init = 0;
  85     static const char * const gregnames[24] = {
  86         "R0_BANK0", "R1_BANK0", "R2_BANK0", "R3_BANK0",
  87         "R4_BANK0", "R5_BANK0", "R6_BANK0", "R7_BANK0",
  88         "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15",
  89         "R0_BANK1", "R1_BANK1", "R2_BANK1", "R3_BANK1",
  90         "R4_BANK1", "R5_BANK1", "R6_BANK1", "R7_BANK1"
  91     };
  92
  93     if (done_init)
  94         return;
  95
  96     cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
  97
  98     for (i = 0; i < 24; i++)
  99         cpu_gregs[i] = tcg_global_mem_new_i32(TCG_AREG0,
 100                                           offsetof(CPUState, gregs[i]),
 101                                           gregnames[i]);
 102
 103     cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
 104                                     offsetof(CPUState, pc), "PC");
 105     cpu_sr = tcg_global_mem_new_i32(TCG_AREG0,
 106                                     offsetof(CPUState, sr), "SR");
 107     cpu_ssr = tcg_global_mem_new_i32(TCG_AREG0,
 108                                      offsetof(CPUState, ssr), "SSR");
 109     cpu_spc = tcg_global_mem_new_i32(TCG_AREG0,
 110                                      offsetof(CPUState, spc), "SPC");
 111     cpu_gbr = tcg_global_mem_new_i32(TCG_AREG0,
 112                                      offsetof(CPUState, gbr), "GBR");
 113     cpu_vbr = tcg_global_mem_new_i32(TCG_AREG0,
 114                                      offsetof(CPUState, vbr), "VBR");
 115     cpu_sgr = tcg_global_mem_new_i32(TCG_AREG0,
 116                                      offsetof(CPUState, sgr), "SGR");
 117     cpu_dbr = tcg_global_mem_new_i32(TCG_AREG0,
 118                                      offsetof(CPUState, dbr), "DBR");
 119     cpu_mach = tcg_global_mem_new_i32(TCG_AREG0,
 120                                       offsetof(CPUState, mach), "MACH");
 121     cpu_macl = tcg_global_mem_new_i32(TCG_AREG0,
 122                                       offsetof(CPUState, macl), "MACL");
 123     cpu_pr = tcg_global_mem_new_i32(TCG_AREG0,
 124                                     offsetof(CPUState, pr), "PR");
 125     cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
 126                                        offsetof(CPUState, fpscr), "FPSCR");
 127     cpu_fpul = tcg_global_mem_new_i32(TCG_AREG0,
 128                                       offsetof(CPUState, fpul), "FPUL");
 129
 130     cpu_flags = tcg_global_mem_new_i32(TCG_AREG0,
 131                                        offsetof(CPUState, flags), "_flags_");
 132     cpu_delayed_pc = tcg_global_mem_new_i32(TCG_AREG0,
 133                                             offsetof(CPUState, delayed_pc),
 134                                             "_delayed_pc_");
 135
 136     /* register helpers */
 137 #define GEN_HELPER 2
 138 #include "helper.h"
 139
 140     done_init = 1;
 141 }
 142
 143 void cpu_dump_state(CPUState * env, FILE * f,
 144                     int (*cpu_fprintf) (FILE * f, const char *fmt, ...),
 145                     int flags)
 146 {
 147     int i;
 148     cpu_fprintf(f, "pc=0x%08x sr=0x%08x pr=0x%08x fpscr=0x%08x\n",
 149                 env->pc, env->sr, env->pr, env->fpscr);
 150     cpu_fprintf(f, "spc=0x%08x ssr=0x%08x gbr=0x%08x vbr=0x%08x\n",
 151                 env->spc, env->ssr, env->gbr, env->vbr);
 152     cpu_fprintf(f, "sgr=0x%08x dbr=0x%08x delayed_pc=0x%08x fpul=0x%08x\n",
 153                 env->sgr, env->dbr, env->delayed_pc, env->fpul);
 154     for (i = 0; i < 24; i += 4) {
 155         cpu_fprintf(f, "r%d=0x%08x r%d=0x%08x r%d=0x%08x r%d=0x%08x\n",
 156                     i, env->gregs[i], i + 1, env->gregs[i + 1],
 157                     i + 2, env->gregs[i + 2], i + 3, env->gregs[i + 3]);
 158     }
 159     if (env->flags & DELAY_SLOT) {
 160         cpu_fprintf(f, "in delay slot (delayed_pc=0x%08x)\n",
 161                     env->delayed_pc);
 162     } else if (env->flags & DELAY_SLOT_CONDITIONAL) {
 163         cpu_fprintf(f, "in conditional delay slot (delayed_pc=0x%08x)\n",
 164                     env->delayed_pc);
 165     }
 166 }
 167
 168 void cpu_sh4_reset(CPUSH4State * env)
 169 {
 170 #if defined(CONFIG_USER_ONLY)
 171     env->sr = SR_FD;            /* FD - kernel does lazy fpu context switch */
 172 #else
 173     env->sr = 0x700000F0;       /* MD, RB, BL, I3-I0 */
 174 #endif
 175     env->vbr = 0;
 176     env->pc = 0xA0000000;
 177 #if defined(CONFIG_USER_ONLY)
 178     env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */
 179     set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */
 180 #else
 181     env->fpscr = 0x00040001; /* CPU reset value according to SH4 manual */
 182     set_float_rounding_mode(float_round_to_zero, &env->fp_status);
 183 #endif
 184     env->mmucr = 0;
 185 }
 186
 187 typedef struct {
 188     const char *name;
 189     int id;
 190     uint32_t pvr;
 191     uint32_t prr;
 192     uint32_t cvr;
 193 } sh4_def_t;
 194
 195 static sh4_def_t sh4_defs[] = {
 196     {
 197         .name = "SH7750R",
 198         .id = SH_CPU_SH7750R,
 199         .pvr = 0x00050000,
 200         .prr = 0x00000100,
 201         .cvr = 0x00110000,
 202     }, {
 203         .name = "SH7751R",
 204         .id = SH_CPU_SH7751R,
 205         .pvr = 0x04050005,
 206         .prr = 0x00000113,
 207         .cvr = 0x00110000,      /* Neutered caches, should be 0x20480000 */
 208     },
 209 };
 210
 211 static const sh4_def_t *cpu_sh4_find_by_name(const char *name)
 212 {
 213     int i;
 214
 215     if (strcasecmp(name, "any") == 0)
 216         return &sh4_defs[0];
 217
 218     for (i = 0; i < sizeof(sh4_defs) / sizeof(*sh4_defs); i++)
 219         if (strcasecmp(name, sh4_defs[i].name) == 0)
 220             return &sh4_defs[i];
 221
 222     return NULL;
 223 }
 224
 225 void sh4_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
 226 {
 227     int i;
 228
 229     for (i = 0; i < sizeof(sh4_defs) / sizeof(*sh4_defs); i++)
 230         (*cpu_fprintf)(f, "%s\n", sh4_defs[i].name);
 231 }
 232
 233 static void cpu_sh4_register(CPUSH4State *env, const sh4_def_t *def)
 234 {
 235     env->pvr = def->pvr;
 236     env->prr = def->prr;
 237     env->cvr = def->cvr;
 238     env->id = def->id;
 239 }
 240
 241 CPUSH4State *cpu_sh4_init(const char *cpu_model)
 242 {
 243     CPUSH4State *env;
 244     const sh4_def_t *def;
 245
 246     def = cpu_sh4_find_by_name(cpu_model);
 247     if (!def)
 248         return NULL;
 249     env = qemu_mallocz(sizeof(CPUSH4State));
 250     if (!env)
 251         return NULL;
 252     cpu_exec_init(env);
 253     sh4_translate_init();
 254     env->cpu_model_str = cpu_model;
 255     cpu_sh4_reset(env);
 256     cpu_sh4_register(env, def);
 257     tlb_flush(env, 1);
 258     return env;
 259 }
 260
 261 static void gen_goto_tb(DisasContext * ctx, int n, target_ulong dest)
 262 {
 263     TranslationBlock *tb;
 264     tb = ctx->tb;
 265
 266     if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
 267         !ctx->singlestep_enabled) {
 268         /* Use a direct jump if in same page and singlestep not enabled */
 269         tcg_gen_goto_tb(n);
 270         tcg_gen_movi_i32(cpu_pc, dest);
 271         tcg_gen_exit_tb((long) tb + n);
 272     } else {
 273         tcg_gen_movi_i32(cpu_pc, dest);
 274         if (ctx->singlestep_enabled)
 275             gen_helper_debug();
 276         tcg_gen_exit_tb(0);
 277     }
 278 }
 279
 280 static void gen_jump(DisasContext * ctx)
 281 {
 282     if (ctx->delayed_pc == (uint32_t) - 1) {
 283         /* Target is not statically known, it comes necessarily from a
 284            delayed jump as immediate jump are conditinal jumps */
 285         tcg_gen_mov_i32(cpu_pc, cpu_delayed_pc);
 286         if (ctx->singlestep_enabled)
 287             gen_helper_debug();
 288         tcg_gen_exit_tb(0);
 289     } else {
 290         gen_goto_tb(ctx, 0, ctx->delayed_pc);
 291     }
 292 }
 293
 294 static inline void gen_branch_slot(uint32_t delayed_pc, int t)
 295 {
 296     TCGv sr;
 297     int label = gen_new_label();
 298     tcg_gen_movi_i32(cpu_delayed_pc, delayed_pc);
 299     sr = tcg_temp_new();
 300     tcg_gen_andi_i32(sr, cpu_sr, SR_T);
 301     tcg_gen_brcondi_i32(TCG_COND_NE, sr, t ? SR_T : 0, label);
 302     tcg_gen_ori_i32(cpu_flags, cpu_flags, DELAY_SLOT_TRUE);
 303     gen_set_label(label);
 304 }
 305
 306 /* Immediate conditional jump (bt or bf) */
 307 static void gen_conditional_jump(DisasContext * ctx,
 308                                  target_ulong ift, target_ulong ifnott)
 309 {
 310     int l1;
 311     TCGv sr;
 312
 313     l1 = gen_new_label();
 314     sr = tcg_temp_new();
 315     tcg_gen_andi_i32(sr, cpu_sr, SR_T);
 316     tcg_gen_brcondi_i32(TCG_COND_EQ, sr, SR_T, l1);
 317     gen_goto_tb(ctx, 0, ifnott);
 318     gen_set_label(l1);
 319     gen_goto_tb(ctx, 1, ift);
 320 }
 321
 322 /* Delayed conditional jump (bt or bf) */
 323 static void gen_delayed_conditional_jump(DisasContext * ctx)
 324 {
 325     int l1;
 326     TCGv ds;
 327
 328     l1 = gen_new_label();
 329     ds = tcg_temp_new();
 330     tcg_gen_andi_i32(ds, cpu_flags, DELAY_SLOT_TRUE);
 331     tcg_gen_brcondi_i32(TCG_COND_EQ, ds, DELAY_SLOT_TRUE, l1);
 332     gen_goto_tb(ctx, 1, ctx->pc + 2);
 333     gen_set_label(l1);
 334     tcg_gen_andi_i32(cpu_flags, cpu_flags, ~DELAY_SLOT_TRUE);
 335     gen_jump(ctx);
 336 }
 337
 338 static inline void gen_set_t(void)
 339 {
 340     tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_T);
 341 }
 342
 343 static inline void gen_clr_t(void)
 344 {
 345     tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
 346 }
 347
 348 static inline void gen_cmp(int cond, TCGv t0, TCGv t1)
 349 {
 350     int label1 = gen_new_label();
 351     int label2 = gen_new_label();
 352     tcg_gen_brcond_i32(cond, t1, t0, label1);
 353     gen_clr_t();
 354     tcg_gen_br(label2);
 355     gen_set_label(label1);
 356     gen_set_t();
 357     gen_set_label(label2);
 358 }
 359
 360 static inline void gen_cmp_imm(int cond, TCGv t0, int32_t imm)
 361 {
 362     int label1 = gen_new_label();
 363     int label2 = gen_new_label();
 364     tcg_gen_brcondi_i32(cond, t0, imm, label1);
 365     gen_clr_t();
 366     tcg_gen_br(label2);
 367     gen_set_label(label1);
 368     gen_set_t();
 369     gen_set_label(label2);
 370 }
 371
 372 static inline void gen_store_flags(uint32_t flags)
 373 {
 374     tcg_gen_andi_i32(cpu_flags, cpu_flags, DELAY_SLOT_TRUE);
 375     tcg_gen_ori_i32(cpu_flags, cpu_flags, flags);
 376 }
 377
 378 static inline void gen_copy_bit_i32(TCGv t0, int p0, TCGv t1, int p1)
 379 {
 380     TCGv tmp = tcg_temp_new();
 381
 382     p0 &= 0x1f;
 383     p1 &= 0x1f;
 384
 385     tcg_gen_andi_i32(tmp, t1, (1 << p1));
 386     tcg_gen_andi_i32(t0, t0, ~(1 << p0));
 387     if (p0 < p1)
 388         tcg_gen_shri_i32(tmp, tmp, p1 - p0);
 389     else if (p0 > p1)
 390         tcg_gen_shli_i32(tmp, tmp, p0 - p1);
 391     tcg_gen_or_i32(t0, t0, tmp);
 392
 393     tcg_temp_free(tmp);
 394 }
 395
 396
 397 static inline void gen_load_fpr32(TCGv_i32 t, int reg)
 398 {
 399     tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, fregs[reg]));
 400 }
 401
 402 static inline void gen_load_fpr64(TCGv_i64 t, int reg)
 403 {
 404     TCGv_i32 tmp1 = tcg_temp_new_i32();
 405     TCGv_i32 tmp2 = tcg_temp_new_i32();
 406
 407     tcg_gen_ld_i32(tmp1, cpu_env, offsetof(CPUState, fregs[reg]));
 408     tcg_gen_ld_i32(tmp2, cpu_env, offsetof(CPUState, fregs[reg + 1]));
 409     tcg_gen_concat_i32_i64(t, tmp2, tmp1);
 410     tcg_temp_free_i32(tmp1);
 411     tcg_temp_free_i32(tmp2);
 412 }
 413
 414 static inline void gen_store_fpr32(TCGv_i32 t, int reg)
 415 {
 416     tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, fregs[reg]));
 417 }
 418
 419 static inline void gen_store_fpr64 (TCGv_i64 t, int reg)
 420 {
 421     TCGv_i32 tmp = tcg_temp_new_i32();
 422
 423     tcg_gen_trunc_i64_i32(tmp, t);
 424     tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, fregs[reg + 1]));
 425     tcg_gen_shri_i64(t, t, 32);
 426     tcg_gen_trunc_i64_i32(tmp, t);
 427     tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, fregs[reg]));
 428     tcg_temp_free_i32(tmp);
 429 }
 430
 431 #define B3_0 (ctx->opcode & 0xf)
 432 #define B6_4 ((ctx->opcode >> 4) & 0x7)
 433 #define B7_4 ((ctx->opcode >> 4) & 0xf)
 434 #define B7_0 (ctx->opcode & 0xff)
 435 #define B7_0s ((int32_t) (int8_t) (ctx->opcode & 0xff))
 436 #define B11_0s (ctx->opcode & 0x800 ? 0xfffff000 | (ctx->opcode & 0xfff) : \
 437   (ctx->opcode & 0xfff))
 438 #define B11_8 ((ctx->opcode >> 8) & 0xf)
 439 #define B15_12 ((ctx->opcode >> 12) & 0xf)
 440
 441 #define REG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB) ? \
 442                 (cpu_gregs[x + 16]) : (cpu_gregs[x]))
 443
 444 #define ALTREG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) != (SR_MD | SR_RB) \
 445                 ? (cpu_gregs[x + 16]) : (cpu_gregs[x]))
 446
 447 #define FREG(x) (ctx->fpscr & FPSCR_FR ? (x) ^ 0x10 : (x))
 448 #define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe))
 449 #define XREG(x) (ctx->fpscr & FPSCR_FR ? XHACK(x) ^ 0x10 : XHACK(x))
 450 #define DREG(x) FREG(x) /* Assumes lsb of (x) is always 0 */
 451
 452 #define CHECK_NOT_DELAY_SLOT \
 453   if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) \
 454   {gen_helper_raise_slot_illegal_instruction(); ctx->bstate = BS_EXCP; \
 455    return;}
 456
 457 #define CHECK_PRIVILEGED                                      \
 458   if (IS_USER(ctx)) {                                         \
 459       gen_helper_raise_illegal_instruction();                 \
 460       ctx->bstate = BS_EXCP;                                  \
 461       return;                                                 \
 462   }
 463
 464 static void _decode_opc(DisasContext * ctx)
 465 {
 466 #if 0
 467     fprintf(stderr, "Translating opcode 0x%04x\n", ctx->opcode);
 468 #endif
 469     switch (ctx->opcode) {
 470     case 0x0019:                /* div0u */
 471         tcg_gen_andi_i32(cpu_sr, cpu_sr, ~(SR_M | SR_Q | SR_T));
 472         return;
 473     case 0x000b:                /* rts */
 474         CHECK_NOT_DELAY_SLOT
 475         tcg_gen_mov_i32(cpu_delayed_pc, cpu_pr);
 476         ctx->flags |= DELAY_SLOT;
 477         ctx->delayed_pc = (uint32_t) - 1;
 478         return;
 479     case 0x0028:                /* clrmac */
 480         tcg_gen_movi_i32(cpu_mach, 0);
 481         tcg_gen_movi_i32(cpu_macl, 0);
 482         return;
 483     case 0x0048:                /* clrs */
 484         tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_S);
 485         return;
 486     case 0x0008:                /* clrt */
 487         gen_clr_t();
 488         return;
 489     case 0x0038:                /* ldtlb */
 490         CHECK_PRIVILEGED
 491         gen_helper_ldtlb();
 492         return;
 493     case 0x002b:                /* rte */
 494         CHECK_PRIVILEGED
 495         CHECK_NOT_DELAY_SLOT
 496         tcg_gen_mov_i32(cpu_sr, cpu_ssr);
 497         tcg_gen_mov_i32(cpu_delayed_pc, cpu_spc);
 498         ctx->flags |= DELAY_SLOT;
 499         ctx->delayed_pc = (uint32_t) - 1;
 500         return;
 501     case 0x0058:                /* sets */
 502         tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_S);
 503         return;
 504     case 0x0018:                /* sett */
 505         gen_set_t();
 506         return;
 507     case 0xfbfd:                /* frchg */
 508         tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_FR);
 509         ctx->bstate = BS_STOP;
 510         return;
 511     case 0xf3fd:                /* fschg */
 512         tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_SZ);
 513         ctx->bstate = BS_STOP;
 514         return;
 515     case 0x0009:                /* nop */
 516         return;
 517     case 0x001b:                /* sleep */
 518         CHECK_PRIVILEGED
 519         gen_helper_sleep(tcg_const_i32(ctx->pc + 2));
 520         return;
 521     }
 522
 523     switch (ctx->opcode & 0xf000) {
 524     case 0x1000:                /* mov.l Rm,@(disp,Rn) */
 525         {
 526             TCGv addr = tcg_temp_new();
 527             tcg_gen_addi_i32(addr, REG(B11_8), B3_0 * 4);
 528             tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx);
 529             tcg_temp_free(addr);
 530         }
 531         return;
 532     case 0x5000:                /* mov.l @(disp,Rm),Rn */
 533         {
 534             TCGv addr = tcg_temp_new();
 535             tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 4);
 536             tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx);
 537             tcg_temp_free(addr);
 538         }
 539         return;
 540     case 0xe000:                /* mov #imm,Rn */
 541         tcg_gen_movi_i32(REG(B11_8), B7_0s);
 542         return;
 543     case 0x9000:                /* mov.w @(disp,PC),Rn */
 544         {
 545             TCGv addr = tcg_const_i32(ctx->pc + 4 + B7_0 * 2);
 546             tcg_gen_qemu_ld16s(REG(B11_8), addr, ctx->memidx);
 547             tcg_temp_free(addr);
 548         }
 549         return;
 550     case 0xd000:                /* mov.l @(disp,PC),Rn */
 551         {
 552             TCGv addr = tcg_const_i32((ctx->pc + 4 + B7_0 * 4) & ~3);
 553             tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx);
 554             tcg_temp_free(addr);
 555         }
 556         return;
 557     case 0x7000:                /* add #imm,Rn */
 558         tcg_gen_addi_i32(REG(B11_8), REG(B11_8), B7_0s);
 559         return;
 560     case 0xa000:                /* bra disp */
 561         CHECK_NOT_DELAY_SLOT
 562         ctx->delayed_pc = ctx->pc + 4 + B11_0s * 2;
 563         tcg_gen_movi_i32(cpu_delayed_pc, ctx->delayed_pc);
 564         ctx->flags |= DELAY_SLOT;
 565         return;
 566     case 0xb000:                /* bsr disp */
 567         CHECK_NOT_DELAY_SLOT
 568         tcg_gen_movi_i32(cpu_pr, ctx->pc + 4);
 569         ctx->delayed_pc = ctx->pc + 4 + B11_0s * 2;
 570         tcg_gen_movi_i32(cpu_delayed_pc, ctx->delayed_pc);
 571         ctx->flags |= DELAY_SLOT;
 572         return;
 573     }
 574
 575     switch (ctx->opcode & 0xf00f) {
 576     case 0x6003:                /* mov Rm,Rn */
 577         tcg_gen_mov_i32(REG(B11_8), REG(B7_4));
 578         return;
 579     case 0x2000:                /* mov.b Rm,@Rn */
 580         tcg_gen_qemu_st8(REG(B7_4), REG(B11_8), ctx->memidx);
 581         return;
 582     case 0x2001:                /* mov.w Rm,@Rn */
 583         tcg_gen_qemu_st16(REG(B7_4), REG(B11_8), ctx->memidx);
 584         return;
 585     case 0x2002:                /* mov.l Rm,@Rn */
 586         tcg_gen_qemu_st32(REG(B7_4), REG(B11_8), ctx->memidx);
 587         return;
 588     case 0x6000:                /* mov.b @Rm,Rn */
 589         tcg_gen_qemu_ld8s(REG(B11_8), REG(B7_4), ctx->memidx);
 590         return;
 591     case 0x6001:                /* mov.w @Rm,Rn */
 592         tcg_gen_qemu_ld16s(REG(B11_8), REG(B7_4), ctx->memidx);
 593         return;
 594     case 0x6002:                /* mov.l @Rm,Rn */
 595         tcg_gen_qemu_ld32s(REG(B11_8), REG(B7_4), ctx->memidx);
 596         return;
 597     case 0x2004:                /* mov.b Rm,@-Rn */
 598         {
 599             TCGv addr = tcg_temp_new();
 600             tcg_gen_subi_i32(addr, REG(B11_8), 1);
 601             tcg_gen_qemu_st8(REG(B7_4), addr, ctx->memidx);     /* might cause re-execution */
 602             tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 1);        /* modify register status */
 603             tcg_temp_free(addr);
 604         }
 605         return;
 606     case 0x2005:                /* mov.w Rm,@-Rn */
 607         {
 608             TCGv addr = tcg_temp_new();
 609             tcg_gen_subi_i32(addr, REG(B11_8), 2);
 610             tcg_gen_qemu_st16(REG(B7_4), addr, ctx->memidx);
 611             tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 2);
 612             tcg_temp_free(addr);
 613         }
 614         return;
 615     case 0x2006:                /* mov.l Rm,@-Rn */
 616         {
 617             TCGv addr = tcg_temp_new();
 618             tcg_gen_subi_i32(addr, REG(B11_8), 4);
 619             tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx);
 620             tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
 621         }
 622         return;
 623     case 0x6004:                /* mov.b @Rm+,Rn */
 624         tcg_gen_qemu_ld8s(REG(B11_8), REG(B7_4), ctx->memidx);
 625         if ( B11_8 != B7_4 )
 626                 tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 1);
 627         return;
 628     case 0x6005:                /* mov.w @Rm+,Rn */
 629         tcg_gen_qemu_ld16s(REG(B11_8), REG(B7_4), ctx->memidx);
 630         if ( B11_8 != B7_4 )
 631                 tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2);
 632         return;
 633     case 0x6006:                /* mov.l @Rm+,Rn */
 634         tcg_gen_qemu_ld32s(REG(B11_8), REG(B7_4), ctx->memidx);
 635         if ( B11_8 != B7_4 )
 636                 tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
 637         return;
 638     case 0x0004:                /* mov.b Rm,@(R0,Rn) */
 639         {
 640             TCGv addr = tcg_temp_new();
 641             tcg_gen_add_i32(addr, REG(B11_8), REG(0));
 642             tcg_gen_qemu_st8(REG(B7_4), addr, ctx->memidx);
 643             tcg_temp_free(addr);
 644         }
 645         return;
 646     case 0x0005:                /* mov.w Rm,@(R0,Rn) */
 647         {
 648             TCGv addr = tcg_temp_new();
 649             tcg_gen_add_i32(addr, REG(B11_8), REG(0));
 650             tcg_gen_qemu_st16(REG(B7_4), addr, ctx->memidx);
 651             tcg_temp_free(addr);
 652         }
 653         return;
 654     case 0x0006:                /* mov.l Rm,@(R0,Rn) */
 655         {
 656             TCGv addr = tcg_temp_new();
 657             tcg_gen_add_i32(addr, REG(B11_8), REG(0));
 658             tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx);
 659             tcg_temp_free(addr);
 660         }
 661         return;
 662     case 0x000c:                /* mov.b @(R0,Rm),Rn */
 663         {
 664             TCGv addr = tcg_temp_new();
 665             tcg_gen_add_i32(addr, REG(B7_4), REG(0));
 666             tcg_gen_qemu_ld8s(REG(B11_8), addr, ctx->memidx);
 667             tcg_temp_free(addr);
 668         }
 669         return;
 670     case 0x000d:                /* mov.w @(R0,Rm),Rn */
 671         {
 672             TCGv addr = tcg_temp_new();
 673             tcg_gen_add_i32(addr, REG(B7_4), REG(0));
 674             tcg_gen_qemu_ld16s(REG(B11_8), addr, ctx->memidx);
 675             tcg_temp_free(addr);
 676         }
 677         return;
 678     case 0x000e:                /* mov.l @(R0,Rm),Rn */
 679         {
 680             TCGv addr = tcg_temp_new();
 681             tcg_gen_add_i32(addr, REG(B7_4), REG(0));
 682             tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx);
 683             tcg_temp_free(addr);
 684         }
 685         return;
 686     case 0x6008:                /* swap.b Rm,Rn */
 687         {
 688             TCGv highw, high, low;
 689             highw = tcg_temp_new();
 690             tcg_gen_andi_i32(highw, REG(B7_4), 0xffff0000);
 691             high = tcg_temp_new();
 692             tcg_gen_ext8u_i32(high, REG(B7_4));
 693             tcg_gen_shli_i32(high, high, 8);
 694             low = tcg_temp_new();
 695             tcg_gen_shri_i32(low, REG(B7_4), 8);
 696             tcg_gen_ext8u_i32(low, low);
 697             tcg_gen_or_i32(REG(B11_8), high, low);
 698             tcg_gen_or_i32(REG(B11_8), REG(B11_8), highw);
 699             tcg_temp_free(low);
 700             tcg_temp_free(high);
 701         }
 702         return;
 703     case 0x6009:                /* swap.w Rm,Rn */
 704         {
 705             TCGv high, low;
 706             high = tcg_temp_new();
 707             tcg_gen_ext16u_i32(high, REG(B7_4));
 708             tcg_gen_shli_i32(high, high, 16);
 709             low = tcg_temp_new();
 710             tcg_gen_shri_i32(low, REG(B7_4), 16);
 711             tcg_gen_ext16u_i32(low, low);
 712             tcg_gen_or_i32(REG(B11_8), high, low);
 713             tcg_temp_free(low);
 714             tcg_temp_free(high);
 715         }
 716         return;
 717     case 0x200d:                /* xtrct Rm,Rn */
 718         {
 719             TCGv high, low;
 720             high = tcg_temp_new();
 721             tcg_gen_ext16u_i32(high, REG(B7_4));
 722             tcg_gen_shli_i32(high, high, 16);
 723             low = tcg_temp_new();
 724             tcg_gen_shri_i32(low, REG(B11_8), 16);
 725             tcg_gen_ext16u_i32(low, low);
 726             tcg_gen_or_i32(REG(B11_8), high, low);
 727             tcg_temp_free(low);
 728             tcg_temp_free(high);
 729         }
 730         return;
 731     case 0x300c:                /* add Rm,Rn */
 732         tcg_gen_add_i32(REG(B11_8), REG(B11_8), REG(B7_4));
 733         return;
 734     case 0x300e:                /* addc Rm,Rn */
 735         gen_helper_addc(REG(B11_8), REG(B7_4), REG(B11_8));
 736         return;
 737     case 0x300f:                /* addv Rm,Rn */
 738         gen_helper_addv(REG(B11_8), REG(B7_4), REG(B11_8));
 739         return;
 740     case 0x2009:                /* and Rm,Rn */
 741         tcg_gen_and_i32(REG(B11_8), REG(B11_8), REG(B7_4));
 742         return;
 743     case 0x3000:                /* cmp/eq Rm,Rn */
 744         gen_cmp(TCG_COND_EQ, REG(B7_4), REG(B11_8));
 745         return;
 746     case 0x3003:                /* cmp/ge Rm,Rn */
 747         gen_cmp(TCG_COND_GE, REG(B7_4), REG(B11_8));
 748         return;
 749     case 0x3007:                /* cmp/gt Rm,Rn */
 750         gen_cmp(TCG_COND_GT, REG(B7_4), REG(B11_8));
 751         return;
 752     case 0x3006:                /* cmp/hi Rm,Rn */
 753         gen_cmp(TCG_COND_GTU, REG(B7_4), REG(B11_8));
 754         return;
 755     case 0x3002:                /* cmp/hs Rm,Rn */
 756         gen_cmp(TCG_COND_GEU, REG(B7_4), REG(B11_8));
 757         return;
 758     case 0x200c:                /* cmp/str Rm,Rn */
 759         {
 760             int label1 = gen_new_label();
 761             int label2 = gen_new_label();
 762             TCGv cmp1 = tcg_temp_local_new(TCG_TYPE_I32);
 763             TCGv cmp2 = tcg_temp_local_new(TCG_TYPE_I32);
 764             tcg_gen_xor_i32(cmp1, REG(B7_4), REG(B11_8));
 765             tcg_gen_andi_i32(cmp2, cmp1, 0xff000000);
 766             tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);
 767             tcg_gen_andi_i32(cmp2, cmp1, 0x00ff0000);
 768             tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);
 769             tcg_gen_andi_i32(cmp2, cmp1, 0x0000ff00);
 770             tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);
 771             tcg_gen_andi_i32(cmp2, cmp1, 0x000000ff);
 772             tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);
 773             tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
 774             tcg_gen_br(label2);
 775             gen_set_label(label1);
 776             tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_T);
 777             gen_set_label(label2);
 778             tcg_temp_free(cmp2);
 779             tcg_temp_free(cmp1);
 780         }
 781         return;
 782     case 0x2007:                /* div0s Rm,Rn */
 783         {
 784             gen_copy_bit_i32(cpu_sr, 8, REG(B11_8), 31);        /* SR_Q */
 785             gen_copy_bit_i32(cpu_sr, 9, REG(B7_4), 31);         /* SR_M */
 786             TCGv val = tcg_temp_new();
 787             tcg_gen_xor_i32(val, REG(B7_4), REG(B11_8));
 788             gen_copy_bit_i32(cpu_sr, 0, val, 31);               /* SR_T */
 789             tcg_temp_free(val);
 790         }
 791         return;
 792     case 0x3004:                /* div1 Rm,Rn */
 793         gen_helper_div1(REG(B11_8), REG(B7_4), REG(B11_8));
 794         return;
 795     case 0x300d:                /* dmuls.l Rm,Rn */
 796         {
 797             TCGv_i64 tmp1 = tcg_temp_new_i64();
 798             TCGv_i64 tmp2 = tcg_temp_new_i64();
 799
 800             tcg_gen_ext_i32_i64(tmp1, REG(B7_4));
 801             tcg_gen_ext_i32_i64(tmp2, REG(B11_8));
 802             tcg_gen_mul_i64(tmp1, tmp1, tmp2);
 803             tcg_gen_trunc_i64_i32(cpu_macl, tmp1);
 804             tcg_gen_shri_i64(tmp1, tmp1, 32);
 805             tcg_gen_trunc_i64_i32(cpu_mach, tmp1);
 806
 807             tcg_temp_free_i64(tmp2);
 808             tcg_temp_free_i64(tmp1);
 809         }
 810         return;
 811     case 0x3005:                /* dmulu.l Rm,Rn */
 812         {
 813             TCGv_i64 tmp1 = tcg_temp_new_i64();
 814             TCGv_i64 tmp2 = tcg_temp_new_i64();
 815
 816             tcg_gen_extu_i32_i64(tmp1, REG(B7_4));
 817             tcg_gen_extu_i32_i64(tmp2, REG(B11_8));
 818             tcg_gen_mul_i64(tmp1, tmp1, tmp2);
 819             tcg_gen_trunc_i64_i32(cpu_macl, tmp1);
 820             tcg_gen_shri_i64(tmp1, tmp1, 32);
 821             tcg_gen_trunc_i64_i32(cpu_mach, tmp1);
 822
 823             tcg_temp_free_i64(tmp2);
 824             tcg_temp_free_i64(tmp1);
 825         }
 826         return;
 827     case 0x600e:                /* exts.b Rm,Rn */
 828         tcg_gen_ext8s_i32(REG(B11_8), REG(B7_4));
 829         return;
 830     case 0x600f:                /* exts.w Rm,Rn */
 831         tcg_gen_ext16s_i32(REG(B11_8), REG(B7_4));
 832         return;
 833     case 0x600c:                /* extu.b Rm,Rn */
 834         tcg_gen_ext8u_i32(REG(B11_8), REG(B7_4));
 835         return;
 836     case 0x600d:                /* extu.w Rm,Rn */
 837         tcg_gen_ext16u_i32(REG(B11_8), REG(B7_4));
 838         return;
 839     case 0x000f:                /* mac.l @Rm+,@Rn+ */
 840         {
 841             TCGv arg0, arg1;
 842             arg0 = tcg_temp_new();
 843             tcg_gen_qemu_ld32s(arg0, REG(B7_4), ctx->memidx);
 844             arg1 = tcg_temp_new();
 845             tcg_gen_qemu_ld32s(arg1, REG(B11_8), ctx->memidx);
 846             gen_helper_macl(arg0, arg1);
 847             tcg_temp_free(arg1);
 848             tcg_temp_free(arg0);
 849             tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
 850             tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
 851         }
 852         return;
 853     case 0x400f:                /* mac.w @Rm+,@Rn+ */
 854         {
 855             TCGv arg0, arg1;
 856             arg0 = tcg_temp_new();
 857             tcg_gen_qemu_ld32s(arg0, REG(B7_4), ctx->memidx);
 858             arg1 = tcg_temp_new();
 859             tcg_gen_qemu_ld32s(arg1, REG(B11_8), ctx->memidx);
 860             gen_helper_macw(arg0, arg1);
 861             tcg_temp_free(arg1);
 862             tcg_temp_free(arg0);
 863             tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 2);
 864             tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2);
 865         }
 866         return;
 867     case 0x0007:                /* mul.l Rm,Rn */
 868         tcg_gen_mul_i32(cpu_macl, REG(B7_4), REG(B11_8));
 869         return;
 870     case 0x200f:                /* muls.w Rm,Rn */
 871         {
 872             TCGv arg0, arg1;
 873             arg0 = tcg_temp_new();
 874             tcg_gen_ext16s_i32(arg0, REG(B7_4));
 875             arg1 = tcg_temp_new();
 876             tcg_gen_ext16s_i32(arg1, REG(B11_8));
 877             tcg_gen_mul_i32(cpu_macl, arg0, arg1);
 878             tcg_temp_free(arg1);
 879             tcg_temp_free(arg0);
 880         }
 881         return;
 882     case 0x200e:                /* mulu.w Rm,Rn */
 883         {
 884             TCGv arg0, arg1;
 885             arg0 = tcg_temp_new();
 886             tcg_gen_ext16u_i32(arg0, REG(B7_4));
 887             arg1 = tcg_temp_new();
 888             tcg_gen_ext16u_i32(arg1, REG(B11_8));
 889             tcg_gen_mul_i32(cpu_macl, arg0, arg1);
 890             tcg_temp_free(arg1);
 891             tcg_temp_free(arg0);
 892         }
 893         return;
 894     case 0x600b:                /* neg Rm,Rn */
 895         tcg_gen_neg_i32(REG(B11_8), REG(B7_4));
 896         return;
 897     case 0x600a:                /* negc Rm,Rn */
 898         gen_helper_negc(REG(B11_8), REG(B7_4));
 899         return;
 900     case 0x6007:                /* not Rm,Rn */
 901         tcg_gen_not_i32(REG(B11_8), REG(B7_4));
 902         return;
 903     case 0x200b:                /* or Rm,Rn */
 904         tcg_gen_or_i32(REG(B11_8), REG(B11_8), REG(B7_4));
 905         return;
 906     case 0x400c:                /* shad Rm,Rn */
 907         {
 908             int label1 = gen_new_label();
 909             int label2 = gen_new_label();
 910             int label3 = gen_new_label();
 911             int label4 = gen_new_label();
 912             TCGv shift = tcg_temp_local_new(TCG_TYPE_I32);
 913             tcg_gen_brcondi_i32(TCG_COND_LT, REG(B7_4), 0, label1);
 914             /* Rm positive, shift to the left */
 915             tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
 916             tcg_gen_shl_i32(REG(B11_8), REG(B11_8), shift);
 917             tcg_gen_br(label4);
 918             /* Rm negative, shift to the right */
 919             gen_set_label(label1);
 920             tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
 921             tcg_gen_brcondi_i32(TCG_COND_EQ, shift, 0, label2);
 922             tcg_gen_not_i32(shift, REG(B7_4));
 923             tcg_gen_andi_i32(shift, shift, 0x1f);
 924             tcg_gen_addi_i32(shift, shift, 1);
 925             tcg_gen_sar_i32(REG(B11_8), REG(B11_8), shift);
 926             tcg_gen_br(label4);
 927             /* Rm = -32 */
 928             gen_set_label(label2);
 929             tcg_gen_brcondi_i32(TCG_COND_LT, REG(B11_8), 0, label3);
 930             tcg_gen_movi_i32(REG(B11_8), 0);
 931             tcg_gen_br(label4);
 932             gen_set_label(label3);
 933             tcg_gen_movi_i32(REG(B11_8), 0xffffffff);
 934             gen_set_label(label4);
 935             tcg_temp_free(shift);
 936         }
 937         return;
 938     case 0x400d:                /* shld Rm,Rn */
 939         {
 940             int label1 = gen_new_label();
 941             int label2 = gen_new_label();
 942             int label3 = gen_new_label();
 943             TCGv shift = tcg_temp_local_new(TCG_TYPE_I32);
 944             tcg_gen_brcondi_i32(TCG_COND_LT, REG(B7_4), 0, label1);
 945             /* Rm positive, shift to the left */
 946             tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
 947             tcg_gen_shl_i32(REG(B11_8), REG(B11_8), shift);
 948             tcg_gen_br(label3);
 949             /* Rm negative, shift to the right */
 950             gen_set_label(label1);
 951             tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
 952             tcg_gen_brcondi_i32(TCG_COND_EQ, shift, 0, label2);
 953             tcg_gen_not_i32(shift, REG(B7_4));
 954             tcg_gen_andi_i32(shift, shift, 0x1f);
 955             tcg_gen_addi_i32(shift, shift, 1);
 956             tcg_gen_shr_i32(REG(B11_8), REG(B11_8), shift);
 957             tcg_gen_br(label3);
 958             /* Rm = -32 */
 959             gen_set_label(label2);
 960             tcg_gen_movi_i32(REG(B11_8), 0);
 961             gen_set_label(label3);
 962             tcg_temp_free(shift);
 963         }
 964         return;
 965     case 0x3008:                /* sub Rm,Rn */
 966         tcg_gen_sub_i32(REG(B11_8), REG(B11_8), REG(B7_4));
 967         return;
 968     case 0x300a:                /* subc Rm,Rn */
 969         gen_helper_subc(REG(B11_8), REG(B7_4), REG(B11_8));
 970         return;
 971     case 0x300b:                /* subv Rm,Rn */
 972         gen_helper_subv(REG(B11_8), REG(B7_4), REG(B11_8));
 973         return;
 974     case 0x2008:                /* tst Rm,Rn */
 975         {
 976             TCGv val = tcg_temp_new();
 977             tcg_gen_and_i32(val, REG(B7_4), REG(B11_8));
 978             gen_cmp_imm(TCG_COND_EQ, val, 0);
 979             tcg_temp_free(val);
 980         }
 981         return;
 982     case 0x200a:                /* xor Rm,Rn */
 983         tcg_gen_xor_i32(REG(B11_8), REG(B11_8), REG(B7_4));
 984         return;
 985     case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */
 986         if (ctx->fpscr & FPSCR_SZ) {
 987             TCGv_i64 fp = tcg_temp_new_i64();
 988             gen_load_fpr64(fp, XREG(B7_4));
 989             gen_store_fpr64(fp, XREG(B11_8));
 990             tcg_temp_free_i64(fp);
 991         } else {
 992             TCGv_i32 fp = tcg_temp_new_i32();
 993             gen_load_fpr32(fp, FREG(B7_4));
 994             gen_store_fpr32(fp, FREG(B11_8));
 995             tcg_temp_free_i32(fp);
 996         }
 997         return;
 998     case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
 999         if (ctx->fpscr & FPSCR_SZ) {
1000             TCGv_i64 fp = tcg_temp_new_i64();
1001             gen_load_fpr64(fp, XREG(B7_4));
1002             tcg_gen_qemu_st64(fp, REG(B11_8), ctx->memidx);
1003             tcg_temp_free_i64(fp);
1004         } else {
1005             TCGv_i32 fp = tcg_temp_new_i32();
1006             gen_load_fpr32(fp, FREG(B7_4));
1007             tcg_gen_qemu_st32(fp, REG(B11_8), ctx->memidx);
1008             tcg_temp_free_i32(fp);
1009         }
1010         return;
1011     case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
1012         if (ctx->fpscr & FPSCR_SZ) {
1013             TCGv_i64 fp = tcg_temp_new_i64();
1014             tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx);
1015             gen_store_fpr64(fp, XREG(B11_8));
1016             tcg_temp_free_i64(fp);
1017         } else {
1018             TCGv_i32 fp = tcg_temp_new_i32();
1019             tcg_gen_qemu_ld32u(fp, REG(B7_4), ctx->memidx);
1020             gen_store_fpr32(fp, FREG(B11_8));
1021             tcg_temp_free_i32(fp);
1022         }
1023         return;
1024     case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
1025         if (ctx->fpscr & FPSCR_SZ) {
1026             TCGv_i64 fp = tcg_temp_new_i64();
1027             tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx);
1028             gen_store_fpr64(fp, XREG(B11_8));
1029             tcg_temp_free_i64(fp);
1030             tcg_gen_addi_i32(REG(B7_4),REG(B7_4), 8);
1031         } else {
1032             TCGv_i32 fp = tcg_temp_new_i32();
1033             tcg_gen_qemu_ld32u(fp, REG(B7_4), ctx->memidx);
1034             gen_store_fpr32(fp, FREG(B11_8));
1035             tcg_temp_free_i32(fp);
1036             tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
1037         }
1038         return;
1039     case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */
1040         if (ctx->fpscr & FPSCR_SZ) {
1041             TCGv addr;
1042             TCGv_i64 fp;
1043             addr = tcg_temp_new();
1044             tcg_gen_subi_i32(addr, REG(B11_8), 8);
1045             fp = tcg_temp_new_i64();
1046             gen_load_fpr64(fp, XREG(B7_4));
1047             tcg_gen_qemu_st64(fp, addr, ctx->memidx);
1048             tcg_temp_free_i64(fp);
1049             tcg_temp_free(addr);
1050             tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 8);
1051         } else {
1052             TCGv addr;
1053             TCGv_i32 fp;
1054             addr = tcg_temp_new_i32();
1055             tcg_gen_subi_i32(addr, REG(B11_8), 4);
1056             fp = tcg_temp_new_i32();
1057             gen_load_fpr32(fp, FREG(B7_4));
1058             tcg_gen_qemu_st32(fp, addr, ctx->memidx);
1059             tcg_temp_free_i32(fp);
1060             tcg_temp_free(addr);
1061             tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
1062         }
1063         return;
1064     case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */
1065         {
1066             TCGv addr = tcg_temp_new_i32();
1067             tcg_gen_add_i32(addr, REG(B7_4), REG(0));
1068             if (ctx->fpscr & FPSCR_SZ) {
1069                 TCGv_i64 fp = tcg_temp_new_i64();
1070                 tcg_gen_qemu_ld64(fp, addr, ctx->memidx);
1071                 gen_store_fpr64(fp, XREG(B11_8));
1072                 tcg_temp_free_i64(fp);
1073             } else {
1074                 TCGv_i32 fp = tcg_temp_new_i32();
1075                 tcg_gen_qemu_ld32u(fp, addr, ctx->memidx);
1076                 gen_store_fpr32(fp, FREG(B11_8));
1077                 tcg_temp_free_i32(fp);
1078             }
1079             tcg_temp_free(addr);
1080         }
1081         return;
1082     case 0xf007: /* fmov {F,D,X}Rn,@(R0,Rn) - FPSCR: Nothing */
1083         {
1084             TCGv addr = tcg_temp_new();
1085             tcg_gen_add_i32(addr, REG(B11_8), REG(0));
1086             if (ctx->fpscr & FPSCR_SZ) {
1087                 TCGv_i64 fp = tcg_temp_new_i64();
1088                 gen_load_fpr64(fp, XREG(B7_4));
1089                 tcg_gen_qemu_st64(fp, addr, ctx->memidx);
1090                 tcg_temp_free_i64(fp);
1091             } else {
1092                 TCGv_i32 fp = tcg_temp_new_i32();
1093                 gen_load_fpr32(fp, FREG(B7_4));
1094                 tcg_gen_qemu_st32(fp, addr, ctx->memidx);
1095                 tcg_temp_free_i32(fp);
1096             }
1097             tcg_temp_free(addr);
1098         }
1099         return;
1100     case 0xf000: /* fadd Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
1101     case 0xf001: /* fsub Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
1102     case 0xf002: /* fmul Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
1103     case 0xf003: /* fdiv Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */
1104     case 0xf004: /* fcmp/eq Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
1105     case 0xf005: /* fcmp/gt Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
1106         {
1107             if (ctx->fpscr & FPSCR_PR) {
1108                 TCGv_i64 fp0, fp1;
1109
1110                 if (ctx->opcode & 0x0110)
1111                     break; /* illegal instruction */
1112                 fp0 = tcg_temp_new_i64();
1113                 fp1 = tcg_temp_new_i64();
1114                 gen_load_fpr64(fp0, DREG(B11_8));
1115                 gen_load_fpr64(fp1, DREG(B7_4));
1116                 switch (ctx->opcode & 0xf00f) {
1117                 case 0xf000:            /* fadd Rm,Rn */
1118                     gen_helper_fadd_DT(fp0, fp0, fp1);
1119                     break;
1120                 case 0xf001:            /* fsub Rm,Rn */
1121                     gen_helper_fsub_DT(fp0, fp0, fp1);
1122                     break;
1123                 case 0xf002:            /* fmul Rm,Rn */
1124                     gen_helper_fmul_DT(fp0, fp0, fp1);
1125                     break;
1126                 case 0xf003:            /* fdiv Rm,Rn */
1127                     gen_helper_fdiv_DT(fp0, fp0, fp1);
1128                     break;
1129                 case 0xf004:            /* fcmp/eq Rm,Rn */
1130                     gen_helper_fcmp_eq_DT(fp0, fp1);
1131                     return;
1132                 case 0xf005:            /* fcmp/gt Rm,Rn */
1133                     gen_helper_fcmp_gt_DT(fp0, fp1);
1134                     return;
1135                 }
1136                 gen_store_fpr64(fp0, DREG(B11_8));
1137                 tcg_temp_free_i64(fp0);
1138                 tcg_temp_free_i64(fp1);
1139             } else {
1140                 TCGv_i32 fp0, fp1;
1141
1142                 fp0 = tcg_temp_new_i32();
1143                 fp1 = tcg_temp_new_i32();
1144                 gen_load_fpr32(fp0, FREG(B11_8));
1145                 gen_load_fpr32(fp1, FREG(B7_4));
1146
1147                 switch (ctx->opcode & 0xf00f) {
1148                 case 0xf000:            /* fadd Rm,Rn */
1149                     gen_helper_fadd_FT(fp0, fp0, fp1);
1150                     break;
1151                 case 0xf001:            /* fsub Rm,Rn */
1152                     gen_helper_fsub_FT(fp0, fp0, fp1);
1153                     break;
1154                 case 0xf002:            /* fmul Rm,Rn */
1155                     gen_helper_fmul_FT(fp0, fp0, fp1);
1156                     break;
1157                 case 0xf003:            /* fdiv Rm,Rn */
1158                     gen_helper_fdiv_FT(fp0, fp0, fp1);
1159                     break;
1160                 case 0xf004:            /* fcmp/eq Rm,Rn */
1161                     gen_helper_fcmp_eq_FT(fp0, fp1);
1162                     return;
1163                 case 0xf005:            /* fcmp/gt Rm,Rn */
1164                     gen_helper_fcmp_gt_FT(fp0, fp1);
1165                     return;
1166                 }
1167                 gen_store_fpr32(fp0, FREG(B11_8));
1168                 tcg_temp_free_i32(fp0);
1169                 tcg_temp_free_i32(fp1);
1170             }
1171         }
1172         return;
1173     }
1174
1175     switch (ctx->opcode & 0xff00) {
1176     case 0xc900:                /* and #imm,R0 */
1177         tcg_gen_andi_i32(REG(0), REG(0), B7_0);
1178         return;
1179     case 0xcd00:                /* and.b #imm,@(R0,GBR) */
1180         {
1181             TCGv addr, val;
1182             addr = tcg_temp_new();
1183             tcg_gen_add_i32(addr, REG(0), cpu_gbr);
1184             val = tcg_temp_new();
1185             tcg_gen_qemu_ld8u(val, addr, ctx->memidx);
1186             tcg_gen_andi_i32(val, val, B7_0);
1187             tcg_gen_qemu_st8(val, addr, ctx->memidx);
1188             tcg_temp_free(val);
1189             tcg_temp_free(addr);
1190         }
1191         return;
1192     case 0x8b00:                /* bf label */
1193         CHECK_NOT_DELAY_SLOT
1194             gen_conditional_jump(ctx, ctx->pc + 2,
1195                                  ctx->pc + 4 + B7_0s * 2);
1196         ctx->bstate = BS_BRANCH;
1197         return;
1198     case 0x8f00:                /* bf/s label */
1199         CHECK_NOT_DELAY_SLOT
1200         gen_branch_slot(ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2, 0);
1201         ctx->flags |= DELAY_SLOT_CONDITIONAL;
1202         return;
1203     case 0x8900:                /* bt label */
1204         CHECK_NOT_DELAY_SLOT
1205             gen_conditional_jump(ctx, ctx->pc + 4 + B7_0s * 2,
1206                                  ctx->pc + 2);
1207         ctx->bstate = BS_BRANCH;
1208         return;
1209     case 0x8d00:                /* bt/s label */
1210         CHECK_NOT_DELAY_SLOT
1211         gen_branch_slot(ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2, 1);
1212         ctx->flags |= DELAY_SLOT_CONDITIONAL;
1213         return;
1214     case 0x8800:                /* cmp/eq #imm,R0 */
1215         gen_cmp_imm(TCG_COND_EQ, REG(0), B7_0s);
1216         return;
1217     case 0xc400:                /* mov.b @(disp,GBR),R0 */
1218         {
1219             TCGv addr = tcg_temp_new();
1220             tcg_gen_addi_i32(addr, cpu_gbr, B7_0);
1221             tcg_gen_qemu_ld8s(REG(0), addr, ctx->memidx);
1222             tcg_temp_free(addr);
1223         }
1224         return;
1225     case 0xc500:                /* mov.w @(disp,GBR),R0 */
1226         {
1227             TCGv addr = tcg_temp_new();
1228             tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 2);
1229             tcg_gen_qemu_ld16s(REG(0), addr, ctx->memidx);
1230             tcg_temp_free(addr);
1231         }
1232         return;
1233     case 0xc600:                /* mov.l @(disp,GBR),R0 */
1234         {
1235             TCGv addr = tcg_temp_new();
1236             tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 4);
1237             tcg_gen_qemu_ld32s(REG(0), addr, ctx->memidx);
1238             tcg_temp_free(addr);
1239         }
1240         return;
1241     case 0xc000:                /* mov.b R0,@(disp,GBR) */
1242         {
1243             TCGv addr = tcg_temp_new();
1244             tcg_gen_addi_i32(addr, cpu_gbr, B7_0);
1245             tcg_gen_qemu_st8(REG(0), addr, ctx->memidx);
1246             tcg_temp_free(addr);
1247         }
1248         return;
1249     case 0xc100:                /* mov.w R0,@(disp,GBR) */
1250         {
1251             TCGv addr = tcg_temp_new();
1252             tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 2);
1253             tcg_gen_qemu_st16(REG(0), addr, ctx->memidx);
1254             tcg_temp_free(addr);
1255         }
1256         return;
1257     case 0xc200:                /* mov.l R0,@(disp,GBR) */
1258         {
1259             TCGv addr = tcg_temp_new();
1260             tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 4);
1261             tcg_gen_qemu_st32(REG(0), addr, ctx->memidx);
1262             tcg_temp_free(addr);
1263         }
1264         return;
1265     case 0x8000:                /* mov.b R0,@(disp,Rn) */
1266         {
1267             TCGv addr = tcg_temp_new();
1268             tcg_gen_addi_i32(addr, REG(B7_4), B3_0);
1269             tcg_gen_qemu_st8(REG(0), addr, ctx->memidx);
1270             tcg_temp_free(addr);
1271         }
1272         return;
1273     case 0x8100:                /* mov.w R0,@(disp,Rn) */
1274         {
1275             TCGv addr = tcg_temp_new();
1276             tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2);
1277             tcg_gen_qemu_st16(REG(0), addr, ctx->memidx);
1278             tcg_temp_free(addr);
1279         }
1280         return;
1281     case 0x8400:                /* mov.b @(disp,Rn),R0 */
1282         {
1283             TCGv addr = tcg_temp_new();
1284             tcg_gen_addi_i32(addr, REG(B7_4), B3_0);
1285             tcg_gen_qemu_ld8s(REG(0), addr, ctx->memidx);
1286             tcg_temp_free(addr);
1287         }
1288         return;
1289     case 0x8500:                /* mov.w @(disp,Rn),R0 */
1290         {
1291             TCGv addr = tcg_temp_new();
1292             tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2);
1293             tcg_gen_qemu_ld16s(REG(0), addr, ctx->memidx);
1294             tcg_temp_free(addr);
1295         }
1296         return;
1297     case 0xc700:                /* mova @(disp,PC),R0 */
1298         tcg_gen_movi_i32(REG(0), ((ctx->pc & 0xfffffffc) + 4 + B7_0 * 4) & ~3);
1299         return;
1300     case 0xcb00:                /* or #imm,R0 */
1301         tcg_gen_ori_i32(REG(0), REG(0), B7_0);
1302         return;
1303     case 0xcf00:                /* or.b #imm,@(R0,GBR) */
1304         {
1305             TCGv addr, val;
1306             addr = tcg_temp_new();
1307             tcg_gen_add_i32(addr, REG(0), cpu_gbr);
1308             val = tcg_temp_new();
1309             tcg_gen_qemu_ld8u(val, addr, ctx->memidx);
1310             tcg_gen_ori_i32(val, val, B7_0);
1311             tcg_gen_qemu_st8(val, addr, ctx->memidx);
1312             tcg_temp_free(val);
1313             tcg_temp_free(addr);
1314         }
1315         return;
1316     case 0xc300:                /* trapa #imm */
1317         {
1318             TCGv imm;
1319             CHECK_NOT_DELAY_SLOT
1320             tcg_gen_movi_i32(cpu_pc, ctx->pc);
1321             imm = tcg_const_i32(B7_0);
1322             gen_helper_trapa(imm);
1323             tcg_temp_free(imm);
1324             ctx->bstate = BS_BRANCH;
1325         }
1326         return;
1327     case 0xc800:                /* tst #imm,R0 */
1328         {
1329             TCGv val = tcg_temp_new();
1330             tcg_gen_andi_i32(val, REG(0), B7_0);
1331             gen_cmp_imm(TCG_COND_EQ, val, 0);
1332             tcg_temp_free(val);
1333         }
1334         return;
1335     case 0xcc00:                /* tst.b #imm,@(R0,GBR) */
1336         {
1337             TCGv val = tcg_temp_new();
1338             tcg_gen_add_i32(val, REG(0), cpu_gbr);
1339             tcg_gen_qemu_ld8u(val, val, ctx->memidx);
1340             tcg_gen_andi_i32(val, val, B7_0);
1341             gen_cmp_imm(TCG_COND_EQ, val, 0);
1342             tcg_temp_free(val);
1343         }
1344         return;
1345     case 0xca00:                /* xor #imm,R0 */
1346         tcg_gen_xori_i32(REG(0), REG(0), B7_0);
1347         return;
1348     case 0xce00:                /* xor.b #imm,@(R0,GBR) */
1349         {
1350             TCGv addr, val;
1351             addr = tcg_temp_new();
1352             tcg_gen_add_i32(addr, REG(0), cpu_gbr);
1353             val = tcg_temp_new();
1354             tcg_gen_qemu_ld8u(val, addr, ctx->memidx);
1355             tcg_gen_xori_i32(val, val, B7_0);
1356             tcg_gen_qemu_st8(val, addr, ctx->memidx);
1357             tcg_temp_free(val);
1358             tcg_temp_free(addr);
1359         }
1360         return;
1361     }
1362
1363     switch (ctx->opcode & 0xf08f) {
1364     case 0x408e:                /* ldc Rm,Rn_BANK */
1365         CHECK_PRIVILEGED
1366         tcg_gen_mov_i32(ALTREG(B6_4), REG(B11_8));
1367         return;
1368     case 0x4087:                /* ldc.l @Rm+,Rn_BANK */
1369         CHECK_PRIVILEGED
1370         tcg_gen_qemu_ld32s(ALTREG(B6_4), REG(B11_8), ctx->memidx);
1371         tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
1372         return;
1373     case 0x0082:                /* stc Rm_BANK,Rn */
1374         CHECK_PRIVILEGED
1375         tcg_gen_mov_i32(REG(B11_8), ALTREG(B6_4));
1376         return;
1377     case 0x4083:                /* stc.l Rm_BANK,@-Rn */
1378         CHECK_PRIVILEGED
1379         {
1380             TCGv addr = tcg_temp_new();
1381             tcg_gen_subi_i32(addr, REG(B11_8), 4);
1382             tcg_gen_qemu_st32(ALTREG(B6_4), addr, ctx->memidx);
1383             tcg_temp_free(addr);
1384             tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
1385         }
1386         return;
1387     }
1388
1389     switch (ctx->opcode & 0xf0ff) {
1390     case 0x0023:                /* braf Rn */
1391         CHECK_NOT_DELAY_SLOT
1392         tcg_gen_addi_i32(cpu_delayed_pc, REG(B11_8), ctx->pc + 4);
1393         ctx->flags |= DELAY_SLOT;
1394         ctx->delayed_pc = (uint32_t) - 1;
1395         return;
1396     case 0x0003:                /* bsrf Rn */
1397         CHECK_NOT_DELAY_SLOT
1398         tcg_gen_movi_i32(cpu_pr, ctx->pc + 4);
1399         tcg_gen_add_i32(cpu_delayed_pc, REG(B11_8), cpu_pr);
1400         ctx->flags |= DELAY_SLOT;
1401         ctx->delayed_pc = (uint32_t) - 1;
1402         return;
1403     case 0x4015:                /* cmp/pl Rn */
1404         gen_cmp_imm(TCG_COND_GT, REG(B11_8), 0);
1405         return;
1406     case 0x4011:                /* cmp/pz Rn */
1407         gen_cmp_imm(TCG_COND_GE, REG(B11_8), 0);
1408         return;
1409     case 0x4010:                /* dt Rn */
1410         tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 1);
1411         gen_cmp_imm(TCG_COND_EQ, REG(B11_8), 0);
1412         return;
1413     case 0x402b:                /* jmp @Rn */
1414         CHECK_NOT_DELAY_SLOT
1415         tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8));
1416         ctx->flags |= DELAY_SLOT;
1417         ctx->delayed_pc = (uint32_t) - 1;
1418         return;
1419     case 0x400b:                /* jsr @Rn */
1420         CHECK_NOT_DELAY_SLOT
1421         tcg_gen_movi_i32(cpu_pr, ctx->pc + 4);
1422         tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8));
1423         ctx->flags |= DELAY_SLOT;
1424         ctx->delayed_pc = (uint32_t) - 1;
1425         return;
1426     case 0x400e:                /* ldc Rm,SR */
1427         CHECK_PRIVILEGED
1428         tcg_gen_andi_i32(cpu_sr, REG(B11_8), 0x700083f3);
1429         ctx->bstate = BS_STOP;
1430         return;
1431     case 0x4007:                /* ldc.l @Rm+,SR */
1432         CHECK_PRIVILEGED
1433         {
1434             TCGv val = tcg_temp_new();
1435             tcg_gen_qemu_ld32s(val, REG(B11_8), ctx->memidx);
1436             tcg_gen_andi_i32(cpu_sr, val, 0x700083f3);
1437             tcg_temp_free(val);
1438             tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
1439             ctx->bstate = BS_STOP;
1440         }
1441         return;
1442     case 0x0002:                /* stc SR,Rn */
1443         CHECK_PRIVILEGED
1444         tcg_gen_mov_i32(REG(B11_8), cpu_sr);
1445         return;
1446     case 0x4003:                /* stc SR,@-Rn */
1447         CHECK_PRIVILEGED
1448         {
1449             TCGv addr = tcg_temp_new();
1450             tcg_gen_subi_i32(addr, REG(B11_8), 4);
1451             tcg_gen_qemu_st32(cpu_sr, addr, ctx->memidx);
1452             tcg_temp_free(addr);
1453             tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
1454         }
1455         return;
1456 #define LDST(reg,ldnum,ldpnum,stnum,stpnum,prechk)              \
1457   case ldnum:                                                   \
1458     prechk                                                      \
1459     tcg_gen_mov_i32 (cpu_##reg, REG(B11_8));                    \
1460     return;                                                     \
1461   case ldpnum:                                                  \
1462     prechk                                                      \
1463     tcg_gen_qemu_ld32s (cpu_##reg, REG(B11_8), ctx->memidx);    \
1464     tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);                \
1465     return;                                                     \
1466   case stnum:                                                   \
1467     prechk                                                      \
1468     tcg_gen_mov_i32 (REG(B11_8), cpu_##reg);                    \
1469     return;                                                     \
1470   case stpnum:                                                  \
1471     prechk                                                      \
1472     {                                                           \
1473         TCGv addr = tcg_temp_new();                     \
1474         tcg_gen_subi_i32(addr, REG(B11_8), 4);                  \
1475         tcg_gen_qemu_st32 (cpu_##reg, addr, ctx->memidx);       \
1476         tcg_temp_free(addr);                                    \
1477         tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);            \
1478     }                                                           \
1479     return;
1480         LDST(gbr,  0x401e, 0x4017, 0x0012, 0x4013, {})
1481         LDST(vbr,  0x402e, 0x4027, 0x0022, 0x4023, CHECK_PRIVILEGED)
1482         LDST(ssr,  0x403e, 0x4037, 0x0032, 0x4033, CHECK_PRIVILEGED)
1483         LDST(spc,  0x404e, 0x4047, 0x0042, 0x4043, CHECK_PRIVILEGED)
1484         LDST(dbr,  0x40fa, 0x40f6, 0x00fa, 0x40f2, CHECK_PRIVILEGED)
1485         LDST(mach, 0x400a, 0x4006, 0x000a, 0x4002, {})
1486         LDST(macl, 0x401a, 0x4016, 0x001a, 0x4012, {})
1487         LDST(pr,   0x402a, 0x4026, 0x002a, 0x4022, {})
1488         LDST(fpul, 0x405a, 0x4056, 0x005a, 0x4052, {})
1489     case 0x406a:                /* lds Rm,FPSCR */
1490         gen_helper_ld_fpscr(REG(B11_8));
1491         ctx->bstate = BS_STOP;
1492         return;
1493     case 0x4066:                /* lds.l @Rm+,FPSCR */
1494         {
1495             TCGv addr = tcg_temp_new();
1496             tcg_gen_qemu_ld32s(addr, REG(B11_8), ctx->memidx);
1497             tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
1498             gen_helper_ld_fpscr(addr);
1499             tcg_temp_free(addr);
1500             ctx->bstate = BS_STOP;
1501         }
1502         return;
1503     case 0x006a:                /* sts FPSCR,Rn */
1504         tcg_gen_andi_i32(REG(B11_8), cpu_fpscr, 0x003fffff);
1505         return;
1506     case 0x4062:                /* sts FPSCR,@-Rn */
1507         {
1508             TCGv addr, val;
1509             val = tcg_temp_new();
1510             tcg_gen_andi_i32(val, cpu_fpscr, 0x003fffff);
1511             addr = tcg_temp_new();
1512             tcg_gen_subi_i32(addr, REG(B11_8), 4);
1513             tcg_gen_qemu_st32(val, addr, ctx->memidx);
1514             tcg_temp_free(addr);
1515             tcg_temp_free(val);
1516             tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
1517         }
1518         return;
1519     case 0x00c3:                /* movca.l R0,@Rm */
1520         tcg_gen_qemu_st32(REG(0), REG(B11_8), ctx->memidx);
1521         return;
1522     case 0x40a9:
1523         /* MOVUA.L @Rm,R0 (Rm) -> R0
1524            Load non-boundary-aligned data */
1525         tcg_gen_qemu_ld32u(REG(0), REG(B11_8), ctx->memidx);
1526         return;
1527     case 0x40e9:
1528         /* MOVUA.L @Rm+,R0   (Rm) -> R0, Rm + 4 -> Rm
1529            Load non-boundary-aligned data */
1530         tcg_gen_qemu_ld32u(REG(0), REG(B11_8), ctx->memidx);
1531         tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
1532         return;
1533     case 0x0029:                /* movt Rn */
1534         tcg_gen_andi_i32(REG(B11_8), cpu_sr, SR_T);
1535         return;
1536     case 0x0093:                /* ocbi @Rn */
1537         {
1538             TCGv dummy = tcg_temp_new();
1539             tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx);
1540             tcg_temp_free(dummy);
1541         }
1542         return;
1543     case 0x00a3:                /* ocbp @Rn */
1544         {
1545             TCGv dummy = tcg_temp_new();
1546             tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx);
1547             tcg_temp_free(dummy);
1548         }
1549         return;
1550     case 0x00b3:                /* ocbwb @Rn */
1551         {
1552             TCGv dummy = tcg_temp_new();
1553             tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx);
1554             tcg_temp_free(dummy);
1555         }
1556         return;
1557     case 0x0083:                /* pref @Rn */
1558         return;
1559     case 0x4024:                /* rotcl Rn */
1560         {
1561             TCGv tmp = tcg_temp_new();
1562             tcg_gen_mov_i32(tmp, cpu_sr);
1563             gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31);
1564             tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1);
1565             gen_copy_bit_i32(REG(B11_8), 0, tmp, 0);
1566             tcg_temp_free(tmp);
1567         }
1568         return;
1569     case 0x4025:                /* rotcr Rn */
1570         {
1571             TCGv tmp = tcg_temp_new();
1572             tcg_gen_mov_i32(tmp, cpu_sr);
1573             gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0);
1574             tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1);
1575             gen_copy_bit_i32(REG(B11_8), 31, tmp, 0);
1576             tcg_temp_free(tmp);
1577         }
1578         return;
1579     case 0x4004:                /* rotl Rn */
1580         gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31);
1581         tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1);
1582         gen_copy_bit_i32(REG(B11_8), 0, cpu_sr, 0);
1583         return;
1584     case 0x4005:                /* rotr Rn */
1585         gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0);
1586         tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1);
1587         gen_copy_bit_i32(REG(B11_8), 31, cpu_sr, 0);
1588         return;
1589     case 0x4000:                /* shll Rn */
1590     case 0x4020:                /* shal Rn */
1591         gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31);
1592         tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1);
1593         return;
1594     case 0x4021:                /* shar Rn */
1595         gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0);
1596         tcg_gen_sari_i32(REG(B11_8), REG(B11_8), 1);
1597         return;
1598     case 0x4001:                /* shlr Rn */
1599         gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0);
1600         tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1);
1601         return;
1602     case 0x4008:                /* shll2 Rn */
1603         tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 2);
1604         return;
1605     case 0x4018:                /* shll8 Rn */
1606         tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 8);
1607         return;
1608     case 0x4028:                /* shll16 Rn */
1609         tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 16);
1610         return;
1611     case 0x4009:                /* shlr2 Rn */
1612         tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 2);
1613         return;
1614     case 0x4019:                /* shlr8 Rn */
1615         tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 8);
1616         return;
1617     case 0x4029:                /* shlr16 Rn */
1618         tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 16);
1619         return;
1620     case 0x401b:                /* tas.b @Rn */
1621         {
1622             TCGv addr, val;
1623             addr = tcg_temp_local_new(TCG_TYPE_I32);
1624             tcg_gen_mov_i32(addr, REG(B11_8));
1625             val = tcg_temp_local_new(TCG_TYPE_I32);
1626             tcg_gen_qemu_ld8u(val, addr, ctx->memidx);
1627             gen_cmp_imm(TCG_COND_EQ, val, 0);
1628             tcg_gen_ori_i32(val, val, 0x80);
1629             tcg_gen_qemu_st8(val, addr, ctx->memidx);
1630             tcg_temp_free(val);
1631             tcg_temp_free(addr);
1632         }
1633         return;
1634     case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */
1635         {
1636             TCGv fp = tcg_temp_new();
1637             tcg_gen_mov_i32(fp, cpu_fpul);
1638             gen_store_fpr32(fp, FREG(B11_8));
1639             tcg_temp_free(fp);
1640         }
1641         return;
1642     case 0xf01d: /* flds FRm,FPUL - FPSCR: Nothing */
1643         {
1644             TCGv fp = tcg_temp_new();
1645             gen_load_fpr32(fp, FREG(B11_8));
1646             tcg_gen_mov_i32(cpu_fpul, fp);
1647             tcg_temp_free(fp);
1648         }
1649         return;
1650     case 0xf02d: /* float FPUL,FRn/DRn - FPSCR: R[PR,Enable.I]/W[Cause,Flag] */
1651         if (ctx->fpscr & FPSCR_PR) {
1652             TCGv_i64 fp;
1653             if (ctx->opcode & 0x0100)
1654                 break; /* illegal instruction */
1655             fp = tcg_temp_new_i64();
1656             gen_helper_float_DT(fp, cpu_fpul);
1657             gen_store_fpr64(fp, DREG(B11_8));
1658             tcg_temp_free_i64(fp);
1659         }
1660         else {
1661             TCGv_i32 fp = tcg_temp_new_i32();
1662             gen_helper_float_FT(fp, cpu_fpul);
1663             gen_store_fpr32(fp, FREG(B11_8));
1664             tcg_temp_free_i32(fp);
1665         }
1666         return;
1667     case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
1668         if (ctx->fpscr & FPSCR_PR) {
1669             TCGv_i64 fp;
1670             if (ctx->opcode & 0x0100)
1671                 break; /* illegal instruction */
1672             fp = tcg_temp_new_i64();
1673             gen_load_fpr64(fp, DREG(B11_8));
1674             gen_helper_ftrc_DT(cpu_fpul, fp);
1675             tcg_temp_free_i64(fp);
1676         }
1677         else {
1678             TCGv_i32 fp = tcg_temp_new_i32();
1679             gen_load_fpr32(fp, FREG(B11_8));
1680             gen_helper_ftrc_FT(cpu_fpul, fp);
1681             tcg_temp_free_i32(fp);
1682         }
1683         return;
1684     case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */
1685         {
1686             TCGv_i32 fp = tcg_temp_new_i32();
1687             gen_load_fpr32(fp, FREG(B11_8));
1688             gen_helper_fneg_T(fp, fp);
1689             gen_store_fpr32(fp, FREG(B11_8));
1690             tcg_temp_free_i32(fp);
1691         }
1692         return;
1693     case 0xf05d: /* fabs FRn/DRn */
1694         if (ctx->fpscr & FPSCR_PR) {
1695             if (ctx->opcode & 0x0100)
1696                 break; /* illegal instruction */
1697             TCGv_i64 fp = tcg_temp_new_i64();
1698             gen_load_fpr64(fp, DREG(B11_8));
1699             gen_helper_fabs_DT(fp, fp);
1700             gen_store_fpr64(fp, DREG(B11_8));
1701             tcg_temp_free_i64(fp);
1702         } else {
1703             TCGv_i32 fp = tcg_temp_new_i32();
1704             gen_load_fpr32(fp, FREG(B11_8));
1705             gen_helper_fabs_FT(fp, fp);
1706             gen_store_fpr32(fp, FREG(B11_8));
1707             tcg_temp_free_i32(fp);
1708         }
1709         return;
1710     case 0xf06d: /* fsqrt FRn */
1711         if (ctx->fpscr & FPSCR_PR) {
1712             if (ctx->opcode & 0x0100)
1713                 break; /* illegal instruction */
1714             TCGv_i64 fp = tcg_temp_new_i64();
1715             gen_load_fpr64(fp, DREG(B11_8));
1716             gen_helper_fsqrt_DT(fp, fp);
1717             gen_store_fpr64(fp, DREG(B11_8));
1718             tcg_temp_free_i64(fp);
1719         } else {
1720             TCGv_i32 fp = tcg_temp_new_i32();
1721             gen_load_fpr32(fp, FREG(B11_8));
1722             gen_helper_fsqrt_FT(fp, fp);
1723             gen_store_fpr32(fp, FREG(B11_8));
1724             tcg_temp_free_i32(fp);
1725         }
1726         return;
1727     case 0xf07d: /* fsrra FRn */
1728         break;
1729     case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */
1730         if (!(ctx->fpscr & FPSCR_PR)) {
1731             TCGv_i32 val = tcg_const_i32(0);
1732             gen_load_fpr32(val, FREG(B11_8));
1733             tcg_temp_free_i32(val);
1734             return;
1735         }
1736         break;
1737     case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */
1738         if (!(ctx->fpscr & FPSCR_PR)) {
1739             TCGv_i32 val = tcg_const_i32(0x3f800000);
1740             gen_load_fpr32(val, FREG(B11_8));
1741             tcg_temp_free_i32(val);
1742             return;
1743         }
1744         break;
1745     case 0xf0ad: /* fcnvsd FPUL,DRn */
1746         {
1747             TCGv_i64 fp = tcg_temp_new_i64();
1748             gen_helper_fcnvsd_FT_DT(fp, cpu_fpul);
1749             gen_store_fpr64(fp, DREG(B11_8));
1750             tcg_temp_free_i64(fp);
1751         }
1752         return;
1753     case 0xf0bd: /* fcnvds DRn,FPUL */
1754         {
1755             TCGv_i64 fp = tcg_temp_new_i64();
1756             gen_load_fpr64(fp, DREG(B11_8));
1757             gen_helper_fcnvds_DT_FT(cpu_fpul, fp);
1758             tcg_temp_free_i64(fp);
1759         }
1760         return;
1761     }
1762
1763     fprintf(stderr, "unknown instruction 0x%04x at pc 0x%08x\n",
1764             ctx->opcode, ctx->pc);
1765     gen_helper_raise_illegal_instruction();
1766     ctx->bstate = BS_EXCP;
1767 }
1768
1769 static void decode_opc(DisasContext * ctx)
1770 {
1771     uint32_t old_flags = ctx->flags;
1772
1773     _decode_opc(ctx);
1774
1775     if (old_flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
1776         if (ctx->flags & DELAY_SLOT_CLEARME) {
1777             gen_store_flags(0);
1778         } else {
1779             /* go out of the delay slot */
1780             uint32_t new_flags = ctx->flags;
1781             new_flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL);
1782             gen_store_flags(new_flags);
1783         }
1784         ctx->flags = 0;
1785         ctx->bstate = BS_BRANCH;
1786         if (old_flags & DELAY_SLOT_CONDITIONAL) {
1787             gen_delayed_conditional_jump(ctx);
1788         } else if (old_flags & DELAY_SLOT) {
1789             gen_jump(ctx);
1790         }
1791
1792     }
1793
1794     /* go into a delay slot */
1795     if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL))
1796         gen_store_flags(ctx->flags);
1797 }
1798
1799 static inline void
1800 gen_intermediate_code_internal(CPUState * env, TranslationBlock * tb,
1801                                int search_pc)
1802 {
1803     DisasContext ctx;
1804     target_ulong pc_start;
1805     static uint16_t *gen_opc_end;
1806     int i, ii;
1807     int num_insns;
1808     int max_insns;
1809
1810     pc_start = tb->pc;
1811     gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
1812     ctx.pc = pc_start;
1813     ctx.flags = (uint32_t)tb->flags;
1814     ctx.bstate = BS_NONE;
1815     ctx.sr = env->sr;
1816     ctx.fpscr = env->fpscr;
1817     ctx.memidx = (env->sr & SR_MD) ? 1 : 0;
1818     /* We don't know if the delayed pc came from a dynamic or static branch,
1819        so assume it is a dynamic branch.  */
1820     ctx.delayed_pc = -1; /* use delayed pc from env pointer */
1821     ctx.tb = tb;
1822     ctx.singlestep_enabled = env->singlestep_enabled;
1823
1824 #ifdef DEBUG_DISAS
1825     if (loglevel & CPU_LOG_TB_CPU) {
1826         fprintf(logfile,
1827                 "------------------------------------------------\n");
1828         cpu_dump_state(env, logfile, fprintf, 0);
1829     }
1830 #endif
1831
1832     ii = -1;
1833     num_insns = 0;
1834     max_insns = tb->cflags & CF_COUNT_MASK;
1835     if (max_insns == 0)
1836         max_insns = CF_COUNT_MASK;
1837     gen_icount_start();
1838     while (ctx.bstate == BS_NONE && gen_opc_ptr < gen_opc_end) {
1839         if (env->nb_breakpoints > 0) {
1840             for (i = 0; i < env->nb_breakpoints; i++) {
1841                 if (ctx.pc == env->breakpoints[i]) {
1842                     /* We have hit a breakpoint - make sure PC is up-to-date */
1843                     tcg_gen_movi_i32(cpu_pc, ctx.pc);
1844                     gen_helper_debug();
1845                     ctx.bstate = BS_EXCP;
1846                     break;
1847                 }
1848             }
1849         }
1850         if (search_pc) {
1851             i = gen_opc_ptr - gen_opc_buf;
1852             if (ii < i) {
1853                 ii++;
1854                 while (ii < i)
1855                     gen_opc_instr_start[ii++] = 0;
1856             }
1857             gen_opc_pc[ii] = ctx.pc;
1858             gen_opc_hflags[ii] = ctx.flags;
1859             gen_opc_instr_start[ii] = 1;
1860             gen_opc_icount[ii] = num_insns;
1861         }
1862         if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
1863             gen_io_start();
1864 #if 0
1865         fprintf(stderr, "Loading opcode at address 0x%08x\n", ctx.pc);
1866         fflush(stderr);
1867 #endif
1868         ctx.opcode = lduw_code(ctx.pc);
1869         decode_opc(&ctx);
1870         num_insns++;
1871         ctx.pc += 2;
1872         if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0)
1873             break;
1874         if (env->singlestep_enabled)
1875             break;
1876         if (num_insns >= max_insns)
1877             break;
1878 #ifdef SH4_SINGLE_STEP
1879         break;
1880 #endif
1881     }
1882     if (tb->cflags & CF_LAST_IO)
1883         gen_io_end();
1884     if (env->singlestep_enabled) {
1885         tcg_gen_movi_i32(cpu_pc, ctx.pc);
1886         gen_helper_debug();
1887     } else {
1888         switch (ctx.bstate) {
1889         case BS_STOP:
1890             /* gen_op_interrupt_restart(); */
1891             /* fall through */
1892         case BS_NONE:
1893             if (ctx.flags) {
1894                 gen_store_flags(ctx.flags | DELAY_SLOT_CLEARME);
1895             }
1896             gen_goto_tb(&ctx, 0, ctx.pc);
1897             break;
1898         case BS_EXCP:
1899             /* gen_op_interrupt_restart(); */
1900             tcg_gen_exit_tb(0);
1901             break;
1902         case BS_BRANCH:
1903         default:
1904             break;
1905         }
1906     }
1907
1908     gen_icount_end(tb, num_insns);
1909     *gen_opc_ptr = INDEX_op_end;
1910     if (search_pc) {
1911         i = gen_opc_ptr - gen_opc_buf;
1912         ii++;
1913         while (ii <= i)
1914             gen_opc_instr_start[ii++] = 0;
1915     } else {
1916         tb->size = ctx.pc - pc_start;
1917         tb->icount = num_insns;
1918     }
1919
1920 #ifdef DEBUG_DISAS
1921 #ifdef SH4_DEBUG_DISAS
1922     if (loglevel & CPU_LOG_TB_IN_ASM)
1923         fprintf(logfile, "\n");
1924 #endif
1925     if (loglevel & CPU_LOG_TB_IN_ASM) {
1926         fprintf(logfile, "IN:\n");      /* , lookup_symbol(pc_start)); */
1927         target_disas(logfile, pc_start, ctx.pc - pc_start, 0);
1928         fprintf(logfile, "\n");
1929     }
1930 #endif
1931 }
1932
1933 void gen_intermediate_code(CPUState * env, struct TranslationBlock *tb)
1934 {
1935     gen_intermediate_code_internal(env, tb, 0);
1936 }
1937
1938 void gen_intermediate_code_pc(CPUState * env, struct TranslationBlock *tb)
1939 {
1940     gen_intermediate_code_internal(env, tb, 1);
1941 }
1942
1943 void gen_pc_load(CPUState *env, TranslationBlock *tb,
1944                 unsigned long searched_pc, int pc_pos, void *puc)
1945 {
1946     env->pc = gen_opc_pc[pc_pos];
1947     env->flags = gen_opc_hflags[pc_pos];
1948 }