6 #if !defined(TARGET_SPARC64)
7 #define TARGET_LONG_BITS 32
8 #define TARGET_FPREGS 32
9 #define TARGET_PAGE_BITS 12 /* 4k */
11 #define TARGET_LONG_BITS 64
12 #define TARGET_FPREGS 64
13 #define TARGET_PAGE_BITS 13 /* 8k */
16 #define TARGET_PHYS_ADDR_BITS 64
20 #include "softfloat.h"
22 #define TARGET_HAS_ICE 1
24 #if !defined(TARGET_SPARC64)
25 #define ELF_MACHINE EM_SPARC
27 #define ELF_MACHINE EM_SPARCV9
30 /*#define EXCP_INTERRUPT 0x100*/
32 /* trap definitions */
33 #ifndef TARGET_SPARC64
34 #define TT_TFAULT 0x01
35 #define TT_ILL_INSN 0x02
36 #define TT_PRIV_INSN 0x03
37 #define TT_NFPU_INSN 0x04
38 #define TT_WIN_OVF 0x05
39 #define TT_WIN_UNF 0x06
40 #define TT_UNALIGNED 0x07
41 #define TT_FP_EXCP 0x08
42 #define TT_DFAULT 0x09
44 #define TT_EXTINT 0x10
45 #define TT_CODE_ACCESS 0x21
46 #define TT_DATA_ACCESS 0x29
47 #define TT_DIV_ZERO 0x2a
48 #define TT_NCP_INSN 0x24
51 #define TT_TFAULT 0x08
53 #define TT_CODE_ACCESS 0x0a
54 #define TT_ILL_INSN 0x10
55 #define TT_PRIV_INSN 0x11
56 #define TT_NFPU_INSN 0x20
57 #define TT_FP_EXCP 0x21
59 #define TT_CLRWIN 0x24
60 #define TT_DIV_ZERO 0x28
61 #define TT_DFAULT 0x30
63 #define TT_DATA_ACCESS 0x32
65 #define TT_UNALIGNED 0x34
66 #define TT_PRIV_ACT 0x37
67 #define TT_EXTINT 0x40
70 #define TT_WOTHER 0x10
74 #define PSR_NEG (1<<23)
75 #define PSR_ZERO (1<<22)
76 #define PSR_OVF (1<<21)
77 #define PSR_CARRY (1<<20)
78 #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
79 #define PSR_EF (1<<12)
86 /* Trap base register */
87 #define TBR_BASE_MASK 0xfffff000
89 #if defined(TARGET_SPARC64)
96 #define PS_PRIV (1<<2)
100 #define FPRS_FEF (1<<2)
102 #define HS_PRIV (1<<2)
106 #define FSR_RD1 (1<<31)
107 #define FSR_RD0 (1<<30)
108 #define FSR_RD_MASK (FSR_RD1 | FSR_RD0)
109 #define FSR_RD_NEAREST 0
110 #define FSR_RD_ZERO FSR_RD0
111 #define FSR_RD_POS FSR_RD1
112 #define FSR_RD_NEG (FSR_RD1 | FSR_RD0)
114 #define FSR_NVM (1<<27)
115 #define FSR_OFM (1<<26)
116 #define FSR_UFM (1<<25)
117 #define FSR_DZM (1<<24)
118 #define FSR_NXM (1<<23)
119 #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
121 #define FSR_NVA (1<<9)
122 #define FSR_OFA (1<<8)
123 #define FSR_UFA (1<<7)
124 #define FSR_DZA (1<<6)
125 #define FSR_NXA (1<<5)
126 #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
128 #define FSR_NVC (1<<4)
129 #define FSR_OFC (1<<3)
130 #define FSR_UFC (1<<2)
131 #define FSR_DZC (1<<1)
132 #define FSR_NXC (1<<0)
133 #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
135 #define FSR_FTT2 (1<<16)
136 #define FSR_FTT1 (1<<15)
137 #define FSR_FTT0 (1<<14)
138 #define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
139 #define FSR_FTT_IEEE_EXCP (1 << 14)
140 #define FSR_FTT_UNIMPFPOP (3 << 14)
141 #define FSR_FTT_SEQ_ERROR (4 << 14)
142 #define FSR_FTT_INVAL_FPR (6 << 14)
144 #define FSR_FCC1 (1<<11)
145 #define FSR_FCC0 (1<<10)
149 #define MMU_NF (1<<1)
151 #define PTE_ENTRYTYPE_MASK 3
152 #define PTE_ACCESS_MASK 0x1c
153 #define PTE_ACCESS_SHIFT 2
154 #define PTE_PPN_SHIFT 7
155 #define PTE_ADDR_MASK 0xffffff00
157 #define PG_ACCESSED_BIT 5
158 #define PG_MODIFIED_BIT 6
159 #define PG_CACHE_BIT 7
161 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
162 #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
163 #define PG_CACHE_MASK (1 << PG_CACHE_BIT)
165 /* 2 <= NWINDOWS <= 32. In QEMU it must also be a power of two. */
168 #if !defined(TARGET_SPARC64)
169 #define NB_MMU_MODES 2
171 #define NB_MMU_MODES 3
172 typedef struct trap_state {
180 typedef struct CPUSPARCState {
181 target_ulong gregs[8]; /* general registers */
182 target_ulong *regwptr; /* pointer to current register window */
183 float32 fpr[TARGET_FPREGS]; /* floating point registers */
184 target_ulong pc; /* program counter */
185 target_ulong npc; /* next program counter */
186 target_ulong y; /* multiply/divide register */
187 uint32_t psr; /* processor state register */
188 target_ulong fsr; /* FPU state register */
189 uint32_t cwp; /* index of current register window (extracted
191 uint32_t wim; /* window invalid mask */
192 target_ulong tbr; /* trap base register */
193 int psrs; /* supervisor mode (extracted from PSR) */
194 int psrps; /* previous supervisor mode */
195 int psret; /* enable traps */
196 uint32_t psrpil; /* interrupt blocking level */
197 uint32_t pil_in; /* incoming interrupt level bitmap */
198 int psref; /* enable fpu */
199 target_ulong version;
204 int interrupt_request;
207 uint32_t mmu_ctpr_mask;
208 uint32_t mmu_cxr_mask;
209 uint32_t mmu_sfsr_mask;
210 uint32_t mmu_trcr_mask;
211 /* NOTE: we allow 8 more registers to handle wrapping */
212 target_ulong regbase[NWINDOWS * 16 + 8];
217 #if defined(TARGET_SPARC64)
221 uint64_t immuregs[16];
222 uint64_t dmmuregs[16];
223 uint64_t itlb_tag[64];
224 uint64_t itlb_tte[64];
225 uint64_t dtlb_tag[64];
226 uint64_t dtlb_tte[64];
228 uint32_t mmuregs[32];
229 uint64_t mxccdata[4];
230 uint64_t mxccregs[8];
233 /* temporary float registers */
236 #if defined(CONFIG_USER_ONLY)
239 float_status fp_status;
240 #if defined(TARGET_SPARC64)
244 trap_state ts[MAXTL];
245 uint32_t xcc; /* Extended integer condition codes */
249 uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
250 uint64_t agregs[8]; /* alternate general registers */
251 uint64_t bgregs[8]; /* backup for normal global registers */
252 uint64_t igregs[8]; /* interrupt general registers */
253 uint64_t mgregs[8]; /* mmu general registers */
255 uint64_t tick_cmpr, stick_cmpr;
258 uint32_t gl; // UA2005
259 /* UA 2005 hyperprivileged registers */
260 uint64_t hpstate, htstate[MAXTL], hintp, htba, hver, hstick_cmpr, ssr;
261 void *hstick; // UA 2005
263 #if !defined(TARGET_SPARC64) && !defined(reg_T2)
267 #if defined(TARGET_SPARC64)
268 #define GET_FSR32(env) (env->fsr & 0xcfc1ffff)
269 #define PUT_FSR32(env, val) do { uint32_t _tmp = val; \
270 env->fsr = (_tmp & 0xcfc1c3ff) | (env->fsr & 0x3f00000000ULL); \
272 #define GET_FSR64(env) (env->fsr & 0x3fcfc1ffffULL)
273 #define PUT_FSR64(env, val) do { uint64_t _tmp = val; \
274 env->fsr = _tmp & 0x3fcfc1c3ffULL; \
277 #define GET_FSR32(env) (env->fsr)
278 #define PUT_FSR32(env, val) do { uint32_t _tmp = val; \
279 env->fsr = (_tmp & 0xcfc1dfff) | (env->fsr & 0x000e0000); \
283 CPUSPARCState *cpu_sparc_init(const char *cpu_model);
284 int cpu_sparc_exec(CPUSPARCState *s);
285 int cpu_sparc_close(CPUSPARCState *s);
286 void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt,
288 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu);
290 #define GET_PSR(env) (env->version | (env->psr & PSR_ICC) | \
291 (env->psref? PSR_EF : 0) | \
292 (env->psrpil << 8) | \
293 (env->psrs? PSR_S : 0) | \
294 (env->psrps? PSR_PS : 0) | \
295 (env->psret? PSR_ET : 0) | env->cwp)
297 #ifndef NO_CPU_IO_DEFS
298 void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
301 #define PUT_PSR(env, val) do { int _tmp = val; \
302 env->psr = _tmp & PSR_ICC; \
303 env->psref = (_tmp & PSR_EF)? 1 : 0; \
304 env->psrpil = (_tmp & PSR_PIL) >> 8; \
305 env->psrs = (_tmp & PSR_S)? 1 : 0; \
306 env->psrps = (_tmp & PSR_PS)? 1 : 0; \
307 env->psret = (_tmp & PSR_ET)? 1 : 0; \
308 cpu_set_cwp(env, _tmp & PSR_CWP); \
311 #ifdef TARGET_SPARC64
312 #define GET_CCR(env) (((env->xcc >> 20) << 4) | ((env->psr & PSR_ICC) >> 20))
313 #define PUT_CCR(env, val) do { int _tmp = val; \
314 env->xcc = (_tmp >> 4) << 20; \
315 env->psr = (_tmp & 0xf) << 20; \
317 #define GET_CWP64(env) (NWINDOWS - 1 - (env)->cwp)
318 #define PUT_CWP64(env, val) \
319 cpu_set_cwp(env, NWINDOWS - 1 - ((val) & (NWINDOWS - 1)))
323 int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
324 void raise_exception(int tt);
325 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
327 void cpu_check_irqs(CPUSPARCState *env);
329 #define CPUState CPUSPARCState
330 #define cpu_init cpu_sparc_init
331 #define cpu_exec cpu_sparc_exec
332 #define cpu_gen_code cpu_sparc_gen_code
333 #define cpu_signal_handler cpu_sparc_signal_handler
334 #define cpu_list sparc_cpu_list
336 /* MMU modes definitions */
337 #define MMU_MODE0_SUFFIX _user
338 #define MMU_MODE1_SUFFIX _kernel
339 #ifdef TARGET_SPARC64
340 #define MMU_MODE2_SUFFIX _hypv
342 #define MMU_USER_IDX 0
343 #define MMU_KERNEL_IDX 1
344 #define MMU_HYPV_IDX 2
346 static inline int cpu_mmu_index (CPUState *env)
348 #if defined(CONFIG_USER_ONLY)
350 #elif !defined(TARGET_SPARC64)
355 else if ((env->hpstate & HS_PRIV) == 0)
356 return MMU_KERNEL_IDX;
362 static inline int cpu_fpu_enabled(CPUState *env)
364 #if defined(CONFIG_USER_ONLY)
366 #elif !defined(TARGET_SPARC64)
369 return ((env->pstate & PS_PEF) != 0) && ((env->fprs & FPRS_FEF) != 0);