6 #if !defined(TARGET_SPARC64)
7 #define TARGET_LONG_BITS 32
8 #define TARGET_FPREGS 32
9 #define TARGET_PAGE_BITS 12 /* 4k */
11 #define TARGET_LONG_BITS 64
12 #define TARGET_FPREGS 64
13 #define TARGET_PAGE_BITS 12 /* XXX */
18 #include "softfloat.h"
20 #define TARGET_HAS_ICE 1
22 #if !defined(TARGET_SPARC64)
23 #define ELF_MACHINE EM_SPARC
25 #define ELF_MACHINE EM_SPARCV9
28 /*#define EXCP_INTERRUPT 0x100*/
30 /* trap definitions */
31 #ifndef TARGET_SPARC64
32 #define TT_TFAULT 0x01
33 #define TT_ILL_INSN 0x02
34 #define TT_PRIV_INSN 0x03
35 #define TT_NFPU_INSN 0x04
36 #define TT_WIN_OVF 0x05
37 #define TT_WIN_UNF 0x06
38 #define TT_FP_EXCP 0x08
39 #define TT_DFAULT 0x09
41 #define TT_EXTINT 0x10
42 #define TT_DIV_ZERO 0x2a
43 #define TT_NCP_INSN 0x24
46 #define TT_TFAULT 0x08
48 #define TT_ILL_INSN 0x10
49 #define TT_PRIV_INSN 0x11
50 #define TT_NFPU_INSN 0x20
51 #define TT_FP_EXCP 0x21
53 #define TT_CLRWIN 0x24
54 #define TT_DIV_ZERO 0x28
55 #define TT_DFAULT 0x30
58 #define TT_PRIV_ACT 0x37
59 #define TT_EXTINT 0x40
62 #define TT_WOTHER 0x10
66 #define PSR_NEG (1<<23)
67 #define PSR_ZERO (1<<22)
68 #define PSR_OVF (1<<21)
69 #define PSR_CARRY (1<<20)
70 #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
71 #define PSR_EF (1<<12)
78 /* Trap base register */
79 #define TBR_BASE_MASK 0xfffff000
81 #if defined(TARGET_SPARC64)
87 #define PS_PRIV (1<<2)
91 #define FPRS_FEF (1<<2)
95 #define FSR_RD1 (1<<31)
96 #define FSR_RD0 (1<<30)
97 #define FSR_RD_MASK (FSR_RD1 | FSR_RD0)
98 #define FSR_RD_NEAREST 0
99 #define FSR_RD_ZERO FSR_RD0
100 #define FSR_RD_POS FSR_RD1
101 #define FSR_RD_NEG (FSR_RD1 | FSR_RD0)
103 #define FSR_NVM (1<<27)
104 #define FSR_OFM (1<<26)
105 #define FSR_UFM (1<<25)
106 #define FSR_DZM (1<<24)
107 #define FSR_NXM (1<<23)
108 #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
110 #define FSR_NVA (1<<9)
111 #define FSR_OFA (1<<8)
112 #define FSR_UFA (1<<7)
113 #define FSR_DZA (1<<6)
114 #define FSR_NXA (1<<5)
115 #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
117 #define FSR_NVC (1<<4)
118 #define FSR_OFC (1<<3)
119 #define FSR_UFC (1<<2)
120 #define FSR_DZC (1<<1)
121 #define FSR_NXC (1<<0)
122 #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
124 #define FSR_FTT2 (1<<16)
125 #define FSR_FTT1 (1<<15)
126 #define FSR_FTT0 (1<<14)
127 #define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
128 #define FSR_FTT_IEEE_EXCP (1 << 14)
129 #define FSR_FTT_UNIMPFPOP (3 << 14)
130 #define FSR_FTT_SEQ_ERROR (4 << 14)
131 #define FSR_FTT_INVAL_FPR (6 << 14)
133 #define FSR_FCC1 (1<<11)
134 #define FSR_FCC0 (1<<10)
138 #define MMU_NF (1<<1)
140 #define PTE_ENTRYTYPE_MASK 3
141 #define PTE_ACCESS_MASK 0x1c
142 #define PTE_ACCESS_SHIFT 2
143 #define PTE_PPN_SHIFT 7
144 #define PTE_ADDR_MASK 0xffffff00
146 #define PG_ACCESSED_BIT 5
147 #define PG_MODIFIED_BIT 6
148 #define PG_CACHE_BIT 7
150 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
151 #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
152 #define PG_CACHE_MASK (1 << PG_CACHE_BIT)
154 /* 2 <= NWINDOWS <= 32. In QEMU it must also be a power of two. */
157 typedef struct sparc_def_t sparc_def_t;
159 typedef struct CPUSPARCState {
160 target_ulong gregs[8]; /* general registers */
161 target_ulong *regwptr; /* pointer to current register window */
162 float32 fpr[TARGET_FPREGS]; /* floating point registers */
163 target_ulong pc; /* program counter */
164 target_ulong npc; /* next program counter */
165 target_ulong y; /* multiply/divide register */
166 uint32_t psr; /* processor state register */
167 target_ulong fsr; /* FPU state register */
168 uint32_t cwp; /* index of current register window (extracted
170 uint32_t wim; /* window invalid mask */
171 target_ulong tbr; /* trap base register */
172 int psrs; /* supervisor mode (extracted from PSR) */
173 int psrps; /* previous supervisor mode */
174 int psret; /* enable traps */
175 uint32_t psrpil; /* interrupt level */
176 int psref; /* enable fpu */
177 target_ulong version;
182 int interrupt_request;
184 /* NOTE: we allow 8 more registers to handle wrapping */
185 target_ulong regbase[NWINDOWS * 16 + 8];
190 #if defined(TARGET_SPARC64)
194 uint64_t immuregs[16];
195 uint64_t dmmuregs[16];
196 uint64_t itlb_tag[64];
197 uint64_t itlb_tte[64];
198 uint64_t dtlb_tag[64];
199 uint64_t dtlb_tte[64];
201 uint32_t mmuregs[16];
203 /* temporary float registers */
206 float_status fp_status;
207 #if defined(TARGET_SPARC64)
211 uint64_t tnpc[MAXTL];
212 uint64_t tstate[MAXTL];
214 uint32_t xcc; /* Extended integer condition codes */
218 uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
219 uint64_t agregs[8]; /* alternate general registers */
220 uint64_t bgregs[8]; /* backup for normal global registers */
221 uint64_t igregs[8]; /* interrupt general registers */
222 uint64_t mgregs[8]; /* mmu general registers */
224 uint64_t tick_cmpr, stick_cmpr;
227 #if !defined(TARGET_SPARC64) && !defined(reg_T2)
231 #if defined(TARGET_SPARC64)
232 #define GET_FSR32(env) (env->fsr & 0xcfc1ffff)
233 #define PUT_FSR32(env, val) do { uint32_t _tmp = val; \
234 env->fsr = (_tmp & 0xcfc1c3ff) | (env->fsr & 0x3f00000000ULL); \
236 #define GET_FSR64(env) (env->fsr & 0x3fcfc1ffffULL)
237 #define PUT_FSR64(env, val) do { uint64_t _tmp = val; \
238 env->fsr = _tmp & 0x3fcfc1c3ffULL; \
241 #define GET_FSR32(env) (env->fsr)
242 #define PUT_FSR32(env, val) do { uint32_t _tmp = val; \
243 env->fsr = (_tmp & 0xcfc1dfff) | (env->fsr & 0x000e0000); \
247 CPUSPARCState *cpu_sparc_init(void);
248 int cpu_sparc_exec(CPUSPARCState *s);
249 int cpu_sparc_close(CPUSPARCState *s);
250 int sparc_find_by_name (const unsigned char *name, const sparc_def_t **def);
251 void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt,
253 int cpu_sparc_register (CPUSPARCState *env, const sparc_def_t *def);
255 #define GET_PSR(env) (env->version | (env->psr & PSR_ICC) | \
256 (env->psref? PSR_EF : 0) | \
257 (env->psrpil << 8) | \
258 (env->psrs? PSR_S : 0) | \
259 (env->psrps? PSR_PS : 0) | \
260 (env->psret? PSR_ET : 0) | env->cwp)
262 #ifndef NO_CPU_IO_DEFS
263 void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
266 #define PUT_PSR(env, val) do { int _tmp = val; \
267 env->psr = _tmp & PSR_ICC; \
268 env->psref = (_tmp & PSR_EF)? 1 : 0; \
269 env->psrpil = (_tmp & PSR_PIL) >> 8; \
270 env->psrs = (_tmp & PSR_S)? 1 : 0; \
271 env->psrps = (_tmp & PSR_PS)? 1 : 0; \
272 env->psret = (_tmp & PSR_ET)? 1 : 0; \
273 cpu_set_cwp(env, _tmp & PSR_CWP); \
276 #ifdef TARGET_SPARC64
277 #define GET_CCR(env) ((env->xcc << 4) | (env->psr & PSR_ICC))
278 #define PUT_CCR(env, val) do { int _tmp = val; \
279 env->xcc = _tmp >> 4; \
280 env->psr = (_tmp & 0xf) << 20; \
284 int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);