6 #if !defined(TARGET_SPARC64)
7 #define TARGET_LONG_BITS 32
8 #define TARGET_FPREGS 32
9 #define TARGET_PAGE_BITS 12 /* 4k */
11 #define TARGET_LONG_BITS 64
12 #define TARGET_FPREGS 64
13 #define TARGET_PAGE_BITS 13 /* 8k */
16 #define TARGET_PHYS_ADDR_BITS 64
20 #include "softfloat.h"
22 #define TARGET_HAS_ICE 1
24 #if !defined(TARGET_SPARC64)
25 #define ELF_MACHINE EM_SPARC
27 #define ELF_MACHINE EM_SPARCV9
30 /*#define EXCP_INTERRUPT 0x100*/
32 /* trap definitions */
33 #ifndef TARGET_SPARC64
34 #define TT_TFAULT 0x01
35 #define TT_ILL_INSN 0x02
36 #define TT_PRIV_INSN 0x03
37 #define TT_NFPU_INSN 0x04
38 #define TT_WIN_OVF 0x05
39 #define TT_WIN_UNF 0x06
40 #define TT_UNALIGNED 0x07
41 #define TT_FP_EXCP 0x08
42 #define TT_DFAULT 0x09
44 #define TT_EXTINT 0x10
45 #define TT_CODE_ACCESS 0x21
46 #define TT_UNIMP_FLUSH 0x25
47 #define TT_DATA_ACCESS 0x29
48 #define TT_DIV_ZERO 0x2a
49 #define TT_NCP_INSN 0x24
52 #define TT_TFAULT 0x08
54 #define TT_CODE_ACCESS 0x0a
55 #define TT_ILL_INSN 0x10
56 #define TT_UNIMP_FLUSH TT_ILL_INSN
57 #define TT_PRIV_INSN 0x11
58 #define TT_NFPU_INSN 0x20
59 #define TT_FP_EXCP 0x21
61 #define TT_CLRWIN 0x24
62 #define TT_DIV_ZERO 0x28
63 #define TT_DFAULT 0x30
65 #define TT_DATA_ACCESS 0x32
67 #define TT_UNALIGNED 0x34
68 #define TT_PRIV_ACT 0x37
69 #define TT_EXTINT 0x40
72 #define TT_WOTHER 0x10
76 #define PSR_NEG_SHIFT 23
77 #define PSR_NEG (1 << PSR_NEG_SHIFT)
78 #define PSR_ZERO_SHIFT 22
79 #define PSR_ZERO (1 << PSR_ZERO_SHIFT)
80 #define PSR_OVF_SHIFT 21
81 #define PSR_OVF (1 << PSR_OVF_SHIFT)
82 #define PSR_CARRY_SHIFT 20
83 #define PSR_CARRY (1 << PSR_CARRY_SHIFT)
84 #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
85 #define PSR_EF (1<<12)
92 /* Trap base register */
93 #define TBR_BASE_MASK 0xfffff000
95 #if defined(TARGET_SPARC64)
100 #define PS_PEF (1<<4)
102 #define PS_PRIV (1<<2)
106 #define FPRS_FEF (1<<2)
108 #define HS_PRIV (1<<2)
112 #define FSR_RD1 (1<<31)
113 #define FSR_RD0 (1<<30)
114 #define FSR_RD_MASK (FSR_RD1 | FSR_RD0)
115 #define FSR_RD_NEAREST 0
116 #define FSR_RD_ZERO FSR_RD0
117 #define FSR_RD_POS FSR_RD1
118 #define FSR_RD_NEG (FSR_RD1 | FSR_RD0)
120 #define FSR_NVM (1<<27)
121 #define FSR_OFM (1<<26)
122 #define FSR_UFM (1<<25)
123 #define FSR_DZM (1<<24)
124 #define FSR_NXM (1<<23)
125 #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
127 #define FSR_NVA (1<<9)
128 #define FSR_OFA (1<<8)
129 #define FSR_UFA (1<<7)
130 #define FSR_DZA (1<<6)
131 #define FSR_NXA (1<<5)
132 #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
134 #define FSR_NVC (1<<4)
135 #define FSR_OFC (1<<3)
136 #define FSR_UFC (1<<2)
137 #define FSR_DZC (1<<1)
138 #define FSR_NXC (1<<0)
139 #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
141 #define FSR_FTT2 (1<<16)
142 #define FSR_FTT1 (1<<15)
143 #define FSR_FTT0 (1<<14)
144 #define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
145 #define FSR_FTT_IEEE_EXCP (1 << 14)
146 #define FSR_FTT_UNIMPFPOP (3 << 14)
147 #define FSR_FTT_SEQ_ERROR (4 << 14)
148 #define FSR_FTT_INVAL_FPR (6 << 14)
150 #define FSR_FCC1_SHIFT 11
151 #define FSR_FCC1 (1 << FSR_FCC1_SHIFT)
152 #define FSR_FCC0_SHIFT 10
153 #define FSR_FCC0 (1 << FSR_FCC0_SHIFT)
157 #define MMU_NF (1<<1)
159 #define PTE_ENTRYTYPE_MASK 3
160 #define PTE_ACCESS_MASK 0x1c
161 #define PTE_ACCESS_SHIFT 2
162 #define PTE_PPN_SHIFT 7
163 #define PTE_ADDR_MASK 0xffffff00
165 #define PG_ACCESSED_BIT 5
166 #define PG_MODIFIED_BIT 6
167 #define PG_CACHE_BIT 7
169 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
170 #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
171 #define PG_CACHE_MASK (1 << PG_CACHE_BIT)
173 /* 2 <= NWINDOWS <= 32. In QEMU it must also be a power of two. */
176 #if !defined(TARGET_SPARC64)
177 #define NB_MMU_MODES 2
179 #define NB_MMU_MODES 3
180 typedef struct trap_state {
188 typedef struct CPUSPARCState {
189 target_ulong gregs[8]; /* general registers */
190 target_ulong *regwptr; /* pointer to current register window */
191 target_ulong pc; /* program counter */
192 target_ulong npc; /* next program counter */
193 target_ulong y; /* multiply/divide register */
195 /* emulator internal flags handling */
196 target_ulong cc_src, cc_src2;
199 target_ulong t0, t1; /* temporaries live across basic blocks */
200 target_ulong cond; /* conditional branch result (XXX: save it in a
201 temporary register when possible) */
203 uint32_t psr; /* processor state register */
204 target_ulong fsr; /* FPU state register */
205 float32 fpr[TARGET_FPREGS]; /* floating point registers */
206 uint32_t cwp; /* index of current register window (extracted
208 uint32_t wim; /* window invalid mask */
209 target_ulong tbr; /* trap base register */
210 int psrs; /* supervisor mode (extracted from PSR) */
211 int psrps; /* previous supervisor mode */
212 int psret; /* enable traps */
213 uint32_t psrpil; /* interrupt blocking level */
214 uint32_t pil_in; /* incoming interrupt level bitmap */
215 int psref; /* enable fpu */
216 target_ulong version;
221 int interrupt_request;
223 uint32_t mmu_ctpr_mask;
224 uint32_t mmu_cxr_mask;
225 uint32_t mmu_sfsr_mask;
226 uint32_t mmu_trcr_mask;
227 /* NOTE: we allow 8 more registers to handle wrapping */
228 target_ulong regbase[NWINDOWS * 16 + 8];
233 #if defined(TARGET_SPARC64)
237 uint64_t immuregs[16];
238 uint64_t dmmuregs[16];
239 uint64_t itlb_tag[64];
240 uint64_t itlb_tte[64];
241 uint64_t dtlb_tag[64];
242 uint64_t dtlb_tte[64];
244 uint32_t mmuregs[32];
245 uint64_t mxccdata[4];
246 uint64_t mxccregs[8];
249 /* temporary float registers */
253 float_status fp_status;
254 #if defined(TARGET_SPARC64)
257 trap_state ts[MAXTL];
258 uint32_t xcc; /* Extended integer condition codes */
262 uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
263 uint64_t agregs[8]; /* alternate general registers */
264 uint64_t bgregs[8]; /* backup for normal global registers */
265 uint64_t igregs[8]; /* interrupt general registers */
266 uint64_t mgregs[8]; /* mmu general registers */
268 uint64_t tick_cmpr, stick_cmpr;
271 uint32_t gl; // UA2005
272 /* UA 2005 hyperprivileged registers */
273 uint64_t hpstate, htstate[MAXTL], hintp, htba, hver, hstick_cmpr, ssr;
274 void *hstick; // UA 2005
279 #define CPU_FEATURE_FLOAT (1 << 0)
280 #define CPU_FEATURE_FLOAT128 (1 << 1)
281 #define CPU_FEATURE_SWAP (1 << 2)
282 #define CPU_FEATURE_MUL (1 << 3)
283 #define CPU_FEATURE_DIV (1 << 4)
284 #define CPU_FEATURE_FLUSH (1 << 5)
285 #define CPU_FEATURE_FSQRT (1 << 6)
286 #define CPU_FEATURE_FMUL (1 << 7)
287 #define CPU_FEATURE_VIS1 (1 << 8)
288 #define CPU_FEATURE_VIS2 (1 << 9)
289 #ifndef TARGET_SPARC64
290 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \
291 CPU_FEATURE_MUL | CPU_FEATURE_DIV | \
292 CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
295 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \
296 CPU_FEATURE_MUL | CPU_FEATURE_DIV | \
297 CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
298 CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 | \
302 #if defined(TARGET_SPARC64)
303 #define GET_FSR32(env) (env->fsr & 0xcfc1ffff)
304 #define PUT_FSR32(env, val) do { uint32_t _tmp = val; \
305 env->fsr = (_tmp & 0xcfc1c3ff) | (env->fsr & 0x3f00000000ULL); \
307 #define GET_FSR64(env) (env->fsr & 0x3fcfc1ffffULL)
308 #define PUT_FSR64(env, val) do { uint64_t _tmp = val; \
309 env->fsr = _tmp & 0x3fcfc1c3ffULL; \
312 #define GET_FSR32(env) (env->fsr)
313 #define PUT_FSR32(env, val) do { uint32_t _tmp = val; \
314 env->fsr = (_tmp & 0xcfc1dfff) | (env->fsr & 0x000e0000); \
318 CPUSPARCState *cpu_sparc_init(const char *cpu_model);
319 void gen_intermediate_code_init(CPUSPARCState *env);
320 int cpu_sparc_exec(CPUSPARCState *s);
321 void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt,
323 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu);
325 #define GET_PSR(env) (env->version | (env->psr & PSR_ICC) | \
326 (env->psref? PSR_EF : 0) | \
327 (env->psrpil << 8) | \
328 (env->psrs? PSR_S : 0) | \
329 (env->psrps? PSR_PS : 0) | \
330 (env->psret? PSR_ET : 0) | env->cwp)
332 #ifndef NO_CPU_IO_DEFS
333 void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
336 #define PUT_PSR(env, val) do { int _tmp = val; \
337 env->psr = _tmp & PSR_ICC; \
338 env->psref = (_tmp & PSR_EF)? 1 : 0; \
339 env->psrpil = (_tmp & PSR_PIL) >> 8; \
340 env->psrs = (_tmp & PSR_S)? 1 : 0; \
341 env->psrps = (_tmp & PSR_PS)? 1 : 0; \
342 env->psret = (_tmp & PSR_ET)? 1 : 0; \
343 cpu_set_cwp(env, _tmp & PSR_CWP); \
346 #ifdef TARGET_SPARC64
347 #define GET_CCR(env) (((env->xcc >> 20) << 4) | ((env->psr & PSR_ICC) >> 20))
348 #define PUT_CCR(env, val) do { int _tmp = val; \
349 env->xcc = (_tmp >> 4) << 20; \
350 env->psr = (_tmp & 0xf) << 20; \
352 #define GET_CWP64(env) (NWINDOWS - 1 - (env)->cwp)
353 #define PUT_CWP64(env, val) \
354 cpu_set_cwp(env, NWINDOWS - 1 - ((val) & (NWINDOWS - 1)))
358 int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
359 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
361 void cpu_check_irqs(CPUSPARCState *env);
363 #define CPUState CPUSPARCState
364 #define cpu_init cpu_sparc_init
365 #define cpu_exec cpu_sparc_exec
366 #define cpu_gen_code cpu_sparc_gen_code
367 #define cpu_signal_handler cpu_sparc_signal_handler
368 #define cpu_list sparc_cpu_list
370 /* MMU modes definitions */
371 #define MMU_MODE0_SUFFIX _user
372 #define MMU_MODE1_SUFFIX _kernel
373 #ifdef TARGET_SPARC64
374 #define MMU_MODE2_SUFFIX _hypv
376 #define MMU_USER_IDX 0
377 #define MMU_KERNEL_IDX 1
378 #define MMU_HYPV_IDX 2
380 static inline int cpu_mmu_index(CPUState *env1)
382 #if defined(CONFIG_USER_ONLY)
384 #elif !defined(TARGET_SPARC64)
389 else if ((env1->hpstate & HS_PRIV) == 0)
390 return MMU_KERNEL_IDX;
396 static inline int cpu_fpu_enabled(CPUState *env1)
398 #if defined(CONFIG_USER_ONLY)
400 #elif !defined(TARGET_SPARC64)
403 return ((env1->pstate & PS_PEF) != 0) && ((env1->fprs & FPRS_FEF) != 0);