6 #if !defined(TARGET_SPARC64)
7 #define TARGET_LONG_BITS 32
8 #define TARGET_FPREGS 32
9 #define TARGET_PAGE_BITS 12 /* 4k */
11 #define TARGET_LONG_BITS 64
12 #define TARGET_FPREGS 64
13 #define TARGET_PAGE_BITS 12 /* XXX */
18 #include "softfloat.h"
20 #define TARGET_HAS_ICE 1
22 #if !defined(TARGET_SPARC64)
23 #define ELF_MACHINE EM_SPARC
25 #define ELF_MACHINE EM_SPARCV9
28 /*#define EXCP_INTERRUPT 0x100*/
30 /* trap definitions */
31 #ifndef TARGET_SPARC64
32 #define TT_TFAULT 0x01
33 #define TT_ILL_INSN 0x02
34 #define TT_PRIV_INSN 0x03
35 #define TT_NFPU_INSN 0x04
36 #define TT_WIN_OVF 0x05
37 #define TT_WIN_UNF 0x06
38 #define TT_FP_EXCP 0x08
39 #define TT_DFAULT 0x09
41 #define TT_EXTINT 0x10
42 #define TT_DIV_ZERO 0x2a
45 #define TT_TFAULT 0x08
47 #define TT_ILL_INSN 0x10
48 #define TT_PRIV_INSN 0x11
49 #define TT_NFPU_INSN 0x20
50 #define TT_FP_EXCP 0x21
52 #define TT_CLRWIN 0x24
53 #define TT_DIV_ZERO 0x28
54 #define TT_DFAULT 0x30
57 #define TT_PRIV_ACT 0x37
58 #define TT_EXTINT 0x40
61 #define TT_WOTHER 0x10
65 #define PSR_NEG (1<<23)
66 #define PSR_ZERO (1<<22)
67 #define PSR_OVF (1<<21)
68 #define PSR_CARRY (1<<20)
69 #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
70 #define PSR_EF (1<<12)
77 /* Trap base register */
78 #define TBR_BASE_MASK 0xfffff000
80 #if defined(TARGET_SPARC64)
86 #define PS_PRIV (1<<2)
90 #define FPRS_FEF (1<<2)
94 #define FSR_RD1 (1<<31)
95 #define FSR_RD0 (1<<30)
96 #define FSR_RD_MASK (FSR_RD1 | FSR_RD0)
97 #define FSR_RD_NEAREST 0
98 #define FSR_RD_ZERO FSR_RD0
99 #define FSR_RD_POS FSR_RD1
100 #define FSR_RD_NEG (FSR_RD1 | FSR_RD0)
102 #define FSR_NVM (1<<27)
103 #define FSR_OFM (1<<26)
104 #define FSR_UFM (1<<25)
105 #define FSR_DZM (1<<24)
106 #define FSR_NXM (1<<23)
107 #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
109 #define FSR_NVA (1<<9)
110 #define FSR_OFA (1<<8)
111 #define FSR_UFA (1<<7)
112 #define FSR_DZA (1<<6)
113 #define FSR_NXA (1<<5)
114 #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
116 #define FSR_NVC (1<<4)
117 #define FSR_OFC (1<<3)
118 #define FSR_UFC (1<<2)
119 #define FSR_DZC (1<<1)
120 #define FSR_NXC (1<<0)
121 #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
123 #define FSR_FTT2 (1<<16)
124 #define FSR_FTT1 (1<<15)
125 #define FSR_FTT0 (1<<14)
126 #define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
127 #define FSR_FTT_IEEE_EXCP (1 << 14)
128 #define FSR_FTT_UNIMPFPOP (3 << 14)
129 #define FSR_FTT_INVAL_FPR (6 << 14)
131 #define FSR_FCC1 (1<<11)
132 #define FSR_FCC0 (1<<10)
136 #define MMU_NF (1<<1)
138 #define PTE_ENTRYTYPE_MASK 3
139 #define PTE_ACCESS_MASK 0x1c
140 #define PTE_ACCESS_SHIFT 2
141 #define PTE_PPN_SHIFT 7
142 #define PTE_ADDR_MASK 0xffffff00
144 #define PG_ACCESSED_BIT 5
145 #define PG_MODIFIED_BIT 6
146 #define PG_CACHE_BIT 7
148 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
149 #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
150 #define PG_CACHE_MASK (1 << PG_CACHE_BIT)
152 /* 2 <= NWINDOWS <= 32. In QEMU it must also be a power of two. */
155 typedef struct CPUSPARCState {
156 target_ulong gregs[8]; /* general registers */
157 target_ulong *regwptr; /* pointer to current register window */
158 float32 fpr[TARGET_FPREGS]; /* floating point registers */
159 target_ulong pc; /* program counter */
160 target_ulong npc; /* next program counter */
161 target_ulong y; /* multiply/divide register */
162 uint32_t psr; /* processor state register */
163 target_ulong fsr; /* FPU state register */
164 uint32_t cwp; /* index of current register window (extracted
166 uint32_t wim; /* window invalid mask */
167 target_ulong tbr; /* trap base register */
168 int psrs; /* supervisor mode (extracted from PSR) */
169 int psrps; /* previous supervisor mode */
170 int psret; /* enable traps */
171 uint32_t psrpil; /* interrupt level */
172 int psref; /* enable fpu */
177 int interrupt_request;
179 /* NOTE: we allow 8 more registers to handle wrapping */
180 target_ulong regbase[NWINDOWS * 16 + 8];
185 #if defined(TARGET_SPARC64)
189 uint64_t immuregs[16];
190 uint64_t dmmuregs[16];
191 uint64_t itlb_tag[64];
192 uint64_t itlb_tte[64];
193 uint64_t dtlb_tag[64];
194 uint64_t dtlb_tte[64];
196 uint32_t mmuregs[16];
198 /* temporary float registers */
201 float_status fp_status;
202 #if defined(TARGET_SPARC64)
206 uint64_t tnpc[MAXTL];
207 uint64_t tstate[MAXTL];
209 uint32_t xcc; /* Extended integer condition codes */
213 uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
214 uint64_t agregs[8]; /* alternate general registers */
215 uint64_t bgregs[8]; /* backup for normal global registers */
216 uint64_t igregs[8]; /* interrupt general registers */
217 uint64_t mgregs[8]; /* mmu general registers */
220 uint64_t tick_cmpr, stick_cmpr;
223 #if !defined(TARGET_SPARC64) && !defined(reg_T2)
227 #if defined(TARGET_SPARC64)
228 #define GET_FSR32(env) (env->fsr & 0xcfc1ffff)
229 #define PUT_FSR32(env, val) do { uint32_t _tmp = val; \
230 env->fsr = (_tmp & 0xcfc1c3ff) | (env->fsr & 0x3f00000000ULL); \
232 #define GET_FSR64(env) (env->fsr & 0x3fcfc1ffffULL)
233 #define PUT_FSR64(env, val) do { uint64_t _tmp = val; \
234 env->fsr = _tmp & 0x3fcfc1c3ffULL; \
236 // Manuf 0x17, version 0x11, mask 0 (UltraSparc-II)
237 #define GET_VER(env) ((0x17ULL << 48) | (0x11ULL << 32) | \
238 (0 << 24) | (MAXTL << 8) | (NWINDOWS - 1))
240 #define GET_FSR32(env) (env->fsr)
241 #define PUT_FSR32(env, val) do { uint32_t _tmp = val; \
242 env->fsr = _tmp & 0xcfc1ffff; \
246 CPUSPARCState *cpu_sparc_init(void);
247 int cpu_sparc_exec(CPUSPARCState *s);
248 int cpu_sparc_close(CPUSPARCState *s);
250 /* Fake impl 0, version 4 */
251 #define GET_PSR(env) ((0 << 28) | (4 << 24) | (env->psr & PSR_ICC) | \
252 (env->psref? PSR_EF : 0) | \
253 (env->psrpil << 8) | \
254 (env->psrs? PSR_S : 0) | \
255 (env->psrps? PSR_PS : 0) | \
256 (env->psret? PSR_ET : 0) | env->cwp)
258 #ifndef NO_CPU_IO_DEFS
259 void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
262 #define PUT_PSR(env, val) do { int _tmp = val; \
263 env->psr = _tmp & PSR_ICC; \
264 env->psref = (_tmp & PSR_EF)? 1 : 0; \
265 env->psrpil = (_tmp & PSR_PIL) >> 8; \
266 env->psrs = (_tmp & PSR_S)? 1 : 0; \
267 env->psrps = (_tmp & PSR_PS)? 1 : 0; \
268 env->psret = (_tmp & PSR_ET)? 1 : 0; \
269 cpu_set_cwp(env, _tmp & PSR_CWP & (NWINDOWS - 1)); \
272 #ifdef TARGET_SPARC64
273 #define GET_CCR(env) ((env->xcc << 4) | (env->psr & PSR_ICC))
274 #define PUT_CCR(env, val) do { int _tmp = val; \
275 env->xcc = _tmp >> 4; \
276 env->psr = (_tmp & 0xf) << 20; \
280 int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);