4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30 #include "qemu-common.h"
34 //#define DEBUG_FEATURES
36 typedef struct sparc_def_t sparc_def_t;
40 target_ulong iu_version;
44 uint32_t mmu_ctpr_mask;
45 uint32_t mmu_cxr_mask;
46 uint32_t mmu_sfsr_mask;
47 uint32_t mmu_trcr_mask;
51 static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model);
53 /* Sparc MMU emulation */
57 spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
61 spin_lock(&global_cpu_lock);
66 spin_unlock(&global_cpu_lock);
69 #if defined(CONFIG_USER_ONLY)
71 int cpu_sparc_handle_mmu_fault(CPUState *env1, target_ulong address, int rw,
72 int mmu_idx, int is_softmmu)
75 env1->exception_index = TT_TFAULT;
77 env1->exception_index = TT_DFAULT;
83 #ifndef TARGET_SPARC64
85 * Sparc V8 Reference MMU (SRMMU)
87 static const int access_table[8][8] = {
88 { 0, 0, 0, 0, 2, 0, 3, 3 },
89 { 0, 0, 0, 0, 2, 0, 0, 0 },
90 { 2, 2, 0, 0, 0, 2, 3, 3 },
91 { 2, 2, 0, 0, 0, 2, 0, 0 },
92 { 2, 0, 2, 0, 2, 2, 3, 3 },
93 { 2, 0, 2, 0, 2, 0, 2, 0 },
94 { 2, 2, 2, 0, 2, 2, 3, 3 },
95 { 2, 2, 2, 0, 2, 2, 2, 0 }
98 static const int perm_table[2][8] = {
101 PAGE_READ | PAGE_WRITE,
102 PAGE_READ | PAGE_EXEC,
103 PAGE_READ | PAGE_WRITE | PAGE_EXEC,
105 PAGE_READ | PAGE_WRITE,
106 PAGE_READ | PAGE_EXEC,
107 PAGE_READ | PAGE_WRITE | PAGE_EXEC
111 PAGE_READ | PAGE_WRITE,
112 PAGE_READ | PAGE_EXEC,
113 PAGE_READ | PAGE_WRITE | PAGE_EXEC,
121 static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
122 int *prot, int *access_index,
123 target_ulong address, int rw, int mmu_idx)
125 int access_perms = 0;
126 target_phys_addr_t pde_ptr;
128 target_ulong virt_addr;
129 int error_code = 0, is_dirty, is_user;
130 unsigned long page_offset;
132 is_user = mmu_idx == MMU_USER_IDX;
133 virt_addr = address & TARGET_PAGE_MASK;
135 if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
136 // Boot mode: instruction fetches are taken from PROM
137 if (rw == 2 && (env->mmuregs[0] & env->mmu_bm)) {
138 *physical = env->prom_addr | (address & 0x7ffffULL);
139 *prot = PAGE_READ | PAGE_EXEC;
143 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
147 *access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1);
148 *physical = 0xffffffffffff0000ULL;
150 /* SPARC reference MMU table walk: Context table->L1->L2->PTE */
151 /* Context base + context number */
152 pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
153 pde = ldl_phys(pde_ptr);
156 switch (pde & PTE_ENTRYTYPE_MASK) {
158 case 0: /* Invalid */
160 case 2: /* L0 PTE, maybe should not happen? */
161 case 3: /* Reserved */
164 pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
165 pde = ldl_phys(pde_ptr);
167 switch (pde & PTE_ENTRYTYPE_MASK) {
169 case 0: /* Invalid */
170 return (1 << 8) | (1 << 2);
171 case 3: /* Reserved */
172 return (1 << 8) | (4 << 2);
174 pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
175 pde = ldl_phys(pde_ptr);
177 switch (pde & PTE_ENTRYTYPE_MASK) {
179 case 0: /* Invalid */
180 return (2 << 8) | (1 << 2);
181 case 3: /* Reserved */
182 return (2 << 8) | (4 << 2);
184 pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
185 pde = ldl_phys(pde_ptr);
187 switch (pde & PTE_ENTRYTYPE_MASK) {
189 case 0: /* Invalid */
190 return (3 << 8) | (1 << 2);
191 case 1: /* PDE, should not happen */
192 case 3: /* Reserved */
193 return (3 << 8) | (4 << 2);
195 virt_addr = address & TARGET_PAGE_MASK;
196 page_offset = (address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1);
200 virt_addr = address & ~0x3ffff;
201 page_offset = address & 0x3ffff;
205 virt_addr = address & ~0xffffff;
206 page_offset = address & 0xffffff;
210 /* update page modified and dirty bits */
211 is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
212 if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
213 pde |= PG_ACCESSED_MASK;
215 pde |= PG_MODIFIED_MASK;
216 stl_phys_notdirty(pde_ptr, pde);
219 access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT;
220 error_code = access_table[*access_index][access_perms];
221 if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user))
224 /* the page can be put in the TLB */
225 *prot = perm_table[is_user][access_perms];
226 if (!(pde & PG_MODIFIED_MASK)) {
227 /* only set write access if already dirty... otherwise wait
229 *prot &= ~PAGE_WRITE;
232 /* Even if large ptes, we map only one 4KB page in the cache to
233 avoid filling it too fast */
234 *physical = ((target_phys_addr_t)(pde & PTE_ADDR_MASK) << 4) + page_offset;
238 /* Perform address translation */
239 int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
240 int mmu_idx, int is_softmmu)
242 target_phys_addr_t paddr;
244 int error_code = 0, prot, ret = 0, access_index;
246 error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, mmu_idx);
247 if (error_code == 0) {
248 vaddr = address & TARGET_PAGE_MASK;
249 paddr &= TARGET_PAGE_MASK;
251 printf("Translate at " TARGET_FMT_lx " -> " TARGET_FMT_plx ", vaddr "
252 TARGET_FMT_lx "\n", address, paddr, vaddr);
254 ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
258 if (env->mmuregs[3]) /* Fault status register */
259 env->mmuregs[3] = 1; /* overflow (not read before another fault) */
260 env->mmuregs[3] |= (access_index << 5) | error_code | 2;
261 env->mmuregs[4] = address; /* Fault address register */
263 if ((env->mmuregs[0] & MMU_NF) || env->psret == 0) {
264 // No fault mode: if a mapping is available, just override
265 // permissions. If no mapping is available, redirect accesses to
266 // neverland. Fake/overridden mappings will be flushed when
267 // switching to normal mode.
268 vaddr = address & TARGET_PAGE_MASK;
269 prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
270 ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
274 env->exception_index = TT_TFAULT;
276 env->exception_index = TT_DFAULT;
281 target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev)
283 target_phys_addr_t pde_ptr;
286 /* Context base + context number */
287 pde_ptr = (target_phys_addr_t)(env->mmuregs[1] << 4) +
288 (env->mmuregs[2] << 2);
289 pde = ldl_phys(pde_ptr);
291 switch (pde & PTE_ENTRYTYPE_MASK) {
293 case 0: /* Invalid */
294 case 2: /* PTE, maybe should not happen? */
295 case 3: /* Reserved */
300 pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
301 pde = ldl_phys(pde_ptr);
303 switch (pde & PTE_ENTRYTYPE_MASK) {
305 case 0: /* Invalid */
306 case 3: /* Reserved */
313 pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
314 pde = ldl_phys(pde_ptr);
316 switch (pde & PTE_ENTRYTYPE_MASK) {
318 case 0: /* Invalid */
319 case 3: /* Reserved */
326 pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
327 pde = ldl_phys(pde_ptr);
329 switch (pde & PTE_ENTRYTYPE_MASK) {
331 case 0: /* Invalid */
332 case 1: /* PDE, should not happen */
333 case 3: /* Reserved */
345 void dump_mmu(CPUState *env)
347 target_ulong va, va1, va2;
348 unsigned int n, m, o;
349 target_phys_addr_t pde_ptr, pa;
352 printf("MMU dump:\n");
353 pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
354 pde = ldl_phys(pde_ptr);
355 printf("Root ptr: " TARGET_FMT_plx ", ctx: %d\n",
356 (target_phys_addr_t)env->mmuregs[1] << 4, env->mmuregs[2]);
357 for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
358 pde = mmu_probe(env, va, 2);
360 pa = cpu_get_phys_page_debug(env, va);
361 printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
362 " PDE: " TARGET_FMT_lx "\n", va, pa, pde);
363 for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
364 pde = mmu_probe(env, va1, 1);
366 pa = cpu_get_phys_page_debug(env, va1);
367 printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
368 " PDE: " TARGET_FMT_lx "\n", va1, pa, pde);
369 for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
370 pde = mmu_probe(env, va2, 0);
372 pa = cpu_get_phys_page_debug(env, va2);
373 printf(" VA: " TARGET_FMT_lx ", PA: "
374 TARGET_FMT_plx " PTE: " TARGET_FMT_lx "\n",
382 printf("MMU dump ends\n");
384 #endif /* DEBUG_MMU */
386 #else /* !TARGET_SPARC64 */
388 * UltraSparc IIi I/DMMUs
390 static int get_physical_address_data(CPUState *env, target_phys_addr_t *physical, int *prot,
391 target_ulong address, int rw, int is_user)
396 if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */
398 *prot = PAGE_READ | PAGE_WRITE;
402 for (i = 0; i < 64; i++) {
403 switch ((env->dtlb_tte[i] >> 61) & 3) {
406 mask = 0xffffffffffffe000ULL;
409 mask = 0xffffffffffff0000ULL;
412 mask = 0xfffffffffff80000ULL;
415 mask = 0xffffffffffc00000ULL;
418 // ctx match, vaddr match?
419 if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) &&
420 (address & mask) == (env->dtlb_tag[i] & ~0x1fffULL)) {
422 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0 ||
423 ((env->dtlb_tte[i] & 0x4) && is_user) ||
424 (!(env->dtlb_tte[i] & 0x2) && (rw == 1))) {
425 if (env->dmmuregs[3]) /* Fault status register */
426 env->dmmuregs[3] = 2; /* overflow (not read before another fault) */
427 env->dmmuregs[3] |= (is_user << 3) | ((rw == 1) << 2) | 1;
428 env->dmmuregs[4] = address; /* Fault address register */
429 env->exception_index = TT_DFAULT;
431 printf("DFAULT at 0x%" PRIx64 "\n", address);
435 *physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
437 if (env->dtlb_tte[i] & 0x2)
443 printf("DMISS at 0x%" PRIx64 "\n", address);
445 env->exception_index = TT_DMISS;
449 static int get_physical_address_code(CPUState *env, target_phys_addr_t *physical, int *prot,
450 target_ulong address, int is_user)
455 if ((env->lsu & IMMU_E) == 0) { /* IMMU disabled */
461 for (i = 0; i < 64; i++) {
462 switch ((env->itlb_tte[i] >> 61) & 3) {
465 mask = 0xffffffffffffe000ULL;
468 mask = 0xffffffffffff0000ULL;
471 mask = 0xfffffffffff80000ULL;
474 mask = 0xffffffffffc00000ULL;
477 // ctx match, vaddr match?
478 if (env->dmmuregs[1] == (env->itlb_tag[i] & 0x1fff) &&
479 (address & mask) == (env->itlb_tag[i] & ~0x1fffULL)) {
481 if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0 ||
482 ((env->itlb_tte[i] & 0x4) && is_user)) {
483 if (env->immuregs[3]) /* Fault status register */
484 env->immuregs[3] = 2; /* overflow (not read before another fault) */
485 env->immuregs[3] |= (is_user << 3) | 1;
486 env->exception_index = TT_TFAULT;
488 printf("TFAULT at 0x%" PRIx64 "\n", address);
492 *physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) + (address & ~mask & 0x1fffffff000ULL);
498 printf("TMISS at 0x%" PRIx64 "\n", address);
500 env->exception_index = TT_TMISS;
504 static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
505 int *prot, int *access_index,
506 target_ulong address, int rw, int mmu_idx)
508 int is_user = mmu_idx == MMU_USER_IDX;
511 return get_physical_address_code(env, physical, prot, address,
514 return get_physical_address_data(env, physical, prot, address, rw,
518 /* Perform address translation */
519 int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
520 int mmu_idx, int is_softmmu)
522 target_ulong virt_addr, vaddr;
523 target_phys_addr_t paddr;
524 int error_code = 0, prot, ret = 0, access_index;
526 error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, mmu_idx);
527 if (error_code == 0) {
528 virt_addr = address & TARGET_PAGE_MASK;
529 vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1));
531 printf("Translate at 0x%" PRIx64 " -> 0x%" PRIx64 ", vaddr 0x%" PRIx64 "\n", address, paddr, vaddr);
533 ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
541 void dump_mmu(CPUState *env)
546 printf("MMU contexts: Primary: %" PRId64 ", Secondary: %" PRId64 "\n", env->dmmuregs[1], env->dmmuregs[2]);
547 if ((env->lsu & DMMU_E) == 0) {
548 printf("DMMU disabled\n");
550 printf("DMMU dump:\n");
551 for (i = 0; i < 64; i++) {
552 switch ((env->dtlb_tte[i] >> 61) & 3) {
567 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) {
568 printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, %s, ctx %" PRId64 "\n",
569 env->dtlb_tag[i] & ~0x1fffULL,
570 env->dtlb_tte[i] & 0x1ffffffe000ULL,
572 env->dtlb_tte[i] & 0x4? "priv": "user",
573 env->dtlb_tte[i] & 0x2? "RW": "RO",
574 env->dtlb_tte[i] & 0x40? "locked": "unlocked",
575 env->dtlb_tag[i] & 0x1fffULL);
579 if ((env->lsu & IMMU_E) == 0) {
580 printf("IMMU disabled\n");
582 printf("IMMU dump:\n");
583 for (i = 0; i < 64; i++) {
584 switch ((env->itlb_tte[i] >> 61) & 3) {
599 if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) {
600 printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx ", %s, %s, %s, ctx %" PRId64 "\n",
601 env->itlb_tag[i] & ~0x1fffULL,
602 env->itlb_tte[i] & 0x1ffffffe000ULL,
604 env->itlb_tte[i] & 0x4? "priv": "user",
605 env->itlb_tte[i] & 0x40? "locked": "unlocked",
606 env->itlb_tag[i] & 0x1fffULL);
611 #endif /* DEBUG_MMU */
613 #endif /* TARGET_SPARC64 */
614 #endif /* !CONFIG_USER_ONLY */
617 #if defined(CONFIG_USER_ONLY)
618 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
624 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
626 target_phys_addr_t phys_addr;
627 int prot, access_index;
629 if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2,
630 MMU_KERNEL_IDX) != 0)
631 if (get_physical_address(env, &phys_addr, &prot, &access_index, addr,
632 0, MMU_KERNEL_IDX) != 0)
634 if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED)
640 void memcpy32(target_ulong *dst, const target_ulong *src)
652 void helper_flush(target_ulong addr)
655 tb_invalidate_page_range(addr, addr + 8);
658 void cpu_reset(CPUSPARCState *env)
663 env->regwptr = env->regbase + (env->cwp * 16);
664 #if defined(CONFIG_USER_ONLY)
665 env->user_mode_only = 1;
666 #ifdef TARGET_SPARC64
667 env->cleanwin = NWINDOWS - 2;
668 env->cansave = NWINDOWS - 2;
669 env->pstate = PS_RMO | PS_PEF | PS_IE;
670 env->asi = 0x82; // Primary no-fault
676 #ifdef TARGET_SPARC64
677 env->pstate = PS_PRIV;
678 env->hpstate = HS_PRIV;
679 env->pc = 0x1fff0000000ULL;
680 env->tsptr = &env->ts[env->tl];
683 env->mmuregs[0] &= ~(MMU_E | MMU_NF);
684 env->mmuregs[0] |= env->mmu_bm;
686 env->npc = env->pc + 4;
690 static int cpu_sparc_register(CPUSPARCState *env, const char *cpu_model)
692 sparc_def_t def1, *def = &def1;
694 if (cpu_sparc_find_by_name(def, cpu_model) < 0)
697 env->features = def->features;
698 env->cpu_model_str = cpu_model;
699 env->version = def->iu_version;
700 env->fsr = def->fpu_version;
701 #if !defined(TARGET_SPARC64)
702 env->mmu_bm = def->mmu_bm;
703 env->mmu_ctpr_mask = def->mmu_ctpr_mask;
704 env->mmu_cxr_mask = def->mmu_cxr_mask;
705 env->mmu_sfsr_mask = def->mmu_sfsr_mask;
706 env->mmu_trcr_mask = def->mmu_trcr_mask;
707 env->mmuregs[0] |= def->mmu_version;
708 cpu_sparc_set_id(env, 0);
713 static void cpu_sparc_close(CPUSPARCState *env)
718 CPUSPARCState *cpu_sparc_init(const char *cpu_model)
722 env = qemu_mallocz(sizeof(CPUSPARCState));
727 gen_intermediate_code_init(env);
729 if (cpu_sparc_register(env, cpu_model) < 0) {
730 cpu_sparc_close(env);
738 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu)
740 #if !defined(TARGET_SPARC64)
741 env->mxccregs[7] = ((cpu + 8) & 0xf) << 24;
745 static const sparc_def_t sparc_defs[] = {
746 #ifdef TARGET_SPARC64
748 .name = "Fujitsu Sparc64",
749 .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)
750 | (MAXTL << 8) | (NWINDOWS - 1)),
751 .fpu_version = 0x00000000,
753 .features = CPU_DEFAULT_FEATURES,
756 .name = "Fujitsu Sparc64 III",
757 .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)
758 | (MAXTL << 8) | (NWINDOWS - 1)),
759 .fpu_version = 0x00000000,
761 .features = CPU_DEFAULT_FEATURES,
764 .name = "Fujitsu Sparc64 IV",
765 .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)
766 | (MAXTL << 8) | (NWINDOWS - 1)),
767 .fpu_version = 0x00000000,
769 .features = CPU_DEFAULT_FEATURES,
772 .name = "Fujitsu Sparc64 V",
773 .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)
774 | (MAXTL << 8) | (NWINDOWS - 1)),
775 .fpu_version = 0x00000000,
777 .features = CPU_DEFAULT_FEATURES,
780 .name = "TI UltraSparc I",
781 .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)
782 | (MAXTL << 8) | (NWINDOWS - 1)),
783 .fpu_version = 0x00000000,
785 .features = CPU_DEFAULT_FEATURES,
788 .name = "TI UltraSparc II",
789 .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)
790 | (MAXTL << 8) | (NWINDOWS - 1)),
791 .fpu_version = 0x00000000,
793 .features = CPU_DEFAULT_FEATURES,
796 .name = "TI UltraSparc IIi",
797 .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)
798 | (MAXTL << 8) | (NWINDOWS - 1)),
799 .fpu_version = 0x00000000,
801 .features = CPU_DEFAULT_FEATURES,
804 .name = "TI UltraSparc IIe",
805 .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)
806 | (MAXTL << 8) | (NWINDOWS - 1)),
807 .fpu_version = 0x00000000,
809 .features = CPU_DEFAULT_FEATURES,
812 .name = "Sun UltraSparc III",
813 .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)
814 | (MAXTL << 8) | (NWINDOWS - 1)),
815 .fpu_version = 0x00000000,
817 .features = CPU_DEFAULT_FEATURES,
820 .name = "Sun UltraSparc III Cu",
821 .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)
822 | (MAXTL << 8) | (NWINDOWS - 1)),
823 .fpu_version = 0x00000000,
825 .features = CPU_DEFAULT_FEATURES,
828 .name = "Sun UltraSparc IIIi",
829 .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)
830 | (MAXTL << 8) | (NWINDOWS - 1)),
831 .fpu_version = 0x00000000,
833 .features = CPU_DEFAULT_FEATURES,
836 .name = "Sun UltraSparc IV",
837 .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)
838 | (MAXTL << 8) | (NWINDOWS - 1)),
839 .fpu_version = 0x00000000,
841 .features = CPU_DEFAULT_FEATURES,
844 .name = "Sun UltraSparc IV+",
845 .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)
846 | (MAXTL << 8) | (NWINDOWS - 1)),
847 .fpu_version = 0x00000000,
849 .features = CPU_DEFAULT_FEATURES,
852 .name = "Sun UltraSparc IIIi+",
853 .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)
854 | (MAXTL << 8) | (NWINDOWS - 1)),
855 .fpu_version = 0x00000000,
857 .features = CPU_DEFAULT_FEATURES,
860 .name = "NEC UltraSparc I",
861 .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)
862 | (MAXTL << 8) | (NWINDOWS - 1)),
863 .fpu_version = 0x00000000,
865 .features = CPU_DEFAULT_FEATURES,
869 .name = "Fujitsu MB86900",
870 .iu_version = 0x00 << 24, /* Impl 0, ver 0 */
871 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
872 .mmu_version = 0x00 << 24, /* Impl 0, ver 0 */
873 .mmu_bm = 0x00004000,
874 .mmu_ctpr_mask = 0x007ffff0,
875 .mmu_cxr_mask = 0x0000003f,
876 .mmu_sfsr_mask = 0xffffffff,
877 .mmu_trcr_mask = 0xffffffff,
878 .features = CPU_FEATURE_FLOAT,
881 .name = "Fujitsu MB86904",
882 .iu_version = 0x04 << 24, /* Impl 0, ver 4 */
883 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
884 .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
885 .mmu_bm = 0x00004000,
886 .mmu_ctpr_mask = 0x00ffffc0,
887 .mmu_cxr_mask = 0x000000ff,
888 .mmu_sfsr_mask = 0x00016fff,
889 .mmu_trcr_mask = 0x00ffffff,
890 .features = CPU_DEFAULT_FEATURES,
893 .name = "Fujitsu MB86907",
894 .iu_version = 0x05 << 24, /* Impl 0, ver 5 */
895 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
896 .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
897 .mmu_bm = 0x00004000,
898 .mmu_ctpr_mask = 0xffffffc0,
899 .mmu_cxr_mask = 0x000000ff,
900 .mmu_sfsr_mask = 0x00016fff,
901 .mmu_trcr_mask = 0xffffffff,
902 .features = CPU_DEFAULT_FEATURES,
905 .name = "LSI L64811",
906 .iu_version = 0x10 << 24, /* Impl 1, ver 0 */
907 .fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */
908 .mmu_version = 0x10 << 24,
909 .mmu_bm = 0x00004000,
910 .mmu_ctpr_mask = 0x007ffff0,
911 .mmu_cxr_mask = 0x0000003f,
912 .mmu_sfsr_mask = 0xffffffff,
913 .mmu_trcr_mask = 0xffffffff,
914 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT,
917 .name = "Cypress CY7C601",
918 .iu_version = 0x11 << 24, /* Impl 1, ver 1 */
919 .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
920 .mmu_version = 0x10 << 24,
921 .mmu_bm = 0x00004000,
922 .mmu_ctpr_mask = 0x007ffff0,
923 .mmu_cxr_mask = 0x0000003f,
924 .mmu_sfsr_mask = 0xffffffff,
925 .mmu_trcr_mask = 0xffffffff,
926 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT,
929 .name = "Cypress CY7C611",
930 .iu_version = 0x13 << 24, /* Impl 1, ver 3 */
931 .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
932 .mmu_version = 0x10 << 24,
933 .mmu_bm = 0x00004000,
934 .mmu_ctpr_mask = 0x007ffff0,
935 .mmu_cxr_mask = 0x0000003f,
936 .mmu_sfsr_mask = 0xffffffff,
937 .mmu_trcr_mask = 0xffffffff,
938 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT,
941 .name = "TI SuperSparc II",
942 .iu_version = 0x40000000,
943 .fpu_version = 0 << 17,
944 .mmu_version = 0x04000000,
945 .mmu_bm = 0x00002000,
946 .mmu_ctpr_mask = 0xffffffc0,
947 .mmu_cxr_mask = 0x0000ffff,
948 .mmu_sfsr_mask = 0xffffffff,
949 .mmu_trcr_mask = 0xffffffff,
950 .features = CPU_DEFAULT_FEATURES,
953 .name = "TI MicroSparc I",
954 .iu_version = 0x41000000,
955 .fpu_version = 4 << 17,
956 .mmu_version = 0x41000000,
957 .mmu_bm = 0x00004000,
958 .mmu_ctpr_mask = 0x007ffff0,
959 .mmu_cxr_mask = 0x0000003f,
960 .mmu_sfsr_mask = 0x00016fff,
961 .mmu_trcr_mask = 0x0000003f,
962 .features = CPU_DEFAULT_FEATURES,
965 .name = "TI MicroSparc II",
966 .iu_version = 0x42000000,
967 .fpu_version = 4 << 17,
968 .mmu_version = 0x02000000,
969 .mmu_bm = 0x00004000,
970 .mmu_ctpr_mask = 0x00ffffc0,
971 .mmu_cxr_mask = 0x000000ff,
972 .mmu_sfsr_mask = 0x00016fff,
973 .mmu_trcr_mask = 0x00ffffff,
974 .features = CPU_DEFAULT_FEATURES,
977 .name = "TI MicroSparc IIep",
978 .iu_version = 0x42000000,
979 .fpu_version = 4 << 17,
980 .mmu_version = 0x04000000,
981 .mmu_bm = 0x00004000,
982 .mmu_ctpr_mask = 0x00ffffc0,
983 .mmu_cxr_mask = 0x000000ff,
984 .mmu_sfsr_mask = 0x00016bff,
985 .mmu_trcr_mask = 0x00ffffff,
986 .features = CPU_DEFAULT_FEATURES,
989 .name = "TI SuperSparc 51",
990 .iu_version = 0x43000000,
991 .fpu_version = 0 << 17,
992 .mmu_version = 0x04000000,
993 .mmu_bm = 0x00002000,
994 .mmu_ctpr_mask = 0xffffffc0,
995 .mmu_cxr_mask = 0x0000ffff,
996 .mmu_sfsr_mask = 0xffffffff,
997 .mmu_trcr_mask = 0xffffffff,
998 .features = CPU_DEFAULT_FEATURES,
1001 .name = "TI SuperSparc 61",
1002 .iu_version = 0x44000000,
1003 .fpu_version = 0 << 17,
1004 .mmu_version = 0x04000000,
1005 .mmu_bm = 0x00002000,
1006 .mmu_ctpr_mask = 0xffffffc0,
1007 .mmu_cxr_mask = 0x0000ffff,
1008 .mmu_sfsr_mask = 0xffffffff,
1009 .mmu_trcr_mask = 0xffffffff,
1010 .features = CPU_DEFAULT_FEATURES,
1013 .name = "Ross RT625",
1014 .iu_version = 0x1e000000,
1015 .fpu_version = 1 << 17,
1016 .mmu_version = 0x1e000000,
1017 .mmu_bm = 0x00004000,
1018 .mmu_ctpr_mask = 0x007ffff0,
1019 .mmu_cxr_mask = 0x0000003f,
1020 .mmu_sfsr_mask = 0xffffffff,
1021 .mmu_trcr_mask = 0xffffffff,
1022 .features = CPU_DEFAULT_FEATURES,
1025 .name = "Ross RT620",
1026 .iu_version = 0x1f000000,
1027 .fpu_version = 1 << 17,
1028 .mmu_version = 0x1f000000,
1029 .mmu_bm = 0x00004000,
1030 .mmu_ctpr_mask = 0x007ffff0,
1031 .mmu_cxr_mask = 0x0000003f,
1032 .mmu_sfsr_mask = 0xffffffff,
1033 .mmu_trcr_mask = 0xffffffff,
1034 .features = CPU_DEFAULT_FEATURES,
1037 .name = "BIT B5010",
1038 .iu_version = 0x20000000,
1039 .fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */
1040 .mmu_version = 0x20000000,
1041 .mmu_bm = 0x00004000,
1042 .mmu_ctpr_mask = 0x007ffff0,
1043 .mmu_cxr_mask = 0x0000003f,
1044 .mmu_sfsr_mask = 0xffffffff,
1045 .mmu_trcr_mask = 0xffffffff,
1046 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT,
1049 .name = "Matsushita MN10501",
1050 .iu_version = 0x50000000,
1051 .fpu_version = 0 << 17,
1052 .mmu_version = 0x50000000,
1053 .mmu_bm = 0x00004000,
1054 .mmu_ctpr_mask = 0x007ffff0,
1055 .mmu_cxr_mask = 0x0000003f,
1056 .mmu_sfsr_mask = 0xffffffff,
1057 .mmu_trcr_mask = 0xffffffff,
1058 .features = CPU_FEATURE_FLOAT | CPU_FEATURE_MUL | CPU_FEATURE_FSQRT,
1061 .name = "Weitek W8601",
1062 .iu_version = 0x90 << 24, /* Impl 9, ver 0 */
1063 .fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */
1064 .mmu_version = 0x10 << 24,
1065 .mmu_bm = 0x00004000,
1066 .mmu_ctpr_mask = 0x007ffff0,
1067 .mmu_cxr_mask = 0x0000003f,
1068 .mmu_sfsr_mask = 0xffffffff,
1069 .mmu_trcr_mask = 0xffffffff,
1070 .features = CPU_DEFAULT_FEATURES,
1074 .iu_version = 0xf2000000,
1075 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
1076 .mmu_version = 0xf2000000,
1077 .mmu_bm = 0x00004000,
1078 .mmu_ctpr_mask = 0x007ffff0,
1079 .mmu_cxr_mask = 0x0000003f,
1080 .mmu_sfsr_mask = 0xffffffff,
1081 .mmu_trcr_mask = 0xffffffff,
1082 .features = CPU_DEFAULT_FEATURES,
1086 .iu_version = 0xf3000000,
1087 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
1088 .mmu_version = 0xf3000000,
1089 .mmu_bm = 0x00004000,
1090 .mmu_ctpr_mask = 0x007ffff0,
1091 .mmu_cxr_mask = 0x0000003f,
1092 .mmu_sfsr_mask = 0xffffffff,
1093 .mmu_trcr_mask = 0xffffffff,
1094 .features = CPU_DEFAULT_FEATURES,
1099 static const char * const feature_name[] = {
1112 static void print_features(FILE *f,
1113 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
1114 uint32_t features, const char *prefix)
1118 for (i = 0; i < ARRAY_SIZE(feature_name); i++)
1119 if (feature_name[i] && (features & (1 << i))) {
1121 (*cpu_fprintf)(f, "%s", prefix);
1122 (*cpu_fprintf)(f, "%s ", feature_name[i]);
1126 static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features)
1130 for (i = 0; i < ARRAY_SIZE(feature_name); i++)
1131 if (feature_name[i] && !strcmp(flagname, feature_name[i])) {
1132 *features |= 1 << i;
1135 fprintf(stderr, "CPU feature %s not found\n", flagname);
1138 static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model)
1141 const sparc_def_t *def = NULL;
1142 char *s = strdup(cpu_model);
1143 char *featurestr, *name = strtok(s, ",");
1144 uint32_t plus_features = 0;
1145 uint32_t minus_features = 0;
1146 long long iu_version;
1147 uint32_t fpu_version, mmu_version;
1149 for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
1150 if (strcasecmp(name, sparc_defs[i].name) == 0) {
1151 def = &sparc_defs[i];
1156 memcpy(cpu_def, def, sizeof(*def));
1158 featurestr = strtok(NULL, ",");
1159 while (featurestr) {
1162 if (featurestr[0] == '+') {
1163 add_flagname_to_bitmaps(featurestr + 1, &plus_features);
1164 } else if (featurestr[0] == '-') {
1165 add_flagname_to_bitmaps(featurestr + 1, &minus_features);
1166 } else if ((val = strchr(featurestr, '='))) {
1168 if (!strcmp(featurestr, "iu_version")) {
1171 iu_version = strtoll(val, &err, 0);
1172 if (!*val || *err) {
1173 fprintf(stderr, "bad numerical value %s\n", val);
1176 cpu_def->iu_version = iu_version;
1177 #ifdef DEBUG_FEATURES
1178 fprintf(stderr, "iu_version %llx\n", iu_version);
1180 } else if (!strcmp(featurestr, "fpu_version")) {
1183 fpu_version = strtol(val, &err, 0);
1184 if (!*val || *err) {
1185 fprintf(stderr, "bad numerical value %s\n", val);
1188 cpu_def->fpu_version = fpu_version;
1189 #ifdef DEBUG_FEATURES
1190 fprintf(stderr, "fpu_version %llx\n", fpu_version);
1192 } else if (!strcmp(featurestr, "mmu_version")) {
1195 mmu_version = strtol(val, &err, 0);
1196 if (!*val || *err) {
1197 fprintf(stderr, "bad numerical value %s\n", val);
1200 cpu_def->mmu_version = mmu_version;
1201 #ifdef DEBUG_FEATURES
1202 fprintf(stderr, "mmu_version %llx\n", mmu_version);
1205 fprintf(stderr, "unrecognized feature %s\n", featurestr);
1209 fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
1212 featurestr = strtok(NULL, ",");
1214 cpu_def->features |= plus_features;
1215 cpu_def->features &= ~minus_features;
1216 #ifdef DEBUG_FEATURES
1217 print_features(stderr, fprintf, cpu_def->features, NULL);
1227 void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
1231 for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
1232 (*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x ",
1234 sparc_defs[i].iu_version,
1235 sparc_defs[i].fpu_version,
1236 sparc_defs[i].mmu_version);
1237 print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES & ~sparc_defs[i].features, "-");
1238 print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES & sparc_defs[i].features, "+");
1239 (*cpu_fprintf)(f, "\n");
1241 (*cpu_fprintf)(f, "CPU feature flags (+/-): ");
1242 print_features(f, cpu_fprintf, -1, NULL);
1243 (*cpu_fprintf)(f, "\n");
1244 (*cpu_fprintf)(f, "Numerical features (=): iu_version fpu_version mmu_version\n");
1247 #define GET_FLAG(a,b) ((env->psr & a)?b:'-')
1249 void cpu_dump_state(CPUState *env, FILE *f,
1250 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
1255 cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, env->npc);
1256 cpu_fprintf(f, "General Registers:\n");
1257 for (i = 0; i < 4; i++)
1258 cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
1259 cpu_fprintf(f, "\n");
1261 cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
1262 cpu_fprintf(f, "\nCurrent Register Window:\n");
1263 for (x = 0; x < 3; x++) {
1264 for (i = 0; i < 4; i++)
1265 cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
1266 (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
1267 env->regwptr[i + x * 8]);
1268 cpu_fprintf(f, "\n");
1270 cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
1271 (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
1272 env->regwptr[i + x * 8]);
1273 cpu_fprintf(f, "\n");
1275 cpu_fprintf(f, "\nFloating Point Registers:\n");
1276 for (i = 0; i < 32; i++) {
1278 cpu_fprintf(f, "%%f%02d:", i);
1279 cpu_fprintf(f, " %016lf", env->fpr[i]);
1281 cpu_fprintf(f, "\n");
1283 #ifdef TARGET_SPARC64
1284 cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
1285 env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs);
1286 cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d cleanwin %d cwp %d\n",
1287 env->cansave, env->canrestore, env->otherwin, env->wstate,
1288 env->cleanwin, NWINDOWS - 1 - env->cwp);
1290 cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
1291 GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
1292 GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
1293 env->psrs?'S':'-', env->psrps?'P':'-',
1294 env->psret?'E':'-', env->wim);
1296 cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env));
1299 #ifdef TARGET_SPARC64
1300 #if !defined(CONFIG_USER_ONLY)
1301 #include "qemu-common.h"
1303 #include "qemu-timer.h"
1306 void helper_tick_set_count(void *opaque, uint64_t count)
1308 #if !defined(CONFIG_USER_ONLY)
1309 ptimer_set_count(opaque, -count);
1313 uint64_t helper_tick_get_count(void *opaque)
1315 #if !defined(CONFIG_USER_ONLY)
1316 return -ptimer_get_count(opaque);
1322 void helper_tick_set_limit(void *opaque, uint64_t limit)
1324 #if !defined(CONFIG_USER_ONLY)
1325 ptimer_set_limit(opaque, -limit, 0);